Kewen Lin [Thu, 21 Nov 2024 07:41:33 +0000 (07:41 +0000)]
rs6000: Remove ISA_3_0_MASKS_IEEE and check P9_VECTOR instead
When working to get rid of mask bit OPTION_MASK_P8_VECTOR,
I noticed that the check on ISA_3_0_MASKS_IEEE is actually
to check TARGET_P9_VECTOR, since we check all three mask
bits together and p9 vector guarantees p8 vector and vsx
should be enabled. So this patch is to adjust this first
as preparatory patch for the following patch to change
all uses of OPTION_MASK_P8_VECTOR and TARGET_P8_VECTOR.
Kewen Lin [Thu, 21 Nov 2024 07:41:33 +0000 (07:41 +0000)]
rs6000: Simplify some conditions or code related to TARGET_DIRECT_MOVE
When I was making a patch to rework TARGET_P8_VECTOR, I
noticed that there are some redundant checks and dead code
related to TARGET_DIRECT_MOVE, so I made this patch as one
separated preparatory patch, it consists of:
- Check either TARGET_DIRECT_MOVE or TARGET_P8_VECTOR only
according to the context, rather than checking both of
them since they are actually the same (TARGET_DIRECT_MOVE
is defined as TARGET_P8_VECTOR).
- Simplify TARGET_VSX && TARGET_DIRECT_MOVE as
TARGET_DIRECT_MOVE since direct move ensures VSX enabled.
- Replace some TARGET_POWERPC64 && TARGET_DIRECT_MOVE as
TARGET_DIRECT_MOVE_64BIT to simplify it.
- Remove some dead code guarded with TARGET_DIRECT_MOVE
but the condition never holds here.
gcc/ChangeLog:
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Simplify
TARGET_P8_VECTOR && TARGET_DIRECT_MOVE as TARGET_P8_VECTOR.
(rs6000_output_move_128bit): Simplify TARGET_VSX && TARGET_DIRECT_MOVE
as TARGET_DIRECT_MOVE.
* config/rs6000/rs6000.h (TARGET_XSCVDPSPN): Simplify conditions
TARGET_DIRECT_MOVE || TARGET_P8_VECTOR as TARGET_P8_VECTOR.
(TARGET_XSCVSPDPN): Likewise.
(TARGET_DIRECT_MOVE_128): Simplify TARGET_DIRECT_MOVE &&
TARGET_POWERPC64 as TARGET_DIRECT_MOVE_64BIT.
(TARGET_VEXTRACTUB): Likewise.
(TARGET_DIRECT_MOVE_64BIT): Simplify TARGET_P8_VECTOR &&
TARGET_DIRECT_MOVE as TARGET_DIRECT_MOVE.
* config/rs6000/rs6000.md (signbit<mode>2, @signbit<mode>2_dm,
*signbit<mode>2_dm_mem, floatsi<mode>2_lfiwax,
floatsi<SFDF:mode>2_lfiwax_<QHI:mode>_mem_zext,
floatunssi<mode>2_lfiwzx, float<QHI:mode><SFDF:mode>2,
*float<QHI:mode><SFDF:mode>2_internal, floatuns<QHI:mode><SFDF:mode>2,
*floatuns<QHI:mode><SFDF:mode>2_internal, p8_mtvsrd_v16qidi2,
p8_mtvsrd_df, p8_xxpermdi_<mode>, reload_vsx_from_gpr<mode>,
p8_mtvsrd_sf, reload_vsx_from_gprsf, p8_mfvsrd_3_<mode>,
reload_gpr_from_vsx<mode>, reload_gpr_from_vsxsf, unpack<mode>_dm):
Simplify TARGET_DIRECT_MOVE && TARGET_POWERPC64 as
TARGET_DIRECT_MOVE_64BIT.
(unpack<mode>_nodm): Simplify !TARGET_DIRECT_MOVE || !TARGET_POWERPC64
as !TARGET_DIRECT_MOVE_64BIT.
(fix_trunc<mode>si2, fix_trunc<mode>si2_stfiwx,
fix_trunc<mode>si2_internal): Simplify TARGET_P8_VECTOR &&
TARGET_DIRECT_MOVE as TARGET_DIRECT_MOVE.
(fix_trunc<mode>si2_stfiwx, fixuns_trunc<mode>si2_stfiwx): Remove some
dead code as the guard TARGET_DIRECT_MOVE there never holds.
(fixuns_trunc<mode>si2_stfiwx): Change TARGET_P8_VECTOR with
TARGET_DIRECT_MOVE which is a better fit.
* config/rs6000/vsx.md (define_peephole2 for SFmode in GPR): Simplify
TARGET_DIRECT_MOVE && TARGET_POWERPC64 as TARGET_DIRECT_MOVE_64BIT.
Lewis Hyatt [Fri, 25 Oct 2024 18:55:09 +0000 (14:55 -0400)]
tree-cfg: Fix call to next_discriminator_for_locus()
While testing future 64-bit location_t support, I ran into an
-fcompare-debug issue that was traced back here. Despite the name,
next_discriminator_for_locus() is meant to take an integer line number
argument, not a location_t. There is one call site which has been passing a
location_t instead. For the most part that is harmless, although in case
there are two CALL stmts on the same line with different location_t, it may
fail to generate a unique discriminator where it should. If/when location_t
changes to be 64-bit, however, it will produce an -fcompare-debug
failure. Fix it by passing the line number rather than the location_t.
I am not aware of a testcase that demonstrates any observable wrong
behavior, but the file debug/pr53466.C is an example where the discriminator
assignment is indeed different before and after this change.
gcc/ChangeLog:
* tree-cfg.cc (assign_discriminators): Fix incorrect value passed to
next_discriminator_for_locus().
Harald Anlauf [Wed, 20 Nov 2024 20:59:22 +0000 (21:59 +0100)]
Fortran: fix checking of protected variables in submodules [PR83135]
When a symbol was use-associated in the ancestor of a submodule, a
PROTECTED attribute was ignored in the submodule or its descendants.
Find the real ancestor of symbols when used in a variable definition
context in a submodule.
PR fortran/83135
gcc/fortran/ChangeLog:
* expr.cc (sym_is_from_ancestor): New helper function.
(gfc_check_vardef_context): Refine checking of PROTECTED attribute
of symbols that are indirectly use-associated in a submodule.
Joseph Myers [Wed, 20 Nov 2024 21:29:48 +0000 (21:29 +0000)]
c: Diagnose compound literal for empty array [PR114266]
As reported in bug 114266, GCC fails to pedwarn for a compound
literal, whose type is an array of unknown size, initialized with an
empty initializer. This case is disallowed by C23 (which doesn't have
zero-size objects); the case of a named object is diagnosed as
expected, but not that for compound literals. (Before C23, the
pedwarn for empty initializers sufficed.) Add a check for this
specific case with a pedwarn.
Bootstrapped with no regressions for x86_64-pc-linux-gnu.
PR c/114266
gcc/c/
* c-decl.cc (build_compound_literal): Diagnose array of unknown
size with empty initializer for C23.
gcc/testsuite/
* gcc.dg/c23-empty-init-4.c: New test.
Antoni Boucher [Thu, 18 Jan 2024 22:54:59 +0000 (17:54 -0500)]
libgccjit: Add support for creating temporary variables
gcc/jit/ChangeLog:
* docs/topics/compatibility.rst (LIBGCCJIT_ABI_33): New ABI tag.
* docs/topics/functions.rst: Document gcc_jit_function_new_temp.
* jit-playback.cc (new_local): Add support for temporary
variables.
* jit-recording.cc (recording::function::new_temp): New method.
(recording::local::write_reproducer): Support temporary
variables.
* jit-recording.h (new_temp): New method.
* libgccjit.cc (gcc_jit_function_new_temp): New function.
* libgccjit.h (gcc_jit_function_new_temp): New function.
* libgccjit.map: New function.
gcc/testsuite/ChangeLog:
* jit.dg/all-non-failing-tests.h: Mention test-temp.c.
* jit.dg/test-temp.c: New test.
[PR116587][LRA]: Fix last chance reload pseudo allocation
On i686 PR116587 test compilation resulted in LRA failure to find
registers for a reload insn pseudo. The insn requires 6 regs for 4
reload insn pseudos where two of them require 2 regs each. But we
have only 5 free regs as sp is a fixed reg, bp is fixed because of
-fno-omit-frame-pointer, bx is assigned to pic_offset_table_pseudo
because of -fPIC. LRA spills pic_offset_table_pseudo as the last
chance approach to allocate registers to the reload pseudo. Although
it makes 2 free registers for the unallocated reload pseudo requiring
also 2 regs, the pseudo still can not be allocated as the 2 free regs
are disjoint. The patch spills all pseudos conflicting with the
unallocated reload pseudo including already allocated reload insn
pseudos, then standard LRA code allocates spilled pseudos requiring
more one register first and avoid situation of the disjoint regs for
reload pseudos requiring more one reg.
gcc/ChangeLog:
PR target/116587
* lra-assigns.cc (find_all_spills_for): Consider all pseudos whose
classes intersect given pseudo class.
gcc/testsuite/ChangeLog:
PR target/116587
* gcc.target/i386/pr116587.c: New test.
Antoni Boucher [Mon, 23 Jan 2023 22:21:15 +0000 (17:21 -0500)]
libgccjit: Add support for machine-dependent builtins
gcc/jit/ChangeLog:
PR jit/108762
* docs/topics/compatibility.rst (LIBGCCJIT_ABI_32): New ABI tag.
* docs/topics/functions.rst: Add documentation for the function
gcc_jit_context_get_target_builtin_function.
* dummy-frontend.cc: Include headers target.h, jit-recording.h,
print-tree.h, unordered_map and string, new variables (target_builtins,
target_function_types, and target_builtins_ctxt), new function
(tree_type_to_jit_type).
* jit-builtins.cc: Specify that the function types are not from
target builtins.
* jit-playback.cc: New argument is_target_builtin to new_function.
* jit-playback.h: New argument is_target_builtin to
new_function.
* jit-recording.cc: New argument is_target_builtin to
new_function_type, function_type constructor and function
constructor, new function
(get_target_builtin_function).
* jit-recording.h: Include headers string and unordered_map, new
variable target_function_types, new argument is_target_builtin
to new_function_type, function_type and function, new functions
(get_target_builtin_function, copy).
* libgccjit.cc: New function
(gcc_jit_context_get_target_builtin_function).
* libgccjit.h: New function
(gcc_jit_context_get_target_builtin_function).
* libgccjit.map: New functions
(gcc_jit_context_get_target_builtin_function).
gcc/testsuite:
PR jit/108762
* jit.dg/all-non-failing-tests.h: New test test-target-builtins.c.
* jit.dg/test-target-builtins.c: New test.
Andrew Pinski [Wed, 20 Nov 2024 03:49:38 +0000 (19:49 -0800)]
aarch64: Fix aarch64 after moving to C23
This fixes a few aarch64 specific testcases after the move to default to GNU C23.
For the SME testcases, the GNU C23 cases as `()` changing to mean `(void)` instead
of a non-prototype declaration; the non-prototype declaration merging was confusing
some of the time so the updated way is the expected way even for that.
For pic-*.c `-Wno-old-style-definition` was added not to warn about old style definitions.
For pr113573.c, I added `-std=gnu17` since I was not sure if `(...)` with C23 would invoke
the same issue.
Andrew Pinski [Wed, 20 Nov 2024 07:45:20 +0000 (23:45 -0800)]
rtl-reader: Disable reuse_rtx support for generator building
reuse_rtx is not documented nor the format to use it is ever documented.
So it should not be supported for the .md files.
This also fixes the problem if an invalid index is supplied for reuse_rtx,
instead of ICEing, put out a real error message. Note since this code
still uses atoi, an invalid index can still be used in some cases but that is
recorded as part of PR 44574.
Note I did a grep of the sources to make sure that this was only used for
the read rtl in the GCC rather than while reading in .md files.
Bootstrapped and tested on x86_64-linux-gnu.
gcc/ChangeLog:
* read-md.h (class rtx_reader): Don't include m_reuse_rtx_by_id
when GENERATOR_FILE is defined.
* read-rtl.cc (rtx_reader::read_rtx_code): Disable reuse_rtx
support when GENERATOR_FILE is defined.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Edwin Lu [Tue, 19 Nov 2024 20:55:15 +0000 (12:55 -0800)]
RISC-V: testsuite: restrict big endian test to non vector
RISC-V vector currently does not support big endian so the postcommit
was getting the sorry, not implemented error on vector targets. Restrict
the testcase to non-vector targets
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr117595.c: Restrict to non vector targets.
Richard Biener [Wed, 20 Nov 2024 15:47:08 +0000 (16:47 +0100)]
tree-optimization/117709 - bogus offset for gather load
When diverting to VMAT_GATHER_SCATTER we fail to zero *poffset
which was previously set if a load was classified as
VMAT_CONTIGUOUS_REVERSE. The following refactors
get_group_load_store_type a bit to avoid this but this all needs
some serious TLC.
PR tree-optimization/117709
* tree-vect-stmts.cc (get_group_load_store_type): Only
set *poffset when we end up with VMAT_CONTIGUOUS_DOWN
or VMAT_CONTIGUOUS_REVERSE.
Richard Biener [Wed, 20 Nov 2024 12:32:48 +0000 (13:32 +0100)]
tree-optimization/117698 - SLP vectorization and alignment
When SLP vectorizing we fail to mark the general alignment check
as irrelevant when using VMAT_STRIDED_SLP (the implementation checks
for itself) and when VMAT_INVARIANT the override isn't effective.
This results in extra FAILs on sparc which the following fixes.
PR tree-optimization/117698
* tree-vect-stmts.cc (get_group_load_store_type): Properly
disregard alignment for VMAT_STRIDED_SLP and VMAT_INVARIANT.
(vectorizable_load): Adjust guard for dumping whether we
vectorize and unaligned access.
(vectorizable_store): Likewise.
Antoni Boucher [Thu, 15 Feb 2024 22:03:22 +0000 (17:03 -0500)]
libgccjit: Add option to allow special characters in function names
gcc/jit/ChangeLog:
* docs/topics/contexts.rst: Add documentation for new option.
* jit-recording.cc (recording::context::get_str_option): New
method.
* jit-recording.h (get_str_option): New method.
* libgccjit.cc (gcc_jit_context_new_function): Allow special
characters in function names.
* libgccjit.h (enum gcc_jit_str_option): New option.
OpenMP: common C/C++ testcases for dispatch + adjust_args
gcc/testsuite/ChangeLog:
* c-c++-common/gomp/declare-variant-2.c: Adjust dg-error directives.
* c-c++-common/gomp/adjust-args-1.c: New test.
* c-c++-common/gomp/adjust-args-2.c: New test.
* c-c++-common/gomp/declare-variant-dup-match-clause.c: New test.
* c-c++-common/gomp/dispatch-1.c: New test.
* c-c++-common/gomp/dispatch-2.c: New test.
* c-c++-common/gomp/dispatch-3.c: New test.
* c-c++-common/gomp/dispatch-4.c: New test.
* c-c++-common/gomp/dispatch-5.c: New test.
* c-c++-common/gomp/dispatch-6.c: New test.
* c-c++-common/gomp/dispatch-7.c: New test.
* c-c++-common/gomp/dispatch-8.c: New test.
* c-c++-common/gomp/dispatch-9.c: New test.
* c-c++-common/gomp/dispatch-10.c: New test.
libgomp/ChangeLog:
* testsuite/libgomp.c-c++-common/dispatch-1.c: New test.
* testsuite/libgomp.c-c++-common/dispatch-2.c: New test.
OpenMP: C++ front-end support for dispatch + adjust_args
This patch adds C++ support for the `dispatch` construct and the `adjust_args`
clause. It relies on the c-family bits comprised in the corresponding C front
end patch for pragmas and attributes.
Additional C/C++ common testcases are provided in a subsequent patch in the
series.
gcc/cp/ChangeLog:
* decl.cc (omp_declare_variant_finalize_one): Set adjust_args
need_device_ptr attribute.
* parser.cc (cp_parser_direct_declarator): Update call to
cp_parser_late_return_type_opt.
(cp_parser_late_return_type_opt): Add 'tree parms' parameter. Update
call to cp_parser_late_parsing_omp_declare_simd.
(cp_parser_omp_clause_name): Handle nocontext and novariants clauses.
(cp_parser_omp_clause_novariants): New function.
(cp_parser_omp_clause_nocontext): Likewise.
(cp_parser_omp_all_clauses): Handle PRAGMA_OMP_CLAUSE_NOVARIANTS and
PRAGMA_OMP_CLAUSE_NOCONTEXT.
(cp_parser_omp_dispatch_body): New function, inspired from
cp_parser_assignment_expression and cp_parser_postfix_expression.
(OMP_DISPATCH_CLAUSE_MASK): Define.
(cp_parser_omp_dispatch): New function.
(cp_finish_omp_declare_variant): Add parameter. Handle adjust_args
clause.
(cp_parser_late_parsing_omp_declare_simd): Add parameter. Update calls
to cp_finish_omp_declare_variant and cp_finish_omp_declare_variant.
(cp_parser_omp_construct): Handle PRAGMA_OMP_DISPATCH.
(cp_parser_pragma): Likewise.
* semantics.cc (finish_omp_clauses): Handle OMP_CLAUSE_NOCONTEXT and
OMP_CLAUSE_NOVARIANTS.
* pt.cc (tsubst_omp_clauses): Handle OMP_CLAUSE_NOCONTEXT and
OMP_CLAUSE_NOVARIANTS.
(tsubst_stmt): Handle OMP_DISPATCH.
(tsubst_expr): Handle IFN_GOMP_DISPATCH.
gcc/testsuite/ChangeLog:
* g++.dg/gomp/adjust-args-1.C: New test.
* g++.dg/gomp/adjust-args-2.C: New test.
* g++.dg/gomp/adjust-args-3.C: New test.
* g++.dg/gomp/dispatch-1.C: New test.
* g++.dg/gomp/dispatch-2.C: New test.
* g++.dg/gomp/dispatch-3.C: New test.
* g++.dg/gomp/dispatch-4.C: New test.
* g++.dg/gomp/dispatch-5.C: New test.
* g++.dg/gomp/dispatch-6.C: New test.
* g++.dg/gomp/dispatch-7.C: New test.
OpenMP: C front-end support for dispatch + adjust_args
This patch adds support to the C front-end to parse the `dispatch` construct and
the `adjust_args` clause. It also includes some common C/C++ bits for pragmas
and attributes.
Additional common C/C++ testcases are in a later patch in the series.
* c-parser.cc (c_parser_omp_dispatch): New function.
(c_parser_omp_clause_name): Handle nocontext and novariants clauses.
(c_parser_omp_clause_novariants): New function.
(c_parser_omp_clause_nocontext): Likewise.
(c_parser_omp_all_clauses): Handle nocontext and novariants clauses.
(c_parser_omp_dispatch_body): New function adapted from
c_parser_expr_no_commas.
(OMP_DISPATCH_CLAUSE_MASK): Define.
(c_parser_omp_dispatch): New function.
(c_finish_omp_declare_variant): Parse adjust_args.
(c_parser_omp_construct): Handle PRAGMA_OMP_DISPATCH.
* c-typeck.cc (c_finish_omp_clauses): Handle OMP_CLAUSE_NOVARIANTS and
OMP_CLAUSE_NOCONTEXT.
gcc/testsuite/ChangeLog:
* gcc.dg/gomp/adjust-args-1.c: New test.
* gcc.dg/gomp/dispatch-1.c: New test.
* gcc.dg/gomp/dispatch-2.c: New test.
* gcc.dg/gomp/dispatch-3.c: New test.
* gcc.dg/gomp/dispatch-4.c: New test.
* gcc.dg/gomp/dispatch-5.c: New test.
OpenMP: middle-end support for dispatch + adjust_args
This patch adds middle-end support for the `dispatch` construct and the
`adjust_args` clause. The heavy lifting is done in `gimplify_omp_dispatch` and
`gimplify_call_expr` respectively. For `adjust_args`, this mostly consists in
emitting a call to `omp_get_mapped_ptr` for the adequate device.
For dispatch, the following steps are performed:
* Handle the device clause, if any: set the default-device ICV at the top of the
dispatch region and restore its previous value at the end.
* Handle novariants and nocontext clauses, if any. Evaluate compile-time
constants and select a variant, if possible. Otherwise, emit code to handle all
possible cases at run time.
OpenMP: dispatch + adjust_args tree data structures and front-end interfaces
This patch introduces the OMP_DISPATCH tree node, as well as two new clauses
`nocontext` and `novariants`. It defines/exposes interfaces that will be
used in subsequent patches that add front-end and middle-end support, but
nothing generates these nodes yet.
gcc/ChangeLog:
* builtin-types.def (BT_FN_PTR_CONST_PTR_INT): New.
* omp-selectors.h (enum omp_ts_code): Add OMP_TRAIT_CONSTRUCT_DISPATCH.
* tree-core.h (enum omp_clause_code): Add OMP_CLAUSE_NOVARIANTS and
OMP_CLAUSE_NOCONTEXT.
* tree-pretty-print.cc (dump_omp_clause): Handle OMP_CLAUSE_NOVARIANTS
and OMP_CLAUSE_NOCONTEXT.
(dump_generic_node): Handle OMP_DISPATCH.
* tree.cc (omp_clause_num_ops): Add OMP_CLAUSE_NOVARIANTS and
OMP_CLAUSE_NOCONTEXT.
(omp_clause_code_name): Add "novariants" and "nocontext".
* tree.def (OMP_DISPATCH): New.
* tree.h (OMP_DISPATCH_BODY): New macro.
(OMP_DISPATCH_CLAUSES): New macro.
(OMP_CLAUSE_NOVARIANTS_EXPR): New macro.
(OMP_CLAUSE_NOCONTEXT_EXPR): New macro.
This patch adds support for FEAT_SME2p1. There are two sets of
new instructions: MOVAZ to read from ZA and zero the source data,
and new forms of ZERO. All of them require streaming mode.
MOVAZ can't reuse the existing UNSPEC_SME_READ* patterns because
of the write to ZA. I did wonder about trying to use a define_subst,
but it seemed a bit too awkward.
gcc/
* config/aarch64/aarch64-option-extensions.def (sme2p1): New extension.
* doc/invoke.texi: Document it.
* config/aarch64/aarch64.h (TARGET_STREAMING_SME2p1): New macro.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Conditionally define __ARM_FEATURE_SME2p1.
* config/aarch64/iterators.md (UNSPEC_SME_READZ, UNSPEC_SME_READZ_HOR)
(UNSPEC_SME_READZ_VER): New unspecs.
(optab, hv): Handle them.
(SME_READZ_HV): New int iterator.
* config/aarch64/aarch64-sme.md
(UNSPEC_SME_ZERO_SLICES): New unspec.
(@aarch64_sme_<SME_READZ_HV:optab><v_int_container><mode>)
(*aarch64_sme_<SME_READZ_HV:optab><v_int_container><mode>_plus)
(@aarch64_sme_<SME_READZ_HV:optab><VNx1TI_ONLY:mode><SVE_FULL:mode>)
(@aarch64_sme_<SME_READZ_HV:optab><SVE_FULLx24:mode><mode>)
(*aarch64_sme_<SME_READZ_HV:optab><SVE_FULLx24:mode><mode>_plus)
(@aarch64_sme_readz<mode>, *aarch64_sme_readz<mode>_plus)
(@aarch64_sme_zero_za_slices<mode>): New patterns.
(*aarch64_sme_zero_za_slices<mode>_plus): Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.h
(inherent_za_slice): Declare.
* config/aarch64/aarch64-sve-builtins-shapes.cc
(inherent_za_slice_def, inherent_za_slice): New shape.
* config/aarch64/aarch64-sve-builtins-sme.h (svreadz_za)
(svreadz_hor_za, svreadz_ver_za): Declare.
* config/aarch64/aarch64-sve-builtins-sme.cc
(svread_za_slice_base): New class, split out from...
(svread_za_impl): ...here.
(svreadz_za_impl, svreadz_za_tile_impl): New type aliases.
(zero_slices_mode): New function.
(svzero_za_impl::expand): Handle the slice forms.
(svreadz_za, svreadz_hor_za, svreadz_ver_za): New functions.
* config/aarch64/aarch64-sve-builtins-sme.def: Add the SME2p1
instructions.
This patch adds support for the SME_F16F16 extension. The extension
adds two new instructions to convert from a single vector of f16s
to two vectors of f32s. It also adds f16 variants of existing SME
ZA instructions.
gcc/
* config/aarch64/aarch64-option-extensions.def
(sme-f16f16): New extension.
* doc/invoke.texi: Document it. Also document that sme-i16i64 and
sme-f64f64 enable SME.
* config/aarch64/aarch64.h (TARGET_STREAMING_SME_F16F16): New macro.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Conditionally define __ARM_FEATURE_SME_F16F16.
* config/aarch64/aarch64-sve-builtins-sve2.def (svcvt, svcvtl): Add
new SME_F16F16 intrinsics.
* config/aarch64/aarch64-sve-builtins-sme.def: Add SME_F16F16 forms
of existing intrinsics.
* config/aarch64/aarch64-sve-builtins.cc (TYPES_h_float)
(TYPES_cvt_f32_f16, TYPES_za_h_float): New type macros.
* config/aarch64/aarch64-sve-builtins-base.cc
(svcvt_impl::expand): Add sext_optab as another possibility.
* config/aarch64/aarch64-sve-builtins-sve2.h (svcvtl): Declare.
* config/aarch64/aarch64-sve-builtins-sve2.cc (svcvtl_impl): New class.
(svcvtl): New function.
* config/aarch64/iterators.md (VNx8SF_ONLY): New mode iterator.
(SME_ZA_SDFx24): Replace with...
(SME_ZA_HSDFx24): ...this.
(SME_MOP_SDF): Replace with...
(SME_MOP_HSDF): ...this.
(SME_BINARY_SLICE_SDF): Replace with...
(SME_BINARY_SLICE_HSDF): ...this.
* config/aarch64/aarch64-sve2.md (extendvnx8hfvnx8sf2)
(@aarch64_sve_cvtl<mode>): New patterns.
* config/aarch64/aarch64-sme.md
(@aarch64_sme_<SME_BINARY_SLICE_SDF:optab><mode>): Extend to...
(@aarch64_sme_<SME_BINARY_SLICE_HSDF:optab><mode>): ...this.
(*aarch64_sme_<SME_BINARY_SLICE_SDF:optab><mode>_plus): Extend to...
(*aarch64_sme_<SME_BINARY_SLICE_HSDF:optab><mode>_plus): ...this.
(@aarch64_sme_<SME_FP_TERNARY_SLICE:optab><mode><mode>): Extend to
HF modes.
(*aarch64_sme_<SME_FP_TERNARY_SLICE:optab><mode><mode>_plus)
(@aarch64_sme_single_<SME_FP_TERNARY_SLICE:optab><mode><mode>)
(*aarch64_sme_single_<SME_FP_TERNARY_SLICE:optab><mode><mode>_plus)
(@aarch64_sme_lane_<SME_FP_TERNARY_SLICE:optab><mode><mode>)
(*aarch64_sme_lane_<SME_FP_TERNARY_SLICE:optab><mode><mode>)
(@aarch64_sme_<SME_FP_MOP:optab><mode><mode>): Likewise.
gcc/testsuite/
* lib/target-supports.exp: Test the assembler for sve-f16f16 support.
* gcc.target/aarch64/pragma_cpp_predefs_4.c: Add tests for
__ARM_FEATURE_SME_F16F16. Also extend the existing SME tests.
* gcc.target/aarch64/sve/acle/asm/test_sve_acle.h
(TEST_X2_WIDE): New macro
* gcc.target/aarch64/sme2/acle-asm/add_za16_f16_vg1x2.c: New test.
* gcc.target/aarch64/sme2/acle-asm/add_za16_f16_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/cvt_f32_f16_x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/cvtl_f32_f16_x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_f16_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_f16_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mla_za16_f16_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mla_za16_f16_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mls_lane_za16_f16_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mls_lane_za16_f16_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mls_za16_f16_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mls_za16_f16_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mopa_za16_f16.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mops_za16_f16.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/sub_za16_f16_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/sub_za16_f16_vg1x4.c: Likewise.
This patch adds support for the SVE_B16B16 extension, which provides
non-widening BF16 versions of existing instructions.
Mostly it's just a simple extension of iterators. The main
complications are:
(1) The new instructions have no immediate forms. This is easy to
handle for the cond_* patterns (the ones that have an explicit
else value) since those are already divided into register and
non-register versions. All we need to do is tighten the predicates.
However, the @aarch64_pred_<optab><mode> patterns handle the
immediates directly. Rather than complicate them further,
it seemed best to add a single @aarch64_pred_<optab><mode> for
all BF16 arithmetic.
(2) There is no BFSUBR, so the usual method of handling reversed
operands breaks down. The patch deals with this using some
new attributes that together disable the "BFSUBR" alternative.
(3) Similarly, there are no BFMAD or BFMSB instructions, so we need
to disable those forms in the BFMLA and BFMLS patterns.
The patch includes support for generic bf16 vectors too.
It would be possible to use these instructions for scalars, as with
the recent FLOGB patch, but that's left as future work.
gcc/
* config/aarch64/aarch64-option-extensions.def
(sve-b16b16): New extension.
* doc/invoke.texi: Document it.
* config/aarch64/aarch64.h (TARGET_SME_B16B16, TARGET_SVE2_OR_SME2)
(TARGET_SSVE_B16B16): New macros.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Conditionally define __ARM_FEATURE_SVE_B16B16
* config/aarch64/aarch64-sve-builtins-sve2.def: Add AARCH64_FL_SVE2
to the SVE2p1 requirements. Add SVE_B16B16 forms of existing
intrinsics.
* config/aarch64/aarch64-sve-builtins.cc (type_suffixes): Treat
bfloat as a floating-point type.
(TYPES_h_bfloat): New macro.
* config/aarch64/aarch64.md (is_bf16, is_rev, supports_bf16_rev)
(mode_enabled): New attributes.
(enabled): Test mode_enabled.
* config/aarch64/iterators.md (SVE_FULL_F_BF): New mode iterator.
(SVE_CLAMP_F): Likewise.
(SVE_Fx24): Add BF16 modes when TARGET_SSVE_B16B16.
(sve_lane_con): Handle BF16 modes.
(b): Handle SF and DF modes.
(is_bf16): New mode attribute.
(supports_bf16, supports_bf16_rev): New int attributes.
* config/aarch64/predicates.md
(aarch64_sve_float_maxmin_immediate): Reject BF16 modes.
* config/aarch64/aarch64-sve.md
(*post_ra_<sve_fp_op><mode>3): Add BF16 support, and likewise
for the associated define_split.
(<optab:SVE_COND_FP_BINARY_OPTAB><mode>): Add BF16 support.
(@cond_<optab:SVE_COND_FP_BINARY><mode>): Likewise.
(*cond_<optab:SVE_COND_FP_BINARY><mode>_2_relaxed): Likewise.
(*cond_<optab:SVE_COND_FP_BINARY><mode>_2_strict): Likewise.
(*cond_<optab:SVE_COND_FP_BINARY><mode>_3_relaxed): Likewise.
(*cond_<optab:SVE_COND_FP_BINARY><mode>_3_strict): Likewise.
(*cond_<optab:SVE_COND_FP_BINARY><mode>_any_relaxed): Likewise.
(*cond_<optab:SVE_COND_FP_BINARY><mode>_any_strict): Likewise.
(@aarch64_mul_lane_<mode>): Likewise.
(<optab:SVE_COND_FP_TERNARY><mode>): Likewise.
(@aarch64_pred_<optab:SVE_COND_FP_TERNARY><mode>): Likewise.
(@cond_<optab:SVE_COND_FP_TERNARY><mode>): Likewise.
(*cond_<optab:SVE_COND_FP_TERNARY><mode>_4_relaxed): Likewise.
(*cond_<optab:SVE_COND_FP_TERNARY><mode>_4_strict): Likewise.
(*cond_<optab:SVE_COND_FP_TERNARY><mode>_any_relaxed): Likewise.
(*cond_<optab:SVE_COND_FP_TERNARY><mode>_any_strict): Likewise.
(@aarch64_<optab:SVE_FP_TERNARY_LANE>_lane_<mode>): Likewise.
* config/aarch64/aarch64-sve2.md
(@aarch64_pred_<optab:SVE_COND_FP_BINARY><mode>): Define BF16 version.
(@aarch64_sve_fclamp<mode>): Add BF16 support.
(*aarch64_sve_fclamp<mode>_x): Likewise.
(*aarch64_sve_<maxmin_uns_op><SVE_Fx24:mode>): Likewise.
(*aarch64_sve_single_<maxmin_uns_op><SVE_Fx24:mode>): Likewise.
* config/aarch64/aarch64.cc (aarch64_sve_float_arith_immediate_p)
(aarch64_sve_float_mul_immediate_p): Return false for BF16 modes.
This patch just renames the iterators SME_READ and SME_WRITE to
SME_READ_HV and SME_WRITE_HV, to distinguish them from other forms
of ZA read and write.
aarch64: Refactor SVE predicated-to-unpredicated splits
There are separate patterns for predicated FADD, FSUB, and FMUL.
Previously they each had their own in-built split to convert the
instruction to unpredicated form where appropriate. However, it's
more convenient for later patches if we use a single separate split
instead.
gcc/
* config/aarch64/iterators.md (SVE_COND_FP): New code attribute.
* config/aarch64/aarch64-sve.md: Use a single define_split to
handle the conversion of predicated FADD, FSUB, and FMUL into
unpredicated forms.
Many of the SME ZA intrinsics have two type suffixes: one for ZA
and one for the vectors. The ZA suffix only conveys an element
size, while the vector suffix conveys both an element type and
an element size. Internally, the ZA suffix maps to an integer mode;
e.g. za32 maps to VNx4SI.
For SME2, it was relatively convenient to use the modes associated
with both suffixes directly. For example, the (non-widening) FMLA
intrinsics used SME_ZA_SDF_I to iterate over the possible ZA modes,
used SME_ZA_SDFx24 to iterate over the possible vector tuple modes,
and used a C++ condition to make sure that the element sizes agree.
However, for later patches it's more convenient to rely only on
the vector mode in cases where the ZA and vector element sizes
are the same. This means splitting the widening MOPA/S patterns
from the non-widening ones, but otherwise it's not a big change.
gcc/
* config/aarch64/iterators.md (SME_ZA_SDF_I): Delete.
(SME_MOP_HSDF): Replace with...
(SME_MOP_SDF): ...this.
* config/aarch64/aarch64-sme.md: Change the non-widening FMLA and
FMLS patterns so that both mode parameters are the same, rather than
using both SME_ZA_SDF_I and SME_ZA_SDFx24 and checking that their
element sizes are the same. Split the FMOPA and FMOPS patterns
into separate non-widening and widening forms, then update the
non-widening forms in a similar way to FMLA and FMLS.
* config/aarch64/aarch64-sve-builtins-functions.h
(sme_2mode_function_t::expand): If the two type suffixes have the same
element size, use the vector tuple mode for both mode parameters.
Mikael Morin [Wed, 20 Nov 2024 12:59:51 +0000 (13:59 +0100)]
fortran: Evaluate once BACK argument of MINLOC/MAXLOC with DIM [PR90608]
Evaluate the BACK argument of MINLOC/MAXLOC once before the
scalarization loops in the case where the DIM argument is present.
This is a follow-up to r15-1994-ga55d24b3cf7f4d07492bb8e6fcee557175b47ea3
which added knowledge of BACK to the scalarizer, to r15-2701-ga10436a8404ad2f0cc5aa4d6a0cc850abe5ef49e which removed it to
handle it out of scalarization instead, and to more immediate previous
patches that added inlining support for MINLOC/MAXLOC with DIM. The
inlining support for MINLOC/MAXLOC with DIM introduced nested loops, which
made the evaluation of BACK (removed from the scalarizer knowledge by the
forementionned commit) wrapped in a loop, so possibly executed more than
once. This change adds BACK to the scalarization chain if MINLOC/MAXLOC
will use nested loops, so that it is evaluated by the scalarizer only once
before the outermost loop in that case.
PR fortran/90608
gcc/fortran/ChangeLog:
* trans-intrinsic.cc
(walk_inline_intrinsic_minmaxloc): Add a scalar element for BACK as
first item of the chain if BACK is present and there will be nested
loops.
(gfc_conv_intrinsic_minmaxloc): Evaluate BACK using an inherited
scalarization chain if there is a nested loop.
gcc/testsuite/ChangeLog:
* gfortran.dg/maxloc_8.f90: New test.
* gfortran.dg/minloc_9.f90: New test.
Uros Bizjak [Wed, 20 Nov 2024 11:57:25 +0000 (12:57 +0100)]
i386: Remove workaround for Solaris ld 64-bit TLS IE limitation
As detailed in PR target/43309, the Solaris linker initially took the
64-bit x86 TLS IE code sequence literally, assuming that the spec only
allowed %rax as target register.
A workaround has been in place for more than a decade, but is no longer
necessary. The bug had already been fixed for Solaris 11.1, while trunk
requires Solaris 11.4.
Uros pointed this out and suggested the attached patch.
Bootstrapped without regressions on i386-pc-solaris2.11.
Pan Li [Wed, 20 Nov 2024 07:16:22 +0000 (15:16 +0800)]
RISC-V: Refine the rtl dump expand check for vector SAT_ADD
This patch would like to remove the unnecessary option for the
vector SAT_ADD testcases at first. And the different optimization
option like O2 and O3 will be passed to the test files for rtl
expand dump check. If there are different dump check times for
different optimization options, the target no-opts and/or any-opts
will be leveraged for the dg-final check.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
Pan Li [Wed, 20 Nov 2024 05:32:47 +0000 (13:32 +0800)]
RISC-V: Introduce riscv/rvv/autovec/sat folder to rvv.exp testsuite
After we move vector SAT_ADD testcases into a isolated folder, aka
riscv/rvv/autovec/sat. We would like to add the folder as one of
the test items of the rvv.exp testsuite.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/rvv.exp: Add the vector sat folder to
the rvv.exp testsuite.
Pan Li [Wed, 20 Nov 2024 05:22:40 +0000 (13:22 +0800)]
RISC-V: Rearrange the test files for vector SAT_ADD [NFC]
The test files of scalar SAT_TRUNC only has numbers as the suffix.
Rearrange the file name to -{form number}-{target-type}. For example,
test form 3 for uint32_t SAT_TRUNC will have -3-u32.c for asm check and
-run-3-u32.c for the run test.
Meanwhile, all related test files moved to riscv/rvv/autovec/sat/.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
Richard Biener [Fri, 15 Nov 2024 10:56:14 +0000 (11:56 +0100)]
tree-optimization/117574 - bougs niter lt-to-ne
When trying to change a IV from IV0 < IV1 to IV0' != IV1' we apply
fancy adjustments to the may_be_zero condition we compute rather
than using the obvious IV0->base >= IV1->base expression (to be
able to use > instead of >=?). This doesn't seem to go well.
PR tree-optimization/117574
* tree-ssa-loop-niter.cc (number_of_iterations_lt_to_ne):
Use the obvious may_be_zero condition.
Expand can implement NEG and ABS of scalar floating-point modes
by using logic ops to manipulate the sign bit. This patch extends
that approach to vectors, since it fits relatively easily into the
same structure.
The motivating use case was to inline bf16 NEG and ABS operations
for AArch64. The patch includes tests for that.
get_absneg_bit_mode required a new opt_mode constructor, so that
opt_mode<T> can be constructed from opt_mode<U> if T is no less
general than U.
gcc/
* machmode.h (opt_mode::opt_mode): New overload.
* optabs-query.h (get_absneg_bit_mode): Declare.
* optabs-query.cc (get_absneg_bit_mode): New function, split
out from expand_absneg_bit.
(can_open_code_p): Use get_absneg_bit_mode.
* optabs.cc (expand_absneg_bit): Likewise. Take an outer and inner
mode, rather than just one. Handle vector modes.
(expand_unop, expand_abs_nojump): Update calls accordingly.
Handle vector modes.
This patch goes through the tree-vect-* code and mechanically replaces
all tests of optab_handler against CODE_FOR_nothing with calls to the
new helper functions.
Mikael Morin [Sat, 18 Nov 2023 19:54:20 +0000 (20:54 +0100)]
fortran: Check for empty MINLOC/MAXLOC ARRAY along DIM only
In the function generating inline code to implement MINLOC and MAXLOC, only
check for ARRAY size along DIM if DIM is present.
The check for ARRAY emptyness had been checking the size of the full array,
which is correct for MINLOC and MAXLOC without DIM. But if DIM is
present, the reduction is along DIM only so the check for emptyness
should consider that dimension only as well.
This sounds like a correctness issue, but fortunately the cases where it
makes a difference are cases where ARRAY is empty, so even if the value
calculated for MINLOC or MAXLOC is wrong, it's wrapped in a zero iteration
loop, and the wrong values are not actually used. In the end this just
avoids unnecessary calculations.
A previous version of this patch regressed on non-constant DIM with rank 1
ARRAY. The new testcase checks that that case is supported.
gcc/fortran/ChangeLog:
* trans-intrinsic.cc (gfc_conv_intrinsic_minmaxloc): Only get the size
along DIM instead of the full size if DIM is present.
MayShao-oc [Thu, 7 Nov 2024 02:57:02 +0000 (10:57 +0800)]
Add microarchtecture tunable for pass_align_tight_loops [PR117438]
Hi Hongtao:
Add m_CASCADELAK, and m_SKYLAKE_AVX512.
Place X86_TUNE_ALIGN_TIGHT_LOOPS in the appropriate section.
Bootstrapped X86_64.
Ok for trunk?
BR
Mayshao
gcc/ChangeLog:
PR target/117438
* config/i386/i386-features.cc (TARGET_ALIGN_TIGHT_LOOPS):
default true in all processors except for m_ZHAOXIN, m_CASCADELAKE, and
m_SKYLAKE_AVX512.
* config/i386/i386.h (TARGET_ALIGN_TIGHT_LOOPS): New Macro.
* config/i386/x86-tune.def (X86_TUNE_ALIGN_TIGHT_LOOPS):
New tune
testsuite: arm: Only check for absence of literal pools in no-literal-pool-m0.c
With the changes in r15-1579-g792f97b44ff, the constants have been
updated.
This patch drops the fragile check on the constants and instead only
checks that there is no literal pool generated.
gcc/testsuite/ChangeLog:
* gcc.target/arm/pure-code/no-literal-pool-m0.c: Only check for
absence of literal pools.
Jonathan Wakely [Tue, 19 Nov 2024 23:59:00 +0000 (23:59 +0000)]
libstdc++: Use const_iterator in std::set::find<K> return type
François noticed that the "wrong" type is used in the return type for a
std::set member function template.
The iterator for our std::set is the same type as const_iterator,
so this doesn't actually matter. But it's clearer if the return type
matches the type used in the function body.
libstdc++-v3/ChangeLog:
* include/bits/stl_set.h (set::find): Use const_iterator in
return type, not iterator.
The __is_key_type specialization that matches a pair<key_type, T>
argument is intended for std::unordered_map, not for
std::unordered_set<std::pair<K,T>>.
This uses a pair<const Args&...> as the template argument for
__is_key_type, so that it won't match a set's key_type.
libstdc++-v3/ChangeLog:
PR libstdc++/117686
* include/bits/hashtable.h (_Hashtable::_M_emplace_uniq):
Adjust usage of __is_key_type to avoid false positive.
* testsuite/23_containers/unordered_set/insert/117686.cc:
New test.
Pan Li [Tue, 19 Nov 2024 07:27:39 +0000 (15:27 +0800)]
RISC-V: Refine the rtl expand check for strided ld/st
This patch would like to remove the unnecessary option for the
strided load/store testcases. After fix the option from the rvv.exp,
both the O2 and O3 will be passed to the test files for rtl expand
dump check but the O2 has 2 time for IFN while the O3 has 4 times with
-fvectorize specificed.
Thus, add xfail O2 for IFN 4 times check, as well as xfail O3 for 2
times check.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
Pan Li [Tue, 19 Nov 2024 07:18:53 +0000 (15:18 +0800)]
RISC-V: Fix incorrect optimization options passing to strided ld/st test
The testcases of vector strided load/store are designed to pick up
different sorts of optimization options but actually these option
are ignored according to the Execution log of gcc.log. This patch
would like to make it correct, and then you will see the build option
similar as below from the gcc.log.
Jeff Law [Wed, 20 Nov 2024 02:24:41 +0000 (19:24 -0700)]
[RISC-V][PR target/117649] Fix branch on masked values splitter
Andreas reported GCC mis-compiled GAS for risc-v Thankfully he also reduced it
to a nice little testcase.
So the whole point of the pattern in question is to "reduce" the constants by
right shifting away common unnecessary bits in RTL expressions like this:
When applicable, the reduced constants in operands 2/3 fit into a simm12 and
thus do not need multi-instruction synthesis. Note that we have to also shift
operand 1.
That shift should have been an arithmetic shift, but was incorrectly coded as a
logical shift.
Fixed with the obvious change on the right shift opcode.
Expecting to push to the trunk once the pre-commit tester renders its verdict.
I've already tested in this my tester for rv32 and rv64.
PR target/117649
gcc/
* config/riscv/riscv.md (branch on masked/shifted operands): Use
arithmetic rather than logical shift for operand 1.
gcc/testsuite
* gcc.target/riscv/branch-1.c: Update expected output.
* gcc.target/riscv/pr117649.c: New test.
Joseph Myers [Wed, 20 Nov 2024 01:37:30 +0000 (01:37 +0000)]
c: Fix ICE for integer constexpr initializers of wrong type [PR115515]
Bug 115515 (plus its duplicate 117139) reports an ICE with constexpr
initializer for an integer type variable that is not of integer type.
Fix this by not calling int_fits_type_p unless the previous check for
an integer constant expression passes.
Bootstrapped with no regressions for x86_64-pc-linux-gnu.
PR c/115515
gcc/c/
* c-typeck.cc (check_constexpr_init): Do not call int_fits_type_p
for arguments that are not integer constant expressions.
gcc/testsuite/
* gcc.dg/c23-constexpr-10.c, gcc.dg/gnu23-constexpr-2.c: New
tests.
Pan Li [Sun, 17 Nov 2024 11:21:26 +0000 (19:21 +0800)]
RISC-V: Remove unnecessary option for all other scalar SAT_* testcase
After we create a isolated folder to hold all SAT scalar test,
we have fully control of what optimization options passing to
the testcase. Thus, it is better to remove the unnecessary
work around for flto option, as well as the -O3 option for
each cases. The riscv.exp will pass sorts of different optimization
options for each case.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
Mikael Morin [Thu, 8 Aug 2024 10:23:16 +0000 (12:23 +0200)]
fortran: Inline non-character MINLOC/MAXLOC with DIM [PR90608]
Enable generation of inline MINLOC/MAXLOC code in the cases where DIM is a
constant, and either ARRAY is of REAL type or MASK is an array. Those cases
are the remaining bits to fully support inlining of non-CHARACTER
MINLOC/MAXLOC with constant DIM. They are treated together because they
generate similar code, the NANs for REAL types being handled a bit like a
second level of masking. These are the cases for which we generate two
loops.
This change affects the code generating the second loop, that was
previously accessible only in cases ARRAY had rank 1.
The main changes are in gfc_conv_intrinsic_minmaxloc the replacement of the
locally initialized scalarization loop with the one provided and previously
initialized by the scalarizer. Same goes for the locally initialized MASK
scalarizer chain.
As this is enabling the code generating a second loop in a context of
reduction and nested loops, care is taken not to advance the parent
scalarization chain twice.
The scalarization chain element(s) for an array MASK are inserted in the
chain at a different place from that of a scalar MASK. This is done on
purpose to match the code consuming the chains which are in different places
for scalar and array MASK.
PR fortran/90608
gcc/fortran/ChangeLog:
* trans-intrinsic.cc (gfc_inline_intrinsic_function_p): Return TRUE
for MINLOC/MAXLOC with constant DIM and either REAL ARRAY or
non-scalar MASK.
(walk_inline_intrinsic_minmaxloc): Walk MASK and if it's an array
add the chain obtained before that of ARRAY.
(gfc_conv_intrinsic_minmaxloc): Use the nested loop if there is one.
To evaluate MASK (respectively ARRAY in the second loop), inherit
the scalarizer chain if in a nested loop, otherwise keep using the
chain obtained by walking MASK (respectively ARRAY). If there is a
nested loop, avoid advancing the parent scalarization chain a second
time in the second loop.
Joseph Myers [Tue, 19 Nov 2024 21:31:24 +0000 (21:31 +0000)]
c: Do not register nullptr_t built-in type [PR114869]
As reported in bug 114869, the C front end wrongly creates nullptr_t
as a built-in typedef; it should only be defined in <stddef.h>. While
the type node needs a name for debug info generation, it doesn't need
to be a valid identifier; use typeof (nullptr) instead, similar to how
the C++ front end uses decltype(nullptr) for this purpose.
Bootstrapped with no regressions for x86_64-pc-linux-gnu.
PR c/114869
gcc/c/
* c-decl.cc (c_init_decl_processing): Register nullptr_type_node
as typeof (nullptr) not nullptr_t.
gcc/testsuite/
* gcc.dg/c23-nullptr-5.c: Use typeof (nullptr) not nullptr_t.
* gcc.dg/c11-nullptr-2.c, gcc.dg/c11-nullptr-3.c,
gcc.dg/c23-nullptr-7.c: New tests
Georg-Johann Lay [Tue, 19 Nov 2024 17:18:20 +0000 (18:18 +0100)]
AVR: target/54378 - Reconsider the default shift costs.
This patch calculates more accurate shift costs, but makes
the costs for larger offsets no more expensive than the costs
for an unrolled shift.
gcc/
PR target/54378
* config/avr/avr.cc (avr_default_shift_costs): New static function.
(avr_rtx_costs_1) [ASHIFT, LSHIFTRT, ASHIFTRT]: Use it
to determine the default shift costs for shifts with a
constant shift offset.
Mikael Morin [Tue, 19 Nov 2024 20:17:37 +0000 (21:17 +0100)]
fortran: Check MASK directly instead of its scalarization chain
Update the conditions used by the inline MINLOC/MAXLOC code generation
function to check directly the properties of MASK instead of the
variable holding its scalarization chain.
The inline implementation of MINLOC/MAXLOC in gfc_conv_intrinsic_minmaxloc
uses several conditions checking the presence of a scalarization chain for
MASK, which means that the argument is present and non-scalar. The next
patch will allow inlining MINLOC/MAXLOC with DIM and MASK, and in that
case the scalarization chain for MASK is initialized elsewhere, so the
variable usually holding it in the function is not used, and the conditions
won't work in that case.
This change updates the conditions to check directly the properties of
MASK so that they work even if the scalarization chain variable is not used.
gcc/fortran/ChangeLog:
* trans-intrinsic.cc (gfc_conv_intrinsic_minmaxloc): Use
conditionals based on the MASK expression rather than on its
scalarization chains.
Jakub Jelinek [Tue, 19 Nov 2024 19:36:00 +0000 (20:36 +0100)]
c-family: Fix ICE with __sync_*_and_* on _BitInt [PR117641]
Only __atomic_* builtins are meant to work on arbitrary _BitInt types
(if not supported in hw we emit a CAS loop which uses __atomic_load_*
in that case), the compatibility __sync_* builtins work only if there
is a corresponding normal integral type (for _BitInt on 32-bit ARM
we'll need to limit even that to no padding, because the padding bits
are well defined there and the hw or libatomic __sync_* APIs don't
guarantee that), IMHO people shouldn't mix very old APIs with very
new ones and I don't see a replacement for the __atomic_load_*.
For size > 16 that is how it already correctly behaves,
in the hunk shown in the patch it is immediately followed by
which returns -1 for the __atomic_* builtins (i.e. !orig_format),
which causes caller to use atomic_bitint_fetch_using_cas_loop,
and otherwise does diagnostic and return 0 (which causes caller
to punt). But for size == 16 if TImode isn't suipported (i.e.
mostly 32-bit arches), we return (correctly) -1 if !orig_format,
so again force atomic_bitint_fetch_using_cas_loop on those arches
for e.g. _BitInt(115), but for orig_format the function returns
16 as if it could do 16 byte __sync_*_and_* (which it can't
because TImode isn't supported; for 16 byte it can only do
(perhaps using libatomic) normal compare and swap). So we need
to error and return 0, rather than return 16.
The following patch ensures that.
2024-11-19 Jakub Jelinek <jakub@redhat.com>
PR c/117641
* c-common.cc (sync_resolve_size): For size == 16 fetch of
BITINT_TYPE if TImode isn't supported scalar mode diagnose
and return 0 if orig_format instead of returning 16.
Jakub Jelinek [Tue, 19 Nov 2024 19:34:36 +0000 (20:34 +0100)]
c: Fix up __builtin_stdc_rotate_{left,right} lowering [PR117456]
Apparently the middle-end/expansion can only handle {L,R}ROTATE_EXPR
on types with mode precision, or large/huge BITINT_TYPE.
So, the following patch uses the rotate exprs only in those cases
where it can be handled, and emits code with shifts/ior otherwise.
As types without mode precision including small/medium BITINT_TYPE
have unlikely power of two precision and TRUNC_MOD_EXPR is on many targets
quite expensive, I chose to expand e.g. __builtin_stdc_rotate_left (arg1,
arg2) as
((tem = arg1, count = arg2 % prec)
? ((tem << count) | (tem >> (prec - count))) : tem)
rather than
(((tem = arg1) << (count = arg2 % prec))
| (tem >> (-count % prec))
(where the assignments are really save_exprs, so no UB), because
I think another TRUNC_MOD_EXPR would be more costly in most cases
when the shift count is non-constant (and when it is constant,
it folds to 2 shifts by constant and ior in either case).
2024-11-19 Jakub Jelinek <jakub@redhat.com>
PR c/117456
gcc/c/
* c-parser.cc (c_parser_postfix_expression): Use LROTATE_EXPR
or RROTATE_EXPR only if type_has_mode_precision_p or if arg1
has BITINT_TYPE with precision larger than MAX_FIXED_MODE_SIZE.
Otherwise build BIT_IOR_EXPR of LSHIFT_EXPR and RSHIFT_EXPR
and wrap it into a COND_EXPR depending on if arg2 is 0 or not.
* c-fold.cc (c_fully_fold_internal): Check for suppression of
-Wshift-count-overflow warning.
gcc/testsuite/
* gcc.dg/builtin-stdc-rotate-4.c: New test.
Martin Uecker [Fri, 8 Nov 2024 17:46:10 +0000 (18:46 +0100)]
c: fix incorrect TBAA for tagged types across translation units [PR117490]
Two different declarations of tagged types in the same translation unit
are incompatible in C before C23 and without tag also in C23. Still,
two such types can be compatible to the same tagged type in a different
translation unit, but this means that pointers can alias.
typedef struct { int i; } s1;
typedef struct { int i; } s2;
int f(s1 *p1, s2 *p2)
{
p1->i = 2;
p2->i = 3; // p2->i can alias p1->i
return p1->i;
}
We need to assign the same TYPE_CANONICAL to both types. This patch fixes
this for C23 and types without tag by also forming equivalence classes for
such types based on their structure as already done for types with tag.
Because this change exposes checking errors related to flexible array
members (cf. PR113688), one test is restricted to C17 for now.
PR c/117490
gcc/c/ChangeLog:
* c-typeck.cc (tagged_types_tu_compatible): Form equivalence
classed for tagless types in C23.
gcc/testsuite/ChangeLog:
* gcc.dg/gnu23-tag-alias-4.c: Adapt test.
* gcc.dg/gnu23-tag-alias-7.c: Adapt test.
* gcc.dg/guality/zero-length-array.c: Restrict to c17.
* gcc.dg/pr117490.c: New test.
Edwin Lu [Mon, 18 Nov 2024 22:36:17 +0000 (14:36 -0800)]
RISC-V: testsuite: fix old-style function definition error [NFC]
The following testcase was failing with the warning: old-style function
definition ever since the c standard version has been updated. Update
the function definition.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul-ice-3.c: Update
function definition.
Georg-Johann Lay [Mon, 18 Nov 2024 16:35:33 +0000 (17:35 +0100)]
AVR: Overhaul shift insns.
This patch adds 3-operand alternatives to the shift insns for
offsets that are one less than the bit-size of the mode.
For example, ashrhi3 can support "r,r,C15" without overhead.
Apart from that, the asm out functions for the shifts now use
avr_asm_len to print assembly and to track the isnsns' lengths.
gcc/
* config/avr/avr.md (ashlhi3, *ashlhi3_const_split, *ashlhi3_const)
(*ashlpsi3_split, *ashlpsi3)
(ashlsi3, *ashlsi3_const_split, *ashlsi3_const)
(ashrhi3, *ashrhi3, ashrpsi3, *ashrpsi3, ashrsi3, *ashrsi3)
(*ashrhi3_const_split, *ashrhi3_const, *ashrsi3_const_split, *ashrsi3_const):
Add constraint alternatives that allow a 3-operand operation when the
shift offset is one less than the mode's bitsize.
* config/avr/avr.cc (ashl<mode>3_out, ashr<mode>3_out)
(lshr<mode>3_out): Use avr_asm_len for asm_out and length tracking.
(ashrhi3_out, ashlhi3_out): Support the new "r,r,C15" alternatives.
(ashrsi3_out, ashlsi3_out): Support the new "r,r,C31" alternatives.
(avr_out_ashrpsi3, avr_out_ashlpsi3): Support the new "r,r,C23" alternatives.
gcc/testsuite/
* gcc.target/avr/torture/test-shift.h: New file.
* gcc.target/avr/torture/shift-l-u32.c: New test.
* gcc.target/avr/torture/shift-r-u32.c: New test.
* gcc.target/avr/torture/shift-r-i32.c: New test.
* gcc.target/avr/torture/shift-l-u24.c: New test.
* gcc.target/avr/torture/shift-r-u24.c: New test.
* gcc.target/avr/torture/shift-r-i24.c: New test.
* gcc.target/avr/torture/shift-l-u16.c: New test.
* gcc.target/avr/torture/shift-r-u16.c: New test.
* gcc.target/avr/torture/shift-r-i16.c: New test.
* gcc.target/avr/torture/shift-l-u8.c: New test.
* gcc.target/avr/torture/shift-r-u8.c: New test.
* gcc.target/avr/torture/shift-r-i8.c: New test.
Georg-Johann Lay [Tue, 19 Nov 2024 13:19:53 +0000 (14:19 +0100)]
AVR: Use more bool.
Now that the C default is C23, we can use bool in avr.h
(which is still used in libgcc via tm.h).
bool is a keyword in C23, so no stdbool.h is required in libgcc.
gcc/
* config/avr/avr.h (avr_args.has_stack_args): Be a bool.
(struct machine_function) <is_naked, is_noblock, is_OS_task,
is_OS_task, sibcall_fails, attributes_checked_p, is_no_gccisr,
use_L__stack_usage, gasisr.yes, gasisr.maybe>: Same.
* config/avr/avr-protos.h (reg_unused_after)
(test_hard_reg_class, jump_over_one_insn_p): Use bool as
return type.
* config/avr/avr.cc (reg_unused_after)
(test_hard_reg_class, jump_over_one_insn_p): Same.
(cfun->machine->attributes_checked_p, cum->has_stack_args)
(cfun->machine->use_L__stack_usage, cfun->machine->gasisr.yes)
(cfun->machine->sibcall_fails): Use like a bool.
When configuring GCC for RV32EC with:
./configure \
--target=riscv32-none-elf \
--with-multilib-generator="rv32ec-ilp32e--" \
--with-abi=ilp32e \
--with-arch=rv32ec
Then the build fails because division is erroneously left enabled:
cc1: error: '-mdiv' requires '-march' to subsume the 'M' extension
-fself-test: 8412281 pass(es) in 0.647173 seconds
Fix by disabling MASK_DIV if multiplication is not available and -mdiv
option has not been explicitly passed.
Tested the above RV32EC-only toolchain using the GNU simulator:
=== gcc Summary ===
# of expected passes 211635
# of unexpected failures 3004
# of expected failures 1061
# of unresolved testcases 5651
# of unsupported tests 18958
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_override_options_internal):
Set division option's default to disabled if multiplication
is not available.
This has been failing since r5-2883-g8cb65b3725f0c3 which caused the
memset to be optimized out. Add an unoptimizable reference to the local
variable to keep it.
* gcc.target/m68k/20100512-1.c (doTest1, doTest2): Add asm that
references foo.
Mikael Morin [Tue, 19 Nov 2024 16:31:25 +0000 (17:31 +0100)]
fortran: Inline MINLOC/MAXLOC with DIM and scalar MASK [PR90608]
Enable the generation of inline code for MINLOC/MAXLOC when argument
ARRAY is of integral type and has rank > 1, DIM is a constant, and MASK is
scalar (only absent MASK or rank 1 ARRAY were inlined before).
Scalar masks are implemented with a wrapping condition around the code
one would generate if MASK wasn't present, so they are easy to support
once inline code without MASK is working.
With this change, there are both expressions evaluated inside the nested
loop (ARRAY, and in the future MASK if non-scalar) and expressions evaluated
outside of it (MASK if scalar). For both one has to advance the
scalarization chain passed as argument SE to gfc_conv_intrinsic_minmaxloc as
they are evaluated, but for expressions evaluated from within the nested
loop one has to advance additionally the nested scalarization chain of the
reduction loop. This is normally handled transparently through the
inheritance that is defined when initializing gfc_se structs, but there has
to be some variable to inherit from, and there is a single one, SE. This
variable is kept as base for out of nested loop expressions only (i.e. for
scalar MASK), and this change introduces a new variable to hold the current
advance of the nested loop scalarization chain and serve as inheritance base
to evaluate nested loop expressions (just ARRAY for now, additionally
non-scalar MASK later).
PR fortran/90608
gcc/fortran/ChangeLog:
* trans-intrinsic.cc (gfc_inline_intrinsic_function_p): Return TRUE
if MASK is scalar.
(walk_inline_intrinsic_minmaxloc): Append to the scalarization chain
a scalar element for MASK if it's present.
(gfc_conv_intrinsic_minmaxloc): Use a local gfc_se struct to serve
as base for all the expressions evaluated in the nested loop. To
evaluate MASK when there is a nested loop, enable usage of the
scalarizer and set the original passed in SE argument as current
scalarization chain element to use. And use the nested loop from
the scalarizer instead of the local loop in that case.
gcc/testsuite/ChangeLog:
* gfortran.dg/maxloc_bounds_8.f90: Accept the error message
generated by the scalarizer in case the MAXLOC intrinsic call is
implemented through inline code.
* gfortran.dg/minmaxloc_20.f90: New test.
Jason Merrill [Mon, 18 Nov 2024 14:00:32 +0000 (15:00 +0100)]
c++: reduce redundant deprecated warnings
If a template uses a deprecated function, we should warn there and not also
whenever the template is instantiated. I implement this by suppressing
the warning at the location; then to make this also work with modules, I
need to make sure to set TREE_NO_WARNING so that the warning spec for this
location gets recorded.
And then I noticed that has_warning_spec was broken such that if it
returned true than get_nowarn_spec would always return null.
gcc/cp/ChangeLog:
* decl2.cc (cp_handle_deprecated_or_unavailable): Avoid redundant
warning.
* call.cc (build_over_call): Set TREE_NO_WARNING for calls
to deprecated functions.
* semantics.cc (finish_call_expr): Propagate TREE_NO_WARNING.
gcc/ChangeLog:
* warning-control.cc (has_warning_spec): Fix handling of
get_no_warning_bit.
gcc/testsuite/ChangeLog:
* g++.dg/warn/deprecated-21.C: New test.
* g++.dg/modules/warn-spec-2_a.C: New test.
* g++.dg/modules/warn-spec-2_b.C: New test.
Georg-Johann Lay [Tue, 19 Nov 2024 13:53:10 +0000 (14:53 +0100)]
AVR: ad target/84211 - Fix a build failure on some hosts.
This fixes a build failure on hosts where HARD_REG_SET is not a scalar.
The issue was introduced with the patch for PR84211 in r15-5415.
PR target/84211
gcc/
* config/avr/avr-passes.cc (memento_t::apply_insn1): Don't
use operator &= on memento_t.known but on memento_t itself.
Evgeny Karpov [Wed, 14 Aug 2024 14:43:41 +0000 (16:43 +0200)]
aarch64: Multiple adjustments to support the SMALL code model correctly
LOCAL_LABEL_PREFIX has been changed to help the assembly
compiler recognize local labels. Emitting locals has been
replaced with the .lcomm directive to declare uninitialized
data without defining an exact section. Functions and objects
were missing declarations. Binutils was not able to distinguish
static from external, or an object from a function.
mingw_pe_declare_object_type has been added to have type
information for relocation on AArch64, which is not the case
for ix86.
This fix relies on changes in binutils.
aarch64: Relocation fixes and LTO
https://sourceware.org/pipermail/binutils/2024-August/136481.html
gcc/ChangeLog:
* config/aarch64/aarch64-coff.h (LOCAL_LABEL_PREFIX):
Use "." as the local label prefix.
(ASM_OUTPUT_ALIGNED_LOCAL): Remove.
(ASM_OUTPUT_LOCAL): New.
* config/aarch64/cygming.h (ASM_OUTPUT_EXTERNAL_LIBCALL):
Update.
(ASM_DECLARE_OBJECT_NAME): New.
(ASM_DECLARE_FUNCTION_NAME): New.
* config/i386/cygming.h (ASM_DECLARE_COLD_FUNCTION_NAME):
Update.
(ASM_OUTPUT_EXTERNAL_LIBCALL): Update.
* config/mingw/winnt.cc (mingw_pe_declare_function_type):
Rename into ...
(mingw_pe_declare_type): ... this.
(i386_pe_start_function): Update.
* config/mingw/winnt.h (mingw_pe_declare_function_type):
Rename into ...
(mingw_pe_declare_type): ... this.
Evgeny Karpov [Wed, 14 Aug 2024 06:34:30 +0000 (08:34 +0200)]
aarch64: Add minimal C++ support
The patch resolves compilation issues for the C++ language. Previous
patch series contributed to C++ as well, however, C++ could not be
tested until we got a C++ compiler and could build at least a "Hello
World" C++ program, and in reality, more than that.
Another issue has been fixed in the libstdc++ patch.
https://gcc.gnu.org/pipermail/libstdc++/2024-September/059472.html
Evgeny Karpov [Fri, 7 Jun 2024 14:55:23 +0000 (16:55 +0200)]
aarch64: Add debugging information
This patch enables DWARF and allows compilation with debugging
information by using "gcc -g". The unwind info is disabled for
the moment and will be revisited after SEH implementation for
the target.
Evgeny Karpov [Wed, 14 Aug 2024 15:56:38 +0000 (17:56 +0200)]
Support weak references
The patch adds support for weak references. The original MinGW
implementation targets ix86, which handles weak symbols differently
compared to AArch64. In AArch64, the weak symbols are replaced by
other symbols which reference the original weak symbols, and the
compiler does not track the original symbol names.
This patch resolves this and declares the original symbols.
Here is an explanation of why this change is needed and what the
difference is between x86_64-w64-mingw32 and aarch64-w64-mingw32.
The way x86_64 calls a weak function:
call weak_fn2
GCC emits the call and creates the required definitions at the end
of the assembly:
projects / thirdparty / gcc.git / log
