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2 months agoMerge tag 'riscv-cache-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel...
Arnd Bergmann [Wed, 21 May 2025 21:14:37 +0000 (23:14 +0200)] 
Merge tag 'riscv-cache-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers

RISC-V cache drivers for v6.16

SiFive:
Add support for the Eswin EIC7700 SoC, which needs to make sure of the
non-standard cache-ops provided by the ccache driver.

Bindings:
Conversions for two Marvell bindings to yaml, and additions of two
soc-specific compatibles to the axm45mp bindings.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-cache-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  dt-bindings: cache: add QiLai compatible to ax45mp
  dt-bindings: cache: Convert marvell,tauros2-cache to DT schema
  dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema
  dt-bindings: cache: add specific RZ/Five compatible to ax45mp
  cache: sifive_ccache: Add ESWIN EIC7700 support
  dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility

Link: https://lore.kernel.org/r/20250516-liability-facility-667fc14a2a85@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 months agoMerge tag 'memory-controller-drv-6.16-2' of https://git.kernel.org/pub/scm/linux...
Arnd Bergmann [Wed, 21 May 2025 21:13:49 +0000 (23:13 +0200)] 
Merge tag 'memory-controller-drv-6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers

Memory controller drivers for v6.16, part two

Few fixes for STM32 Octo Memory Manager driver introduced for the same
cycle in few commits before.  These fixes were reported only after wider
coverage by bots through linux-next exposure.

* tag 'memory-controller-drv-6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: stm32_omm: Fix error handling in stm32_omm_disable_child()
  memory: stm32_omm: Fix NULL vs IS_ERR() check in probe()
  memory: stm32_omm: Fix error handling in stm32_omm_configure()
  memory: stm32: Fix spelling mistake "resset" -> "reset"

Link: https://lore.kernel.org/r/20250516082415.7871-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 months agoMerge tag 'samsung-drivers-6.16-2' of https://git.kernel.org/pub/scm/linux/kernel...
Arnd Bergmann [Wed, 21 May 2025 21:12:35 +0000 (23:12 +0200)] 
Merge tag 'samsung-drivers-6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers

Samsung SoC drivers for v6.16, part two

Add CPU hotplug support on Google GS101 by toggling respective bits in
secondary PMU intr block (Power Management Unit (PMU) Interrupt
Generation) from the main PMU driver.

* tag 'samsung-drivers-6.16-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  soc: samsung: exynos-pmu: enable CPU hotplug support for gs101
  MAINTAINERS: Add google,gs101-pmu-intr-gen.yaml binding file
  dt-bindings: soc: samsung: exynos-pmu: gs101: add google,pmu-intr-gen phandle
  dt-bindings: soc: google: Add gs101-pmu-intr-gen binding documentation

Link: https://lore.kernel.org/r/20250516082037.7248-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 months agosoc: aspeed: Add NULL check in aspeed_lpc_enable_snoop()
Henry Martin [Thu, 15 May 2025 06:30:44 +0000 (16:00 +0930)] 
soc: aspeed: Add NULL check in aspeed_lpc_enable_snoop()

devm_kasprintf() returns NULL when memory allocation fails. Currently,
aspeed_lpc_enable_snoop() does not check for this case, which results in a
NULL pointer dereference.

Add NULL check after devm_kasprintf() to prevent this issue.

Fixes: 3772e5da4454 ("drivers/misc: Aspeed LPC snoop output using misc chardev")
Signed-off-by: Henry Martin <bsdhenrymartin@gmail.com>
Link: https://patch.msgid.link/20250401074647.21300-1-bsdhenrymartin@gmail.com
[arj: Fix Fixes: tag to use subject from 3772e5da4454]
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 months agosoc: aspeed: lpc: Fix impossible judgment condition
Su Hui [Thu, 15 May 2025 06:30:43 +0000 (16:00 +0930)] 
soc: aspeed: lpc: Fix impossible judgment condition

smatch error:
drivers/soc/aspeed/aspeed-lpc-snoop.c:169
aspeed_lpc_snoop_config_irq() warn: platform_get_irq() does not return zero

platform_get_irq() return non-zero IRQ number or negative error code,
change '!lpc_snoop->irq' to 'lpc_snoop->irq < 0' to fix this.

Fixes: 9f4f9ae81d0a ("drivers/misc: add Aspeed LPC snoop driver")
Signed-off-by: Su Hui <suhui@nfschina.com>
Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://lore.kernel.org/r/20231027020703.1231875-1-suhui@nfschina.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 months agoARM: aspeed: Don't select SRAM
Joel Stanley [Thu, 15 May 2025 06:30:42 +0000 (16:00 +0930)] 
ARM: aspeed: Don't select SRAM

The ASPEED devices have SRAM, but don't require it for basic function
(or any function; there's no known users of the driver).

Fixes: 8c2ed9bcfbeb ("arm: Add Aspeed machine")
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patch.msgid.link/20250115103942.421429-1-joel@jms.id.au
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 months agoMerge tag 'riscv-sophgo-soc-for-v6.16' of https://github.com/sophgo/linux into soc...
Arnd Bergmann [Wed, 21 May 2025 17:25:07 +0000 (19:25 +0200)] 
Merge tag 'riscv-sophgo-soc-for-v6.16' of https://github.com/sophgo/linux into soc/drivers

RISC-V SoC for v6.16

Sophgo:

Add support for SG2044 TOP syscon device. The SG2044 TOP
device provide PLL clock function in its area.

Add RTC support for CV1800 series SoC. The device
is called RTC, but contains control registers of other
HW blocks in its address space, most notably of
Power-on-Reset (PoR) module, DW8051 IP (MCU core),
accompanying SRAM, hence putting it in SoC subsystem.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
* tag 'riscv-sophgo-soc-for-v6.16' of https://github.com/sophgo/linux:
  soc: sophgo: cv1800: rtcsys: New driver (handling RTC only)
  dt-bindings: soc: sophgo: add RTC support for Sophgo CV1800 series
  soc: sophgo: sg2044: Add support for SG2044 TOP syscon device

Link: https://lore.kernel.org/r/MA0P287MB2262B041A26A0F5EAD1E296CFE91A@MA0P287MB2262.INDP287.PROD.OUTLOOK.COM
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 months agoMerge tag 'qcom-drivers-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel...
Arnd Bergmann [Wed, 21 May 2025 17:23:43 +0000 (19:23 +0200)] 
Merge tag 'qcom-drivers-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers

Qualcomm driver updates for v6.16

Allow list QSEECOM for EFI variable services on on the Asus Zenbook A14,
and block list TZMEM on the SM7150 platform to avoid issues with rmtfs.

Extend the last-level cache (llcc) driver to support version 6 of the
hardware and enable SM8750 support.
Also add socinfo for the SM8750 platform.

Re-enable UCSI support on SC8280XP, now that the reported crash has been
dealt with, and filter the altmode notifications to avoid spurious
hotplug events being propagated to user space.

Add SM7150 support to pd-mapper.

* tag 'qcom-drivers-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  soc: qcom: llcc-qcom: Add support for SM8750
  soc: qcom: llcc-qcom: Add support for LLCC V6
  dt-bindings: cache: qcom,llcc: Document SM8750 LLCC block
  soc: qcom: socinfo: add SM8750 SoC ID
  dt-bindings: arm: qcom,ids: add SoC ID for SM8750
  dt-bindings: soc: qcom: qcom,rpm: add missing clock/-names properties
  dt-bindings: soc: qcom,rpm: add missing clock-controller node
  soc: qcom: smem: Update max processor count
  firmware: qcom: tzmem: disable sm7150 platform
  soc: qcom: pd-mapper: Add support for SM7150
  soc: qcom: pmic_glink_altmode: fix spurious DP hotplug events
  soc: qcom: smp2p: Fix fallback to qcom,ipc parse
  soc: qcom: pmic_glink: enable UCSI on sc8280xp
  firmware: qcom: scm: Allow QSEECOM on Asus Zenbook A14
  dt-bindings: soc: qcom,rpmh-rsc: Limit power-domains requirement

Link: https://lore.kernel.org/r/20250513215656.44448-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 months agoMerge tag 'soc-drivers-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk...
Arnd Bergmann [Wed, 21 May 2025 17:22:13 +0000 (19:22 +0200)] 
Merge tag 'soc-drivers-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/drivers

VT8500 (and FSL) SoC drivers for v6.16

1. VT8500: Add SCC socinfo/hwinfo driver.
2. Cleanup unused function in PowerPC Freescale QE driver to have W=1
   builds warnings free.

* tag 'soc-drivers-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt:
  soc: fsl: qe: remove unused qe_ic_from_irq function
  ARM: vt8500: MAINTAINERS: Include vt8500 soc driver in maintainers entry
  soc: Add VIA/WonderMedia SoC identification driver
  dt-bindings: hwinfo: Add VIA/WonderMedia SoC identification

Link: https://lore.kernel.org/r/20250513104216.25803-6-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 months agoMerge tag 'amlogic-driver-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel...
Arnd Bergmann [Wed, 21 May 2025 17:21:24 +0000 (19:21 +0200)] 
Merge tag 'amlogic-driver-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/drivers

Amlogic Driver for v6.16:
- Amlogic clk measure memory usage optimization
- Amlogic clk measure support for S4 & C3 Socs
- Amlogic A4/A5 reset controller bindings

* tag 'amlogic-driver-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
  dt-bindings: reset: Add compatible for Amlogic A4/A5 Reset Controller
  soc: amlogic: clk-measure: Add support for S4
  soc: amlogic: clk-measure: Add support for C3
  dt-bindings: soc: amlogic: S4 supports clk-measure
  dt-bindings: soc: amlogic: C3 supports clk-measure
  soc: amlogic: clk-measure: Define MSR_CLK's register offset separately
  soc: amlogic: clk-measure: Optimize the memory size of clk-measure

Link: https://lore.kernel.org/r/04908842-4c55-44a0-b74c-3aca82a1f204@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 months agoMerge tag 'ti-driver-soc-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel...
Arnd Bergmann [Wed, 21 May 2025 17:04:33 +0000 (19:04 +0200)] 
Merge tag 'ti-driver-soc-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/drivers

TI SoC driver updates for v6.16

- ti_sci: Bug fix in CPU latency conversion from us to ms for TISCI protocol
- k3-socinfo: Add JTAG ID for AM62LX
- Code cleanups: wkup_m3_ipc: Use dev_err_probe, k3-ringacc: use
  device_match_of_probe and knav_qmss_queue: drop unnecessary NULL check

* tag 'ti-driver-soc-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
  soc: ti: wkup_m3_ipc: Use dev_err_probe
  firmware: ti_sci: Convert CPU latency constraint from us to ms
  soc: ti: k3-socinfo: Add JTAG ID for AM62LX
  soc: ti: knav_qmss_queue: Remove unnecessary NULL check before free_percpu()
  soc: ti: k3-ringacc: Use device_match_of_node()

Link: https://lore.kernel.org/r/20250512144719.mpkyw2jbyzslb5hy@yearly
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 months agoMerge tag 'reset-for-v6.16' of git://git.pengutronix.de/pza/linux into soc/drivers
Arnd Bergmann [Wed, 21 May 2025 17:03:42 +0000 (19:03 +0200)] 
Merge tag 'reset-for-v6.16' of git://git.pengutronix.de/pza/linux into soc/drivers

Reset controller updates for v6.16

* Add T-HEAD TH1520 and Renesas RZ/V2H(P) USB2PHY reset controller
  drivers.
* Add devm_reset_control_array_get_exclusive_released() variant to allow
  using the acquire/release hand-off mechanism for exclusive reset
  controls bundled into reset control arrays.
* Add Sophgo SG2044 reset controller to device tree bindings.

* tag 'reset-for-v6.16' of git://git.pengutronix.de/pza/linux:
  dt-bindings: reset: sophgo: Add SG2044 bindings.
  MAINTAINERS: Add entry for Renesas RZ/V2H(P) USB2PHY Port Reset driver
  reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P)
  dt-bindings: reset: Document RZ/V2H(P) USB2PHY reset
  reset: Add devm_reset_control_array_get_exclusive_released()
  reset: thead: Add TH1520 reset controller driver
  dt-bindings: reset: Add T-HEAD TH1520 SoC Reset Controller

Link: https://lore.kernel.org/r/20250513092516.3331585-1-p.zabel@pengutronix.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 months agodt-bindings: cache: add QiLai compatible to ax45mp
Ben Zong-You Xie [Wed, 14 May 2025 09:53:47 +0000 (17:53 +0800)] 
dt-bindings: cache: add QiLai compatible to ax45mp

Add a new compatible string for ax45mp-cache on QiLai SoC.

Also, add allOf constraints to enforce specific cache-sets and cache-size
values for qilai-ax45mp-cache.

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
3 months agomemory: stm32_omm: Fix error handling in stm32_omm_disable_child()
Patrice Chotard [Tue, 13 May 2025 15:34:31 +0000 (17:34 +0200)] 
memory: stm32_omm: Fix error handling in stm32_omm_disable_child()

Fix stm32_omm_toggle_child_clock() return value test, we should exit
only on non zero value.

Fixes: 8181d061dcff ("memory: Add STM32 Octo Memory Manager driver")
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20250513-stm32_omm_fix_typo-v1-1-5b90ec8b52e7@foss.st.com
Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Closes: https://lore.kernel.org/all/aB29hOrv0nU73RCn@stanley.mountain/
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agodt-bindings: cache: Convert marvell,tauros2-cache to DT schema
Rob Herring (Arm) [Tue, 13 May 2025 01:53:01 +0000 (20:53 -0500)] 
dt-bindings: cache: Convert marvell,tauros2-cache to DT schema

Convert the Marvell Tauros2 Cache binding to DT schema.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
3 months agodt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema
Rob Herring (Arm) [Tue, 13 May 2025 01:52:51 +0000 (20:52 -0500)] 
dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema

Convert the Marvell Feroceon/Kirkwood Cache binding to DT schema format.

Use "marvell,kirkwood-cache" for the filename instead as that's only
compatible used in a .dts upstream.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
3 months agosoc: samsung: exynos-pmu: enable CPU hotplug support for gs101
Peter Griffin [Tue, 6 May 2025 20:57:31 +0000 (21:57 +0100)] 
soc: samsung: exynos-pmu: enable CPU hotplug support for gs101

Some additional register writes are required when hotplugging CPUs
on gs101, without these the system hangs when hotplugging.

Specifically a CPU_INFORM register needs to be programmed with
a hint value which is used by the EL3 firmware (el3mon) and the
pmu-intr-gen registers need to be programmed.

With this patch applied, and corresponding DT update CPU hotplug
now works as expected. e.g.

echo 0 > /sys/devices/system/cpu/cpu6/online
echo 1 > /sys/devices/system/cpu/cpu6/online

Note: to maintain compatibility with older DTs that didn't specify
pmu-intr-gen phandle only a warning is issued if the syscon can't
be obtained.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-5-9f64a2657316@linaro.org
[krzk: few blank line and white-space alignment fixes from checkpatch]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agoMAINTAINERS: Add google,gs101-pmu-intr-gen.yaml binding file
Peter Griffin [Tue, 6 May 2025 20:57:29 +0000 (21:57 +0100)] 
MAINTAINERS: Add google,gs101-pmu-intr-gen.yaml binding file

Add the newly added google,gs101-pmu-intr-gen.yaml file to the
Tensor section.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-3-9f64a2657316@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agodt-bindings: soc: samsung: exynos-pmu: gs101: add google,pmu-intr-gen phandle
Peter Griffin [Tue, 6 May 2025 20:57:28 +0000 (21:57 +0100)] 
dt-bindings: soc: samsung: exynos-pmu: gs101: add google,pmu-intr-gen phandle

gs101 requires access to the pmu interrupt generation register region
which is exposed as a syscon. Update the exynos-pmu bindings documentation
to reflect this.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-2-9f64a2657316@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agodt-bindings: soc: google: Add gs101-pmu-intr-gen binding documentation
Peter Griffin [Tue, 6 May 2025 20:57:27 +0000 (21:57 +0100)] 
dt-bindings: soc: google: Add gs101-pmu-intr-gen binding documentation

Add bindings documentation for the Power Management Unit (PMU) interrupt
generator.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250506-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v4-1-9f64a2657316@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agosoc: qcom: llcc-qcom: Add support for SM8750
Melody Olvera [Mon, 12 May 2025 20:54:43 +0000 (13:54 -0700)] 
soc: qcom: llcc-qcom: Add support for SM8750

Add system cache table and configs for SM8750 SoCs.

Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250512-sm8750_llcc_master-v5-3-d78dca6282a5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agosoc: qcom: llcc-qcom: Add support for LLCC V6
Melody Olvera [Mon, 12 May 2025 20:54:42 +0000 (13:54 -0700)] 
soc: qcom: llcc-qcom: Add support for LLCC V6

Add support for LLCC V6. V6 adds several additional usecase IDs,
rearrages several registers and offsets, and supports slice IDs
over 31, so add a new function for programming LLCC V6.

Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250512-sm8750_llcc_master-v5-2-d78dca6282a5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agodt-bindings: cache: qcom,llcc: Document SM8750 LLCC block
Melody Olvera [Mon, 12 May 2025 20:54:41 +0000 (13:54 -0700)] 
dt-bindings: cache: qcom,llcc: Document SM8750 LLCC block

Add documentation for the SM8750 LLCC.

Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250512-sm8750_llcc_master-v5-1-d78dca6282a5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agodt-bindings: cache: add specific RZ/Five compatible to ax45mp
Conor Dooley [Mon, 12 May 2025 13:48:14 +0000 (14:48 +0100)] 
dt-bindings: cache: add specific RZ/Five compatible to ax45mp

When the binding was originally written, it was assumed that all
ax45mp-caches had the same properties etc. This has turned out to be
incorrect, as the QiLai SoC has a different number of cache-sets.

Add a specific compatible for the RZ/Five for property enforcement and
in case there turns out to be additional differences between these
implementations of the cache controller.

Acked-by: Ben Zong-You Xie <ben717@andestech.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
3 months agoMerge tag 'imx-drivers-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/shawn...
Arnd Bergmann [Mon, 12 May 2025 12:16:15 +0000 (14:16 +0200)] 
Merge tag 'imx-drivers-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/drivers

i.MX drivers change for 6.16:

- A series from Peng Fan to dump full 128-bits UID for i.MX8MP

* tag 'imx-drivers-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  soc: imx8m: Dump higher 64bits UID
  soc: imx8m: Introduce soc_uid hook
  soc: imx8m: Cleanup with adding imx8m_soc_[un]prepare

Link: https://lore.kernel.org/r/20250512103858.50501-1-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 months agoMerge branch 'cznic/platform' of https://git.kernel.org/pub/scm/linux/kernel/git...
Arnd Bergmann [Mon, 12 May 2025 11:33:57 +0000 (13:33 +0200)] 
Merge branch 'cznic/platform' of https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc into soc/drivers

These are updates from Marek Behún for the cznic platform drivers:

  This series adds support for generating ECDSA signatures with hardware
  stored private key on Turris Omnia and Turris MOX.
  This ability is exposed via the keyctl() syscall.

* 'cznic/platform' of https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  platform: cznic: use ffs() instead of __bf_shf()
  firmware: turris-mox-rwtm: fix building without CONFIG_KEYS
  platform: cznic: fix function parameter names
  firmware: turris-mox-rwtm: Add support for ECDSA signatures with HW private key
  firmware: turris-mox-rwtm: Drop ECDSA signatures via debugfs
  platform: cznic: turris-omnia-mcu: Add support for digital message signing with HW private key
  platform: cznic: Add keyctl helpers for Turris platform
  platform: cznic: turris-omnia-mcu: Refactor requesting MCU interrupt

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 months agoMerge tag 'omap-for-v6.16/drivers-signed' of https://git.kernel.org/pub/scm/linux...
Arnd Bergmann [Mon, 12 May 2025 08:23:48 +0000 (10:23 +0200)] 
Merge tag 'omap-for-v6.16/drivers-signed' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/drivers

OMAP driver updates for v6.16

* tag 'omap-for-v6.16/drivers-signed' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap:
  Revert "bus: ti-sysc: Probe for l4_wkup and l4_cfg interconnect devices first"

Link: https://lore.kernel.org/r/7h5xi7rtix.fsf@baylibre.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 months agomemory: stm32_omm: Fix NULL vs IS_ERR() check in probe()
Dan Carpenter [Fri, 9 May 2025 11:04:37 +0000 (14:04 +0300)] 
memory: stm32_omm: Fix NULL vs IS_ERR() check in probe()

The platform_get_resource_byname() function returns NULL on error.  It
doesn't return error pointers.  Update the check to match.

Fixes: 8181d061dcff ("memory: Add STM32 Octo Memory Manager driver")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://lore.kernel.org/r/a1645f1eedaa9b2ae62ac07feed0552eea75bc46.1746781081.git.dan.carpenter@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agomemory: stm32_omm: Fix error handling in stm32_omm_configure()
Dan Carpenter [Fri, 9 May 2025 11:04:31 +0000 (14:04 +0300)] 
memory: stm32_omm: Fix error handling in stm32_omm_configure()

There are two error handling bugs in the stm32_omm_configure() function.
1) The error code needs to be set if clk_get_rate() fails.
2) If devm_reset_control_get_exclusive() then call
   pm_runtime_put_sync_suspend() before returning.

Fixes: 8181d061dcff ("memory: Add STM32 Octo Memory Manager driver")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://lore.kernel.org/r/a69ce0445324e994ea2ed7493bda1f6046c7ff69.1746781081.git.dan.carpenter@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agomemory: stm32: Fix spelling mistake "resset" -> "reset"
Colin Ian King [Fri, 9 May 2025 10:44:58 +0000 (11:44 +0100)] 
memory: stm32: Fix spelling mistake "resset" -> "reset"

There is a spelling mistake in a dev_err message. Fix it.

Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Link: https://lore.kernel.org/r/20250509104459.28167-1-colin.i.king@gmail.com
Fixes: 8181d061dcff ("memory: Add STM32 Octo Memory Manager driver")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agosoc: qcom: socinfo: add SM8750 SoC ID
Mukesh Ojha [Thu, 8 May 2025 13:46:34 +0000 (19:16 +0530)] 
soc: qcom: socinfo: add SM8750 SoC ID

Update soc_id table for the Qualcomm SM8750 SoC to represent
SM8750 machine.

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Reviewed-by: Melody Olvera <melody.olvera@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250508134635.1627031-1-mukesh.ojha@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agodt-bindings: arm: qcom,ids: add SoC ID for SM8750
Mukesh Ojha [Thu, 8 May 2025 13:46:35 +0000 (19:16 +0530)] 
dt-bindings: arm: qcom,ids: add SoC ID for SM8750

Add the unique ID for Qualcomm SM8750 SoC.
This value is used to differentiate the SoC across qcom targets.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Reviewed-by: Melody Olvera <melody.olvera@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250508134635.1627031-2-mukesh.ojha@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agoMerge tag 'tee-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/jenswi...
Arnd Bergmann [Sat, 10 May 2025 09:09:43 +0000 (11:09 +0200)] 
Merge tag 'tee-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee into soc/drivers

Small TEE updates for v6.16

- Remove an unnecessary NULL check before release_firmware() in the
  OP-TEE driver
- Prevent a size wrap in the TEE subsystem. The wrap would have been caught
  later in the code so no security consequences.

* tag 'tee-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee:
  tee: Prevent size calculation wraparound on 32-bit kernels
  tee: optee: smc: remove unnecessary NULL check before release_firmware()

Link: https://lore.kernel.org/r/20250509065114.GA4188600@rayden
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 months agodt-bindings: soc: qcom: qcom,rpm: add missing clock/-names properties
Dmitry Baryshkov [Tue, 18 Mar 2025 13:21:55 +0000 (15:21 +0200)] 
dt-bindings: soc: qcom: qcom,rpm: add missing clock/-names properties

Qualcomm MSM8660 and IPQ0864 platforms use additional clock for the RPM
device. Document it in the schema.

Fixes: aa0c4b815045 ("mfd: devicetree: bindings: Add Qualcomm RPM DT binding")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250318-fix-nexus-4-v2-2-bcedd1406790@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agodt-bindings: soc: qcom,rpm: add missing clock-controller node
Dmitry Baryshkov [Tue, 18 Mar 2025 13:21:54 +0000 (15:21 +0200)] 
dt-bindings: soc: qcom,rpm: add missing clock-controller node

On Qualcomm platforms in addition to regulators the RPM also provides
clocks via the child clock-controller node. Describe it properly in the
schema.

Fixes: 872f91b5ea72 ("clk: qcom: Add support for RPM Clocks")
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250318-fix-nexus-4-v2-1-bcedd1406790@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agosoc: qcom: smem: Update max processor count
Unnathi Chalicheemala [Thu, 24 Apr 2025 23:45:41 +0000 (16:45 -0700)] 
soc: qcom: smem: Update max processor count

Update max processor count to reflect the number of co-processors on
upcoming SoC.

Signed-off-by: Unnathi Chalicheemala <unnathi.chalicheemala@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250424-smem_count-v1-1-931cf68f71a8@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agofirmware: qcom: tzmem: disable sm7150 platform
Danila Tikhonov [Tue, 22 Apr 2025 21:31:33 +0000 (00:31 +0300)] 
firmware: qcom: tzmem: disable sm7150 platform

The SHM bridge makes the SM7150 devices reset while probing the RMTFS
(in qcom_scm_assign_mem()). Blacklist the SHM Bridge on corresponding
platforms using SoC-level compat string.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250422213137.80366-13-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agosoc: qcom: pd-mapper: Add support for SM7150
Jens Reidel [Tue, 22 Apr 2025 21:31:31 +0000 (00:31 +0300)] 
soc: qcom: pd-mapper: Add support for SM7150

SM7150 protection domains are the same as SC7180, with the subtle
difference that SM7150 has a CDSP.

Signed-off-by: Jens Reidel <adrian@mainlining.org>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250422213137.80366-11-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agosoc: qcom: pmic_glink_altmode: fix spurious DP hotplug events
Johan Hovold [Mon, 24 Mar 2025 13:24:48 +0000 (14:24 +0100)] 
soc: qcom: pmic_glink_altmode: fix spurious DP hotplug events

The PMIC GLINK driver is currently generating DisplayPort hotplug
notifications whenever something is connected to (or disconnected from)
a port regardless of the type of notification sent by the firmware.

These notifications are forwarded to user space by the DRM subsystem as
connector "change" uevents:

    KERNEL[1556.223776] change   /devices/platform/soc@0/ae00000.display-subsystem/ae01000.display-controller/drm/card0 (drm)
    ACTION=change
    DEVPATH=/devices/platform/soc@0/ae00000.display-subsystem/ae01000.display-controller/drm/card0
    SUBSYSTEM=drm
    HOTPLUG=1
    CONNECTOR=36
    DEVNAME=/dev/dri/card0
    DEVTYPE=drm_minor
    SEQNUM=4176
    MAJOR=226
    MINOR=0

On the Lenovo ThinkPad X13s and T14s, the PMIC GLINK firmware sends two
identical notifications with orientation information when connecting a
charger, each generating a bogus DRM hotplug event. On the X13s, two
such notification are also sent every 90 seconds while a charger remains
connected, which again are forwarded to user space:

    port = 1, svid = ff00, mode = 255, hpd_state = 0
    payload = 01 00 00 00 00 00 00 ff 00 00 00 00 00 00 00 00

Note that the firmware only sends on of these when connecting an
ethernet adapter.

Fix the spurious hotplug events by only forwarding hotplug notifications
for the Type-C DisplayPort service id. This also reduces the number of
uevents from four to two when an actual DisplayPort altmode device is
connected:

    port = 0, svid = ff01, mode = 2, hpd_state = 0
    payload = 00 01 02 00 f2 0c 01 ff 03 00 00 00 00 00 00 00
    port = 0, svid = ff01, mode = 2, hpd_state = 1
    payload = 00 01 02 00 f2 0c 01 ff 43 00 00 00 00 00 00 00

Fixes: 080b4e24852b ("soc: qcom: pmic_glink: Introduce altmode support")
Cc: stable@vger.kernel.org # 6.3
Cc: Bjorn Andersson <andersson@kernel.org>
Reported-by: Clayton Craft <clayton@craftyguy.net>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Clayton Craft <clayton@craftyguy.net>
Link: https://lore.kernel.org/r/20250324132448.6134-1-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agosoc: qcom: smp2p: Fix fallback to qcom,ipc parse
Barnabás Czémán [Mon, 21 Apr 2025 02:04:17 +0000 (04:04 +0200)] 
soc: qcom: smp2p: Fix fallback to qcom,ipc parse

mbox_request_channel() returning value was changed in case of error.
It uses returning value of of_parse_phandle_with_args().
It is returning with -ENOENT instead of -ENODEV when no mboxes property
exists.

Fixes: 24fdd5074b20 ("mailbox: use error ret code of of_parse_phandle_with_args()")
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Reviewed-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Tested-by: Stephan Gerhold <stephan.gerhold@linaro.org> # msm8939
Link: https://lore.kernel.org/r/20250421-fix-qcom-smd-v1-2-574d071d3f27@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agoMerge tag 'renesas-drivers-for-v6.16-tag2' of https://git.kernel.org/pub/scm/linux...
Arnd Bergmann [Fri, 9 May 2025 21:15:29 +0000 (23:15 +0200)] 
Merge tag 'renesas-drivers-for-v6.16-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers

Renesas driver updates for v6.16 (take two)

  - Cover all R-Car drivers in the ARM/RISC-V/RENESAS ARCHITECTURE
    maintainer entry,
  - Identify the Renesas RZ/V2N (R9A09G056) SoC.

* tag 'renesas-drivers-for-v6.16-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: rz-sysc: Add SoC identification for RZ/V2N SoC
  MAINTAINERS: Generalize ARM/RISC-V/RENESAS ARCHITECTURE

Link: https://lore.kernel.org/r/cover.1746798752.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 months agoMerge tag 'amd-tee-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git...
Arnd Bergmann [Fri, 9 May 2025 21:14:57 +0000 (23:14 +0200)] 
Merge tag 'amd-tee-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee into soc/drivers

AMD-TEE driver updates for v6.16

- Sort header includes
- Use pr_fmt

* tag 'amd-tee-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee:
  amdtee: Sort header includes
  amdtee: Use pr_fmt for messages

Link: https://lore.kernel.org/r/20250509065833.GB4188600@rayden
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 months agoMerge tag 'hisi-drivers-for-6.16' of https://github.com/hisilicon/linux-hisi into...
Arnd Bergmann [Fri, 9 May 2025 21:12:37 +0000 (23:12 +0200)] 
Merge tag 'hisi-drivers-for-6.16' of https://github.com/hisilicon/linux-hisi into soc/drivers

HiSilicon driver updates for v6.16

- Simplify PCC shared memory region handling in HCCS driver

* tag 'hisi-drivers-for-6.16' of https://github.com/hisilicon/linux-hisi:
  soc: hisilicon: kunpeng_hccs: Simplify PCC shared memory region handling

Link: https://lore.kernel.org/r/681D9FC4.6080508@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 months agoMerge tag 'memory-controller-drv-6.16' of https://git.kernel.org/pub/scm/linux/kernel...
Arnd Bergmann [Fri, 9 May 2025 21:11:48 +0000 (23:11 +0200)] 
Merge tag 'memory-controller-drv-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers

Memory controller drivers for v6.16

1. Mediatek: Add support for MT6893 MTK SMI.
2. STM32: Add new driver for STM32 Octo Memory Manager (OMM), which
   manages muxing between two OSPI busses.
3. Several cleanups and minor improvements (OMAP GPMC, Kconfig entries,
   BT1 L2).

* tag 'memory-controller-drv-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  MAINTAINERS: add entry for STM32 OCTO MEMORY MANAGER driver
  memory: Add STM32 Octo Memory Manager driver
  dt-bindings: memory-controllers: Add STM32 Octo Memory Manager controller
  bus: firewall: Fix missing static inline annotations for stubs
  memory: bt1-l2-ctl: replace scnprintf() with sysfs_emit()
  memory: mtk-smi: Add support for Dimensity 1200 MT6893 SMI
  dt-bindings: memory: mtk-smi: Add support for MT6893
  memory: tegra: Do not enable by default during compile testing
  memory: Simplify 'default' choice in Kconfig
  memory: omap-gpmc: remove GPIO set() and direction_output() callbacks
  memory: omap-gpmc: use the dedicated define for GPIO direction

Link: https://lore.kernel.org/r/20250508093451.55755-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 months agoMerge tag 'memory-controller-drv-renesas-6.16' of https://git.kernel.org/pub/scm...
Arnd Bergmann [Fri, 9 May 2025 21:10:31 +0000 (23:10 +0200)] 
Merge tag 'memory-controller-drv-renesas-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers

Renesas memory controller drivers for v6.16

Improvements and new device support for the Renesas RPC IF memory
controller driver:
1. Minor cleanup and improvements.
2. Refactor the driver to accommodate for newly added Renesas RZ/G3E support:
   - Acquire two resets instead of only one,
   - Add RZ/G3E xSPI support with different register layout and its own,
     new interface for Renesas SPI.

* tag 'memory-controller-drv-renesas-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: renesas-rpc-if: Add missing static keyword
  memory: renesas-rpc-if: Add RZ/G3E xSPI support
  memory: renesas-rpc-if: Add wrapper functions
  memory: renesas-rpc-if: Add regmap to struct rpcif_info
  memory: renesas-rpc-if: Use devm_reset_control_array_get_exclusive()
  memory: renesas-rpc-if: Move rpc-if reg definitions
  dt-bindings: memory: Document RZ/G3E support
  memory: renesas-rpc-if: Move rpcif_info definitions near to the user
  memory: renesas-rpc-if: Fix RPCIF_DRENR_CDB macro error

Link: https://lore.kernel.org/r/20250508090749.51379-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 months agoMerge tag 'scmi-updates-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git...
Arnd Bergmann [Fri, 9 May 2025 21:08:52 +0000 (23:08 +0200)] 
Merge tag 'scmi-updates-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers

Arm SCMI updates for v6.16

1. Quirk framework to handle buggy firmware

   With SCMI gaining broader adoption across arm64 platforms, it's
   increasingly important to address how we consistently manage out-of-spec
   SCMI firmware already deployed in the field. This change introduces a
   lightweight quirk framework built around static_keys, enabling developers to:
    - Define quirks and their match criteria, which can include:
       o A list of compatibles ({ comp, comp2, NULL })
       o Vendor ID / Sub-Vendor ID
       o Firmware implementation version ranges ([Min_Vers, Max_Vers])

   Matching proceeds from the most specific (longest match) to the least
   specific. NULL entries are treated as wildcards (i.e., match any value).
   This flexibility allows matching very specific combinations or just a
   general compatible string.

   The quirk code blocks/snippets implementing the workaround are placed near
   their intended usage and guarded by a static_key that's tied to the quirk.
   Once the SCMI core stack is initialized and retrieves platform info via the
   base protocol, any matching quirks will have their associated static_keys
   enabled.

2. Quirk for Qualcomm X1E platforms

   On some Qualcomm X1E platforms, such as the Lenovo ThinkPad T14s, the
   SCMI firmware fails to set the FastChannel support bit for PERF_LEVEL_GET,
   yet it crashes when the driver attempts to fall back to standard messaging
   which is clearly out-of-spec behavior.

   To work around this, the new SCMI quirk framework is used to
   unconditionally enable FC initialization for this firmware version.

   In the future, once the fixed firmware version is identified, an upper
   version bound can be added to the quirk match criteria. Alternatively,
   matching can be further restricted using a SoC-specific compatible string
   if always enabling FC proves problematic elsewhere.

3. Support for NXP i.MX LMM/CPU vendor protocol extensions

   The i.MX95 System Manager (SM) implements Logical Machine Management (LMM)
   and a CPU protocol to manage Logical Machines (LM) and CPUs (e.g., M7).

   These changes integrate the vendor-specific protocol extensions
   implementing the LMM and CPU protocols for the i.MX95, facilitating
   standardized communication between the operating system and the platform's
   firmware, which will be used by remoteproc drivers. The changes also
   include the necessary device tree bindings.

4. Miscellaneous cleanups/changes

   These mainly include polling support in SCMI raw mode. The cleanups
   centralize error logging for SCMI device creation into a single helper
   function, consolidate the device matching logic into a single function, and
   ensure that devices must have a name for registration—removing support for
   unnamed devices when matching drivers and devices for probing. Transport
   devices are now excluded from bus matching, and the correct assignment of
   the parent device for the arm-scmi platform device is ensured in the
   transport drivers.

* tag 'scmi-updates-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  firmware: arm_scmi: quirk: Force perf level get fastchannel
  firmware: arm_scmi: quirk: Fix CLOCK_DESCRIBE_RATES triplet
  firmware: arm_scmi: Add common framework to handle firmware quirks
  firmware: arm_scmi: Ensure that the message-id supports fastchannel
  MAINTAINERS: add entry for i.MX SCMI extensions
  firmware: imx: Add i.MX95 SCMI CPU driver
  firmware: imx: Add i.MX95 SCMI LMM driver
  firmware: arm_scmi: imx: Add i.MX95 CPU Protocol
  firmware: arm_scmi: imx: Add i.MX95 LMM protocol
  dt-bindings: firmware: Add i.MX95 SCMI LMM and CPU protocol
  firmware: arm_scmi: imx: Add LMM and CPU documentation
  firmware: arm_scmi: Add polling support to raw mode
  firmware: arm_scmi: Exclude transport devices from bus matching
  firmware: arm_scmi: Assign correct parent to arm-scmi platform device
  firmware: arm_scmi: Refactor error logging from SCMI device creation to single helper
  firmware: arm_scmi: Refactor device matching logic to eliminate duplication
  firmware: arm_scmi: Ensure scmi_devices are always matched by name as well

Link: https://lore.kernel.org/r/20250507134713.49039-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 months agoMerge tag 'mtk-soc-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git...
Arnd Bergmann [Fri, 9 May 2025 21:08:05 +0000 (23:08 +0200)] 
Merge tag 'mtk-soc-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/drivers

MediaTek driver updates for v6.16

This brings some cleanups to the MediaTek DVFSRC driver, commonizing
the bandwidth constraints platform data, and also adds support for
the DVFSRC hardware found in the MediaTek Dimensity 1200 MT6893 SoC.

* tag 'mtk-soc-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
  soc: mediatek: mtk-dvfsrc: remove an unused variable
  soc: mediatek: mtk-dvfsrc: Add support for Dimensity 1200 MT6893
  soc: mediatek: mtk-dvfsrc: Rename and move bw constraints data
  dt-bindings: soc: mediatek: dvfsrc: Add support for MT6893

Link: https://lore.kernel.org/r/20250506091736.125733-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 months agoMerge tag 'arm-soc/for-6.16/drivers' of https://github.com/Broadcom/stblinux into...
Arnd Bergmann [Fri, 9 May 2025 21:07:27 +0000 (23:07 +0200)] 
Merge tag 'arm-soc/for-6.16/drivers' of https://github.com/Broadcom/stblinux into soc/drivers

This pull request contains Broadcom SoC driver updates for 6.16, please
pull the following:

- Ovidiu updates the brcmstb_gisb driver to use the dev_groups instead
  of manually adding those

* tag 'arm-soc/for-6.16/drivers' of https://github.com/Broadcom/stblinux:
  bus: brcmstb_gisb: use dev_groups to register attribute groups

Link: https://lore.kernel.org/r/20250505165810.1948927-3-florian.fainelli@broadcom.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 months agoMerge tag 'samsung-drivers-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git...
Arnd Bergmann [Fri, 9 May 2025 21:06:21 +0000 (23:06 +0200)] 
Merge tag 'samsung-drivers-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers

Samsung SoC drivers for v6.16

Several improvements to Exynos ACPM (Alive Clock and Power Manager)
driver:
1. Handle communication timeous better.
2. Avoid sleeping, so users (PMIC) can still transfer during system
   shutdown.
3. Fix reading longer messages from them firmware.
4. Deferred probe improvements.
5. Model the user of ACPM - PMIC - a as child device and export
   devm_acpm_get_by_node() for such use case.

* tag 'samsung-drivers-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  firmware: exynos-acpm: Correct kerneldoc and use typical np argument name
  firmware: exynos-acpm: introduce devm_acpm_get_by_node()
  firmware: exynos-acpm: populate devices from device tree data
  firmware: exynos-acpm: silence EPROBE_DEFER error on boot
  firmware: exynos-acpm: fix reading longer results
  dt-bindings: firmware: google,gs101-acpm-ipc: add PMIC child node
  firmware: exynos-acpm: allow use during system shutdown
  firmware: exynos-acpm: use ktime APIs for timeout detection

Link: https://lore.kernel.org/r/20250501103541.13795-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 months agoMerge tag 'renesas-drivers-for-v6.16-tag1' of https://git.kernel.org/pub/scm/linux...
Arnd Bergmann [Fri, 9 May 2025 21:05:41 +0000 (23:05 +0200)] 
Merge tag 'renesas-drivers-for-v6.16-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers

Renesas driver updates for v6.16

  - Enable all Renesas SoCs by default when ARCH_RENESAS is set, which
    will allow up to remove all individual Renesas SoC entries from the
    various defconfigs,
  - Initial support for the Renesas RZ/V2N (R9A09G056) SoC.

* tag 'renesas-drivers-for-v6.16-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: Add config option for RZ/V2N (R9A09G056) SoC
  soc: renesas: Kconfig: Enable SoCs by default when ARCH_RENESAS is set

Link: https://lore.kernel.org/r/cover.1745582592.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 months agodt-bindings: reset: Add compatible for Amlogic A4/A5 Reset Controller
Zelong Dong [Fri, 11 Apr 2025 11:38:15 +0000 (19:38 +0800)] 
dt-bindings: reset: Add compatible for Amlogic A4/A5 Reset Controller

Add compatibles for Amlogic A4 and A5 reset controllers,
which fall back to 'amlogic,meson-s4-reset'.

Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20240918074211.8067-2-zelong.dong@amlogic.com
Signed-off-by: Kelvin Zhang <kelvin.zhang@amlogic.com>
Link: https://lore.kernel.org/r/20250411-a4-a5-reset-v6-1-89963278c686@amlogic.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
3 months agosoc: fsl: qe: remove unused qe_ic_from_irq function
Tom Rix [Mon, 20 Mar 2023 12:52:02 +0000 (08:52 -0400)] 
soc: fsl: qe: remove unused qe_ic_from_irq function

clang with W=1 reports
drivers/soc/fsl/qe/qe_ic.c:235:29: error: unused function  'qe_ic_from_irq' [-Werror,-Wunused-function]

The use of this function was removed with
commit d7c2878cfcfa ("soc: fsl: qe: remove unused qe_ic_set_* functions")

Signed-off-by: Tom Rix <trix@redhat.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20230320125202.1721775-1-trix@redhat.com
Link: https://lore.kernel.org/all/1619002613-18216-1-git-send-email-jiapeng.chong@linux.alibaba.com/
[krzk: Adjust commit msg]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agosoc: ti: wkup_m3_ipc: Use dev_err_probe
Alexander Stein [Fri, 9 May 2025 09:36:52 +0000 (11:36 +0200)] 
soc: ti: wkup_m3_ipc: Use dev_err_probe

During probe the mailbox channel might not yet be available. Use
dev_err_probe to silence this deferred probe error message:
wkup_m3_ipc 44e11324.wkup_m3_ipc: IPC Request for A8->M3 Channel failed! -517

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Link: https://lore.kernel.org/r/20250509093652.1866566-1-alexander.stein@ew.tq-group.com
Signed-off-by: Nishanth Menon <nm@ti.com>
3 months agosoc: imx8m: Dump higher 64bits UID
Peng Fan [Wed, 23 Apr 2025 14:37:06 +0000 (22:37 +0800)] 
soc: imx8m: Dump higher 64bits UID

i.MX8MP UID is actually 128bits and partitioned into two parts.
The 1st 64bits are at 0x410 and 0x420, and 2nd 64bits are at 0xE00
and 0xE10.

Dump the whole 128bits for i.MX8MP, by set soc_uid as an array with two
u64.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
3 months agosoc: imx8m: Introduce soc_uid hook
Peng Fan [Wed, 23 Apr 2025 14:37:05 +0000 (22:37 +0800)] 
soc: imx8m: Introduce soc_uid hook

Cleanup code by introducing soc_uid hook, i.MX8MQ/M/N could reuse
one function imx8m_soc_uid, i.MX8MP could have its own one.

With this patch, it will easy to add 128bits UID support for i.MX8MP.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
3 months agosoc: imx8m: Cleanup with adding imx8m_soc_[un]prepare
Peng Fan [Wed, 23 Apr 2025 14:37:04 +0000 (22:37 +0800)] 
soc: imx8m: Cleanup with adding imx8m_soc_[un]prepare

There is a common flow to i.MX8M family, map OCOTP register base and
enable ocotp clk first before read Unique ID from OCOTP.

So introduce imx8m_soc_prepare to do ioremap and enable the ocotp clk,
and introduce imx8m_soc_unprepare to disable the clk and do iounmap.

With this patch, no need to spread the ioremap and clk handling in
each soc_revision hook.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
3 months agomemory: renesas-rpc-if: Add missing static keyword
Biju Das [Wed, 7 May 2025 16:21:44 +0000 (17:21 +0100)] 
memory: renesas-rpc-if: Add missing static keyword

Fix the below sparse warnings:
 symbol 'rpcif_impl' was not declared. Should it be static?
 symbol 'xspi_impl' was not declared. Should it be static?

Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202505072013.1EqwjtaR-lkp@intel.com/
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20250507162146.140494-1-biju.das.jz@bp.renesas.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agosoc: qcom: pmic_glink: enable UCSI on sc8280xp
Johan Hovold [Wed, 26 Mar 2025 12:49:44 +0000 (13:49 +0100)] 
soc: qcom: pmic_glink: enable UCSI on sc8280xp

Commit ad3dd9592b2a ("soc: qcom: pmic_glink: disable UCSI on sc8280xp")
disabled UCSI shortly after it had been enabled to fix a regression that
was observed on the Lenovo ThinkPad X13s.

Specifically, disconnecting an external display would trigger a system
error and hypervisor reset but no one cared enough to track down the bug
at the time.

The same issue was recently observed on X Elite machines, and commit
f47eba045e6c ("usb: typec: ucsi: Set orientation as none when connector
is unplugged") worked around the underlying issue by setting the
connector orientation to 'none' on disconnect events to avoid having the
PHY driver crash the machine in one orientation.

Enable UCSI support also on sc8280xp now that the DisplayPort disconnect
crashes are gone.

Cc: Abel Vesa <abel.vesa@linaro.org>
Cc: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250326124944.6338-1-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agoMAINTAINERS: add entry for STM32 OCTO MEMORY MANAGER driver
Patrice Chotard [Mon, 28 Apr 2025 08:58:32 +0000 (10:58 +0200)] 
MAINTAINERS: add entry for STM32 OCTO MEMORY MANAGER driver

Add myself as STM32 OCTO MEMORY MANAGER maintainer.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20250428-upstream_ospi_v6-v11-3-1548736fd9d2@foss.st.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agomemory: Add STM32 Octo Memory Manager driver
Patrice Chotard [Mon, 28 Apr 2025 08:58:31 +0000 (10:58 +0200)] 
memory: Add STM32 Octo Memory Manager driver

Octo Memory Manager driver (OMM) manages:
  - the muxing between 2 OSPI busses and 2 output ports.
    There are 4 possible muxing configurations:
      - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2
        output is on port 2
      - OSPI1 and OSPI2 are multiplexed over the same output port 1
      - swapped mode (no multiplexing), OSPI1 output is on port 2,
        OSPI2 output is on port 1
      - OSPI1 and OSPI2 are multiplexed over the same output port 2
  - the split of the memory area shared between the 2 OSPI instances.
  - chip select selection override.
  - the time between 2 transactions in multiplexed mode.
  - check firewall access.

Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20250428-upstream_ospi_v6-v11-2-1548736fd9d2@foss.st.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agodt-bindings: memory-controllers: Add STM32 Octo Memory Manager controller
Patrice Chotard [Mon, 28 Apr 2025 08:58:30 +0000 (10:58 +0200)] 
dt-bindings: memory-controllers: Add STM32 Octo Memory Manager controller

Add bindings for STM32 Octo Memory Manager (OMM) controller.

OMM manages:
  - the muxing between 2 OSPI busses and 2 output ports.
    There are 4 possible muxing configurations:
      - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2
        output is on port 2
      - OSPI1 and OSPI2 are multiplexed over the same output port 1
      - swapped mode (no multiplexing), OSPI1 output is on port 2,
        OSPI2 output is on port 1
      - OSPI1 and OSPI2 are multiplexed over the same output port 2
  - the split of the memory area shared between the 2 OSPI instances.
  - chip select selection override.
  - the time between 2 transactions in multiplexed mode.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250428-upstream_ospi_v6-v11-1-1548736fd9d2@foss.st.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agobus: firewall: Fix missing static inline annotations for stubs
Krzysztof Kozlowski [Wed, 7 May 2025 09:21:22 +0000 (11:21 +0200)] 
bus: firewall: Fix missing static inline annotations for stubs

Stubs in the header file for !CONFIG_STM32_FIREWALL case should be both
static and inline, because they do not come with earlier declaration and
should be inlined in every unit including the header.

Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: stable@vger.kernel.org
Fixes: 5c9668cfc6d7 ("firewall: introduce stm32_firewall framework")
Link: https://lore.kernel.org/r/20250507092121.95121-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agomemory: bt1-l2-ctl: replace scnprintf() with sysfs_emit()
Salah Triki [Mon, 5 May 2025 21:43:26 +0000 (22:43 +0100)] 
memory: bt1-l2-ctl: replace scnprintf() with sysfs_emit()

Documentation/filesystems/sysfs.rst mentions that show() should only
use sysfs_emit() or sysfs_emit_at() when formating the value to be
returned to user space. So replace scnprintf() with sysfs_emit().

Signed-off-by: Salah Triki <salah.triki@gmail.com>
Link: https://lore.kernel.org/r/aBkw_p9GkH2fm2UJ@pc
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agosoc: sophgo: cv1800: rtcsys: New driver (handling RTC only)
Alexander Sverdlin [Sat, 15 Mar 2025 22:49:13 +0000 (23:49 +0100)] 
soc: sophgo: cv1800: rtcsys: New driver (handling RTC only)

Add driver for Sophgo CV1800 series SoC RTC subsystem. The RTC module
comprises a 32kHz oscillator, Power-on-Reset (PoR) sub-module, HW state
machine to control chip power-on, power-off and reset. Furthermore, the
8051 subsystem is located within RTCSYS including associated SRAM block.

This patch only populates RTC sub-device.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Reviewed-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250315224921.3627852-3-alexander.sverdlin@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
3 months agodt-bindings: soc: sophgo: add RTC support for Sophgo CV1800 series
Jingbao Qiu [Sat, 15 Mar 2025 22:49:12 +0000 (23:49 +0100)] 
dt-bindings: soc: sophgo: add RTC support for Sophgo CV1800 series

Add RTC devicetree binding for Sophgo CV1800 series SoC. The device is
called RTC, but contains control registers of other HW blocks in its
address space, most notably of Power-on-Reset (PoR) module, DW8051 IP
(MCU core), accompanying SRAM, hence putting it in SoC subsystem.

Signed-off-by: Jingbao Qiu <qiujingbao.dlmu@gmail.com>
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250315224921.3627852-2-alexander.sverdlin@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
3 months agosoc: sophgo: sg2044: Add support for SG2044 TOP syscon device
Inochi Amaoto [Fri, 18 Apr 2025 02:03:21 +0000 (10:03 +0800)] 
soc: sophgo: sg2044: Add support for SG2044 TOP syscon device

The SG2044 TOP device provide PLL clock function in its area.
Add a mfd definition for it.

Link: https://lore.kernel.org/r/20250418020325.421257-3-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
3 months agofirmware: qcom: scm: Allow QSEECOM on Asus Zenbook A14
Aleksandrs Vinarskis [Sat, 26 Apr 2025 12:57:59 +0000 (14:57 +0200)] 
firmware: qcom: scm: Allow QSEECOM on Asus Zenbook A14

Allow particular machine accessing eg. efivars.

Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com>
Link: https://lore.kernel.org/r/20250426130203.37659-4-alex.vinarskis@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agofirmware: ti_sci: Convert CPU latency constraint from us to ms
Kendall Willis [Mon, 28 Apr 2025 20:53:36 +0000 (15:53 -0500)] 
firmware: ti_sci: Convert CPU latency constraint from us to ms

Fix CPU resume latency constraint units sent to device manager through the
TI SCI API. The device manager expects CPU resume latency to be in msecs
which is passed in with the TI SCI API [1]. CPU latency constraints are
set in userspace using the PM QoS framework which uses usecs as the unit.
Since PM QoS uses usecs for units and the device manager expects msecs as
the unit, TI SCI needs to convert from usecs to msecs before passing to
device manager.

[1] https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/pm/lpm.html#tisci-msg-lpm-set-latency-constraint

Cc: stable@vger.kernel.org
Fixes: a7a15754c7f7 ("firmware: ti_sci: add CPU latency constraint management")
Signed-off-by: Kendall Willis <k-willis@ti.com>
Link: https://lore.kernel.org/r/20250428205336.2947118-1-k-willis@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
3 months agofirmware: arm_scmi: quirk: Force perf level get fastchannel
Johan Hovold [Wed, 30 Apr 2025 13:51:46 +0000 (15:51 +0200)] 
firmware: arm_scmi: quirk: Force perf level get fastchannel

The Qualcomm SCP firmware in X1E machines like the Lenovo ThinkPad T14s
does not set the FastChannel supported attribute bit for PERF_LEVEL_GET
but crashes when falling back to regular messaging.

Use the new SCMI quirk framework to force FastChannel initialisation for
this implementation.

Note that we can add an upper bound on the version matching when we
learn which version has a fix (or limit matching using a SoC compatible
string in the unlikely event that always enabling FC causes trouble
somewhere).

Link: https://lore.kernel.org/lkml/Z4Dt8E7C6upVtEGV@hovoldconsulting.com/
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Message-Id: <20250430135146.5154-1-johan+linaro@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
3 months agofirmware: arm_scmi: quirk: Fix CLOCK_DESCRIBE_RATES triplet
Cristian Marussi [Tue, 29 Apr 2025 14:11:08 +0000 (15:11 +0100)] 
firmware: arm_scmi: quirk: Fix CLOCK_DESCRIBE_RATES triplet

Convert an existing quirk in CLOCK_DESCRIBE_RATES parsing to the new quirk
framework. This is a sort of a peculiar quirk since it matches any platform
and any firmware.

Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
Message-Id: <20250429141108.406045-4-cristian.marussi@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
3 months agofirmware: arm_scmi: Add common framework to handle firmware quirks
Cristian Marussi [Tue, 29 Apr 2025 14:11:07 +0000 (15:11 +0100)] 
firmware: arm_scmi: Add common framework to handle firmware quirks

Add a common framework to describe SCMI quirks and associate them with a
specific platform or a specific set of SCMI firmware versions.

All the matching SCMI quirks will be enabled when the SCMI core stack
probes and after all the needed SCMI firmware versioning information was
retrieved using the base protocol.

Tested-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
Message-Id: <20250429141108.406045-3-cristian.marussi@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
3 months agofirmware: arm_scmi: Ensure that the message-id supports fastchannel
Sibi Sankar [Tue, 29 Apr 2025 14:11:06 +0000 (15:11 +0100)] 
firmware: arm_scmi: Ensure that the message-id supports fastchannel

Currently the perf and powercap protocol relies on the protocol domain
attributes, which just ensures that one fastchannel per domain, before
instantiating fastchannels for all possible message-ids. Fix this by
ensuring that each message-id supports fastchannel before initialization.

Logs:
  |  scmi: Failed to get FC for protocol 13 [MSG_ID:6 / RES_ID:0] - ret:-95. Using regular messaging
  |  scmi: Failed to get FC for protocol 13 [MSG_ID:6 / RES_ID:1] - ret:-95. Using regular messaging
  |  scmi: Failed to get FC for protocol 13 [MSG_ID:6 / RES_ID:2] - ret:-95. Using regular messaging

CC: stable@vger.kernel.org
Reported-by: Johan Hovold <johan+linaro@kernel.org>
Closes: https://lore.kernel.org/lkml/ZoQjAWse2YxwyRJv@hovoldconsulting.com/
Fixes: 6f9ea4dabd2d ("firmware: arm_scmi: Generalize the fast channel support")
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
[Cristian: Modified the condition checked to establish support or not]
Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
Message-Id: <20250429141108.406045-2-cristian.marussi@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
3 months agoARM: vt8500: MAINTAINERS: Include vt8500 soc driver in maintainers entry
Krzysztof Kozlowski [Sun, 4 May 2025 17:31:26 +0000 (19:31 +0200)] 
ARM: vt8500: MAINTAINERS: Include vt8500 soc driver in maintainers entry

Include the SoC hwinfo/soc information driver in VT8500 maintainers
entry.

Link: https://lore.kernel.org/r/20250504173125.104419-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agodt-bindings: reset: sophgo: Add SG2044 bindings.
Inochi Amaoto [Sun, 13 Apr 2025 22:34:59 +0000 (06:34 +0800)] 
dt-bindings: reset: sophgo: Add SG2044 bindings.

The SG2044 shares the same reset controller as SG2042, so it
is just enough to use the compatible string of SG2042 as a
basis.

Add compatible string for the reset controller of SG2044.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Acked-by: "Rob Herring (Arm)" <robh@kernel.org>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/20250413223507.46480-6-inochiama@gmail.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
3 months agoMAINTAINERS: Add entry for Renesas RZ/V2H(P) USB2PHY Port Reset driver
Lad Prabhakar [Tue, 15 Apr 2025 19:51:31 +0000 (20:51 +0100)] 
MAINTAINERS: Add entry for Renesas RZ/V2H(P) USB2PHY Port Reset driver

Add a new MAINTAINERS entry for the Renesas RZ/V2H(P) USB2PHY Port Reset
driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20250415195131.281060-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
3 months agoreset: Add USB2PHY port reset driver for Renesas RZ/V2H(P)
Lad Prabhakar [Tue, 15 Apr 2025 19:51:30 +0000 (20:51 +0100)] 
reset: Add USB2PHY port reset driver for Renesas RZ/V2H(P)

Implement a USB2PHY port reset driver for the Renesas RZ/V2H(P) SoC.
Enable control of USB2.0 PHY reset and power-down operations, including
assert and deassert functionalities for the PHY.

Leverage device tree (OF) data to support future SoCs with similar USB2PHY
hardware but varying register configurations. Define initialization values
and control register settings to ensure flexibility for upcoming platforms.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20250415195131.281060-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
3 months agodt-bindings: reset: Document RZ/V2H(P) USB2PHY reset
Lad Prabhakar [Tue, 15 Apr 2025 19:51:29 +0000 (20:51 +0100)] 
dt-bindings: reset: Document RZ/V2H(P) USB2PHY reset

Add a device tree binding document for the Renesas RZ/V2H(P) USB2PHY reset
controller. This block manages the reset and power-down of the USB 2.0 PHY,
which is used in both host and function modes.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/20250415195131.281060-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
3 months agoreset: Add devm_reset_control_array_get_exclusive_released()
Patrice Chotard [Fri, 11 Apr 2025 12:41:10 +0000 (14:41 +0200)] 
reset: Add devm_reset_control_array_get_exclusive_released()

Add the released variant of devm_reset_control_array_get_exclusive().
Needed by spi-smt32-ospi driver as same reset line is ulso used by
stm32-omm driver.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20250411-b4-upstream_ospi_reset_update-v2-1-4de7f5dd2a91@foss.st.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
3 months agosoc: renesas: rz-sysc: Add SoC identification for RZ/V2N SoC
Lad Prabhakar [Tue, 15 Apr 2025 08:54:38 +0000 (09:54 +0100)] 
soc: renesas: rz-sysc: Add SoC identification for RZ/V2N SoC

Add SoC identification for the RZ/V2N SoC using the System Controller
(SYS) block.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250415085438.83856-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agoMAINTAINERS: Generalize ARM/RISC-V/RENESAS ARCHITECTURE
Uwe Kleine-König [Fri, 4 Apr 2025 08:00:43 +0000 (10:00 +0200)] 
MAINTAINERS: Generalize ARM/RISC-V/RENESAS ARCHITECTURE

Triggered by noticing that the pwm-rcar driver isn't covered by the
Renesas maintainer entry, add this driver to it. Instead of adding it
explicitly, just add a file regex for "rcar" (and drop the one entry
that gets redundant by that).

Looking at the output of

$ git ls-files | grep rcar

only shows files related to that architecture, so no X: line is
currently needed.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250404080045.367845-2-u.kleine-koenig@baylibre.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
3 months agosoc: Add VIA/WonderMedia SoC identification driver
Alexey Charkov [Sat, 3 May 2025 11:52:32 +0000 (15:52 +0400)] 
soc: Add VIA/WonderMedia SoC identification driver

Add a small SOC bus driver to parse the chip ID and revision made
available on VIA/WonderMedia SoCs via their system configuration
controller's SCC_ID register.

This is intended to select appropriate sets of on-chip device quirks
at runtime, as it has been found that even within the same SoC
version there can be register-incompatible differences, such as
with the SDMMC controller on WM8505 rev. A0-A1 vs. rev. A2.

The list of SoC versions is compiled from various vendor source dumps
and not all of them have corresponding mainline driver support.
Some of them also have been seen with varying on-chip markings while
sharing the same hardware chip ID's (as is the case with e.g. WM8850
vs. WM8950). In such cases the selection of names to use here among
those seen in various source dumps and chip markings was arbitrary.

Suggested by Krzysztof at [1] - thanks a lot!

[1] https://lore.kernel.org/all/14de236b-e2a7-4bde-986d-1e5ffddd01b4@kernel.org/

Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://lore.kernel.org/r/20250503-wmt-soc-driver-v3-2-2daa9056fa10@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agodt-bindings: hwinfo: Add VIA/WonderMedia SoC identification
Alexey Charkov [Sat, 3 May 2025 11:52:31 +0000 (15:52 +0400)] 
dt-bindings: hwinfo: Add VIA/WonderMedia SoC identification

VIA/WonderMedia SoC's have a chip ID register inside their system
configuration controller space, which can be used to identify
appropriate hardware quirks at runtime. Add binding for it.

Signed-off-by: Alexey Charkov <alchark@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250503-wmt-soc-driver-v3-1-2daa9056fa10@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agomemory: renesas-rpc-if: Add RZ/G3E xSPI support
Biju Das [Thu, 24 Apr 2025 08:59:54 +0000 (09:59 +0100)] 
memory: renesas-rpc-if: Add RZ/G3E xSPI support

Add support for RZ/G3E xSPI. Compared to RPC-IF, it can support writes on
memory-mapped area. Introduce struct rpcif_impl for holding the function
pointers and data to handle the differences between xspi and rpc-if
interface.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250424090000.136804-7-biju.das.jz@bp.renesas.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agomemory: renesas-rpc-if: Add wrapper functions
Biju Das [Thu, 24 Apr 2025 08:59:53 +0000 (09:59 +0100)] 
memory: renesas-rpc-if: Add wrapper functions

Even though XSPI and RPCIF has different register layout, reuse the code
by adding wrapper functions to support both XSPI and RPC-IF.

While at it, replace error check for pm_runtime_resume_and_get().

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250424090000.136804-6-biju.das.jz@bp.renesas.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agomemory: renesas-rpc-if: Add regmap to struct rpcif_info
Biju Das [Thu, 24 Apr 2025 08:59:52 +0000 (09:59 +0100)] 
memory: renesas-rpc-if: Add regmap to struct rpcif_info

The RZ/G3E XSPI has different regmap compared to RPC-IF. Add regmap to
struct rpcif_info in order to support RZ/G3E XSPI.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250424090000.136804-5-biju.das.jz@bp.renesas.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agomemory: renesas-rpc-if: Use devm_reset_control_array_get_exclusive()
Biju Das [Thu, 24 Apr 2025 08:59:51 +0000 (09:59 +0100)] 
memory: renesas-rpc-if: Use devm_reset_control_array_get_exclusive()

Replace devm_*_get_exclusive()->devm_*_array_get_exclusive() to support
existing SoCs along with RZ/G3E as RZ/G3E has 2 resets.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250424090000.136804-4-biju.das.jz@bp.renesas.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agomemory: renesas-rpc-if: Move rpc-if reg definitions
Biju Das [Thu, 24 Apr 2025 08:59:50 +0000 (09:59 +0100)] 
memory: renesas-rpc-if: Move rpc-if reg definitions

Move rpc-if reg definitions to a header file for the preparation of adding
support for RZ/G3E XSPI that has different register definitions.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250424090000.136804-3-biju.das.jz@bp.renesas.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agodt-bindings: memory: Document RZ/G3E support
Biju Das [Thu, 24 Apr 2025 08:59:49 +0000 (09:59 +0100)] 
dt-bindings: memory: Document RZ/G3E support

Document support for the Expanded Serial Peripheral Interface (xSPI)
Controller in the Renesas RZ/G3E (R9A09G047) SoC.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250424090000.136804-2-biju.das.jz@bp.renesas.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agotee: Prevent size calculation wraparound on 32-bit kernels
Jann Horn [Mon, 28 Apr 2025 13:06:43 +0000 (15:06 +0200)] 
tee: Prevent size calculation wraparound on 32-bit kernels

The current code around TEE_IOCTL_PARAM_SIZE() is a bit wrong on
32-bit kernels: Multiplying a user-provided 32-bit value with the
size of a structure can wrap around on such platforms.

Fix it by using saturating arithmetic for the size calculation.

This has no security consequences because, in all users of
TEE_IOCTL_PARAM_SIZE(), the subsequent kcalloc() implicitly checks
for wrapping.

Signed-off-by: Jann Horn <jannh@google.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Rouven Czerwinski <rouven.czerwinski@linaro.org>
3 months agoamdtee: Sort header includes
Mario Limonciello [Mon, 21 Apr 2025 15:22:23 +0000 (10:22 -0500)] 
amdtee: Sort header includes

Various headers have been added over time that are not added alphabetically
and a private header is used before one of the linux/ headers.

Resort the list.

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
3 months agoamdtee: Use pr_fmt for messages
Mario Limonciello [Mon, 21 Apr 2025 15:22:22 +0000 (10:22 -0500)] 
amdtee: Use pr_fmt for messages

amd-tee inconsistently uses the word amd-tee in error messages.

Add a `pr_fmt()` define and remove the hardcoded use of amd-tee.
Also, remove the unnecessary driver init successful message because
there will be a message if failed and a user can assume it was successful
otherwise.

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
3 months agotee: optee: smc: remove unnecessary NULL check before release_firmware()
Chen Ni [Thu, 10 Apr 2025 07:56:35 +0000 (15:56 +0800)] 
tee: optee: smc: remove unnecessary NULL check before release_firmware()

release_firmware() checks for NULL pointers internally.
Remove unneeded NULL check for fmw here.

Signed-off-by: Chen Ni <nichen@iscas.ac.cn>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
3 months agofirmware: exynos-acpm: Correct kerneldoc and use typical np argument name
Krzysztof Kozlowski [Thu, 24 Apr 2025 20:33:09 +0000 (22:33 +0200)] 
firmware: exynos-acpm: Correct kerneldoc and use typical np argument name

Correct kerneldoc warnings after commit a8dc26a0ec43 ("firmware:
exynos-acpm: introduce devm_acpm_get_by_node()") changed the function
prototype:

  exynos-acpm.c:672: warning: Function parameter or struct member 'acpm_np' not described in 'acpm_get_by_node'
  exynos-acpm.c:672: warning: expecting prototype for acpm_get_by_phandle(). Prototype was for acpm_get_by_node() instead

While touching the lines, change the name of device_node pointer to
'np' to match convention.

Fixes: a8dc26a0ec43 ("firmware: exynos-acpm: introduce devm_acpm_get_by_node()")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202504222051.7TqaSQ48-lkp@intel.com/
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20250424203308.402168-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
3 months agosoc: mediatek: mtk-dvfsrc: remove an unused variable
Arnd Bergmann [Wed, 23 Apr 2025 16:29:52 +0000 (18:29 +0200)] 
soc: mediatek: mtk-dvfsrc: remove an unused variable

This structure was left unused by a previous patch:

drivers/soc/mediatek/mtk-dvfsrc.c:542:43: error: unused variable 'dvfsrc_bw_constr_mt8195' [-Werror,-Wunused-const-variable]

Fixes: b06785283ec1 ("soc: mediatek: mtk-dvfsrc: Rename and move bw constraints data")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20250423162958.2223689-1-arnd@kernel.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
3 months agodt-bindings: soc: qcom,rpmh-rsc: Limit power-domains requirement
Konrad Dybcio [Thu, 27 Mar 2025 01:47:03 +0000 (02:47 +0100)] 
dt-bindings: soc: qcom,rpmh-rsc: Limit power-domains requirement

Certain platforms (such as Chrome SDM845 and SC7180 with a TF-A running
as secure firmware) do not have a OSI-mode capable PSCI implementation.

That in turn means the PSCI-associated power domain which represents the
system's power state can't provide enough feedback to the RSC device.

Don't require power-domains on platforms where this may be the case.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250327-topic-more_dt_bindings_fixes-v2-1-b763d958545f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agosoc: amlogic: clk-measure: Add support for S4
Chuan Liu [Tue, 15 Apr 2025 02:45:28 +0000 (10:45 +0800)] 
soc: amlogic: clk-measure: Add support for S4

Add the clk-measurer clocks IDs for the Amlogic S4 SoC family.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20250415-clk-measure-v3-5-9b8551dd33b4@amlogic.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
3 months agosoc: amlogic: clk-measure: Add support for C3
Chuan Liu [Tue, 15 Apr 2025 02:45:27 +0000 (10:45 +0800)] 
soc: amlogic: clk-measure: Add support for C3

Add the clk-measurer clocks IDs for the Amlogic C3 SoC family.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20250415-clk-measure-v3-4-9b8551dd33b4@amlogic.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
3 months agodt-bindings: soc: amlogic: S4 supports clk-measure
Chuan Liu [Tue, 15 Apr 2025 02:45:26 +0000 (10:45 +0800)] 
dt-bindings: soc: amlogic: S4 supports clk-measure

S4 adds support for clk-measure.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20250415-clk-measure-v3-3-9b8551dd33b4@amlogic.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
3 months agodt-bindings: soc: amlogic: C3 supports clk-measure
Chuan Liu [Tue, 15 Apr 2025 02:45:25 +0000 (10:45 +0800)] 
dt-bindings: soc: amlogic: C3 supports clk-measure

C3 adds support for clk-measure.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20250415-clk-measure-v3-2-9b8551dd33b4@amlogic.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
3 months agosoc: amlogic: clk-measure: Define MSR_CLK's register offset separately
Chuan Liu [Tue, 15 Apr 2025 02:45:24 +0000 (10:45 +0800)] 
soc: amlogic: clk-measure: Define MSR_CLK's register offset separately

Since the MSR_CLK register offset differs between chip variants, we
replace the macro-based definition with chip-specific assignments.

Change the max_register in regmap_config to be retrieved from DTS.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20250415-clk-measure-v3-1-9b8551dd33b4@amlogic.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>