Birger Koblitz [Sun, 30 Jan 2022 05:20:25 +0000 (06:20 +0100)]
realtek: Add specific PHY polling options to support the Zyxel XGS1250/XGS1210
Both the Aquantia AQR113c and the RTL8226 PHYs in the Zyxel XGS1250 and the
Zyxel XGS1210 require special polling configuration settings in the
RTL930X_SMI_10GPHY_POLLING_REGxx_CFG configuration registers. Set them.
Additionally, for RTL 1GBit phys set the RTL930X_SMI_PRVTE_POLLING_CTRL bits
in the poll mask.
Birger Koblitz [Wed, 19 Jan 2022 17:00:44 +0000 (18:00 +0100)]
realtek: Store and Restore MC memberships for port enable/disable
We need to store and restore MC memberships in HW when a port joins or
leaves a bridge as well as when it is enabled or disabled, as these
properties should not change in these situations.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Birger Koblitz [Tue, 18 Jan 2022 16:18:43 +0000 (17:18 +0100)]
realtek: Backport bridge configuration for DSA
Adds the DSA API for bridge configuration (flooding, L2 learning,
and aging) offload as found in Linux 5.12 so that we can implement
it in our drivver.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Birger Koblitz [Tue, 18 Jan 2022 13:20:40 +0000 (14:20 +0100)]
realtek: Add Link Aggregation (aka trunking) support
This adds LAG support for all 4 SoC families, including support
ofr the use of different distribution algorithm for the load-
balancing between individual links.
Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Birger Koblitz [Mon, 17 Jan 2022 14:31:43 +0000 (15:31 +0100)]
realtek: Add support for ZxXEL XGS1250-12 Switch
The ZyXEL XGS1250-12 Switch is a 11 + 1 port multi-GBit switch with
8 x 1000BaseT, 3 x 1000/2500/5000/10000BaseT Ethernet ports and
1 SFP+ module slot.
Hardware:
- RTL9302B SoC
- Macronix MX25L12833F (16MB flash)
- Nanja NT5CC64M16GP-1 (128MB DDR3 SDRAM)
- RTL8231 GPIO extender to control the port LEDs
- RTL8218D 8x Gigabit PHY
- Aquantia AQR113c 1/2.5/5/10 Gigabit PHYs
- SFP+ 10GBit slot
Power is supplied via a 12V 2A standard barrel connector. At the
right side behind the grid is UART serial connector. A Serial
header can be connected to from the outside of the switch trough
the airvents with a standard 2.54mm header.
Pins are from top to bottom Vcc(3.3V), TX, RX and GND. Serial
connection is via 115200 baud, 8N1.
A reset button is accessble through a hole in the front panel
At the time of this commit, all ethernet ports work under OpenWRT,
including the various NBaseT modes, however the 10GBit SFP+ slot is not
supported.
Installation
--------------
* Connect serial as per the layout above. Connection parameters: 115200 8N1.
* Navigate to 'Management' in the OEM web interface and click on 'Firmware upgrade'
to the left.
* Upload the OpenWrt initramfs image, and wait till the switch reboots.
* Connect to the device through serial and change the U-boot boot command.
> fw_setenv bootcmd 'rtk network on; boota'
* Reboot, scp the sysupgrade image to /tmp, verify the checksum and flash it:
> sysupgrade /tmp/openwrt-realtek-rtl930x-zyxel_xgs1250-12-squashfs-sysupgrade.bin
* Upon reboot, you have a functional OpenWrt installation. Leave the bootcmd
value as is - without 'rtk network on' the switch will fail to initialise
the network.
Web recovery
------------
The XGS1250-12 has a handy web recovery that will load when U-boot does
not find a bootable kernel. In case you would like to trigger the web
recovery manually, partially overwrite the firmware partition with some
zeroes:
# dd if=/dev/zero of=/dev/mtd5 bs=1M count=2
If you have serial connected you'll see U-boot will start the web recovery
and print it's listening on 192.168.1.1, but by default it seems to be on
the OEM default IP for the switch - 192.168.1.3. The web recovery only
listens on HTTP (80) and *not* on 443 (HTTPS) unlike the web UI.
Return to stock
---------------
You can flash the ZyXEL firmware images to return to stock:
Birger Koblitz [Mon, 17 Jan 2022 12:19:13 +0000 (13:19 +0100)]
realtek: Improve MAC config handling for all SoCs
Adds a rtl931x_phylink_mac_config for the RTL931X and improve
the handling of the RTL930X phylink configuration. Add separate
handling of the RTL839x since some configurations are different
from the RTL838X.
Birger Koblitz [Sun, 16 Jan 2022 06:03:11 +0000 (07:03 +0100)]
realtek: Allow PHY-IDs to differ from Port numbers
We were using the PHY-ids (the reg entries in the PHY
sections of the .dts) as the port numbers. Now scan the
ports section in the .dts, and use the actual port numbers,
following the phy-handle to the PHY properties.
Birger Koblitz [Fri, 7 Jan 2022 16:21:29 +0000 (17:21 +0100)]
realtek: Use new CEVT timer
Selects the new CEVT timer for Realtek instead of the previous
timer driver. While we are at it, we explicitily state we do
not use the I2C driver of the RTL9300.
Birger Koblitz [Thu, 6 Jan 2022 19:27:01 +0000 (20:27 +0100)]
realtek: Replace the RTL9300 generic timer with a CEVT timer
The RTL9300 has a broken R4K MIPS timer interrupt, however, the
R4K clocksource works. We replace the RTL9300 timer with a
Clock Event Timer (CEVT), which is VSMP aware and can be instantiated
as part of brining a VSMTP cpu up instead of the R4K CEVT source.
For this we place the RTL9300 CEVT timer in arch/mips/kernel
together with other MIPS CEVT timers, initialize the SoC IRQs
from a modified smp-mt.c and instantiate each timer as part
of the MIPS time setup in arch/mips/include/asm/time.h instead
of the R4K CEVT, similarly as is done by other MIPS CEVT timers.
Birger Koblitz [Sun, 2 Jan 2022 18:12:48 +0000 (19:12 +0100)]
realtek: Fix RTL931X Ethernet driver
Various fixes to enable Ethernet on the RTL931X:
- Network start and stop sequence for RTL931X HW
- MDIO access on RTL931X SoC
- Chip initialization
- SerDes setup
Birger Koblitz [Sat, 1 Jan 2022 12:52:04 +0000 (13:52 +0100)]
realtek: rename rtl838x_reg structure
Rename the SoC-specific rtl838x_reg structure in the Ethernet
driver to avoid confusion with the structure of the same name
in the DSA driver. New name is: rtl838x_eth_reg
Birger Koblitz [Fri, 31 Dec 2021 17:39:22 +0000 (18:39 +0100)]
realtek: Fix RTL839x TX CPU-Tag
Setting bits 20 and 23 in a u16 is obviously wrong.
According to https://www.svanheule.net/realtek/cypress/cputag
cpu_tag[2] starts at bit 48 in the cpu-tag structure, so
bit 43 is bit 5 in cpu_tag[2] and bit 40 is bit 8 in
cpu_tag[2].
Birger Koblitz [Fri, 31 Dec 2021 16:53:40 +0000 (17:53 +0100)]
realtek: Increase zone size for Ethernet driver DMA
Set CONFIG_FORCE_MAX_ZONEORDER setting to 13 to allow larger
contiguous memory allocation for the DMA of the Ethernet
driver. Increase the number of entries in the RX ring
to 300 making use of the larger DMA region now possible for
receiveing packets.
Birger Koblitz [Fri, 31 Dec 2021 11:51:45 +0000 (12:51 +0100)]
realtek: Add support for ZyXEL GS1900-48 Switch
The GS1900-48 is a 48 + 2 port Gigabit L2 switch with 48 gigabit ports.
Hardware:
RTL8393M SoC
Macronix MX25l12805D (16MB flash)
128MB RAM
6 * RTL8218B external PHY
2 * RTL8231 GPIO extenders to control the port LEDs, system LED and
Reset button
2 Uplink ports are SFP cages which support 1000 Base-X mini GBIC modules.
Power is supplied via a 230 volt mains connector.
The board has a hard reset switch SW1, which is is not reachable from the outside.
J4 provides a 12V RS232 serial connector which is connected through U8 to
the 3.3V UART of the RTL8393. Conversion is done by U8, a SIPEX 3232EC.
To connect to the UART, wires can be soldered to R603 (TX) and R602 (RX).
Installation:
Install the squashfs image via Realtek's original Web-Interface.
Birger Koblitz [Fri, 31 Dec 2021 11:18:05 +0000 (12:18 +0100)]
realtek: Update rtl839x.dtsi for realtek,rtl-intc, new gpio controller remove RTL8231 node
Update the IRQ configuration to work with the new rtl-intc controller.
Also change all KSEG1 addresses in reg = <> of the devics to physical
addresses.
Use the new gpio-otto controller instead of the legacy driver.
Also remove the memory node as this is better put into a device .dts.
Also remove the RTL8231 GPIO controller node from this base file
since the chip might not be found in all Realtek RTL839x devices.
Birger Koblitz [Thu, 13 Jan 2022 06:23:13 +0000 (07:23 +0100)]
realtek: Update RTL838X DTS to new Realtek IRQ controller notation
Replace the interrupt controller node with the new realtek,rtl-intc
node and change all device interrupts to use the 2 field notation:
interrupts = <[SoC IRQ] [Index to MIPS IRQ]>
Birger Koblitz [Fri, 31 Dec 2021 10:56:49 +0000 (11:56 +0100)]
realtek: Add VPE support for the IRQ driver
In order to support VSMP, enable support for both VPEs
of the RTL839X and RTL930X SoCs in the irq-realtek-rtl
driver. Add support for IRQ affinity setting.
Birger Koblitz [Wed, 29 Dec 2021 20:54:21 +0000 (21:54 +0100)]
realtek: Create 4 different Realtek Platforms
Creates RTL83XX as a basic kernel config parameter for the
RTL838X, RTL839x, RTL930X and RTL931X platforms with respective
configurations for the SoCs, which are introduced in addition.
Birger Koblitz [Sun, 16 Jan 2022 10:18:38 +0000 (11:18 +0100)]
realtek: Add support for SFP EEPROM-access over SMBus
The EEPROMs on SFP modules are compatible both to I2C as well
as SMBus. However, the kernel so far only supports I2C
access. We add SMBus access routines, because the I2C driver
for the RTL9300 HW only supports that protocol. At the same
time we disable I2C access to PHYs on SFP modules as otherwise
detection of any SFP module would fail. This is not in any
way problematic at this point in time since the RTL93XX
platform so far does not support PHYs on SFP modules.
The patches are copied and rebased version of:
https://bootlin.com/blog/sfp-modules-on-a-board-running-linux/
Signed-off-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
Birger Koblitz [Sat, 11 Dec 2021 19:25:37 +0000 (20:25 +0100)]
realtek: Add support for RTL9300/RTL9310 I2C multiplexing
The RTL9300/RTL9310 I2C controllers have support for 2 independent I2C
masters, each with a fixed SCL pin, that cannot be changed. Each of these
masters can use 8 (RTL9300) or 16 (RTL9310) different pins for SDA.
This multiplexer directly controls the two masters and their shared
IO configuration registers to allow multiplexing between any of these
busses. The two masters cannot be used in parallel as the multiplex
is protected by a standard multiplex lock.
Birger Koblitz [Sat, 11 Dec 2021 19:14:47 +0000 (20:14 +0100)]
realtek: Add support for RTL9300/RTL9310 I2C controller
This adds support for the RTL9300 and RTL9310 I2C controller.
The controller implements the SMBus protocol for SMBus transfers
over an I2C bus. The driver supports selecting one of the 2 possible
SCL pins and any of the 8 possible SDA pins. Bus speeds of
100kHz (standard speed) and 400kHz (high speed I2C) are supported.
Daniel Golle [Thu, 17 Feb 2022 15:10:00 +0000 (15:10 +0000)]
base-files: Make sure rootfs_data_max is considered
For sysupgrade on NAND/UBI devices there is the U-Boot environment
variable rootfs_data_max which can be used to limit the size of the
rootfs_data volume created on sysupgrade.
This stopped working reliable with recent kernels, probably due to a
race condition when reading the number of free erase blocks from sysfs
just after removing a volume.
Change the script to just try creating rootfs_data with the desired
size and retry with maximum size in case that fails. Hence calculating
the available size in the script can be dropped which works around the
problem.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Felix Fietkau [Wed, 16 Feb 2022 20:25:13 +0000 (21:25 +0100)]
ramips: fix NAND flash driver ECC bit position mask
The bit position mask was accidentally made too wide, overlapping with the LSB
from the byte position mask. This caused ECC calculation to fail for odd bytes
Signed-off-by: Chad Monroe <chad.monroe@smartrg.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
Chuanhong Guo [Thu, 10 Feb 2022 15:09:46 +0000 (23:09 +0800)]
ramips: mt7621: do memory detection on KSEG1
It's reported that current memory detection code occasionally detects
larger memory under some bootloaders.
Current memory detection code tests whether address space wraps around
on KSEG0, which is unreliable because it's cached.
Rewrite memory size detection to perform the same test on KSEG1 instead.
While at it, this patch also does the following two things:
1. use a fixed pattern instead of a random function pointer as the magic
value.
2. add an additional memory write and a second comparison as part of the
test to prevent possible smaller memory detection result due to
leftover values in memory.
Daniel Golle [Sun, 13 Feb 2022 23:26:45 +0000 (23:26 +0000)]
procd: simplify uxc init script
'uxc boot' is inteded to be called multiple times, so there is not need
to guard the first call on boot -- the actual code anyway didn't do
that, so just remove it.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Felix Fietkau [Sat, 12 Feb 2022 22:18:51 +0000 (23:18 +0100)]
kernel: add a fast path for the bridge code
This caches flows between MAC addresses on separate ports, including their VLAN
in order to bypass the normal bridge forwarding code.
In my test on MT7622, this reduces LAN->WLAN bridging CPU usage by 6-10%,
potentially even more on weaker platforms
Hauke Mehrtens [Sat, 12 Feb 2022 22:13:47 +0000 (23:13 +0100)]
tcpdump: Fix CVE-2018-16301
This fixes the following security problem:
The command-line argument parser in tcpdump before 4.99.0 has a buffer
overflow in tcpdump.c:read_infile(). To trigger this vulnerability the
attacker needs to create a 4GB file on the local filesystem and to
specify the file name as the value of the -F command-line argument of
tcpdump.
Jo-Philipp Wich [Fri, 11 Feb 2022 19:41:23 +0000 (20:41 +0100)]
firewall4: update to latest Git HEAD
53caa1a fw4: resolve zone layer 2 devices for hw flow offloading 9fe58f5 fw4: rework and fix family inheritance logic 8795296 tests: mocklib: fix infinite recursion in wrapped print() 281b1bc tests: change mocked wan interface type to PPPoE 93b710d tests: mocklib: forward compatibility change 1a94915 fw4: only stage reflection rules if all required addrs are known 5c21714 fw4: add device iifname/oifname matches to DSCP and MARK rules 3eacc97 tests: adjust 01_ruleset test case to latest changes
Jo-Philipp Wich [Fri, 11 Feb 2022 19:38:35 +0000 (20:38 +0100)]
ucode: update to latest Git HEAD
a29bad9 compiler: fix patchlist corruption on switch statement syntax errors 86f0662 lib: change `ord()` to always return single byte value 116a8ce vallist: fix storing/retrieving short strings with 8bit byte value
John Audia [Tue, 8 Feb 2022 19:25:03 +0000 (14:25 -0500)]
kernel: bump 5.10 to 5.10.99
Had to update generic defconfig (make kernel_menuconfig CONFIG_TARGET=generic)
for this bump, but since that only modifies the target defined in .config,
and since that target also needed to be updated for unrelated reasons, manually
propagated the newly added symbol to the generic config.
1. Boot WRC-2533GS2 normally with "Router" mode
2. Access to "http://192.168.2.1/" and open firmware update page
("ファームウェア更新")
3. Select the OpenWrt factory image and click apply ("適用") button
4. Wait ~120 seconds to complete flashing
INAGAKI Hiroshi [Sat, 5 Feb 2022 09:57:14 +0000 (18:57 +0900)]
ramips: move MAC configs to device dts from wrc-gs-2pci.dtsi
The locations of MAC addresses in mtd for LAN/WAN on ELECOM WRC-2533GS2
are changed from the other WRC-GS/GST devices with 2x PCIe. So move the
related configurations in mt7621_elecom_wrc-gs-2pci.dtsi to dts of each
model.
Notes:
* This device has a dual-boot partition scheme, but this firmware works
only on boot partition 1. The stock web interface will flash only on the
inactive boot partition, but the recovery web page will always flash on
boot partition 1.
Installation via recovery mode:
1. Press reset button, power up the device, wait >10s for CPU LED
to stop blinking.
2. Upload recovery image through the recovery web page at 192.168.0.1.
Revert to stock firmware:
1. Install stock image via recovery mode.
Daniel Golle [Thu, 10 Feb 2022 14:12:45 +0000 (14:12 +0000)]
mt7622: linksys-e8450: enable using mt7531 switch irq
Turns out the MT7531 switch IRQ line is connected to GPIO#53 just like
on the BPi-R64, so this seems to be part of the reference design and
will probably apply to most MT7622+MT7531 boards.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
DENG Qingfang [Thu, 10 Feb 2022 05:59:46 +0000 (13:59 +0800)]
kernel: backport MT7530 IRQ support
Support MT7530 PHY link change interrupts, and enable for MT7621.
For external MT7530, a GPIO IRQ line is required, which is
board-specific, so it should be added to each DTS. In case the
interrupt-controller property is missing, it will fall back to
polling mode.
DENG Qingfang [Thu, 3 Feb 2022 12:07:04 +0000 (20:07 +0800)]
kernel: backport MediaTek Ethernet PHY driver
Add support for MediaTek Gigabit Ethernet PHYs found in MT7530 and
MT7531. Fix some link up/down issues.
The errornous check for the PHY mode which broke things with MT7531
has been removed as suggested by patch
net: phy: mediatek: remove PHY mode check on MT7531
As a result, things are working fine now on MT7622+MT7531 as well.
Signed-off-by: DENG Qingfang <dqfext@gmail.com> Tested-by: Daniel Golle <daniel@makrotopia.org> Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com> Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
Rui Salvaterra [Sun, 19 Dec 2021 19:29:58 +0000 (19:29 +0000)]
kernel: generic: select the fq_codel qdisc by default
The kernel configuration allows us to select a default qdisc. Let's do this for
5.10 (as 5.4 is on its way out) and get rid of the hacky patch we've been
carrying.
Sungbo Eo [Wed, 2 Feb 2022 15:10:04 +0000 (00:10 +0900)]
ramips: move KERNEL_LOADADDR into Device/Default
Commit f4a79148f8cb ("ramips: add support for ipTIME AX2004M") was
reverted due to KERNEL_LOADADDR leakage, and it seems the problem can be
mitigated by moving the variable definition into Device/Default. By this,
KERNEL_LOADADDR redefined in a device recipe will not be leaked into the
subsequent device recipes anymore and thus will remain as a per-device
variable.
Ref: cd6a6e3030ff ("Revert "ramips: add support for ipTIME AX2004M"") Signed-off-by: Sungbo Eo <mans0n@gorani.run>
Mike Lothian [Mon, 17 May 2021 09:15:20 +0000 (10:15 +0100)]
ipq806x: Enlarge D7800 flash - use netgear partition
Increase the available flash memory size in Netgear R7800
by repurposing the unused "netgear" partition that is
located after the firmware partition.
Available flash space for kernel+rootfs+overlay increases
by 68 MB from 32 MB to 100 MB.
In a typical build, overlay space increases from 15 to 85,
increasing the package installation possibilities greatly.
Reverting to the OEM firmware is still possible, as the OEM
firmware contains logic to initialise the "netgear" partition
if its contents do not match expectations. In OEM firmware,
"netgear" contains 6 UBI sub-partitions that are defined in
/etc/netgear.cfg and initialisation is done by /etc/preinit
When the uci configuration is created automatically during a very early
stage, where no entropy daemon is set up, generating the key directly is
not an option. Therefore we allow to set the private_key to "generate"
and generate the private key directly before the interface is taken up.
projects / thirdparty / openwrt.git / log
