Yao Zi [Mon, 10 Mar 2025 14:09:17 +0000 (14:09 +0000)]
arm64: dts: rockchip: Fix PWM pinctrl names
These Rockchip boards assign "active" as the pinctrl name for PWM
controllers, which has never been supported in mainline Rockchip PWM
driver. It seems the name used by downstream kernel is accidentally
brought into maineline. Let's fix them.
Fixes: 4403e1237be3 ("arm64: dts: rockchip: Add devicetree for board roc-rk3308-cc") Fixes: 964ed0807b5f ("arm64: dts: rockchip: add rk3318 A95X Z2 board") Fixes: e7a095908227 ("arm64: dts: rockchip: Add devicetree for NanoPC-T4") Fixes: 3f5d336d64d6 ("arm64: dts: rockchip: Add support for rk3588s based board Cool Pi 4B") Signed-off-by: Yao Zi <ziyao@disroot.org> Link: https://lore.kernel.org/r/20250310140916.14384-2-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Downstream Linux, and consequently both downstream and mainline TF-A,
all use a different set of clock IDs from mainline Linux. If we want to
fiddle with these clocks through SCMI, we'll need to use the right IDs.
If we don't do this we'll end up changing unrelated clocks all over the
place.
Change the clock IDs to the newly added SCMI clock IDs for the CPU and
GPU nodes, which are currently the only ones using SCMI clocks. This
fixes the terrible GPU performance, as we weren't reclocking it
properly.
Fixes: 57b1ce903966 ("arm64: dts: rockchip: Add rk3576 SoC base DT") Reported-by: Jonas Karlman <jonas@kwiboo.se> Closes: https://libera.irclog.whitequark.org/linux-rockchip/2025-03-09#1741542223-1741542875; Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250310-rk3576-scmi-clocks-v1-2-e165deb034e8@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Mainline Linux uses different clock IDs from both downstream and
mainline TF-A, which both got them from downstream Linux. If we want to
control clocks through SCMI, we'll need to know about these IDs.
Add the relevant ones prefixed with SCMI_ to the header.
Jianfeng Liu [Tue, 11 Mar 2025 14:12:39 +0000 (22:12 +0800)]
arm64: dts: rockchip: Fix pcie reset gpio on Orange Pi 5 Max
According to the schematic, pcie reset gpio is GPIO3_D4,
not GPIO4_D4.
Fixes: c600d252dc52 ("arm64: dts: rockchip: Add Orange Pi 5 Max board") Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com> Reviewed-by: Jimmy Hon <honyuenkwun@gmail.com> Link: https://lore.kernel.org/r/20250311141245.2719796-1-liujianfeng1994@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Chen-Yu Tsai [Thu, 20 Feb 2025 16:50:51 +0000 (00:50 +0800)]
arm64: dts: rockchip: Remove bluetooth node from rock-3a
The Bluetooth node described in the device tree is actually on an M.2
slot. What module is present depends on what the end user installed,
and should be left to an overlay.
Remove the existing bluetooth node. This gets rid of bogus timeout
errors.
Fixes: 8cf890aabd45 ("arm64: dts: rockchip: Add nodes for SDIO/UART Wi-Fi/Bluetooth modules to Radxa Rock 3A") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/r/20250220165051.1889055-1-wens@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Jianfeng Liu [Tue, 11 Mar 2025 14:27:50 +0000 (22:27 +0800)]
arm64: dts: rockchip: Add AP6275P wireless support to ArmSoM Sige7
ArmSoM Sige7 uses the PCI-e AP6275P Wi-Fi 6 module. The pcie@0 node can
be used as Bridge1, so the wifi@0 node is used as a device under the
bridge 1 similar with Khadas Edge 2.
The Quality-of-Service (QsS) node stores/restores specific
register contents when the power domains is turned off/on.
Add QoS node so that they can connect to the power domain.
Patrick Wildt [Sun, 2 Mar 2025 20:08:24 +0000 (21:08 +0100)]
arm64: dts: rockchip: add MNT Reform 2 laptop
MNT Reform 2 is an open source laptop with replaceable CPU modules,
including a version with the RK3588-based MNT RCORE[1], which is based
on Firefly's iCore-3588Q SoM:
- Rockchip RK3588
- Quad A76 and Quad A55 CPU
- 6 TOPS NPU
- up to 32GB LPDDR4x RAM
- SD Card slot
- Gigabit ethernet port
- HDMI port
- 2x mPCIe ports for WiFi or NVMe
- 3x USB 3.0 Type-A HOST port
[1] https://shop.mntre.com/products/mnt-reform
Co-developed-by: "Lukas F. Hartmann" <lukas@mntre.com> Signed-off-by: "Lukas F. Hartmann" <lukas@mntre.com> Signed-off-by: Patrick Wildt <patrick@blueri.se> Link: https://lore.kernel.org/r/Z8S6uDM634KJuyKP@windev.fritz.box Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Jonas Karlman [Fri, 28 Feb 2025 06:40:10 +0000 (06:40 +0000)]
arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528
Add pinctrl and gpio nodes for RK3528 and import rk3528-pinctrl.dtsi
from vendor linux-6.1-stan-rkr5 kernel with the hdmi-pins-idle node
removed due to missing label reference to pcfg_output_low_pull_down.
Heiko Stuebner [Fri, 28 Feb 2025 15:08:53 +0000 (16:08 +0100)]
arm64: dts: rockchip: add usb typec host support to rk3588-jaguar
Jaguar has two type-c ports connected to fusb302 controllers that can
work both in host and device mode and can also run in display-port
altmode.
While these ports can work in dual-role data mode, they do not support
powering the device itself as power-sink. This causes issues because
the current infrastructure does not cope well with dual-role data
without dual-role power.
So add the necessary nodes for the type-c controllers as well as enable
the relevant core usb nodes. So far host modes works reliably, but
device-mode does not. So devicemode needs more investigation.
arm64: dts: rockchip: Add GPU power domain regulator dependency for RK3588
Enabling the GPU power domain requires that the GPU regulator is
enabled. The regulator is enabled at boot time, but gets disabled
automatically when there are no users.
This means the system might run into a failure state hanging the
whole system for the following use cases:
* if the GPU driver is being probed late (e.g. build as a
module and firmware is not in initramfs), the regulator
might already have been disabled. In that case the power
domain is enabled before the regulator.
* unbinding the GPU driver will disable the PM domain and
the regulator. When the driver is bound again, the PM
domain will be enabled before the regulator and error
appears.
Avoid this by adding an explicit regulator dependency to the
power domain.
Tested-by: Heiko Stuebner <heiko@sntech.de> Reported-by: Adrián MartÃnez Larumbe <adrian.larumbe@collabora.com> Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Jimmy Hon [Sat, 22 Feb 2025 19:33:30 +0000 (13:33 -0600)]
arm64: dts: rockchip: Add Orange Pi 5 Ultra board
The RK3588 Single Board Computer includes
- eMMC
- microSD
- UART
- 2 PWM LEDs
- RTC
- RTL8125 network controller on PCIe 2.0x1.
- M.2 M-key connector routed to PCIe 3.0x4
- PWM controlled heat sink fan.
- 2 USB2 ports
- lower USB3 port
- upper USB3 port with OTG capability
- Mali GPU
- SPI NOR flash
- Mask Rom button
- Analog audio using es8388 codec via the headset jack and onboard mic
- HDMI1
- HDMI IN
the vcc5v0_usb30 regulator shares the same enable gpio pin as the
vcc5v0_usb20 regulator.
The Orange Pi 5 Ultra is a single board computer powered by the Rockchip
RK3588 with similar board layout as the 5 Max but with the HDMI0 swapped
for HDMI IN.
Jimmy Hon [Sat, 22 Feb 2025 19:33:29 +0000 (13:33 -0600)]
dt-bindings: arm: rockchip: Add Xunlong Orange Pi 5 Ultra
Add devicetree binding for the Xunlong Orange Pi 5 Ultra board.
The Orange Pi 5 Ultra is a single board computer powered by the Rockchip
RK3588 with similar board layout as the 5 Max but with the HDMI0 swapped
for HDMI IN.
Jimmy Hon [Sat, 22 Feb 2025 19:33:28 +0000 (13:33 -0600)]
arm64: dts: rockchip: Adapt to differences between Orange Pi 5 Max and Ultra
The Orange Pi 5 Plus and Orange Pi 5 Max have 2SK3018s attached to the
PWM LEDs. The Orange Pi 5 Ultra does not, and thus needs the PWM
polarity inverted.
Also remove the model/compatible from the dtsi. It should be at the
board level only.
Detlev Casanova [Mon, 17 Feb 2025 21:47:41 +0000 (16:47 -0500)]
arm64: dts: rockchip: Add HDMI audio outputs for rk3588
For hdmi0_sound, use the simple-audio-card driver with the hdmi0 QP node
as CODEC and the i2s5 device as CPU.
Similarly for hdmi1_sound, the CODEC is the hdmi1 node and the CPU is
i2s6, but only added in the rk3588-extra.dtsi device tree as the second
TX HDMI port is not available on base versions of the SoC.
The simple-audio-card,mclk-fs value is set to 128 as it is done in
the downstream driver.
The #sound-dai-cells value is set to 0 in the hdmi0 and hdmi1 nodes so
that they can be used as audio codec nodes.
arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on RK3588
VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
more accurate pixel clock source to improve handling of display modes up
to 4K@60Hz on video ports 0, 1 and 2.
The HDMI1 PHY PLL clock source cannot be added directly to vop node in
rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an
optional feature and its PHY node belongs to a separate (extra) DT file.
Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its
clocks & clock-names properties in the extra DT file.
arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588
Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock
provider support"), the HDMI PHY PLL can be used as an alternative and
more accurate pixel clock source for VOP2 to improve display modes
handling on RK3588 SoC.
Add the missing #clock-cells property to allow using the clock provider
functionality of HDMI1 PHY.
Yao Zi [Mon, 17 Feb 2025 06:11:45 +0000 (06:11 +0000)]
arm64: dts: rockchip: Add clock generators for RK3528 SoC
Add dt node for RK3528 clock and reset unit. Clock "gmac0_clk" is
generated by internal Ethernet phy, a fixed clock node is added as a
placeholder to avoid orphans.
Yao Zi [Mon, 17 Feb 2025 06:11:42 +0000 (06:11 +0000)]
dt-bindings: clock: Document clock and reset unit of RK3528
There are two types of clocks in RK3528 SoC, CRU-managed and
SCMI-managed. Independent IDs are assigned to them.
For the reset part, differing from previous Rockchip SoCs and
downstream bindings which embeds register offsets into the IDs, gapless
numbers starting from zero are used.
Quentin Schulz [Tue, 18 Feb 2025 11:49:20 +0000 (12:49 +0100)]
arm64: dts: rockchip: disable I2C2 bus by default on RK3588 Tiger
RK3588 Tiger routes I2C2 signals to the Q7 Camera FFC connector (P2) but
nothing on the SoM itself is on that bus, therefore it'll be up to the
adapter connected to the Q7 Camera FFC connector (P2) to enable the I2C2
controller, if need be.
Quentin Schulz [Tue, 18 Feb 2025 11:49:19 +0000 (12:49 +0100)]
arm64: dts: rockchip: enable I2C3 in Haikou carrierboard, not Ringneck DTSI
PX30 Ringneck only exposes I2C3 as LVDS_BLC_CLK/DAT on Q7 golden fingers
but nothing is on that bus on the SoM itself. Therefore, let's enable
the I2C3 bus where it makes sense, in the Haikou carrierboard DTS.
Quentin Schulz [Tue, 18 Feb 2025 11:49:18 +0000 (12:49 +0100)]
arm64: dts: rockchip: enable Ethernet in Haikou carrierboard, not Puma DTSI
The signals are exposed on Q7 golden fingers but it's not a given that
the carrierboard will have an Ethernet jack. So let's move the enabling
of the Ethernet controller to the carrierboard DTS instead.
Quentin Schulz [Tue, 18 Feb 2025 11:49:17 +0000 (12:49 +0100)]
arm64: dts: rockchip: add EEPROM found on RK3399 Puma Haikou
The Haikou carrierboard has an EEPROM on LVDS_BLC_CLK/DAT which are
signals that can carry either I2C or be used as HPD for eDP0/1.
Only eDP0 is routed from RK3399 Puma SoM but only exposed on Haikou
through the Video Connector, a fake PCIe connector. So to be able to use
eDP one would need to use a Device Tree overlay. Therefore, let's
default to having an EEPROM in Haikou carrierboard DTS.
Quentin Schulz [Tue, 18 Feb 2025 11:49:16 +0000 (12:49 +0100)]
arm64: dts: rockchip: enable I2S0 in Haikou carrierboard, not Puma DTSI
I2S0 is routed to the Q7 golden fingers and, on Haikou carrierboard, to
an I2S codec. Nothing aside from signal routing is done on the SoM,
therefore it's the duty of the carrierboard to enable I2S0 whenever an
I2S codec is present.
Such is the case of the Haikou carrierboard, therefore let's migrate the
enabling of this controller to the carrierboard DTS instead of the SoM
DTSI.
Quentin Schulz [Tue, 18 Feb 2025 11:49:14 +0000 (12:49 +0100)]
arm64: dts: rockchip: move I2C6 from Haikou carrierboard to Puma DTSI
I2C6 is not exposed on Q7 golden fingers which is for routing signals to
the carrierboard but on Q7 Camera connector, for routing signals to an
additional adapter (e.g. Q7 Camera Demo adapter).
Therefore, let's move the modification of I2C6 bus to Puma DTSI.
Quentin Schulz [Tue, 18 Feb 2025 11:49:12 +0000 (12:49 +0100)]
arm64: dts: rockchip: enable UART5 on RK3588 Tiger Haikou
In its default configuration (SW2 on "UART1"), UART5 is exposed on the
DB9 RS232/RS485 connector. While the same signals are also exposed on
Q7_GPIO5 and Q7_GPIO6, a GPIO header, and thus could be used for other
purposes, RK3399 Puma Haikou and PX30 Ringneck Haikou do enable the UART
controller exposed on the DB9 connector, so let's keep consistency
across our modules and enable it on RK3588 Tiger Haikou by default too.
Add a comment while at it to explicit where this controller is routed
to.
Quentin Schulz [Fri, 21 Feb 2025 14:04:37 +0000 (15:04 +0100)]
arm64: dts: rockchip: add overlay for RK3399 Puma Haikou Video Demo adapter
This adds support for the video-demo-adapter DEVKIT ADDON CAM-TS-A01
(https://embedded.cherry.de/product/development-kit/) for the Haikou
devkit with RK3399 Puma SoM.
The Video Demo adapter is an adapter connected to the fake PCIe slot
labeled "Video Connector" on the Haikou devkit.
Its main feature is a Leadtek DSI-display with touchscreen and a camera
(that is not supported yet because the expected clock rate by the driver
cannot be exactly reached by the clock driver). To drive these
components a number of additional regulators are grouped on the adapter
as well as a PCA9670 gpio-expander to provide the needed additional
gpio-lines.
Quentin Schulz [Fri, 21 Feb 2025 14:04:36 +0000 (15:04 +0100)]
arm64: dts: rockchip: add overlay for PX30 Ringneck Haikou Video Demo adapter
This adds support for the video-demo-adapter DEVKIT ADDON CAM-TS-A01
(https://embedded.cherry.de/product/development-kit/) for the Haikou
devkit with PX30 Ringneck SoM.
The Video Demo adapter is an adapter connected to the fake PCIe slot
labeled "Video Connector" on the Haikou devkit.
Itss main feature is a Leadtek DSI-display with touchscreen and a camera
(that is not supported yet because the expected clock rate by the driver
cannot be exactly reached by the clock driver). To drive these
components a number of additional regulators are grouped on the adapter
as well as a PCA9670 gpio-expander to provide the needed additional
gpio-lines.
Quentin Schulz [Fri, 21 Feb 2025 14:04:35 +0000 (15:04 +0100)]
arm64: dts: rockchip: add support for HAIKOU-LVDS-9904379 adapter for PX30 Ringneck
The HAIKOU-LVDS-9904379 adapter is an adapter for PX30 Ringneck with the
Haikou carrierboard. It is to be inserted in the fake PCIe slot labelled
Video Connector.
This adapter expects an Admatec 9904379 1024x600 LVDS display with
backlight and touchscreen. An EEPROM is also found on the adapter.
This adds support for this adapter on PX30 Ringneck when inserted in
Haikou carrierboard.
Quentin Schulz [Tue, 11 Feb 2025 14:02:53 +0000 (15:02 +0100)]
arm64: dts: rockchip: minimal support for Pre-ICT tester adapter for RK3588 Jaguar
The Pre-ICT tester adapter connects to RK3588 Jaguar SBC through its
proprietary Mezzanine connector.
It exposes a PCIe Gen2 1x M.2 connector and two proprietary camera
connectors. Support for the latter will come once the rest of the camera
stack is supported.
Additionally, the adapter loops some GPIOs together as well as route
some GPIOs to power rails.
This adapter is used for manufacturing RK3588 Jaguar to be able to test
the Mezzanine connector is properly soldered.
Quentin Schulz [Tue, 11 Feb 2025 14:02:52 +0000 (15:02 +0100)]
arm64: dts: rockchip: add overlay tests for Rock 5B PCIe overlays
According to commit 40658534756f ("arm64: dts: rockchip: Add rock5b
overlays for PCIe endpoint mode"), Rock 5B can operate in PCIe endpoint
mode. For that to work, the rk3588-rock-5b-pcie-ep.dtbo overlay needs to
be applied on Rock 5B base Device Tree. If that Rock 5B is connected to
another Rock 5B, the latter needs to apply the
rk3588-rock-5b-pcie-srns.dtbo overlay.
In order to make sure the overlays are still valid in the future, let's
add a validation test by applying the overlays on top of the main base
at build time.
Quentin Schulz [Tue, 11 Feb 2025 14:02:51 +0000 (15:02 +0100)]
arm64: dts: rockchip: add overlay test for Edgeble NCM6A/NCM6B
The Edgeble NCM6A/NCM6B can have WiFi modules connected and this is
handled via an overlay (commit 951d6aaa37fe ("arm64: dts: rockchip: Add
Edgeble NCM6A WiFi6 Overlay")).
Despite the name of the overlay, it applies to both NCM6A and NCM6B[1].
In order to make sure the overlay is still valid in the future, let's
add a validation test by applying the overlay on top of the main bases
at build time.
Quentin Schulz [Tue, 11 Feb 2025 14:02:50 +0000 (15:02 +0100)]
arm64: dts: rockchip: add overlay test for WolfVision PF5
The WolfVision PF5 can have a PF5 Visualizer display and PF5 IO Expander
board connected to it. Therefore, let's generate an overlay test so the
application of the two overlays are validated against the base DTB.
Dragan Simic [Mon, 10 Feb 2025 20:17:00 +0000 (21:17 +0100)]
arm64: dts: rockchip: linewrap gmac assigned-clocks on Quartz64 Model A/B files a bit
Going over the 80-column width limit, and using all 100 columns, is intended
for improving code readability. This wasn't the case in a few places in the
Quartz64 Model A/B board dts files, so let's reflow them a bit, to both obey
the 80-column limit and make them a bit more readable.
No intended functional changes are introduced by these changes.
Chris Morgan [Thu, 30 Jan 2025 18:10:04 +0000 (12:10 -0600)]
arm64: dts: rockchip: remove rk3588 optee node
Remove Optee node from rk3588 devicetree. When Optee is present and
used the node will be added automatically by U-Boot when
CONFIG_OPTEE_LIB=y and CONFIG_SPL_ATF_NO_PLATFORM_PARAM is not set.
When Optee is not present or used, the node will trigger a probe
that generates a (harmless) message on the kernel log.
arm64: dts: rockchip: Add PHY node for HDMI1 TX port on RK3588
In preparation to enable the second HDMI output port found on RK3588
SoC, add the related PHY node. This requires a GRF, hence add the
dependent node as well.
Junhao Xie [Tue, 14 Jan 2025 00:14:11 +0000 (08:14 +0800)]
arm64: dts: rockchip: add dts for Ariaboard Photonicat RK3568
Add dts for Ariaboard Photonicat RK3568.
Partially based on downstream board dts. [1]
Working IO:
Debug UART
SDIO QCA9377 WiFi and Bluetooth
M.2 E-Key PCIe WiFi and Bluetooth
M.2 B-Key USB Modem WWAN
Ethernet WAN Port
MicroSD Card slot
eMMC
HDMI Output
Mali GPU
USB Type-A
Not working IO:
Ethernet LAN Port (Lack of SGMII support)
Power management MCU on UART4 (Driver pending)
Not working IO in MCU:
Battery voltage sensor
Board temperature sensor
Hardware Power-off
Hardware Watchdog
Network status LED
Real-time clock
USB Charger voltage sensor
About onboard power management MCU:
A heartbeat must be sent to the MCU within 60 seconds,
otherwise the MCU will restart the system.
When powering off, a shutdown command needs to be sent to the MCU.
When the power button is long pressed, the MCU will send a shutdown
command to the system. If system does not shutdown within 60 seconds,
the power will be turned off directly.
MCU only provides voltage for charger and battery.
Manufacturer removed RK8xx PMIC.
Alexey Charkov [Tue, 4 Feb 2025 09:02:28 +0000 (13:02 +0400)]
arm64: dts: rockchip: switch Rock 5C to PMIC-based TSHUT reset
Radxa Rock 5C supports both CRU-based (default) and PMIC-based reset
upon thermal runaway conditions. The former resets the SoC by internally
poking the CRU from TSADC, while the latter power-cycles the whole board
by pulling the PMIC reset line low in case of uncontrolled overheating.
Switch to a PMIC-based reset, as the more 'thorough' of the two.
Tested by temporarily setting rockchip,hw-tshut-temp to 65C to simulate
overheating - this causes the board to reset when any of the on-chip
temperature sensors surpasses the tshut temperature.
Damon Ding [Thu, 6 Feb 2025 03:03:30 +0000 (11:03 +0800)]
arm64: dts: rockchip: Fix label name of hdptxphy for RK3588
The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP
and eDP Link. Therefore, it is better to name it hdptxphy0 other than
hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes.
arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588
VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
more accurate pixel clock source to improve handling of display modes up
to 4K@60Hz on video ports 0, 1 and 2.
For now only HDMI0 output is supported, hence add the related PLL clock.
arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock
provider support"), the HDMI PHY PLL can be used as an alternative and
more accurate pixel clock source for VOP2 to improve display modes
handling on RK3588 SoC.
Add the missing #clock-cells property to allow using the clock provider
functionality of HDMI0 PHY.
Dragan Simic [Wed, 8 Jan 2025 04:26:45 +0000 (05:26 +0100)]
arm64: dts: rockchip: Use "dma-noncoherent" in base RK3588 SoC dtsi
The preferred way to denote hardware with non-coherent DMA is to use the
"dma-noncoherent" DT property, at both the GIC redistributor and the GIC ITS
levels, [1] instead of relying on the compatibles to handle hardware errata,
in this case the Rockchip 3588001 errata. [2]
Let's have the preferred way employed in the base Rockchip RK3588 SoC dtsi,
which also goes along with adding initial support for the Rockchip RK3582 SoC
variant, with its separate compatible. [2][3]
Dragan Simic [Mon, 2 Dec 2024 14:44:06 +0000 (15:44 +0100)]
arm64: dts: rockchip: Describe why is HWRNG disabled in RK356x base dtsi
Despite the presence of the hardware random number generator (HWRNG) in the
different Rockchip RK356x SoC variants, it remains disabled for the RK3566
SoC because testing showed [1] that it produces unacceptably low quality of
random data, for some yet unknown reason. The HWRNG is enabled for the RK3568
SoC, on which the testing showed good quality of the generated random data.
To avoid possible confusion in the future, [2] let's have this described
briefly in the RK356x base SoC dtsi.
projects / thirdparty / linux.git / log
