Carl Love [Wed, 17 May 2017 20:09:46 +0000 (20:09 +0000)]
PPC64, ISA 3.0 fixes
- Fix mffs instruction, FPSCR, C_FPCC field access is not
working correctly.
- Fix xscmpexpdp again still had a bug.
- Remove duplicate tests from test_isa_3_0.c
- Comment out he tests for the new ISA 3.0B instructions. There
seem to be some issues between the simulator and early HW that
need to be sorted out.
Petar Jovanovic [Tue, 16 May 2017 15:21:35 +0000 (15:21 +0000)]
mips: rewrite parts of mips_dirtyhelper_rdhwr
The idea behind this change is to be less dependent on build-flags, and
more dependent on runtime environment.
So, if the code is compiled for mips32r1, it should be able to execute
mips32r2 code if the platforms supports it.
Ivo Raisr [Tue, 16 May 2017 07:59:31 +0000 (07:59 +0000)]
Reduce the number of compiler warnings on MIPS platforms
Partial fix for BZ#370028
Slightly modified patch by: Tamara Vlahovic <tamara.vlahovic@imgtec.com>
Julian Seward [Tue, 16 May 2017 06:26:48 +0000 (06:26 +0000)]
arm64-linux: detect Cavium CPUs (implementer = 0x43) and enable the
fallback LLSC implementation in that case. Pertains to bug #369459.
(VEX side changes)
Julian Seward [Thu, 11 May 2017 14:28:10 +0000 (14:28 +0000)]
Bug 371491 - handleAddrOverrides() is truncating the segment base address when ASO prefix is used.
Patch from Michael Daniels (mdaniels@blackberry.com).
Carl Love [Wed, 3 May 2017 17:24:55 +0000 (17:24 +0000)]
PPC64 ISA 3.0B, add support for the additional instructions: addex, mffscdrn,
mffscdrni, mffsce, mffscrn, mffscrni, mffsl. vmsumudm.
Additionally, the OV32 and CA32 bits were introduced in ISA 3.0 but
Valgrind add support for setting these bits for ISA 3.0. The OV32 and CA32
bits must now be set on a number of pre ISA 3.0 instructions. So now the
instructions produce different results in the XER register. Thus we need pre
and post ISA 3.0 expect files. Command line options were added to thee
pre ISA test cases so instructions that didn't change could be run with one
set of command line args. The instructions that have different XER results
are run using a different set of command line args. The tests were split into
two, one for instructions that didn't change on for instructions that do
change under ISA 3.0. We then create ISA3.0 expect files only for the tests
that run differently. By doing this we minimized the size of the expect files
needed.
Petar Jovanovic [Tue, 25 Apr 2017 14:40:54 +0000 (14:40 +0000)]
mips: limit cvt.s.l instruction translation to fp_mode64
The documentation says:
"For CVT.S.L, the result of this instruction is UNPREDICTABLE if the
processor is executing in the FR=0 32-bit FPU register model; it is
predictable if executing on a 64-bit FPU in the FR=1 mode, but not with
FR=0, and not on a 32-bit FPU."
Bug 369459 - valgrind on arm64 violates the ARMv8 spec (ldxr/stxr)
This implements a fallback LL/SC implementation as described in bug 344524.
The fallback implementation is not enabled by default, and there is no
auto-detection for when it should be used. To use it, run with the
flag --sim-hints=fallback-llsc. This commit also allows the existing
MIPS fallback implementation to be enabled with that flag.
VEX side changes:
* priv/main_main.c, pub/libvex.h
Adds new field guest__use_fallback_LLSC to VexAbiInfo
Petar Jovanovic [Wed, 12 Apr 2017 17:51:45 +0000 (17:51 +0000)]
fix early initialization of s390_host_hwcaps in LibVEX_FrontEnd
This is a follow-up to r3341 and r3344. r3341 split LibVEX_Translate into
LibVEX_FrontEnd and LibVEX_BackEnd. s390_host_hwcaps needs to be initialized
early when arch_host is VexArchS390X.
This also fixes none/tests/libvexmultiarch_test on MIPS64 BE platforms.
Mark VPMULHRSW ymm3/m256, ymm2, ymm1 as a "verbose instruction". This
pertains to failures documented at https://bugs.kde.org/show_bug.cgi?id=375839
comments 10 to 18.
Mark Wielaard [Tue, 4 Apr 2017 12:02:14 +0000 (12:02 +0000)]
Initialize s390_host_hwcaps early in LibVEX_FrontEnd.
VEX svn r3341 split LibVEX_Translate into LibVEX_FrontEnd and
LibVEX_BackEnd. The s390_host_hwcaps (KLUDGE) needs to be initialized
early in LibVEX_FrontEnd.
Petar Jovanovic [Mon, 3 Apr 2017 14:30:13 +0000 (14:30 +0000)]
mips64: sign-extend results from dirty helper
Values returned from the dirty helper may not be sign-extended, so let's
make sure the values get passed as sign-extended for Ity_I32, Ity_I16, and
Ity_I8 cases.
At the same time, we can remove now redundant sign-extensions introduced in
VEX r3304.
This fixes memcheck/test/bug340392 on some MIPS64 boards.
Split LibVEX_Translate into front- and back-end parts. Also, removes use
of __typeof__ when built with MSVC. A combination of parts of two patches
from Andrew Dutcher <andrewrdutcher@gmail.com>.
x86 guest: switch descriptor table registers to ULong type so they will take up
consistent amount of space (VEX side). Andrew Dutcher <andrewrdutcher@gmail.com>.
Julian Seward [Wed, 29 Mar 2017 16:13:35 +0000 (16:13 +0000)]
Add a mechanism for hinting to the core disassembler loop, that the
just-disassembled instruction is very verbose. This allows dynamic changes to
the maximum number of guest instructions allowed in the current IRSB.
Fixes #375839.
This is in support of "Bug 375839 - Temporary storage exhausted, when long
sequence of vfmadd231ps instructions to be executed", and reduces code size by
around 3% in that case.
Julian Seward [Mon, 27 Mar 2017 18:32:10 +0000 (18:32 +0000)]
Rewrite dis_FMA so it generates not-quite-so-terrible code. It's still terrible
(breaks vectors into scalars) but this rewrite does it in a way which makes it
interact better with put-to-get forwarding. It also removes all the
Iop_Reinterp casting involved. For long sequences of FMA instructions this
reduces the amount of memcheck-generated code to about 75% of what it was
before. Improves the situation for
Bug 375839 - Temporary storage exhusted , when long sequence of vfmadd231ps instructions to be executed
but isn't a convincing fix.
Ivo Raisr [Fri, 24 Mar 2017 13:46:15 +0000 (13:46 +0000)]
Use consistently chase1() in MSVC specific transformation hacks.
This code is experimental and not used by default but should be self-consistent.
n-i-bz
The lfdpx, stdpx, lfdp and stfdp instructions work on a register pair. The
register pair test must only be applied to these instructions in the
dis_fp_pair() function.
Petar Jovanovic [Mon, 13 Feb 2017 16:15:24 +0000 (16:15 +0000)]
mips64: do correct 32-bit comparison for Iop_CmpNE32
Make sure that we take into account 32-bit size of values in comparison
on MIPS64-platforms. This is done either by sign extending these values
before comparison or sign extending xored values (depending on what
comparison we do). This should avoid false-positives like the one
reported in BZ #341481.
Patch based on code provided by Crestez Dan Leonard and Tamara Vlahovic.
Petar Jovanovic [Fri, 10 Feb 2017 17:58:40 +0000 (17:58 +0000)]
mips: rewrite mips_irgen_load_and_add32|64 and code around it
Make sure that mips_irgen_load_and_add32 gets both expected value and
new value, so the function code makes more sense and does load/store in
a atomic way.
Julian Seward [Mon, 16 Jan 2017 05:14:24 +0000 (05:14 +0000)]
dis_neon_data_3same: don't silently accept invalid instructions. Instead,
"return False" for any instruction not accepted by this function. Also,
add a few switch default backstops.
Carl Love [Mon, 7 Nov 2016 19:41:30 +0000 (19:41 +0000)]
Fix xxsel parsing error.
The xxsel instruction uses part of the standard opc2 field to specify
a additional operand or other values. A subset of the field is used for
the actual opcode. The masking and array lookup was getting confused by
bits in the the additional operand field. The arrays were split so only
the opcodes that should be found for a given mask is in the array. This
also speeds up the search as you are not searching through values that
cannot match. The small groups of opcodes for a couple of the masks are
now done in a case statement as that is probably faster then doing an array
look up.
Julian Seward [Wed, 19 Oct 2016 16:57:11 +0000 (16:57 +0000)]
Allow early writeback of SP base register in "strd rD, [sp, #-16]" so
as to avoid Memcheck complaining about writes below SP. Previously
this was allowed only for the #-8 case. n-i-bz.
Carl Love [Tue, 18 Oct 2016 15:52:09 +0000 (15:52 +0000)]
Fix PPC BE in 32-bit mode.
The 64-bit compares are not supported in 32-bit mode. Change the 64-bit
compares to 32-bit compares when doing byte compares. Add routine for
doing V128 GT compare using 32-bit compares.
The clean caller support was missing for 32-bit mode
Update the expected output file jm_vec_isa_2_07.stdout.exp
Carl Love [Fri, 7 Oct 2016 22:53:52 +0000 (22:53 +0000)]
ISA 3.0 BE fixes for various new instructions
This is an additional commit to fix issues found with the
new Power ISA 3.0 instructions for BE mode. The instructions
fixed in this patch include: lxvl, lxvx, lxvwsx, lxvh8x, lxvh16x,
stxvx, stxvh8x, stxvh16x, lxsibzx, lxsihzx, xscvqpdp, xscvqpdp0,
xvcvsphp.
Carl Love [Mon, 3 Oct 2016 15:30:46 +0000 (15:30 +0000)]
Fix rounding mode check and instruction stxvl
In BE mode, the function FPU_rounding_mode_isOdd() has the assert
vassert(mode->Iex.Const.con->Ico.U8 == 0x8);
The value was set using mkU32 but in BE mode the U8 maps to the upper
bits in the memory location not the lower bits. The comparison was
fixed by changing the .U8 to .U32 to be consistent with how the field
was set.
The stxvl instruction called the 64-bit NOT not the 128-bit NOT when
calculating the store_val.
The stxvx instruction the temp word values were initialized I32 not I64.
Not sure why this wasn't caught on LE.
Julian Seward [Fri, 19 Aug 2016 11:47:59 +0000 (11:47 +0000)]
Add a dummy initialisation and a dummy path to avoid warnings with gcc -Og.
Neither are actually necessary, but gcc's flow analysis at -Og is weaker than
at -O or above and so it produces false warnings here. No functional change.
Most of these instructions required adding a new Iop as they could not
be emulated with existing Iops. In some cases, some of the above instrctions
could be emulated using another instruction from the above list.
Most of the instructions add support for 128-bit instructions. There are a
number of helper functions that check a values for zero, infinity, NaN, etc.
for various sizes. The new 128-bit instructions require a new version of these
existing functions for a 128-bit operand. Rather then adding another size
specific version of these functions, the existing size specific functions were
replaced with a single function that takes the size of operand to be operated
on. There are some additional helper functions that are added to support
the size independent version of these functions.
Note this is the last of the 5 patches required to complete the ISA 3.0
support.
Julian Seward [Wed, 3 Aug 2016 11:53:11 +0000 (11:53 +0000)]
arm32 backend stuff needed to support IR artefacts resulting from
guest support of 32-bit V8 crypto instructions:
* add new pseudo-instruction ARMin_VXferQ, to move values between
two D regs and a Q reg, in either direction. Use this to implement
Iop_64HLtoV128 much more efficiently than before, and to implement
Iop_V128HIto64 and Iop_V128to64.
* Generate code for helper calls in which have four or more
(32-bit) word-sized arguments and a V128 return value.
These require passing arguments on the stack.
dis_neon_data_3same: for the case A==12, don't silently produce invalid IR
which then causes the sanity checker to abort the run. Instead synthesise
a SIGILL in the normal way.
projects / thirdparty / valgrind.git / log
