Dmitry Baryshkov [Tue, 13 Jan 2026 16:41:59 +0000 (18:41 +0200)]
arm64: dts: qcom: agatti: enable FastRPC on the ADSP
On Agatti platform the ADSP provides FastRPC support. Add corresponding
device node, in order to be able to utilize the DSP offload from the
Linux side.
Viken Dadhaniya [Tue, 11 Nov 2025 17:03:50 +0000 (22:33 +0530)]
arm64: dts: qcom: talos: Drop opp-shared from QUP OPP table
QUP devices are currently marked with opp-shared in their OPP table,
causing the kernel to treat them as part of a shared OPP domain. This
leads to the qcom_geni_serial driver failing to probe with error
-EBUSY (-16).
Remove the opp-shared property to ensure the OPP framework treats the
QUP OPP table as device-specific, allowing the serial driver to probe
successfully
Abel Vesa [Wed, 24 Dec 2025 10:45:21 +0000 (12:45 +0200)]
arm64: dts: qcom: hamoa: Add the APSS watchdog
The watchdog support in EL1 is SBSA compliant, handled by Gunyah
hypervisor, but in EL2. the watchdog is an instance of the APSS WDT HW
block, same as older platforms. So describe the APSS WDT node and mark
it as reserved, as it will only be enabled in EL2 overlay.
Luca Weiss [Tue, 28 Oct 2025 16:40:49 +0000 (17:40 +0100)]
arm64: dts: qcom: msm8953: Re-sort tlmm pinctrl states
Follow the Devicetree Sources Coding Style and sort the pinctrl nodes by
the pins property. This makes it simpler to add new pinctrl states in
the future.
Jingyi Wang [Fri, 31 Oct 2025 07:41:44 +0000 (00:41 -0700)]
dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur Platforms
Document the Inter-Processor Communication Controller on the Qualcomm
Kaanapali and Glymur Platforms, which will be used to route interrupts
across various subsystems found on the SoC.
Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20251031-knp-ipcc-v3-1-62ffb4168dff@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The Thinkpad T14s embeds a transparent 4lanes DP->HDMI transceiver
connected to the third QMP Combo PHY 4 lanes.
Add all the data routing, disable mode switching and specify the
QMP Combo PHY should be in DP-Only mode to route the 4 lanes to
the underlying DP phy.
Jonathan Marek [Thu, 27 Nov 2025 21:29:42 +0000 (16:29 -0500)]
arm64: dts: qcom: x1e: bus is 40-bits (fix 64GB models)
Unlike the phone SoCs this was copied from, x1e has a 40-bit physical bus.
The upper address space is used to support more than 32GB of memory.
This fixes issues when DMA buffers are allocated outside the 36-bit range.
Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251127212943.24480-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Mukesh Ojha [Mon, 5 Jan 2026 13:23:02 +0000 (18:53 +0530)]
arm64: dts: qcom: lemans; Add EL2 overlay
All the Lemans IOT variants boards are using Gunyah hypervisor which
means that, so far, Linux-based OS could only boot in EL1 on those
devices. However, it is possible for us to boot Linux at EL2 on these
devices [1].
When running under Gunyah, the remote processor firmware IOMMU streams
are controlled by Gunyah. However, without Gunyah, the IOMMU is managed
by the consumer of this DeviceTree. Therefore, describe the firmware
streams for each remote processor.
Add a EL2-specific DT overlay and apply it to Lemans IOT variant
devices to create -el2.dtb for each of them alongside "normal" dtb.
arm64: dts: qcom: sdm845-db845c: drop CS from SPIO0
On SDM845 SPI uses hardware-provided chip select, while specifying
cs-gpio makes the driver request GPIO pin, which on DB845c conflicts
with the normal host controllers pinctrl entry.
Drop the cs-gpios property to restore SPI functionality.
Fixes: cb29e7106d4e ("arm64: dts: qcom: db845c: Add support for MCP2517FD") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260106-wcn3990-pwrctl-v2-7-0386204328be@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Follow commit 9c92d36b0b1e ("arm64: dts: qcom: qrb2210-rb1: Fix UART3
wakeup IRQ storm") and apply the similar fix to the RB2 platform.
Having RX / TX pins as pull up and wakup interrupt as high-level
triggered generates an interrupt storm when trying to suspend the
device. Avoid the storm by using the falling edge trigger (as all other
platforms do).
Yuanjie Yang [Thu, 8 Jan 2026 09:25:41 +0000 (17:25 +0800)]
arm64: dts: qcom: talos: switch to interrupt-cells 4 to add PPI partitions
The ARM PMUs shares the same per-cpu (PPI) interrupt, so we need to switch
to interrupt-cells = <4> in the GIC node to allow adding an interrupt
partition map phandle as the 4th cell value for GIC_PPI interrupts.
arm64: dts: qcom: ipq5018: Correct USB DWC3 wrapper interrupts
Interrupts for DWC3 node were completely mixed up - SPI interrupt 62 is
not listed in reference manual at all. It was also causing dtbs_check
warnings:
ipq5018-rdp432-c2.dtb: usb@8af8800 (qcom,ipq5018-dwc3): interrupt-names:0: 'pwr_event' was expected
ipq5018-rdp432-c2.dtb: usb@8af8800 (qcom,ipq5018-dwc3): interrupt-names: ['hs_phy_irq'] is too short
Warning itself was introduced by commit 53c6d854be4e ("dt-bindings: usb:
dwc3: Clean up hs_phy_irq in binding"), but this was trying to bring
sanity to the interrupts overall, although did a mistake for IPQ5018.
IPQ5018 does not have QUSB2 PHY and its interrupts should rather match
ones used in IPQ5332.
Correct it by using interrupts matching the bindings and reference
manual.
Ziyue Zhang [Fri, 9 Jan 2026 10:45:04 +0000 (18:45 +0800)]
arm64: dts: qcom: Add PCIe3 and PCIe5 regulators for HAMAO-IOT-EVK board
HAMAO IoT EVK uses PCIe5 to connect an SDX65 module for WWAN functionality
and PCIe3 to connect a SATA controller. These interfaces require multiple
voltage rails: PCIe5 needs 3.3V supplied by vreg_wwan, while PCIe3 requires
12V, 3.3V, and 3.3V AUX rails, controlled via PMIC GPIOs.
Add the required fixed regulators with related pin configuration, and
connect them to the PCIe3 and PCIe5 ports to ensure proper power for the
SDX65 module and SATA controller.
Move reset and wake GPIO properties from RC nodes to port nodes.
Ziyue Zhang [Fri, 9 Jan 2026 10:45:03 +0000 (18:45 +0800)]
arm64: dts: qcom: Add PCIe3 and PCIe5 support for HAMOA-IOT-SOM platform
HAMOA IoT SOM requires PCIe3 and PCIe5 connectivity for SATA controller
and SDX65.
Add the required sideband signals (PERST#, WAKE#, CLKREQ#), pinctrl states
and power supply properties in the device tree, which PCIe3 and PCIe5
require.
Ziyue Zhang [Fri, 9 Jan 2026 10:45:02 +0000 (18:45 +0800)]
arm64: dts: qcom: hamoa: Move PHY, PERST, and Wake GPIOs to PCIe port nodes and add port Nodes for all PCIe ports
Since describing the PCIe PHY directly under the RC node is now
deprecated, move the references to the respective PCIe port nodes,
creating them where necessary.Also add port nodes for PCIe5 and PCIe6a
with proper PHY references.
And also move the PCIe PERST and wake GPIOs from the controller nodes to
the corresponding PCIe port nodes on Hamoa-based platforms:
Richard Acayan [Fri, 9 Jan 2026 14:03:59 +0000 (17:03 +0300)]
arm64: dts: qcom: sdm630: Add LPASS LPI TLMM
The LPASS LPI TLMM pin controller controls pins for use by the analog
and digital codecs, such as the PDM bus, the digital microphone pins,
and the compander pins. Add it to support the codecs.
Platforms with this SoC using AudioReach won't be impacted due to
qcs6490-audioreach.dtsi already setting clocks & clock-names for
q6prmcc. The sc7280-chrome-common.dtsi has also been adjusted to keep
the behavior the same as they also do not use Elite with q6afecc.
Konrad Dybcio [Fri, 27 Jun 2025 19:37:55 +0000 (21:37 +0200)]
arm64: dts: qcom: qcs615: Drop IPA interconnects
In the same spirit as e.g. Commit 6314184be391 ("arm64: dts: qcom:
sc8180x: Drop ipa-virt interconnect") drop the resources that should
be taken care of through the clk-rpmh driver.
Xiangxu Yin [Tue, 4 Nov 2025 01:33:25 +0000 (09:33 +0800)]
arm64: dts: qcom: talos: Add DisplayPort and QMP USB3-DP PHY
Introduce DisplayPort controller node and associated QMP USB3-DP PHY
for SM6150 SoC. Add data-lanes property to the DP endpoint and update
clock assignments for proper DP integration.
Add Iris video codec to SM8750 SoC, which comes with significantly
different powering up sequence than previous SM8650, thus different
clocks and resets. For consistency keep existing clock and clock-names
naming, so the list shares common part.
Luca Weiss [Wed, 10 Dec 2025 01:43:29 +0000 (10:43 +0900)]
arm64: dts: qcom: pm8550vs: Disable different PMIC SIDs by default
Keep the different PMIC definitions in pm8550vs.dtsi disabled by
default, and only enable them in boards explicitly.
This allows to support boards better which only have pm8550vs_c, like
the Milos/SM7635-based Fairphone (Gen. 6).
Note: I assume that at least some of these devices with PM8550VS also
don't have _c, _d, _e and _g, but this patch is keeping the resulting
devicetree the same as before this change, disabling them on boards that
don't actually have those is out of scope for this patch.
arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1.
PCIe0 is routed to an m.2 E key connector on the mainboard for wifi
attaches while PCIe1 routes to a standard PCIe x4 expansion slot.
Hence, enable the PCIe0 and PCIe1 controller and phy-nodes.
Bindings always required "qcom,num-ees" and "num-channels" properties,
as reported by dtbs_check:
sm8750-mtp.dtb: dma-controller@1dc4000 (qcom,bam-v1.7.4): 'anyOf' conditional failed, one must be fixed:
'qcom,powered-remotely' is a required property
'num-channels' is a required property
'qcom,num-ees' is a required property
'clocks' is a required property
'clock-names' is a required property
However since commit 5068b5254812 ("dmaengine: qcom: bam_dma: Fix DT
error handling for num-channels/ees") missing properties are actually
fatal and BAM does not probe:
bam-dma-engine 1dc4000.dma-controller: num-channels unspecified in dt
bam-dma-engine 1dc4000.dma-controller: probe with driver bam-dma-engine failed with error -22
Abhinaba Rakshit [Wed, 24 Dec 2025 08:33:02 +0000 (14:03 +0530)]
arm64: dts: qcom: monaco: add QCrypto node
Add Qualcomm Crypto Engine device node for Monaco platform.
QCE and Crypto DMA nodes patch was applied as part of
commit a86d84409947 ("arm64: dts: qcom: qcs8300: add QCrypto nodes"),
however was partially reverted by commit cdc117c40537 ("arm64: dts: qcom:
qcs8300: Partially revert "arm64: dts: qcom: qcs8300: add QCrypto nodes"")
due to compatible string being mismatched against schema.
Abhinaba Rakshit [Wed, 24 Dec 2025 10:20:24 +0000 (15:50 +0530)]
arm64: dts: qcom: lemans: add QCrypto node
Add Qualcomm Crypto Engine device node for LeMans platform.
QCE and Crypto DMA nodes patch was applied as part of the
commit 7ff3da43ef44 ("arm64: dts: qcom: sa8775p: add QCrypto nodes"),
however was partially reverted by commit 92979f12a201 ("arm64: dts: qcom:
sa8775p: Partially revert "arm64: dts: qcom: sa8775p: add QCrypto nodes"")
due to compatible-string being miss-matched against schema.
Per the agreement, the firmware paths (even for devices not supported in
linux-firmware) should follow the SoC/Vendor/device pattern. Update
firmware names for Medion SPRCHRGD 14 S1 to follow that pattern.
Fixes: 8cf65490cdb0 ("arm64: dts: qcom: Add dts for Medion SPRCHRGD 14 S1") Cc: Georg Gottleuber <ggo@tuxedocomputers.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251224-fix-medion-v1-1-305747dff79a@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arm64: dts: qcom: msm8994-octagon: Fix Analog Devices vendor prefix of AD7147
Trivial change, Analog Devices vendor prefix is "adi", but there is
a valid "ad" vendor prefix of another company, this may explain why
the issue hasn't been discovered by the automatic tests.
A problem of not described compatible value is out of this change scope.
Fixes: c636eeb751f6 ("arm64: dts: qcom: msm8994-octagon: Add AD7147 and APDS9930 sensors") Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251226003923.3341904-1-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Abel Vesa [Wed, 24 Dec 2025 10:53:29 +0000 (12:53 +0200)]
arm64: dts: qcom: x1e80100: Add missing TCSR ref clock to the DP PHYs
The DP PHYs on X1E80100 need the ref clock which is provided by the
TCSR CC.
The current X Elite devices supported upstream work fine without this
clock, because the boot firmware leaves this clock enabled. But we should
not rely on that. Also, even though this change breaks the ABI, it is
needed in order to make the driver disables this clock along with the
other ones, for a proper bring-down of the entire PHY.
So lets attach it to each of the DP PHYs in order to do that.
Vincent Knecht [Sun, 4 Jan 2026 18:31:53 +0000 (19:31 +0100)]
arm64: dts: qcom: msm8939: Add camss and cci
Add the camera subsystem and CCI used to interface with cameras on the
Snapdragon 615.
Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
[André: Make order of items the same as in 8916] Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: André Apitzsch <git@apitzsch.eu> Link: https://lore.kernel.org/r/20260104-camss-8x39-vbif-v9-1-0d47c7afbb2f@apitzsch.eu Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add a node for the TC9563 PCIe switch, which has three downstream ports.
Two embedded Ethernet devices are present on one of the downstream ports.
As all these ports are present in the node represent the downstream
ports and embedded endpoints.
Power to the TC9563 is supplied through two LDO regulators, controlled by
two GPIOs, which are added as fixed regulators. Configure the TC9563
through I2C.
Abel Vesa [Mon, 3 Nov 2025 16:51:40 +0000 (18:51 +0200)]
arm64: dts: qcom: x1e80100: Fix USB combo PHYs SS1 and SS2 ref clocks
It seems the USB combo SS1 and SS2 ref clocks have another gate, unlike
the SS0. These gates are part of the TCSR clock controller.
At least on Dell XPS 13 (9345), if the ref clock provided by the TCSR
clock controller for SS1 PHY is disabled on the clk_disable_unused late
initcall, the PHY fails to initialize. It doesn't happen on the SS0 PHY
and the SS2 is not used on this device.
This doesn't seem to be a problem on CRD though. It might be that the
RPMh has a vote for it from some other consumer and does not actually
disable it when ther kernel drops its vote.
Either way, these TCSR provided clocks seem to be the correct ones for
the SS1 and SS2, so use them instead.
Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251103-dts-qcom-x1e80100-fix-combo-ref-clks-v1-1-f395ec3cb7e8@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
In order to enable CDSP support for SDM660 SoC:
* add shared memory p2p nodes for CDSP
* add CDSP-specific smmu node
* add CDSP peripheral image loader node
Memory region for CDSP in SDM660 occupies the same spot as
TZ buffer mem defined in sdm630.dtsi (which does not have CDSP).
In sdm660.dtsi replace buffer_mem inherited from SDM630 with
cdsp_region, which is also larger in size.
SDM636 also doesn't have CDSP, so remove inherited from sdm660.dtsi
related nodes and add buffer_mem back.
Yongxing Mou [Wed, 12 Nov 2025 04:21:23 +0000 (12:21 +0800)]
arm64: dts: qcom: hamoa-iot-evk: Add backlight support for eDP panel
The backlight on the Hamoa IoT EVK is controlled through a PWM signal.
Aligned with other x1e80100-based platforms: the PWM signal is controlled
by PMK8550, and the backlight enable signal is handled by PMC8380.
Describe the backlight device and connect it to the eDP panel to allow
for brightness control.
Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251112-hamoa_dvt_backlight-v3-1-f35b44af7fc4@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Add RED and GREEN LED channels for the RGB device connected to PMC8380C
PWM-LED pins. Omit BLUE channel to match default hardware setup where
it's tied to EDL indicator.
Casey Connolly [Tue, 18 Nov 2025 14:52:25 +0000 (15:52 +0100)]
arm64: dts: qcom: sdm845-oneplus: Don't mark ts supply boot-on
The touchscreen isn't enabled by bootloader and doesn't need to be
enabled at boot, only when the driver probes, thus remove the
regulator-boot-on property.
If the OS does not support recovering the state left by the
bootloader it needs a way to reset display hardware, so that it can
start from a clean state. Add a reference to the relevant reset.
It fixes display init issue appeared in Linux v6.17: without reset
device boots into black screen and you need to turn display off/on
to "fix" it. Also sometimes it can boot into solid blue color
with these messages in kernel log:
hw recovery is not complete for ctl:2
[drm:dpu_encoder_phys_vid_prepare_for_kickoff:569] [dpu error]enc33
intf1 ctl 2 reset failure: -22
[drm:dpu_encoder_frame_done_timeout:2727] [dpu error]enc33 frame
done timeout
Riccardo Mereu [Thu, 20 Nov 2025 15:58:25 +0000 (16:58 +0100)]
arm64: dts: qcom: qrb2210: add dts for Arduino unoq
Arduino UnoQ is a single-board computer combining Qualcomm
Dragonwing™ QRB2210 microprocessor with STMicroelectronics STM32U585
microcontroller.
Support to a simply boot to shell environment includes:
- UART, I2C, SPI
- onboard LEDS
- eMMC
- WLAN and BT
Krishna Kurapati [Fri, 28 Nov 2025 10:25:07 +0000 (15:55 +0530)]
arm64: dts: qcom: lemans-evk: Add OTG support for primary USB controller
Enable OTG support for primary USB controller on EVK Platform. Add
HD3SS3220 Type-C port controller present between Type-C port and SoC
that provides role switch notifications to controller.
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