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Julian Seward [Sun, 24 Jun 2012 12:12:20 +0000 (12:12 +0000)]

Implement more AVX insns:

VPCMPGTB = VEX.NDS.128.66.0F.WIG 64 /r
VPCMPGTW = VEX.NDS.128.66.0F.WIG 65 /r
VCMPPD ymm3/m256(E=argL), ymm2(V=argR), ymm1(G)
VCMPPS xmm3/m128(E=argL), xmm2(V=argR), xmm1(G)
VCMPPS ymm3/m256(E=argL), ymm2(V=argR), ymm1(G)
VADDSUBPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D0 /r
VADDSUBPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG D0 /r
VADDSUBPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.F2.0F.WIG D0 /r
VADDSUBPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.F2.0F.WIG D0 /r
VPMADDWD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG F5 /r
VPMULDQ xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 28 /r

(Jakub Jelinek, jakub@redhat.com), #273475 comment 132.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2404

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Julian Seward [Sun, 24 Jun 2012 11:09:37 +0000 (11:09 +0000)]

VROUND{PS,PD}: fix incorrect comments.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2403

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Petar Jovanovic [Fri, 22 Jun 2012 12:36:19 +0000 (12:36 +0000)]

Fix for incorrectly passed params to IRExpr_Mux0X in MIPS port.

Input params to IRExpr_Mux0X have swapped positions in a few places inside
disInstr_MIPS_WRK(). This patch fixes none/tests/mips32/MoveIns.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2402

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Julian Seward [Fri, 22 Jun 2012 09:27:54 +0000 (09:27 +0000)]

Implement (inexplicably missing) UHADD16.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2401

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Julian Seward [Thu, 21 Jun 2012 09:17:58 +0000 (09:17 +0000)]

Add support for

VPSUBSB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E8 /r
VPSUBSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E9 /r
VROUNDPS imm8, xmm3/m128, xmm2, xmm1
VROUNDPS imm8, ymm3/m256, ymm2, ymm1
VROUNDPD imm8, xmm3/m128, xmm2, xmm1
VROUNDPD imm8, ymm3/m256, ymm2, ymm1
VROUNDSS imm8, xmm3/m32, xmm2, xmm1
VROUNDSD imm8, xmm3/m64, xmm2, xmm1

(Jakub Jelinek, jakub@redhat.com), #273475 comment 130.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2400

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Julian Seward [Thu, 21 Jun 2012 09:08:19 +0000 (09:08 +0000)]

Add support for

VPSRLW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D1 /r
VPSRLD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D2 /r
VPSRLQ xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D3 /r
VPSRAW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E1 /r
VPSRAD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E2 /r
VPSLLW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG F1 /r
VPSLLD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG F2 /r
VPSLLQ xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG F3 /r
VBLENDVPS xmmG, xmmE/memE, xmmV, xmmIS4
VBLENDVPS ymmG, ymmE/memE, ymmV, ymmIS4
VBLENDVPD xmmG, xmmE/memE, xmmV, xmmIS4
VBLENDVPD ymmG, ymmE/memE, ymmV, ymmIS4

(Jakub Jelinek, jakub@redhat.com), #273475 comment 129.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2399

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Julian Seward [Thu, 21 Jun 2012 08:53:48 +0000 (08:53 +0000)]

Add support for

VTESTPS xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 0E /r
VTESTPS ymm2/m256, ymm1 = VEX.256.66.0F38.WIG 0E /r
VTESTPD xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 0F /r
VTESTPD ymm2/m256, ymm1 = VEX.256.66.0F38.WIG 0F /r
VPTEST xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 17 /r
VPTEST ymm2/m256, ymm1 = VEX.256.66.0F38.WIG 17 /r

(Jakub Jelinek, jakub@redhat.com), #273475 comment 127.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2398

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Julian Seward [Thu, 21 Jun 2012 08:34:19 +0000 (08:34 +0000)]

Fix incorrect implementation of VPERMILP{S,D} variable form.
(Jakub Jelinek, jakub@redhat.com), #273475 comment 128.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2397

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Petar Jovanovic [Wed, 20 Jun 2012 17:53:32 +0000 (17:53 +0000)]

Moving Iop_F64toI32S to correct (binary ops) place in iselWordExpr_R_wrk.

In a previous commit (r2393), a break has been misplaced and caused two issues,
and that revelead that Iop_F64toI32S was in the wrong (unary op) case.
This fixes none/tests/mips32/round and memcheck/tests/vcpu_fnfns for MIPS.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2396

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Julian Seward [Wed, 20 Jun 2012 11:46:19 +0000 (11:46 +0000)]

Implement

VPERMILPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.W0 0C /r
VPERMILPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.W0 0C /r
VPERMILPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.W0 0D /r
VPERMILPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.W0 0D /r

git-svn-id: svn://svn.valgrind.org/vex/trunk@2395

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Julian Seward [Wed, 20 Jun 2012 10:21:05 +0000 (10:21 +0000)]

Add support for

VMOVSLDUP xmm2/m128, xmm1 = VEX.NDS.128.F3.0F.WIG 12 /r
VMOVSLDUP ymm2/m256, ymm1 = VEX.NDS.256.F3.0F.WIG 12 /r
VMOVSHDUP xmm2/m128, xmm1 = VEX.NDS.128.F3.0F.WIG 16 /r
VMOVSHDUP ymm2/m256, ymm1 = VEX.NDS.256.F3.0F.WIG 16 /r

VMOVSS xmm3, xmm2, xmm1 = VEX.LIG.F3.0F.WIG 10 /r
VMOVSS xmm3, xmm2, xmm1 = VEX.LIG.F3.0F.WIG 11 /r

VPSLLW imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 71 /6 ib
VPSRAD imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 72 /4 ib

(Jakub Jelinek, jakub@redhat.com), #273475 comments 121, 122, 124

git-svn-id: svn://svn.valgrind.org/vex/trunk@2394

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Julian Seward [Tue, 19 Jun 2012 16:33:47 +0000 (16:33 +0000)]

Add some missing breaks as spotted by BEAM.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2393

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Julian Seward [Tue, 19 Jun 2012 13:29:00 +0000 (13:29 +0000)]

s390_insn_cdas_emit: comment out unused variable r3p1
(a relative of C3PO, perhaps?)

git-svn-id: svn://svn.valgrind.org/vex/trunk@2392

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Julian Seward [Tue, 19 Jun 2012 06:57:59 +0000 (06:57 +0000)]

Move new 256-bit FP Iops to a better place.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2391

commit | commitdiff | tree

Julian Seward [Mon, 18 Jun 2012 23:15:16 +0000 (23:15 +0000)]

More AVX insns:

VMOVUPS ymm2/m256, ymm1 = VEX.256.0F.WIG 10 /r
VSQRTSS xmm3/m64(E), xmm2(V), xmm1(G) = VEX.NDS.LIG.F3.0F.WIG 51 /r
VSQRTPS xmm2/m128(E), xmm1(G) = VEX.NDS.128.0F.WIG 51 /r
VSQRTPS ymm2/m256(E), ymm1(G) = VEX.NDS.256.0F.WIG 51 /r
VSQRTPD xmm2/m128(E), xmm1(G) = VEX.NDS.128.66.0F.WIG 51 /r
VSQRTPD ymm2/m256(E), ymm1(G) = VEX.NDS.256.66.0F.WIG 51 /r
VRSQRTSS xmm3/m64(E), xmm2(V), xmm1(G) = VEX.NDS.LIG.F3.0F.WIG 52 /r
VRSQRTPS xmm2/m128(E), xmm1(G) = VEX.NDS.128.0F.WIG 52 /r
VRSQRTPS ymm2/m256(E), ymm1(G) = VEX.NDS.256.0F.WIG 52 /r
VZEROALL = VEX.256.0F.WIG 77
VMOVDQU ymm1, ymm2/m256 = VEX.256.F3.0F.WIG 7F
VCVTPS2PD xmm2/m128, ymm1 = VEX.256.0F.WIG 5A /r
VCVTPS2DQ ymm2/m256, ymm1 = VEX.256.66.0F.WIG 5B /r
VCVTTPS2DQ xmm2/m128, xmm1 = VEX.128.F3.0F.WIG 5B /r
VCVTTPS2DQ ymm2/m256, ymm1 = VEX.256.F3.0F.WIG 5B /r
VCVTDQ2PS xmm2/m128, xmm1 = VEX.128.0F.WIG 5B /r
VCVTDQ2PS ymm2/m256, ymm1 = VEX.256.0F.WIG 5B /r
VCVTTPD2DQ xmm2/m128, xmm1 = VEX.128.66.0F.WIG E6 /r
VCVTTPD2DQ ymm2/m256, xmm1 = VEX.256.66.0F.WIG E6 /r
VCVTPD2DQ xmm2/m128, xmm1 = VEX.128.F2.0F.WIG E6 /r
VCVTPD2DQ ymm2/m256, xmm1 = VEX.256.F2.0F.WIG E6 /r

(Jakub Jelinek, jakub@redhat.com). #273475 comments 115, 116.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2390

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Julian Seward [Mon, 18 Jun 2012 22:09:33 +0000 (22:09 +0000)]

Remove incorrect masking of the imm8 in VSHUFPD.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2389

commit | commitdiff | tree

Julian Seward [Mon, 18 Jun 2012 15:01:30 +0000 (15:01 +0000)]

More AVX insns:

VMOVUPD ymm1, ymm2/m256 = VEX.256.66.0F.WIG 11 /r
VMOVUPS ymm1, ymm2/m256 = VEX.256.0F.WIG 11 /r
VCOMISD xmm2/m64, xmm1 = VEX.LIG.66.0F.WIG 2F /r
VPCMPGTD r/m, rV, r ::: r = rV `>s-by-32s` r/m
VPMOVSXBD xmm2/m32, xmm1
VPMOVZXBD xmm2/m32, xmm1
VDPPD xmm3/m128,xmm2,xmm1 = VEX.NDS.128.66.0F3A.WIG 41 /r ib

and common up duplication in implementation of PINSRW/VPINSRW.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2388

commit | commitdiff | tree

Julian Seward [Mon, 18 Jun 2012 14:05:52 +0000 (14:05 +0000)]

More AVX insns:

VMOVSD xmm3, xmm2, xmm1 = VEX.LIG.F2.0F.WIG 10 /r
VMOVSD xmm3, xmm2, xmm1 = VEX.LIG.F2.0F.WIG 11 /r
VMOVLPD m64, xmm1, xmm2 = VEX.NDS.128.66.0F.WIG 12 /r
VMOVLPD xmm1, m64 = VEX.128.66.0F.WIG 13 /r
VPINSRW r32/m16, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG C4 /r ib
VSHUFPD imm8, xmm3/m128, xmm2, xmm1, xmm2
VSHUFPD imm8, ymm3/m256, ymm2, ymm1, ymm2
VPERMILPS imm8, xmm2/m128, xmm1 = VEX.128.66.0F3A.WIG 04 /r ib
VBLENDPS imm8, ymm3/m256, ymm2, ymm1
VBLENDPS = VEX.NDS.128.66.0F3A.WIG 0C /r ib
VBLENDPD = VEX.NDS.256.66.0F3A.WIG 0D /r ib
VBLENDPD = VEX.NDS.128.66.0F3A.WIG 0D /r ib
VPBLENDW = VEX.NDS.128.66.0F3A.WIG 0E /r ib
VPINSRB r32/m8, xmm2, xmm1 = VEX.NDS.128.66.0F3A.WIG C4 /r ib

(Jakub Jelinek, jakub@redhat.com). #273475 comment 110.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2387

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Julian Seward [Mon, 18 Jun 2012 13:56:55 +0000 (13:56 +0000)]

More AVX insns:

VBROADCASTSS m32, ymm1 = VEX.256.66.0F38.WIG 18 /r
VPALIGNR imm8, xmm3/m128, xmm2, xmm1

(Jakub Jelinek, jakub@redhat.com). #273475 comment 109.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2386

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Florian Krohm [Fri, 15 Jun 2012 20:55:43 +0000 (20:55 +0000)]

Fix a few issues as reported by the BEAM tool.
Patch by Carl Love (cel@linux.vnet.ibm.com).

git-svn-id: svn://svn.valgrind.org/vex/trunk@2385

commit | commitdiff | tree

Julian Seward [Fri, 15 Jun 2012 15:48:07 +0000 (15:48 +0000)]

Add a CPUID emulation which announces AVX support, but don't enable it
yet.

Add support for the following instructions:

0F 01 D0 = XGETBV
VPUNPCKHQDQ r/m, rV, r ::: r = interleave-hi-64bitses(rV, r/m)
VPSRAW imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 71 /4 ib
VSTMXCSR m32 = VEX.LZ.0F.WIG AE /3
VLDMXCSR m32 = VEX.LZ.0F.WIG AE /2
VPMULHW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E5 /r
VPERMILPS imm8, ymm2/m256, ymm1 = VEX.256.66.0F3A.W0 04 /r ib

git-svn-id: svn://svn.valgrind.org/vex/trunk@2384

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Julian Seward [Thu, 14 Jun 2012 23:32:02 +0000 (23:32 +0000)]

Fill in some missing AVX insns:

VANDPS = VEX.NDS.256.0F.WIG 54 /r
VANDNPD = VEX.NDS.256.66.0F.WIG 55 /r
ANDNPS = VEX.NDS.256.0F.WIG 55 /r
VORPD = VEX.NDS.256.66.0F.WIG 56 /r
VORPS = VEX.NDS.256.0F.WIG 56 /r
VXORPS = VEX.NDS.256.0F.WIG 57 /r
VDIVPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 5E /r

Modified version of a patch by Jakub Jelinek, jakub@redhat.com
(bug 273475 comment 96)

git-svn-id: svn://svn.valgrind.org/vex/trunk@2383

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Julian Seward [Thu, 14 Jun 2012 08:51:35 +0000 (08:51 +0000)]

Implement even more insns created by gcc-4.7.0 -mavx -O3.

VMOVHPD m64, xmm1, xmm2 = VEX.NDS.128.66.0F.WIG 16 /r
VMOVAPS ymm2/m256, ymm1 = VEX.256.0F.WIG 28 /r
VCVTPD2PS ymm2/m256, xmm1 = VEX.256.66.0F.WIG 5A /r
VPUNPCKHDQ = VEX.NDS.128.66.0F.WIG 6A /r
VPCMPEQW r/m, rV, r ::: r = rV `eq-by-16s` r/m
VPSUBUSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D9 /r
VCVTDQ2PD xmm2/m128, ymm1 = VEX.256.F3.0F.WIG E6 /r
VPADDB r/m, rV, r ::: r = rV + r/m
VBROADCASTSS m32, xmm1 = VEX.128.66.0F38.W0 18 /r
VPMOVSXBW xmm2/m64, xmm1
VPMOVSXWD xmm2/m64, xmm1
VPMOVSXDQ xmm2/m64, xmm1

git-svn-id: svn://svn.valgrind.org/vex/trunk@2382

commit | commitdiff | tree

Julian Seward [Wed, 13 Jun 2012 11:10:20 +0000 (11:10 +0000)]

Implement even more instructions generated by "gcc-4.7.0 -mavx -O3".
This is the first point at which coverage for -O3 generated code could
be construed as "somewhat usable".

git-svn-id: svn://svn.valgrind.org/vex/trunk@2381

commit | commitdiff | tree

Julian Seward [Tue, 12 Jun 2012 14:59:17 +0000 (14:59 +0000)]

Implement a bunch more AVX instructions generated by "gcc-4.7.0 -mavx -O3":

VPSLLQ imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 73 /6 ib
VPEXTRW imm8, xmm1, reg32 = VEX.128.66.0F.W0 C5 /r ib
VPMINUB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG DA /r
VPMAXUB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG DE /r
VPMINSW r/m, rV, r ::: r = min-signed16s(rV, r/m)
VPMAXSW r/m, rV, r ::: r = max-signed16s(rV, r/m)
VPMULUDQ xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG F4 /r
VPMINSB r/m, rV, r ::: r = min-signed-8s(rV, r/m)
VPMINUW r/m, rV, r ::: r = min-unsigned-16s(rV, r/m)
VPMINUD r/m, rV, r ::: r = min-unsigned-32s(rV, r/m)
VPMAXSB r/m, rV, r ::: r = max-signed-8s(rV, r/m)
VPMAXUW r/m, rV, r ::: r = max-unsigned-16s(rV, r/m)
VPMAXUD r/m, rV, r ::: r = max-unsigned-32s(rV, r/m)
VPMULLD r/m, rV, r ::: r = mul-32s(rV, r/m)
VPHMINPOSUW xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 41 /r
VPERMILPD imm8, ymm2/m256, ymm1 = VEX.256.66.0F3A.W0 05 /r ib
VPERMILPD imm8, xmm2/m128, xmm1 = VEX.128.66.0F3A.W0 05 /r ib
VPERM2F128 imm8, ymm3/m256, ymm2, ymm1 = VEX.NDS.66.0F3A.W0 06 /r ib
VPEXTRB imm8, xmm2, reg/m8 = VEX.128.66.0F3A.W0 14 /r ib

git-svn-id: svn://svn.valgrind.org/vex/trunk@2380

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Julian Seward [Tue, 12 Jun 2012 08:45:39 +0000 (08:45 +0000)]

Make a start at implementing 256-bit AVX instructions generated by
"gcc-4.7.0 -mavx -O3":

VMOVUPD xmm2/m128, xmm1 = VEX.128.66.0F.WIG 10 /r
VMOVUPS xmm2/m128, xmm1 = VEX.128.0F.WIG 10 /r
VUNPCKHPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 15 /r
VUNPCKLPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 14 /r
VUNPCKHPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 15 /r
VADDPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 58 /r
VADDPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 58 /r
VADDPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 58 /r
VMULPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 59 /r
VMULPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 59 /r
VMULPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 59 /r
VSUBPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 5C /r
VSUBPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 5C /r
VSUBPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 5C /r
VDIVPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 5E /r
VDIVPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 5E /r
VPSRLQ imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 73 /2 ib
VPCMPEQQ = VEX.NDS.128.66.0F38.WIG 29 /r
VPCMPGTQ = VEX.NDS.128.66.0F38.WIG 37 /r
VPEXTRQ = VEX.128.66.0F3A.W1 16 /r ib

git-svn-id: svn://svn.valgrind.org/vex/trunk@2379

commit | commitdiff | tree

Julian Seward [Mon, 11 Jun 2012 21:54:58 +0000 (21:54 +0000)]

16-bit Thumb PUSH and POP: fix incorrect assertions.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2378

commit | commitdiff | tree

Petar Jovanovic [Thu, 7 Jun 2012 16:52:41 +0000 (16:52 +0000)]

Small improvement for getIReg on MIPS when reading from r0.

zero register on MIPS is actually a constant, and front end should be aware of
that. MIPS port is currently tracked as bug #270777.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2377

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Julian Seward [Thu, 7 Jun 2012 08:59:53 +0000 (08:59 +0000)]

Merge in a port for mips32-linux, by Petar Jovanovic and Dejan Jevtic,
mips-valgrind@rt-rk.com, Bug 270777.

VEX: new files for mips32.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2376

commit | commitdiff | tree

Julian Seward [Thu, 7 Jun 2012 08:51:02 +0000 (08:51 +0000)]

Merge in a port for mips32-linux, by Petar Jovanovic and Dejan Jevtic,
mips-valgrind@rt-rk.com, Bug 270777.

VEX: changes to existing files.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2375

commit | commitdiff | tree

Florian Krohm [Wed, 6 Jun 2012 12:53:14 +0000 (12:53 +0000)]

Fix a copy'n paste error spotted by Julian.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2374

commit | commitdiff | tree

Florian Krohm [Wed, 6 Jun 2012 02:44:53 +0000 (02:44 +0000)]

Fix debug printing of s390 V-insns. Alu ops and such are 2-address insns

git-svn-id: svn://svn.valgrind.org/vex/trunk@2373

commit | commitdiff | tree

Florian Krohm [Wed, 6 Jun 2012 02:26:01 +0000 (02:26 +0000)]

Support "compare double ansd swap" insns: CDS, CDSY, and CDSG
VEX bits for fixing bugzilla #291865

git-svn-id: svn://svn.valgrind.org/vex/trunk@2372

commit | commitdiff | tree

Julian Seward [Mon, 4 Jun 2012 07:38:10 +0000 (07:38 +0000)]

dis_AVX128_E_V_to_G is a special case of
dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple, so implement the former by
calling the latter.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2371

commit | commitdiff | tree

Julian Seward [Sun, 3 Jun 2012 23:12:33 +0000 (23:12 +0000)]

Implement
VMOVUPD ymm2/m256, ymm1 = VEX.256.66.0F.WIG 10 /r
VMOVUPD ymm1, ymm2/m256 = VEX.256.66.0F.WIG 11 /r

git-svn-id: svn://svn.valgrind.org/vex/trunk@2370

commit | commitdiff | tree

Julian Seward [Sun, 3 Jun 2012 23:11:49 +0000 (23:11 +0000)]

Move VEX_HWCAPS_PPC32_DFP to a more logical place.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2369

commit | commitdiff | tree

Florian Krohm [Sun, 3 Jun 2012 02:10:08 +0000 (02:10 +0000)]

Fix two Binop / Unop mixups.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2368

commit | commitdiff | tree

Julian Seward [Sat, 2 Jun 2012 23:47:02 +0000 (23:47 +0000)]

POWER Processor decimal FP support, part 5 (VEX side). Bug #299694.
(Carl Love, carll@us.ibm.com and Maynard Johnson, maynardj@us.ibm.com)

This patch adds support for Power Decimal Floating Point (DFP) . This
is the fifth patch set in the series of five to add the DFP
instruction support to Valgrind. Adds support for the ddedpd,
ddedpdq, denbcd, denbcdq, dtstsf, and dtstsfq instructions.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2367

commit | commitdiff | tree

Florian Krohm [Sat, 2 Jun 2012 20:29:22 +0000 (20:29 +0000)]

Put the Triop member into a separate struct (IRTriop) and link to that
from IRExpr. Reduces size of IRExpr from 40 bytes to 32 bytes on LP64
and from 20 bytes to 16 bytes on ILP32.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2366

commit | commitdiff | tree

Julian Seward [Sat, 2 Jun 2012 11:55:25 +0000 (11:55 +0000)]

Implement
   VMOVAPD ymm1, ymm2/m256 = VEX.256.66.0F.WIG 29 /r
   VMOVAPS ymm1, ymm2/m256 = VEX.256.0F.WIG 29 /r
   VPADDQ r/m, rV, r ::: r = rV + r/m
   VPSUBW r/m, rV, r ::: r = rV - r/m
   VPSUBQ = VEX.NDS.128.66.0F.WIG FB /r
   VPINSRQ r64/m64, xmm2, xmm1 = VEX.NDS.128.66.0F3A.W1 22 /r ib

git-svn-id: svn://svn.valgrind.org/vex/trunk@2365

commit | commitdiff | tree

Florian Krohm [Fri, 1 Jun 2012 22:04:27 +0000 (22:04 +0000)]

Fix a cut'n paste error.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2364

commit | commitdiff | tree

Florian Krohm [Fri, 1 Jun 2012 20:41:24 +0000 (20:41 +0000)]

Put the Qop member into a separate struct (IRQop) and link to that
from IRExpr. Reduces size of IRExpr from 48 to 40 bytes on LP64.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2363

commit | commitdiff | tree

Julian Seward [Fri, 1 Jun 2012 16:09:50 +0000 (16:09 +0000)]

Enhance the guest state effects notation on IRDirty calls, so as to be
able to describe accesses to arrays of non-consecutive guest state
sections. This is needed to describe the behaviour of FXSAVE and
FXRSTOR in an environment where we also support AVX.

The IRDirty struct has got smaller (112 bytes vs 136 before, for a 64
bit target) whilst holding more information.

The new facility is then used to describe said FXSAVE and FXRSTOR on
amd64. For x86 there is no change since we don't model AVX state for
x86.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2362

commit | commitdiff | tree

Florian Krohm [Thu, 31 May 2012 15:46:18 +0000 (15:46 +0000)]

Reduce size of an IRStmt from 40 bytes to 32 bytes on LP64
by allocating the details of a PutI statement into a struct
of its own and link to that (as is being done for Dirty and CAS).

These are the VEX bits.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2361

commit | commitdiff | tree

Florian Krohm [Mon, 28 May 2012 03:10:02 +0000 (03:10 +0000)]

Add forgotten update. Should have been part of r2359.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2360

commit | commitdiff | tree

Florian Krohm [Mon, 28 May 2012 02:58:19 +0000 (02:58 +0000)]

Cleanup after t-chaining changes.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2359

commit | commitdiff | tree

Florian Krohm [Sun, 27 May 2012 17:20:47 +0000 (17:20 +0000)]

Update a comment.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2358

commit | commitdiff | tree

Florian Krohm [Sun, 27 May 2012 16:59:56 +0000 (16:59 +0000)]

Fix an out-of-date comment.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2357

commit | commitdiff | tree

Florian Krohm [Sun, 27 May 2012 16:52:43 +0000 (16:52 +0000)]

Change S390_INSN_HELPER_CALL such that returning a value is part
of the call. Previously, this was a separate insn.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2356

commit | commitdiff | tree

Julian Seward [Sun, 27 May 2012 16:18:13 +0000 (16:18 +0000)]

Remove, or (where it might later come in handy) comment out artefacts
for 256 bit (AVX) code generation on amd64.  Although that was the
plan at first, it turns out to be infeasible to generate 256 bit
instructions for the IR created by Memcheck's instrumentation of 256
bit Ity_V256 IR.  This is because it would require 256 bit integer
SIMD operations, and AVX as currently available only provides 256 bit
operations for floating point.  So, fall back to generating 256 IR
into 128-bit XMM register pairs, and using the existing SSE facilities
in the back end.  This change only affects the amd64 back end -- it
does not affect IR, which remains unchanged, and capable of
representing 256 bit vector operations wherever needed.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2355

commit | commitdiff | tree

Julian Seward [Sun, 27 May 2012 13:50:42 +0000 (13:50 +0000)]

Fix the behaviour of VEXTRACTF128, VCMPSD and VCMPSS, all of which were
identified as incorrectly implemented by avx-1.c.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2354

commit | commitdiff | tree

Julian Seward [Sun, 27 May 2012 08:25:42 +0000 (08:25 +0000)]

Implement VINSERTPS imm8, xmm3/m32, xmm2, xmm1
Fix VCVTPD2PS

git-svn-id: svn://svn.valgrind.org/vex/trunk@2353

commit | commitdiff | tree

Florian Krohm [Sat, 26 May 2012 01:59:21 +0000 (01:59 +0000)]

Take advantage of compare immediate insns as more than half
of all comparisons are like that.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2352

commit | commitdiff | tree

Julian Seward [Fri, 25 May 2012 15:53:01 +0000 (15:53 +0000)]

Implement
   VPUNPCKLDQ r/m, rV, r ::: r = interleave-lo-dwords(rV, r/m)
   VPACKSSDW r/m, rV, r ::: r = QNarrowBin32Sto16Sx8(rV, r/m)
   VPUNPCKLQDQ r/m, rV, r ::: r = interleave-lo-64bitses(rV, r/m)
   VPSRLW imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 71 /2 ib
   VPADDW r/m, rV, r ::: r = rV + r/m
   VPINSRD r32/m32, xmm2, xmm1 = VEX.NDS.128.66.0F3A.W0 22 /r ib

git-svn-id: svn://svn.valgrind.org/vex/trunk@2351

commit | commitdiff | tree

Julian Seward [Fri, 25 May 2012 13:51:07 +0000 (13:51 +0000)]

Implement
   VADDPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 58 /r
   VMULPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 59 /r
   VCVTPS2DQ xmm2/m128, xmm1 = VEX.128.66.0F.WIG 5B /r
   VSUBPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 5C /r
   VMINPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 5D /r
   VMAXPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 5F /r
   VPUNPCKLWD r/m, rV, r ::: r = interleave-lo-words(rV, r/m)
   VPUNPCKHWD r/m, rV, r ::: r = interleave-hi-words(rV, r/m)
   VPSHUFLW imm8, xmm2/m128, xmm1 = VEX.128.F2.0F.WIG 70 /r ib
   VPSHUFHW imm8, xmm2/m128, xmm1 = VEX.128.F3.0F.WIG 70 /r ib
   VPSRLD imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 72 /2 ib
   VPSLLDQ imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 73 /7 ib
   VSHUFPS imm8, xmm3/m128, xmm2, xmm1, xmm2
   VPMULLW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D5 /r
   VPSUBUSB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D8 /r
   VPANDN r/m, rV, r ::: r = rV & ~r/m (is that correct, re the ~ ?)
   VPADDUSB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG DC /r
   VPADDUSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG DD /r
   VPMULHUW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E4 /r

git-svn-id: svn://svn.valgrind.org/vex/trunk@2350

commit | commitdiff | tree

Julian Seward [Thu, 24 May 2012 16:29:18 +0000 (16:29 +0000)]

Implement
   /* VEX.NDS.128.66.0F.WIG DB /r = VPAND xmm3/m128, xmm2, xmm1 */
   /* VPCMPEQB = VEX.NDS.128.66.0F.WIG 74 /r */
   /* VCVTTSS2SI xmm1/m64, r64 = VEX.LIG.F3.0F.W1 2C /r */
   /* VMOVHPD xmm1, m64 = VEX.128.66.0F.WIG 17 /r */

git-svn-id: svn://svn.valgrind.org/vex/trunk@2349

commit | commitdiff | tree

Julian Seward [Thu, 24 May 2012 06:31:21 +0000 (06:31 +0000)]

Fix two more incorrect disAMode calls, recently introduced in AVX
support code.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2348

commit | commitdiff | tree

Julian Seward [Thu, 24 May 2012 06:17:14 +0000 (06:17 +0000)]

Fix incorrect uses of disAMode in some SSE4 instructions that have an
immediate byte as a subopcode. Fixes #294260. (Patrick J. LoPresti,
lopresti@gmail.com)

git-svn-id: svn://svn.valgrind.org/vex/trunk@2347

commit | commitdiff | tree

Julian Seward [Thu, 24 May 2012 00:09:27 +0000 (00:09 +0000)]

Implement VPACKUWSB = VEX.NDS.128.66.0F.WIG 67 /r

git-svn-id: svn://svn.valgrind.org/vex/trunk@2346

commit | commitdiff | tree

Julian Seward [Wed, 23 May 2012 23:54:30 +0000 (23:54 +0000)]

Implement
   VMOVD xmm1, r32 = VEX.128.66.0F.W0 7E /r (reg case only)
   VCVTSS2SD xmm3/m32, xmm2, xmm1 = VEX.NDS.LIG.F3.0F.WIG 5A /r
   VCVTSD2SS xmm3/m64, xmm2, xmm1 = VEX.NDS.LIG.F2.0F.WIG 5A /r

git-svn-id: svn://svn.valgrind.org/vex/trunk@2345

commit | commitdiff | tree

Julian Seward [Wed, 23 May 2012 12:42:39 +0000 (12:42 +0000)]

Implement
   VEX.128.66.0F3A.WIG 63 /r ib = VPCMPISTRI imm8, xmm2/m128, xmm1
   VEX.128.66.0F3A.WIG 62 /r ib = VPCMPISTRM imm8, xmm2/m128, xmm1
   VEX.128.66.0F3A.WIG 61 /r ib = VPCMPESTRI imm8, xmm2/m128, xmm1
   VEX.128.66.0F3A.WIG 60 /r ib = VPCMPESTRM imm8, xmm2/m128, xmm1

git-svn-id: svn://svn.valgrind.org/vex/trunk@2344

commit | commitdiff | tree

Julian Seward [Wed, 23 May 2012 11:33:56 +0000 (11:33 +0000)]

Implement
   VMOVUPS xmm1, xmm2/m128 = VEX.128.0F.WIG 11 /r
   VMOVQ r64/m64, xmm1 = VEX.128.66.0F.W1 6E
   MOVNTDQ xmm1, m128 = VEX.128.66.0F.WIG E7 /r

git-svn-id: svn://svn.valgrind.org/vex/trunk@2343

commit | commitdiff | tree

Julian Seward [Wed, 23 May 2012 06:16:26 +0000 (06:16 +0000)]

Implement
VMOVLHPS xmm3, xmm2, xmm1 = VEX.NDS.128.0F.WIG 16 /r

git-svn-id: svn://svn.valgrind.org/vex/trunk@2342

commit | commitdiff | tree

Julian Seward [Wed, 23 May 2012 05:56:53 +0000 (05:56 +0000)]

Implement
VPABSD xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 1E /r

git-svn-id: svn://svn.valgrind.org/vex/trunk@2341

commit | commitdiff | tree

Julian Seward [Tue, 22 May 2012 23:34:06 +0000 (23:34 +0000)]

Implement
VMOVHLPS xmm3, xmm2, xmm1 = VEX.NDS.128.0F.WIG 12 /r

git-svn-id: svn://svn.valgrind.org/vex/trunk@2340

commit | commitdiff | tree

Julian Seward [Tue, 22 May 2012 23:12:13 +0000 (23:12 +0000)]

Implement
VMOVQ xmm1, r64 = VEX.128.66.0F.W1 7E /r (reg case only)
If this is documented in the Intel manuals, I can't find it.
GNU binutils and GDB seem to have heard of it, though.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2339

commit | commitdiff | tree

Julian Seward [Tue, 22 May 2012 10:48:13 +0000 (10:48 +0000)]

Implement VCVTTSS2SI xmm1/m32, r32 = VEX.LIG.F3.0F.W0 2C /r

git-svn-id: svn://svn.valgrind.org/vex/trunk@2338

commit | commitdiff | tree

Julian Seward [Tue, 22 May 2012 09:14:15 +0000 (09:14 +0000)]

Implement AVX insns
VPUNPCKHBW = VEX.NDS.128.0F.WIG 68 /r
VPUNPCKLBW = VEX.NDS.128.0F.WIG 60 /r
Catchy names, huh?!

git-svn-id: svn://svn.valgrind.org/vex/trunk@2337

commit | commitdiff | tree

Florian Krohm [Tue, 22 May 2012 01:51:26 +0000 (01:51 +0000)]

Tweak initialisation of padding bytes such that future adjustments
only require changing one spot (libvex_guest_s390x.h).

git-svn-id: svn://svn.valgrind.org/vex/trunk@2336

commit | commitdiff | tree

Julian Seward [Mon, 21 May 2012 21:51:36 +0000 (21:51 +0000)]

Enable FCOMS/FCOMPS on amd64. Fixes #300414.
(Eliot Moss, moss@cs.umass.edu)

git-svn-id: svn://svn.valgrind.org/vex/trunk@2335

commit | commitdiff | tree

Julian Seward [Mon, 21 May 2012 16:16:13 +0000 (16:16 +0000)]

Fix feature recognition on AMD Bulldozer following the recent AVX
commits. Fixes #300389.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2334

commit | commitdiff | tree

Julian Seward [Mon, 21 May 2012 15:45:34 +0000 (15:45 +0000)]

Ensure s390x guest state size is 32-byte aligned, as per increase in
alignment requirements resulting from r12569/r2330.
(Christian Borntraeger <borntraeger@de.ibm.com>)

git-svn-id: svn://svn.valgrind.org/vex/trunk@2333

commit | commitdiff | tree

Julian Seward [Mon, 21 May 2012 11:21:50 +0000 (11:21 +0000)]

Ensure arm guest state size is 32-byte aligned, as per increase in
alignment requirements resulting from r12569/r2330.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2332

commit | commitdiff | tree

Julian Seward [Mon, 21 May 2012 11:00:41 +0000 (11:00 +0000)]

Ensure ppc64 guest state size is 32-byte aligned, as per increase in
alignment requirements resulting from r12569/r2330.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2331

commit | commitdiff | tree

Julian Seward [Mon, 21 May 2012 10:18:49 +0000 (10:18 +0000)]

Add initial support for Intel AVX instructions (VEX side).
Tracker bug is #273475.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2330

commit | commitdiff | tree

Florian Krohm [Sat, 12 May 2012 16:14:08 +0000 (16:14 +0000)]

Fix disassembly for asi and agsi

git-svn-id: svn://svn.valgrind.org/vex/trunk@2329

commit | commitdiff | tree

Florian Krohm [Sat, 12 May 2012 15:26:44 +0000 (15:26 +0000)]

Eliminate helper s390_calculate_icc. Rewrite and factor the code to use
s390_calculate_cond instead. The benefit is that the latter has comprehensive
spec_helpers whereas the former had not.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2328

commit | commitdiff | tree

Florian Krohm [Sat, 12 May 2012 03:44:49 +0000 (03:44 +0000)]

Back out VEX r2326. It was not working correctly. The guard condition
has to be evaluated after argument evaluation. Add clarifying comments
in libvex_ir.h

git-svn-id: svn://svn.valgrind.org/vex/trunk@2327

commit | commitdiff | tree

Florian Krohm [Wed, 9 May 2012 13:31:09 +0000 (13:31 +0000)]

Improve insn selection for helper calls. Attempt to evaluate arguments
into the real register that is mandated by the ABI instead of evaluating
it in a virtual register and then move the result.
Observed savings in insns between 0.5% and 1.4%.
Probably an overrated optimization given current helper functions which
rarely take more than one argument.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2326

commit | commitdiff | tree

Florian Krohm [Tue, 8 May 2012 20:16:17 +0000 (20:16 +0000)]

Use make_gpr throughout. Remove unused parameter.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2325

commit | commitdiff | tree

Florian Krohm [Mon, 7 May 2012 03:28:18 +0000 (03:28 +0000)]

Remove an out-of-date comment.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2324

commit | commitdiff | tree

Florian Krohm [Sun, 6 May 2012 03:34:55 +0000 (03:34 +0000)]

Add the counter pseudo register to the list of guest registers to
be tracked during insn selection. Saves 0.2% or so of insns depending on
how often insns with implicit loops like MVC are being used.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2323

commit | commitdiff | tree

Florian Krohm [Sat, 5 May 2012 02:55:24 +0000 (02:55 +0000)]

Special-case the TR insn for EX.
With this change all insns of the SS format with a length field
are special-cased for EX.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2322

commit | commitdiff | tree

Florian Krohm [Sat, 5 May 2012 02:20:30 +0000 (02:20 +0000)]

More refactoring to avoid code duplication (irgen_CLC/CLC_EX and
irgen_MVC/MVC_EX)

git-svn-id: svn://svn.valgrind.org/vex/trunk@2321

commit | commitdiff | tree

Florian Krohm [Sat, 5 May 2012 00:01:16 +0000 (00:01 +0000)]

Add NC and OC to the list of insns that get special treatment under EX.
Refactored code such that s390_irgen_xonc can be reused thereby avoiding
code duplication.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2320

commit | commitdiff | tree

Florian Krohm [Thu, 3 May 2012 01:30:48 +0000 (01:30 +0000)]

Add ETF3 facility (VEX bits). Part of fixing Bugzilla #289839.
Patch by Divya Vyas (divyvyas@linux.vnet.ibm.com)

git-svn-id: svn://svn.valgrind.org/vex/trunk@2319

commit | commitdiff | tree

Julian Seward [Mon, 30 Apr 2012 08:10:11 +0000 (08:10 +0000)]

Don't use constants of the form 0b...; apparently older compilers
don't know about them. Fixes compile breaking resulting from r2317.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2318

commit | commitdiff | tree

Julian Seward [Sun, 29 Apr 2012 20:19:17 +0000 (20:19 +0000)]

Add support for POWER Power Decimal Floating Point (DFP) test class,
test group and test exponent instructions dtstdc, dtstdcq, dtstdg,
dtstdgq, dtstex and dtstexq. Bug #298862. (Carl Love,
carll@us.ibm.com)

git-svn-id: svn://svn.valgrind.org/vex/trunk@2317

commit | commitdiff | tree

Julian Seward [Thu, 26 Apr 2012 14:16:52 +0000 (14:16 +0000)]

Add a feature check flag for AVX.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2316

commit | commitdiff | tree

Julian Seward [Wed, 25 Apr 2012 16:47:53 +0000 (16:47 +0000)]

Try to fold out some of the lousy code generated by the amd64 front
end for 32 bit shifts.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2315

commit | commitdiff | tree

Julian Seward [Wed, 25 Apr 2012 14:33:03 +0000 (14:33 +0000)]

Add spec rules for Z and NZ after LOGICW.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2314

commit | commitdiff | tree

Julian Seward [Tue, 24 Apr 2012 11:49:03 +0000 (11:49 +0000)]

(stats only) Let the callers of LibVEX_Translate know how many guest
instructions got incorporated into the IRSB.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2313

commit | commitdiff | tree

Julian Seward [Mon, 23 Apr 2012 11:21:12 +0000 (11:21 +0000)]

POWER Processor decimal floating point instruction support, part 3
(Carl Love, carll@us.ibm.com). Bug 298080.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2312

commit | commitdiff | tree

Julian Seward [Mon, 23 Apr 2012 09:48:14 +0000 (09:48 +0000)]

For each backend, unify the sets of IRJumpKinds handled for Ist_Exit
and iselNext, so as to avoid potential failures caused by branch sense
switching at the IR level.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2311

commit | commitdiff | tree

Florian Krohm [Sun, 22 Apr 2012 19:25:39 +0000 (19:25 +0000)]

Fix makefile to allow compilation with gcc -g3.
Part of fixing bugzilla #297993.
Patch by Daniel Richard G. (skunk@iskunk.org).

git-svn-id: svn://svn.valgrind.org/vex/trunk@2310

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Florian Krohm [Sun, 22 Apr 2012 17:46:31 +0000 (17:46 +0000)]

tchain optimization for s390 (continued)
Take advantage of hardware capabilities when loading a 64-bit
immediate.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2309

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Florian Krohm [Sun, 22 Apr 2012 17:38:46 +0000 (17:38 +0000)]

tchain optimisation for s390 (VEX bits)
Loading a 64-bit immediate into a register requires 4 insns on a
z900 machine, the oldest model supported. Depending on hardware
capabilities, newer machines can do the same using 2 insns.
Naturally, we want to take advantage of that.
However, currently, in disp_cp_chain_me_to_slowEP/fastEP we assume that
the length of loading a 64-bit immediate is a compile time constant:
S390_TCHAIN_LOAD64_LEN
For what we want to do this constant needs to be a runtime constant.

So in this patch we move this address arithmetic out of the dispatch
code. The general idea being that the value in %r1 does not need to
be adjusted to recover the place to patch. Upon reaching
disp_cp_chain_me_to_slowEP/fastEP %r1 contains the correct address.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2308

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Florian Krohm [Sun, 22 Apr 2012 03:48:52 +0000 (03:48 +0000)]

Rename to VEX_S390X_MODEL_UNKNOWN.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2307

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Florian Krohm [Sun, 22 Apr 2012 02:51:27 +0000 (02:51 +0000)]

(post-tchain-merge cleanup) Stop s390x asserting on illegal insns.
none/tests/s390x/op_exception will now pass.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2306

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Florian Krohm [Sat, 21 Apr 2012 16:06:04 +0000 (16:06 +0000)]

(post-tchain-merge cleanup): Use ASI and AGSI for increment / decrement if
available.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2305

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