ada: Remove redundant protection against empty lists

Calls to First on No_List intentionally return Empty node, so explicit
guards against No_List are unnecessary. Code cleanup; semantics is
unaffected.

gcc/ada/

* sem_util.adb (New_Copy_Tree): Remove redundant calls to Present.

ada: Simplify lookup of predecessor in homonym chain

gcc/ada/

* sem_ch8.adb (End_Scope): Simplify lookup of predecessor in
homonym chain.

ada: Accept aggregates with OTHERS clause in unchecked type conversions

When inlining subprogram calls in GNATprove mode, the actual parameter
is wrapped in an unchecked conversion. If this actual parameter is an
aggregate OTHERS clause, then the type of unchecked conversion allows us
to resolve this clause (just like for aggregates wrapped in a qualified
expression).

Previously such aggregates were rejected, which caused spurious and
cryptic errors; now they are accepted.

gcc/ada/

* sem_aggr.adb (Resolve_Aggregate): Accept aggregates with OTHERS
appearing inside unchecked conversions.

ada: Emit warnings for (some) ineffective static predicate tests

Generate a warning if a static predicate tests for a value that
does not belong to the parent subtype. For example, in
  subtype S is Positive with Static_Predicate => S not in 0 | 11 | 222;
the 0 is ineffective because Positive already excludes that value.
Generation of this new warning is controlled by the -gnatw_s switch,
which can also be enabled via -gnatwa.

gcc/ada/

* warnsw.ads: Add a new element,
Warn_On_Ineffective_Predicate_Test, to the Opt_Warnings_Enum
enumeration type.
* warnsw.adb: Bind "-gnatw_s" to the new
Warn_On_Ineffective_Predicate_Test switch. Add the new switch to
the set of switches enabled by -gnata .
* sem_ch13.adb
(Build_Discrete_Static_Predicate): Declare new local procedure,
Warn_If_Test_Ineffective, which conditionally generates new
warning. Call this new procedure when building a new element of an
RList.
* doc/gnat_ugn/building_executable_programs_with_gnat.rst:
Document the -gnatw_s switch (and the corresponding -gnatw_S
switch).
* gnat_ugn.texi: Regenerate.

ada: Update comment after SPARK RM change

gcc/ada/

* sem_attr.adb: Update comment referring to rule number.

ada: Improve check of attribute reference

Before this patch, the front end failed to catch many illegal uses
of access attributes of task types.

This patch makes referring to the access attributes of a task type
raise an error, except in the current instance case defined in
clause 8.6 of the reference manual.

gcc/ada/

* sem_attr.adb: sem_attr.adb (Analyze_Access_Attribute): Tighten
validity check for task types.

ada: Fix minor documentation formatting issue

gcc/ada/

* doc/gnat_rm/implementation_defined_characteristics.rst: Fix
minor documentation formatting issue.
* gnat_rm.texi: Regenerate.
* gnat_ugn.texi: Regenerate.

ada: Optimize 2**N to avoid explicit 'if' in modular case

The compiler usually turns 2**N into Shift_Left(1,N).
This patch removes the check for "shift amount too big" in the
modular case, because Shift_Left works properly in that case
(i.e. if N is very large, it returns 0).

This removes a redundant check on most hardware; Shift_Left
takes care of large shirt amounts as necessary, even though
most hardware does not.

gcc/ada/

* exp_ch4.adb
(Expand_N_Op_Expon): Remove the too-big check. Simplify. Signed
and modular cases are combined, etc. Remove code with comment "We
only handle cases where the right type is a[sic] integer", because
the right operand must always be an integer at this point.

ada: Add Check_Error_Detected before "raise Bad_Attribute"

We shouldn't raise Bad_Attribute if there is no error.
This patch adds a call to Check_Error_Detected to make sure that's true.
(There are other cases where we raise Bad_Attribute;
this patch doesn't try to fix them all.)

gcc/ada/

* sem_attr.adb
(Analyze_Attribute): Add a call to Check_Error_Detected.

ada: Fix handling of pragma Warnings (Toolname, Off/On)

Pragma Warnings On/Off with a preceding toolname (which could be GNAT
or GNATprove) was ignored due an error in accessing the expression of
a pragma association in the parser. Now fixed.

gcc/ada/

* par-prag.adb (First_Arg_Is_Matching_Tool_Name): Fix access to
expression in pragma association.

ada: Fix invalid JSON for extended variant record with -gnatRj

This fixes the output of -gnatRj for an extension of a tagged type which has
a variant part and also deals with the case where the parent type is private
with unknown discriminants.

gcc/ada/

* repinfo.ads (JSON output format): Document special case of
Present member of a Variant object.
* repinfo.adb (List_Structural_Record_Layout): Change the type of
Ext_Level parameter to Integer. Restrict the first recursion with
increasing levels to the fixed part and implement a second
recursion with decreasing levels for the variant part. Deal with
an extension of a type with unknown discriminants.

ada: Fix proof of runtime unit System.Value*

Use cut operations to restore the proof of System.Value*.

gcc/ada/

* libgnat/s-valueu.adb: Use cut operations inside assertion to
restore proofs
* gcc-interface/Make-lang.in (GNAT_ADA_OBJS): Add s-spark and
s-spcuop dependencies.

ada: Allow pragmas Annotate between loop pragmas

Pragma Annotate is now allowed between loop pragmas, in order to
be able to justify separate loop checks in GNATprove.

gcc/ada/

* sem_prag.adb (Check_Grouping): Allow Annotate pragmas between
loop pragmas.

ada: INOX: prototype RFC on String Interpolation

gcc/ada/

* doc/gnat_rm/implementation_defined_pragmas.rst
(Extensions_Allowed): Document string interpolation.
* gnat_rm.texi: Regenerate.
* gnat_ugn.texi: Regenerate.

ada: GNAT UGN: Add section documenting PIE being enabled by default on Linux

This commit updates the Linux-specific chapter to add a new section
documenting the fact that PIE is enabled by default, and provides
some information about the impact that this might have on some
projects, as well as recommendations on how to handle issues.

gcc/ada/

* doc/gnat_ugn/platform_specific_information.rst
(_PIE_Enabled_By_Default_On_Linux): New section.
* gnat-style.texi: Regenerate.
* gnat_ugn.texi: Regenerate.

ada: Skip dynamic interface conversion under native runtime

gcc/ada/

* exp_disp.adb
(Has_Dispatching_Constructor_Call): New subprogram.
(Expand_Interface_Conversion): No need to perform dynamic
interface conversion when the operand and the target type are
interface types and the target interface type is an ancestor of
the operand type. The unique exception to this rule is when the
operand has a dispatching constructor call (as documented in the
sources).

ada: Reject attribute Initialize on unchecked unions

Attribute Initialized is expanded into Valid_Scalars, which can't work
on unchecked unions, so Initialized on unchecked unions needs to be
rejected before expansion.

gcc/ada/

* sem_attr.adb (Analyze_Attribute): Reject attribute Initialized
on unchecked unions; fix grammar in comment.

ada: Fix Unchecked_Conversion in edge case

Before this patch, Set_Can_Use_Internal_Rep was called on access
to subprogram subtypes when instantiating Unchecked_Conversion
from System.Address to an access to subprogram subtype (or the
reverse). This was incorrect and caused an assertion failure.

This patch fixes that by modifying the Can_Use_Internal_Rep
attribute of the base type of the subtype instead.

gcc/ada/

* sem_ch13.adb (Validate_Unchecked_Conversion): Fix behavior on
System.Address to access to subprogram subtype conversion.

ada: Fix link to parent when copying with Copy_Separate_Tree

When flag More_Ids is set on a node, then syntactic children will have
their Parent link set to the last node in the chain of Mode_Ids.

For example, parameter associations in declaration like:

   procedure P (X, Y : T);

will have More_Ids set for "X", Prev_Ids set on "Y" and both will have
the same node of "T" as their child. However, "T" will have only one
parent, i.e. "Y".

This anomaly was taken into account in New_Copy_Tree, but not in
Copy_Separate_Tree. This was leading to spurious errors in check for
ghost-correctness applied to copied specs.

gcc/ada/

* atree.ads
(Is_Syntactic_Node): Refactored from New_Copy_Tree.
* atree.adb
(Is_Syntactic_Node): Likewise.
(Copy_Separate_Tree): Use Is_Syntactic_Node.
* sem_util.adb
(Has_More_Ids): Move to Atree.
(Is_Syntactic_Node): Likewise.

aarch64: PR target/99195 annotate vector compare patterns for vec-concat-zero

This instalment of the series goes through the vector comparison patterns in the backend.
One wart are the int64x1_t comparisons that this patch doesn't touch.
Those are a bit trickier because they have define_insn_and_split mechanisms for falling back to
GP reg comparisons after reload and I don't think a simple annotation will catch those cases correctly.
Those will need more custom thinking.
As said, this patch doesn't touch those and is a decent straightforward improvement on its own.

Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.

gcc/ChangeLog:

PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_cm<optab><mode>): Rename to...
(aarch64_cm<optab><mode><vczle><vczbe>): ... This.
(aarch64_cmtst<mode>): Rename to...
(aarch64_cmtst<mode><vczle><vczbe>): ... This.
(*aarch64_cmtst_same_<mode>): Rename to...
(*aarch64_cmtst_same_<mode><vczle><vczbe>): ... This.
(*aarch64_cmtstdi): Rename to...
(*aarch64_cmtstdi<vczle><vczbe>): ... This.
(aarch64_fac<optab><mode>): Rename to...
(aarch64_fac<optab><mode><vczle><vczbe>): ... This.

gcc/testsuite/ChangeLog:

PR target/99195
* gcc.target/aarch64/simd/pr99195_7.c: New test.

aarch64: PR target/99195 annotate qabs,qneg patterns for vec-concat-zero

Straightforward like previous patches in this series.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.

gcc/ChangeLog:

PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_s<optab><mode>): Rename to...
(aarch64_s<optab><mode><vczle><vczbe>): ... This.

gcc/testsuite/ChangeLog:

PR target/99195
* gcc.target/aarch64/simd/pr99195_4.c: Add testing for qabs, qneg.

RISC-V: Optimize vsetvl AVL for VLS VLMAX auto-vectorization

This patch is optimizing the AVL for VLS auto-vectorzation.

Given below sample code:

typedef int8_t vnx2qi __attribute__ ((vector_size (2)));

__attribute__ ((noipa)) void
f_vnx2qi (int8_t a, int8_t b, int8_t *out)
{
  vnx2qi v = {a, b};
  *(vnx2qi *) out = v;
}

Before this patch:
f_vnx2qi:
        vsetvli a5,zero,e8,mf8,ta,ma
        vmv.v.x v1,a0
        vslide1down.vx  v1,v1,a1
        vse8.v  v1,0(a2)
        ret

After this patch:
f_vnx2qi:
        vsetivli        zero,2,e8,mf8,ta,ma
        vmv.v.x v1,a0
        vslide1down.vx  v1,v1,a1
        vse8.v  v1,0(a2)
        ret

Signed-off-by: Pan Li <pan2.li@intel.com>
Co-authored-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Co-authored-by: kito-cheng <kito.cheng@sifive.com>
gcc/ChangeLog:

* config/riscv/riscv-v.cc (const_vlmax_p): New function for
deciding the mode is constant or not.
(set_len_and_policy): Optimize VLS-VLMAX code gen to vsetivli.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vf_avl-1.c: New test.

tree-optimization/109848 - fix TARGET_MEM_REF store from CTOR simplification

I've put the preparation stmt in the wrong place.

PR tree-optimization/109848
* tree-ssa-forwprop.cc (pass_forwprop::execute): Put the
TARGET_MEM_REF address preparation before the store, not
before the CTOR.

Fix gcc.dg/vect/pr108950.c

The following puts the dg-require-effective-target properly after
the dg-do.

* gcc.dg/vect/pr108950.c: Re-order dg-require-effective-target
and dg-do.

RISC-V: Support TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT to optimize codegen of both VLA && VLS auto-vectorization

This patch optimizes both RVV VLA && VLS vectorization.

Consider this following case:
void __attribute__((noinline, noclone))
f (int * __restrict dst, int * __restrict op1, int * __restrict op2, int
count)
{
  for (int i = 0; i < count; ++i)
    dst[i] = op1[i] + op2[i];
}

VLA:
Before this patch:
        ble a3,zero,.L1
        srli a4,a1,2
        negw a4,a4
        andi a5,a4,3
        sext.w a3,a3
        beq a5,zero,.L3
        lw a7,0(a1)
        lw a6,0(a2)
        andi a4,a4,2
        addw a6,a6,a7
        sw a6,0(a0)
        beq a4,zero,.L3
        lw a7,4(a1)
        lw a4,4(a2)
        li a6,3
        addw a4,a4,a7
        sw a4,4(a0)
        bne a5,a6,.L3
        lw a6,8(a2)
        lw a4,8(a1)
        addw a4,a4,a6
        sw a4,8(a0)
.L3:
        subw a3,a3,a5
        slli a4,a3,32
        csrr a6,vlenb
        srli a4,a4,32
        srli a6,a6,2
        slli a3,a5,2
        mv a5,a4
        bgtu a4,a6,.L17
.L5:
        csrr a6,vlenb
        add a1,a1,a3
        add a2,a2,a3
        add a0,a0,a3
        srli a7,a6,2
        li a3,0
.L8:
        vsetvli zero,a5,e32,m1,ta,ma
        vle32.v v1,0(a1)
        vle32.v v2,0(a2)
        vsetvli t1,zero,e32,m1,ta,ma
        add a3,a3,a7
        vadd.vv v1,v1,v2
        vsetvli zero,a5,e32,m1,ta,ma
        vse32.v v1,0(a0)
        mv a5,a4
        bleu a4,a3,.L6
        mv a5,a3
.L6:
        sub a5,a4,a5
        bleu a5,a7,.L7
        mv a5,a7
.L7:
        add a1,a1,a6
        add a2,a2,a6
        add a0,a0,a6
        bne a5,zero,.L8
.L1:
        ret
.L17:
        mv a5,a6
        j .L5

After this patch:
f:
        ble     a3,zero,.L1
        csrr    a4,vlenb
        srli    a4,a4,2
        mv      a5,a3
        bgtu    a3,a4,.L9
.L3:
        csrr    a6,vlenb
        li      a4,0
        srli    a7,a6,2
.L6:
        vsetvli zero,a5,e32,m1,ta,ma
        vle32.v v2,0(a1)
        vle32.v v1,0(a2)
        vsetvli t1,zero,e32,m1,ta,ma
        add     a4,a4,a7
        vadd.vv v1,v1,v2
        vsetvli zero,a5,e32,m1,ta,ma
        vse32.v v1,0(a0)
        mv      a5,a3
        bleu    a3,a4,.L4
        mv      a5,a4
.L4:
        sub     a5,a3,a5
        bleu    a5,a7,.L5
        mv      a5,a7
.L5:
        add     a0,a0,a6
        add     a2,a2,a6
        add     a1,a1,a6
        bne     a5,zero,.L6
.L1:
        ret
.L9:
        mv      a5,a4
        j       .L3

VLS:
Before this patch:
f3:
        ble a3,zero,.L1
        srli a5,a1,2
        negw a5,a5
        andi a4,a5,3
        sext.w a3,a3
        beq a4,zero,.L3
        lw a7,0(a1)
        lw a6,0(a2)
        andi a5,a5,2
        addw a6,a6,a7
        sw a6,0(a0)
        beq a5,zero,.L3
        lw a7,4(a1)
        lw a5,4(a2)
        li a6,3
        addw a5,a5,a7
        sw a5,4(a0)
        bne a4,a6,.L3
        lw a6,8(a2)
        lw a5,8(a1)
        addw a5,a5,a6
        sw a5,8(a0)
.L3:
        subw a3,a3,a4
        slli a6,a4,2
        slli a5,a3,32
        srli a5,a5,32
        add a1,a1,a6
        add a2,a2,a6
        add a0,a0,a6
        li a3,4
.L6:
        mv a4,a5
        bleu a5,a3,.L5
        li a4,4
.L5:
        vsetvli zero,a4,e32,m1,ta,ma
        vle32.v v1,0(a1)
        vle32.v v2,0(a2)
        vsetivli zero,4,e32,m1,ta,ma
        sub a5,a5,a4
        vadd.vv v1,v1,v2
        vsetvli zero,a4,e32,m1,ta,ma
        vse32.v v1,0(a0)
        addi a1,a1,16
        addi a2,a2,16
        addi a0,a0,16
        bne a5,zero,.L6
.L1:
        ret

After this patch:
f3:
        ble a3,zero,.L1
        li a4,4
.L4:
        mv a5,a3
        bleu a3,a4,.L3
        li a5,4
.L3:
        vsetvli zero,a5,e32,m1,ta,ma
        vle32.v v2,0(a1)
        vle32.v v1,0(a2)
        vsetivli zero,4,e32,m1,ta,ma
        sub a3,a3,a5
        vadd.vv v1,v1,v2
        vsetvli zero,a5,e32,m1,ta,ma
        vse32.v v1,0(a0)
        addi a2,a2,16
        addi a0,a0,16
        addi a1,a1,16
        bne a3,zero,.L4
.L1:
        ret

Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:

* config/riscv/riscv.cc
(riscv_vectorize_preferred_vector_alignment): New function.
(TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT): New target hook.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Adapt testcase.
* gcc.target/riscv/rvv/autovec/align-1.c: New test.
* gcc.target/riscv/rvv/autovec/align-2.c: New test.

Daily bump.

MATCH: Add pattern for `signbit(x) ? x : -x` into abs (and swapped)

This adds a simple pattern to match.pd for `signbit(x) ? x : -x`
into abs<x>. This can be done for all types even ones that honor
signed zeros and NaNs because both signbit and - are considered
only looking at/touching the sign bit of those types and does
not trap either.

OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.

PR tree-optimization/109829

gcc/ChangeLog:

* match.pd: Add pattern for `signbit(x) !=/== 0 ? x : -x`.

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/abs-3.c: New test.
* gcc.dg/tree-ssa/abs-4.c: New test.

i386: Handle unsupported modes from ix86_widen_mult_cost [PR109807]

Revert my previous change that faked handling of V4HI and V2SImodes
in ix86_widen_mult_cost and rather return arbitrary high value
for unsupported modes. This should prevent cost estimator from
selecting non-existent vector widen multiply operation.

gcc/ChangeLog:

PR target/109807
* config/i386/i386.cc: Revert the 2023-05-11 change.
(ix86_widen_mult_cost): Return high value instead of
ICEing for unsupported modes.

gcc/testsuite/ChangeLog:

PR target/109807
* gcc.target/i386/pr109825.c: New test.

i386: Honour -mdirect-extern-access when calling __fentry__

The small and medium PIC code models generate profiling calls that
always load the address of __fentry__() via the GOT, even if
-mdirect-extern-access is in effect.

This deviates from the behavior with respect to other external
references, and results in a longer opcode that relies on linker
relaxation to eliminate the GOT load. In this particular case, the
transformation replaces an indirect 'CALL *__fentry__@GOTPCREL(%rip)'
with either 'CALL __fentry__; NOP' or 'NOP; CALL __fentry__', where the
NOP is a 1 byte NOP that preserves the 6 byte length of the sequence.

This is problematic for the Linux kernel, which generally relies on
-mdirect-extern-access and hidden visibility to eliminate GOT based
symbol references in code generated with -fpie/-fpic, without having to
depend on linker relaxation.

The Linux kernel relies on code patching to replace these opcodes with
NOPs at runtime, and this is complicated code that we'd prefer not to
complicate even more by adding support for patching both 5 and 6 byte
sequences as well as parsing the instruction stream to decide which
variant of CALL+NOP we are dealing with.

So let's honour -mdirect-extern-access, and only load the address of
__fentry__ via the GOT if direct references to external symbols are not
permitted.

Note that the GOT reference in question is in fact a data reference: we
explicitly load the address of __fentry__ from the GOT, which amounts to
eager binding, rather than emitting a PLT call that could bind eagerly,
lazily or directly at link time.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
gcc/ChangeLog:

* config/i386/i386.cc (x86_function_profiler): Take
ix86_direct_extern_access into account when generating calls
to __fentry__()

RISC-V: Refactor the or pattern to switch cases

This patch refactor the pattern A or B or C or D, to the switch case for
easy add/remove new types, as well as human reading friendly.

Before this patch:
return A || B || C || D;

After this patch:
switch (type)
  {
    case A:
    case B:
    case C:
    case D:
      return true;
    default:
      return false;
  }

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:

* config/riscv/riscv-vector-builtins.cc (required_extensions_p):
Refactor the or pattern to switch cases.

Daily bump.

Replace bool as boolean instead of int in libgm2

This patch tidies KeyBoardLEDs.cc, RTco.cc, sckt.cc
and wrapc.cc by removing the TRUE/FALSE macros and using
bool, true and false.

libgm2/ChangeLog:

* libm2cor/KeyBoardLEDs.cc (TRUE): Remove.
(FALSE): Remove.
(init): Replace TRUE with true.
* libm2iso/RTco.cc (TRUE): Remove.
(FALSE): Remove.
(initSem): Replace int with bool.
(init): Replace FALSE with false.
* libm2pim/sckt.cc (TRUE): Remove.
(FALSE): Remove.
* libm2pim/wrapc.cc: Replace TRUE with true
and FALSE with false.
(FALSE): Remove.
(TRUE): Remove.

Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>

[aarch64] Recursively intialize even and odd sub-parts and merge with zip1.

gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_expand_vector_init_fallback): Rename
aarch64_expand_vector_init to this, and remove  interleaving case.
Recursively call aarch64_expand_vector_init_fallback, instead of
aarch64_expand_vector_init.
(aarch64_unzip_vector_init): New function.
(aarch64_expand_vector_init): Likewise.

gcc/testsuite/ChangeLog:
* gcc.target/aarch64/ldp_stp_16.c (cons2_8_float): Adjust for new
code-gen.
* gcc.target/aarch64/sve/acle/general/dupq_5.c: Likewise.
* gcc.target/aarch64/sve/acle/general/dupq_6.c: Likewise.
* gcc.target/aarch64/interleave-init-1.c: Rename to ...
* gcc.target/aarch64/vec-init-18.c: ... this.
* gcc.target/aarch64/vec-init-19.c: New test.
* gcc.target/aarch64/vec-init-20.c: Likewise.
* gcc.target/aarch64/vec-init-21.c: Likewise.
* gcc.target/aarch64/vec-init-22-size.c: Likewise.
* gcc.target/aarch64/vec-init-22-speed.c: Likewise.
* gcc.target/aarch64/vec-init-22.h: New header.

RISC-V: Pull out function call with side effect from gcc_assert.

It will broken when release mode.

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (pass_vsetvl::cleanup_insns):
Pull out function call from the gcc_assert.

RISC-V: Improve vector_insn_info::dump for LMUL and policy

Convert vlmul and policy to human readable string, some example below:

Before:
[VALID,Demand field={1(VL),0(DEMAND_NONZERO_AVL),1(SEW),0(DEMAND_GE_SEW),1(LMUL),0(RATIO),0(TAIL_POLICY),0(MASK_POLICY)}
AVL=(reg:DI 0 zero)
SEW=16,VLMUL=3,RATIO=2,TAIL_POLICY=1,MASK_POLICY=1]
             ^                     ^             ^

After:
[VALID,Demand field={1(VL),0(DEMAND_NONZERO_AVL),1(SEW),0(DEMAND_GE_SEW),1(LMUL),0(RATIO),0(TAIL_POLICY),0(MASK_POLICY)}
AVL=(reg:DI 0 zero)
SEW=16,VLMUL=m8,RATIO=2,TAIL_POLICY=agnostic,MASK_POLICY=agnostic]
             ^^                     ^^^^^^^^             ^^^^^^^^

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (vlmul_to_str): New.
(policy_to_str): New.
(vector_insn_info::dump): Use vlmul_to_str and policy_to_str.

MATCH: Fix PR 109834, ICE with popcount combined with bswap

After r14-673-gc0dd80e4c4c3, there was a check in the match
patterns which was checking the type is unsigned but
instead of using the type, the patch used the expression.
This adds the needed TREE_TYPE so get the correct answer and don't ICE.

Committed as obvious after a bootstrap/test on x86_64-linux-gnu.

PR tree-optimization/109834

gcc/ChangeLog:

* match.pd (popcount(bswap(x))->popcount(x)): Fix up unsigned type checking.
(popcount(rotate(x,y))->popcount(x)): Likewise.

gcc/testsuite/ChangeLog:

* gcc.c-torture/compile/pr109834-1.c: New test.
* gcc.dg/tree-ssa/pr109834-1.c: New test.

Daily bump.

Fortran: Revise a namelist test case.

PR fortran/109662

gcc/testsuite/ChangeLog:

* gfortran.dg/pr109662-a.f90: Add a section to verify that
a short namelist read does not modify the variable.

Fortran: Initialize last_char for internal units.

PR fortran/109662

libgfortran/ChangeLog:

* io/unit.c (set_internal_unit): Set the internal unit
last_char to zero so that previous EOF characters do not
influence the next read.

i386: Cleanup ix86_expand_vecop_qihi{,2}

Some cleanups while looking at these two functions.

gcc/ChangeLog:

* config/i386/i386-expand.cc (ix86_expand_vecop_qihi2): Also
reject ymm instructions for TARGET_PREFER_AVX128.  Use generic
gen_extend_insn to generate zero/sign extension instructions.
Fix comments.
(ix86_expand_vecop_qihi): Initialize interleave functions
for MULT code only.  Fix comments.

libstdc++: Fix -Wnonnull warnings during configure

We should not test for nan by passing it a null pointer, as this can
trigger -Wnonnull warnings.

Also fix an outdated comment about the default -std mode.

libstdc++-v3/ChangeLog:

* acinclude.m4 (GLIBCXX_CHECK_C99_TR1): Use a non-null pointer
to check for nan, nanf, and nanl.
* configure: Regenerate.

libstdc++: Remove redundant dependencies on _GLIBCXX_USE_C99_STDINT_TR1

We never need to use std::make_unsigned in std::char_traits<char16_t>
and std::char_traits<char32_t> because <cstdint> guarantees to provide
the types we need, since r9-2028-g8ba7f29e3dd064.

Similarly, experimental::source_location can just assume uint_least32_t
is defined by <cstdint>.

libstdc++-v3/ChangeLog:

* include/bits/char_traits.h (char_traits<char16_t>): Do not
depend on _GLIBCXX_USE_C99_STDINT_TR1.
(char_traits<char32_t>): Likewise.
* include/experimental/source_location: Likewise.

libstdc++: Reduce <atomic> dependency on _GLIBCXX_USE_C99_STDINT_TR1

Since r9-2028-g8ba7f29e3dd064 we've defined most of <cstdint>
unconditionally, so we can do the same for most of the std::atomic
aliases such as std::atomic_int_least32_t.

The only aliases that need to depend on _GLIBCXX_USE_C99_STDINT_TR1 are
the ones for the integer types that are not guaranteed to be defined,
e.g. std::atomic_int32_t.

libstdc++-v3/ChangeLog:

* include/std/atomic (atomic_int_least8_t, atomic_uint_least8_t)
(atomic_int_least16_t, atomic_uint_least16_t)
(atomic_int_least32_t, atomic_uint_least32_t)
(atomic_int_least64_t, atomic_uint_least64_t)
(atomic_int_fast16_t, atomic_uint_fast16_t)
(atomic_int_fast32_t, atomic_uint_fast32_t)
(atomic_int_fast64_t, atomic_uint_fast64_t)
(atomic_intmax_t, atomic_uintmax_t): Define unconditionally.
* testsuite/29_atomics/headers/stdatomic.h/c_compat.cc: Adjust.

libstdc++: Remove <random> dependency on _GLIBCXX_USE_C99_STDINT_TR1

Since r9-2028-g8ba7f29e3dd064 we've defined most of <cstdint>
unconditionally, including uint_least32_t. This means that all of
<random> can be defined unconditionally, which means that std::shuffle
and std::ranges::shuffle can be too.

libstdc++-v3/ChangeLog:

* include/bits/algorithmfwd.h (shuffle): Do not depend on
_GLIBCXX_USE_C99_STDINT_TR1.
* include/bits/ranges_algo.h (shuffle): Likewise.
* include/bits/stl_algo.h (shuffle): Likewise.
* include/ext/random: Likewise.
* include/ext/throw_allocator.h (random_condition): Likewise.
* include/std/random: Likewise.
* src/c++11/cow-string-inst.cc: Likewise.
* src/c++11/random.cc: Likewise.

PR modula2/109830 m2iso library SeqFile.mod appending to a file overwrites content

This patch is for the m2iso library SeqFile.mod to fix a bug when a
file is opened using OpenAppend.  The patch checks to see if the file
exists and it uses FIO.OpenForRandom to ensure the file is not
overwritten.

gcc/m2/ChangeLog:

PR modula2/109830
* gm2-libs-iso/SeqFile.mod (newCid): New parameter toAppend
used to select FIO.OpenForRandom.
(OpenRead): Pass extra parameter to newCid.
(OpenWrite): Pass extra parameter to newCid.
(OpenAppend): Pass extra parameter to newCid.

gcc/testsuite/ChangeLog:

PR modula2/109830
* gm2/isolib/run/pass/seqappend.mod: New test.

Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>

i386: Remove mulv2si emulated sequence for TARGET_SSE2 [PR109797]

Remove mulv2si emulated sequence for TARGET_SSE2 and enable
only native PMULLD instruction for TARGET_SSE4_1.  Ideally, the
vectorization for TARGET_SSE2 should depend on more precise cost
estimation (the PR contains patch for ix86_multiplication_cost),
but even with patched cost function the runtime regression
was not fixed.

PR target/109797

gcc/ChangeLog:

* config/i386/mmx.md (mulv2si3): Remove expander.
(mulv2si3): Rename insn pattern from *mulv2si.

LTO: Fix writing of toplevel asm with offloading [PR109816]

When offloading was enabled, top-level 'asm' were added to the offloading
section, confusing assemblers which did not support the syntax. Additionally,
with offloading and -flto, the top-level assembler code did not end up
in the host files.

As r14-321-g9a41d2cdbcd added top-level 'asm' to one libstdc++ header file,
the issue became more apparent, causing fails with nvptx for some
C++ testcases.

PR libstdc++/109816

gcc/ChangeLog:

* lto-cgraph.cc (output_symtab): Guard lto_output_toplevel_asms by
'!lto_stream_offload_p'.

libgomp/ChangeLog:

* testsuite/libgomp.c++/target-map-class-1.C: New test.
* testsuite/libgomp.c++/target-map-class-2.C: New test.

libstdc++: Remove test dependency on _GLIBCXX_USE_C99_STDINT_TR1

This should have been done in r9-2028-g8ba7f29e3dd064 when
std::shared_mutex was changed to be defined without depending on
_GLIBCXX_USE_C99_STDINT_TR1.

libstdc++-v3/ChangeLog:

* testsuite/experimental/feat-cxx14.cc: Remove dependency on
_GLIBCXX_USE_C99_STDINT_TR1.

libstdc++: Remove test dependency on _GLIBCXX_USE_C99_STDINT_TR1

This should have been removed in r9-2029-g612c9c702e2c9e when the
char16_t and char32_t specializations of std::codecvt were changed to be
defined unconditionally.

libstdc++-v3/ChangeLog:

* testsuite/22_locale/locale/cons/unicode.cc: Remove dependency
on _GLIBCXX_USE_C99_STDINT_TR1.

libstdc++: Remove test dependencies on _GLIBCXX_USE_C99_STDINT_TR1

These #ifdef checks should have been removed in r9-2029-g612c9c702e2c9e
when the u16string_view and u32string_view aliases were changed to be
defined unconditionally.

libstdc++-v3/ChangeLog:

* testsuite/21_strings/basic_string_view/typedefs.cc: Remove
dependency on _GLIBCXX_USE_C99_STDINT_TR1.
* testsuite/experimental/string_view/typedefs.cc: Likewise.

RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli [PR 109743]

Rebase to trunk and send V3 patch for:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617821.html

This patch is fixing: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109743.

This issue happens is because we are currently very conservative in optimization of user vsetvli.

Consider this following case:

bb 1:
  vsetvli a5,a4... (demand AVL = a4).
bb 2:
  RVV insn use a5 (demand AVL = a5).

LCM will hoist vsetvl of bb 2 into bb 1.
We don't do AVL propagation for this situation since it's complicated that
we should analyze the code sequence between vsetvli in bb 1 and RVV insn in bb 2.
They are not necessary the consecutive blocks.

This patch is doing the optimizations after LCM, we will check and eliminate the vsetvli
in LCM inserted edge if such vsetvli is redundant. Such approach is much simplier and safe.

code:
void
foo2 (int32_t *a, int32_t *b, int n)
{
  if (n <= 0)
      return;
  int i = n;
  size_t vl = __riscv_vsetvl_e32m1 (i);

  for (; i >= 0; i--)
  {
    vint32m1_t v = __riscv_vle32_v_i32m1 (a, vl);
    __riscv_vse32_v_i32m1 (b, v, vl);

    if (i >= vl)
      continue;

    if (i == 0)
      return;

    vl = __riscv_vsetvl_e32m1 (i);
  }
}

Before this patch:
foo2:
.LFB2:
.cfi_startproc
ble     a2,zero,.L1
mv      a4,a2
li      a3,-1
vsetvli a5,a2,e32,m1,ta,mu
vsetvli zero,a5,e32,m1,ta,ma  <- can be eliminated.
.L5:
vle32.v v1,0(a0)
vse32.v v1,0(a1)
bgeu    a4,a5,.L3
.L10:
beq     a2,zero,.L1
vsetvli a5,a4,e32,m1,ta,mu
addi    a4,a4,-1
vsetvli zero,a5,e32,m1,ta,ma  <- can be eliminated.
vle32.v v1,0(a0)
vse32.v v1,0(a1)
addiw   a2,a2,-1
bltu    a4,a5,.L10
.L3:
addiw   a2,a2,-1
addi    a4,a4,-1
bne     a2,a3,.L5
.L1:
ret

After this patch:
f:
ble     a2,zero,.L1
mv      a4,a2
li      a3,-1
vsetvli a5,a2,e32,m1,ta,ma
.L5:
vle32.v v1,0(a0)
vse32.v v1,0(a1)
bgeu    a4,a5,.L3
.L10:
beq     a2,zero,.L1
vsetvli a5,a4,e32,m1,ta,ma
addi    a4,a4,-1
vle32.v v1,0(a0)
vse32.v v1,0(a1)
addiw   a2,a2,-1
bltu    a4,a5,.L10
.L3:
addiw   a2,a2,-1
addi    a4,a4,-1
bne     a2,a3,.L5
.L1:
ret

PR target/109743

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (pass_vsetvl::get_vsetvl_at_end): New.
(local_avl_compatible_p): New.
(pass_vsetvl::local_eliminate_vsetvl_insn): Enhance local optimizations
for LCM, rewrite as a backward algorithm.
(pass_vsetvl::cleanup_insns): Use new local_eliminate_vsetvl_insn
interface, handle a BB at once.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/pr109743-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/pr109743-2.c: New test.
* gcc.target/riscv/rvv/vsetvl/pr109743-3.c: New test.
* gcc.target/riscv/rvv/vsetvl/pr109743-4.c: New test.

Co-authored-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>

tree-optimization/64731 - extend store-from CTOR lowering to TARGET_MEM_REF

The following also covers TARGET_MEM_REF when decomposing stores from
CTORs to supported elementwise operations.  This avoids spilling
and cleans up after vector lowering which doesn't touch loads or
stores.  It also mimics what we already do for loads.

PR tree-optimization/64731
* tree-ssa-forwprop.cc (pass_forwprop::execute): Also
handle TARGET_MEM_REF destinations of stores from vector
CTORs.

* gcc.target/i386/pr64731.c: New testcase.

c++: remove redundant testcase [PR83258]

I noticed only after the fact that the new testcase template/function2.C
(from r14-708-gc3afdb8ba8f183) is just a subset of ext/visibility/anon8.C,
so let's get rid of it.

PR c++/83258

gcc/testsuite/ChangeLog:

* g++.dg/ext/visibility/anon8.C: Mention PR83258.
* g++.dg/template/function2.C: Removed.

c++: robustify testcase [PR109752]

This rewrites the testcase for PR109752 to make it simpler and more
robust (i.e. no longer dependent on r13-4035-gc41bbfcaf9d6ef).

PR c++/109752

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/concepts-pr109752.C: Rename to ...
* g++.dg/cpp2a/concepts-complete4.C: ... this.  Rewrite.

tree-optimization/109791 - simplify (unsigned)&foo - (unsigned)(&foo + o)

The following adds another variant of address difference simplification.
The utility ptr_difference_const only handles constant differences
(we also cannot code generate anything else), so exposing a possible
POINTER_PLUS_EXPR in the match and computing the difference on the
base only makes it possible to handle one case of a variable offset.
This simplifies

(unsigned long) &MEM <char[3]> [(void *)&str + 2B] - (unsigned long) (&str + (_69 + 1))

down to (1 - (unsigned long) _69) during niter analysis, allowing
ranger to eliminate a condition later and avoiding a bogus
-Wstringop-overflow diagnostic for the testcase in the PR.

PR tree-optimization/109791
* match.pd (minus (convert ADDR_EXPR@0) (convert (pointer_plus @1 @2))):
New pattern.
(minus (convert (pointer_plus @1 @2)) (convert ADDR_EXPR@0)):
Likewise.

arm: [MVE intrinsics] rework vsriq

Implement vsriq using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vsriq): New.
* config/arm/arm-mve-builtins-base.def (vsriq): New.
* config/arm/arm-mve-builtins-base.h (vsriq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vsriq.
* config/arm/arm_mve.h (vsriq): Remove.
(vsriq_m): Remove.
(vsriq_n_u8): Remove.
(vsriq_n_s8): Remove.
(vsriq_n_u16): Remove.
(vsriq_n_s16): Remove.
(vsriq_n_u32): Remove.
(vsriq_n_s32): Remove.
(vsriq_m_n_s8): Remove.
(vsriq_m_n_u8): Remove.
(vsriq_m_n_s16): Remove.
(vsriq_m_n_u16): Remove.
(vsriq_m_n_s32): Remove.
(vsriq_m_n_u32): Remove.
(__arm_vsriq_n_u8): Remove.
(__arm_vsriq_n_s8): Remove.
(__arm_vsriq_n_u16): Remove.
(__arm_vsriq_n_s16): Remove.
(__arm_vsriq_n_u32): Remove.
(__arm_vsriq_n_s32): Remove.
(__arm_vsriq_m_n_s8): Remove.
(__arm_vsriq_m_n_u8): Remove.
(__arm_vsriq_m_n_s16): Remove.
(__arm_vsriq_m_n_u16): Remove.
(__arm_vsriq_m_n_s32): Remove.
(__arm_vsriq_m_n_u32): Remove.
(__arm_vsriq): Remove.
(__arm_vsriq_m): Remove.

arm: [MVE intrinsics] factorize vsriq

Factorize vsriq builtins so that they use parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (mve_insn): Add vsri.
* config/arm/mve.md (mve_vsriq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): .,. this.
(mve_vsriq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.

arm: [MVE intrinsics] add ternary_rshift shape

This patch adds the ternary_rshift shape description.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (ternary_rshift): New.
* config/arm/arm-mve-builtins-shapes.h (ternary_rshift): New.

arm: [MVE intrinsics] rework vsliq

Implement vsliq using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vsliq): New.
* config/arm/arm-mve-builtins-base.def (vsliq): New.
* config/arm/arm-mve-builtins-base.h (vsliq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vsliq.
* config/arm/arm_mve.h (vsliq): Remove.
(vsliq_m): Remove.
(vsliq_n_u8): Remove.
(vsliq_n_s8): Remove.
(vsliq_n_u16): Remove.
(vsliq_n_s16): Remove.
(vsliq_n_u32): Remove.
(vsliq_n_s32): Remove.
(vsliq_m_n_s8): Remove.
(vsliq_m_n_s32): Remove.
(vsliq_m_n_s16): Remove.
(vsliq_m_n_u8): Remove.
(vsliq_m_n_u32): Remove.
(vsliq_m_n_u16): Remove.
(__arm_vsliq_n_u8): Remove.
(__arm_vsliq_n_s8): Remove.
(__arm_vsliq_n_u16): Remove.
(__arm_vsliq_n_s16): Remove.
(__arm_vsliq_n_u32): Remove.
(__arm_vsliq_n_s32): Remove.
(__arm_vsliq_m_n_s8): Remove.
(__arm_vsliq_m_n_s32): Remove.
(__arm_vsliq_m_n_s16): Remove.
(__arm_vsliq_m_n_u8): Remove.
(__arm_vsliq_m_n_u32): Remove.
(__arm_vsliq_m_n_u16): Remove.
(__arm_vsliq): Remove.
(__arm_vsliq_m): Remove.

arm: [MVE intrinsics] factorize vsliq

Factorize vsliq builtins so that they use parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (mve_insn>): Add vsli.
* config/arm/mve.md (mve_vsliq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vsliq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.

arm: [MVE intrinsics] add ternary_lshift shape

This patch adds the ternary_lshift shape description.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (ternary_lshift): New.
* config/arm/arm-mve-builtins-shapes.h (ternary_lshift): New.

arm: [MVE intrinsics] rework vpselq

Implement vpselq using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vpselq): New.
* config/arm/arm-mve-builtins-base.def (vpselq): New.
* config/arm/arm-mve-builtins-base.h (vpselq): New.
* config/arm/arm_mve.h (vpselq): Remove.
(vpselq_u8): Remove.
(vpselq_s8): Remove.
(vpselq_u16): Remove.
(vpselq_s16): Remove.
(vpselq_u32): Remove.
(vpselq_s32): Remove.
(vpselq_u64): Remove.
(vpselq_s64): Remove.
(vpselq_f16): Remove.
(vpselq_f32): Remove.
(__arm_vpselq_u8): Remove.
(__arm_vpselq_s8): Remove.
(__arm_vpselq_u16): Remove.
(__arm_vpselq_s16): Remove.
(__arm_vpselq_u32): Remove.
(__arm_vpselq_s32): Remove.
(__arm_vpselq_u64): Remove.
(__arm_vpselq_s64): Remove.
(__arm_vpselq_f16): Remove.
(__arm_vpselq_f32): Remove.
(__arm_vpselq): Remove.

arm: [MVE intrinsics] add vpsel shape

This patch adds the vpsel shape description.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (vpsel): New.
* config/arm/arm-mve-builtins-shapes.h (vpsel): New.

arm: [MVE intrinsics] factorize vpselq

Factorize vpselq builtins so that they use parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm.cc (arm_expand_vcond): Use gen_mve_q instead of
gen_mve_vpselq.
* config/arm/iterators.md (MVE_VPSELQ_F): New.
(mve_insn): Add vpsel.
* config/arm/mve.md (@mve_vpselq_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(@mve_vpselq_f<mode>): Rename into ...
(@mve_<mve_insn>q_f<mode>): ... this.

arm: [MVE intrinsics] rework vfmaq vfmasq vfmsq

Implement vfmaq, vfmasq, vfmsq using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vfmaq, vfmasq, vfmsq): New.
* config/arm/arm-mve-builtins-base.def (vfmaq, vfmasq, vfmsq): New.
* config/arm/arm-mve-builtins-base.h (vfmaq, vfmasq, vfmsq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vfmaq, vfmasq,
vfmsq.
* config/arm/arm_mve.h (vfmaq): Remove.
(vfmasq): Remove.
(vfmsq): Remove.
(vfmaq_m): Remove.
(vfmasq_m): Remove.
(vfmsq_m): Remove.
(vfmaq_f16): Remove.
(vfmaq_n_f16): Remove.
(vfmasq_n_f16): Remove.
(vfmsq_f16): Remove.
(vfmaq_f32): Remove.
(vfmaq_n_f32): Remove.
(vfmasq_n_f32): Remove.
(vfmsq_f32): Remove.
(vfmaq_m_f32): Remove.
(vfmaq_m_f16): Remove.
(vfmaq_m_n_f32): Remove.
(vfmaq_m_n_f16): Remove.
(vfmasq_m_n_f32): Remove.
(vfmasq_m_n_f16): Remove.
(vfmsq_m_f32): Remove.
(vfmsq_m_f16): Remove.
(__arm_vfmaq_f16): Remove.
(__arm_vfmaq_n_f16): Remove.
(__arm_vfmasq_n_f16): Remove.
(__arm_vfmsq_f16): Remove.
(__arm_vfmaq_f32): Remove.
(__arm_vfmaq_n_f32): Remove.
(__arm_vfmasq_n_f32): Remove.
(__arm_vfmsq_f32): Remove.
(__arm_vfmaq_m_f32): Remove.
(__arm_vfmaq_m_f16): Remove.
(__arm_vfmaq_m_n_f32): Remove.
(__arm_vfmaq_m_n_f16): Remove.
(__arm_vfmasq_m_n_f32): Remove.
(__arm_vfmasq_m_n_f16): Remove.
(__arm_vfmsq_m_f32): Remove.
(__arm_vfmsq_m_f16): Remove.
(__arm_vfmaq): Remove.
(__arm_vfmasq): Remove.
(__arm_vfmsq): Remove.
(__arm_vfmaq_m): Remove.
(__arm_vfmasq_m): Remove.
(__arm_vfmsq_m): Remove.

arm: [MVE intrinsics] factorize vfmaq vfmsq vfmasq

Factorize vmvnq builtins so that they use parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_FP_M_BINARY): Add VFMAQ_M_F,
VFMSQ_M_F.
(MVE_FP_M_N_BINARY): Add VFMAQ_M_N_F, VFMASQ_M_N_F.
(MVE_VFMxQ_F, MVE_VFMAxQ_N_F): New.
(mve_insn): Add vfma, vfmas, vfms.
* config/arm/mve.md (mve_vfmaq_f<mode>, mve_vfmsq_f<mode>): Merge
into ...
(@mve_<mve_insn>q_f<mode>): ... this.
(mve_vfmaq_n_f<mode>, mve_vfmasq_n_f<mode>): Merge into ...
(@mve_<mve_insn>q_n_f<mode>): ... this.
(mve_vfmaq_m_f<mode>, mve_vfmsq_m_f<mode>): Merge into
@mve_<mve_insn>q_m_f<mode>.
(mve_vfmaq_m_n_f<mode>, mve_vfmasq_m_n_f<mode>): Merge into
@mve_<mve_insn>q_m_n_f<mode>.

arm: [MVE intrinsics] add ternary_opt_n shape

This patch adds the ternary_opt_n shape description.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (ternary_opt_n): New.
* config/arm/arm-mve-builtins-shapes.h (ternary_opt_n): New.

arm: [MVE intrinsics] rework vmvnq

Implement vmvnq using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc
(FUNCTION_WITH_RTX_M_N_NO_F): New.
(vmvnq): New.
* config/arm/arm-mve-builtins-base.def (vmvnq): New.
* config/arm/arm-mve-builtins-base.h (vmvnq): New.
* config/arm/arm_mve.h (vmvnq): Remove.
(vmvnq_m): Remove.
(vmvnq_x): Remove.
(vmvnq_s8): Remove.
(vmvnq_s16): Remove.
(vmvnq_s32): Remove.
(vmvnq_n_s16): Remove.
(vmvnq_n_s32): Remove.
(vmvnq_u8): Remove.
(vmvnq_u16): Remove.
(vmvnq_u32): Remove.
(vmvnq_n_u16): Remove.
(vmvnq_n_u32): Remove.
(vmvnq_m_u8): Remove.
(vmvnq_m_s8): Remove.
(vmvnq_m_u16): Remove.
(vmvnq_m_s16): Remove.
(vmvnq_m_u32): Remove.
(vmvnq_m_s32): Remove.
(vmvnq_m_n_s16): Remove.
(vmvnq_m_n_u16): Remove.
(vmvnq_m_n_s32): Remove.
(vmvnq_m_n_u32): Remove.
(vmvnq_x_s8): Remove.
(vmvnq_x_s16): Remove.
(vmvnq_x_s32): Remove.
(vmvnq_x_u8): Remove.
(vmvnq_x_u16): Remove.
(vmvnq_x_u32): Remove.
(vmvnq_x_n_s16): Remove.
(vmvnq_x_n_s32): Remove.
(vmvnq_x_n_u16): Remove.
(vmvnq_x_n_u32): Remove.
(__arm_vmvnq_s8): Remove.
(__arm_vmvnq_s16): Remove.
(__arm_vmvnq_s32): Remove.
(__arm_vmvnq_n_s16): Remove.
(__arm_vmvnq_n_s32): Remove.
(__arm_vmvnq_u8): Remove.
(__arm_vmvnq_u16): Remove.
(__arm_vmvnq_u32): Remove.
(__arm_vmvnq_n_u16): Remove.
(__arm_vmvnq_n_u32): Remove.
(__arm_vmvnq_m_u8): Remove.
(__arm_vmvnq_m_s8): Remove.
(__arm_vmvnq_m_u16): Remove.
(__arm_vmvnq_m_s16): Remove.
(__arm_vmvnq_m_u32): Remove.
(__arm_vmvnq_m_s32): Remove.
(__arm_vmvnq_m_n_s16): Remove.
(__arm_vmvnq_m_n_u16): Remove.
(__arm_vmvnq_m_n_s32): Remove.
(__arm_vmvnq_m_n_u32): Remove.
(__arm_vmvnq_x_s8): Remove.
(__arm_vmvnq_x_s16): Remove.
(__arm_vmvnq_x_s32): Remove.
(__arm_vmvnq_x_u8): Remove.
(__arm_vmvnq_x_u16): Remove.
(__arm_vmvnq_x_u32): Remove.
(__arm_vmvnq_x_n_s16): Remove.
(__arm_vmvnq_x_n_s32): Remove.
(__arm_vmvnq_x_n_u16): Remove.
(__arm_vmvnq_x_n_u32): Remove.
(__arm_vmvnq): Remove.
(__arm_vmvnq_m): Remove.
(__arm_vmvnq_x): Remove.

arm: [MVE intrinsics] factorize vmvnq

Factorize vmvnq builtins so that they use parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (mve_insn): Add vmvn.
* config/arm/mve.md (mve_vmvnq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vmvnq_m_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_<supf><mode>): ... this.
(mve_vmvnq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.

arm: [MVE intrinsics] add mvn shape

This patch adds the mvn shape description.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (mvn): New.
* config/arm/arm-mve-builtins-shapes.h (mvn): New.

arm: [MVE intrinsics] rework vbrsrq

Implement vbrsrq using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vbrsrq): New.
* config/arm/arm-mve-builtins-base.def (vbrsrq): New.
* config/arm/arm-mve-builtins-base.h (vbrsrq): New.
* config/arm/arm_mve.h (vbrsrq): Remove.
(vbrsrq_m): Remove.
(vbrsrq_x): Remove.
(vbrsrq_n_f16): Remove.
(vbrsrq_n_f32): Remove.
(vbrsrq_n_u8): Remove.
(vbrsrq_n_s8): Remove.
(vbrsrq_n_u16): Remove.
(vbrsrq_n_s16): Remove.
(vbrsrq_n_u32): Remove.
(vbrsrq_n_s32): Remove.
(vbrsrq_m_n_s8): Remove.
(vbrsrq_m_n_s32): Remove.
(vbrsrq_m_n_s16): Remove.
(vbrsrq_m_n_u8): Remove.
(vbrsrq_m_n_u32): Remove.
(vbrsrq_m_n_u16): Remove.
(vbrsrq_m_n_f32): Remove.
(vbrsrq_m_n_f16): Remove.
(vbrsrq_x_n_s8): Remove.
(vbrsrq_x_n_s16): Remove.
(vbrsrq_x_n_s32): Remove.
(vbrsrq_x_n_u8): Remove.
(vbrsrq_x_n_u16): Remove.
(vbrsrq_x_n_u32): Remove.
(vbrsrq_x_n_f16): Remove.
(vbrsrq_x_n_f32): Remove.
(__arm_vbrsrq_n_u8): Remove.
(__arm_vbrsrq_n_s8): Remove.
(__arm_vbrsrq_n_u16): Remove.
(__arm_vbrsrq_n_s16): Remove.
(__arm_vbrsrq_n_u32): Remove.
(__arm_vbrsrq_n_s32): Remove.
(__arm_vbrsrq_m_n_s8): Remove.
(__arm_vbrsrq_m_n_s32): Remove.
(__arm_vbrsrq_m_n_s16): Remove.
(__arm_vbrsrq_m_n_u8): Remove.
(__arm_vbrsrq_m_n_u32): Remove.
(__arm_vbrsrq_m_n_u16): Remove.
(__arm_vbrsrq_x_n_s8): Remove.
(__arm_vbrsrq_x_n_s16): Remove.
(__arm_vbrsrq_x_n_s32): Remove.
(__arm_vbrsrq_x_n_u8): Remove.
(__arm_vbrsrq_x_n_u16): Remove.
(__arm_vbrsrq_x_n_u32): Remove.
(__arm_vbrsrq_n_f16): Remove.
(__arm_vbrsrq_n_f32): Remove.
(__arm_vbrsrq_m_n_f32): Remove.
(__arm_vbrsrq_m_n_f16): Remove.
(__arm_vbrsrq_x_n_f16): Remove.
(__arm_vbrsrq_x_n_f32): Remove.
(__arm_vbrsrq): Remove.
(__arm_vbrsrq_m): Remove.
(__arm_vbrsrq_x): Remove.

arm: [MVE intrinsics] factorize vrbsrq

Factorize vrbsrq builtins so that they use parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_VBRSR_M_N_FP, MVE_VBRSR_N_FP): New.
(mve_insn): Add vbrsr.
* config/arm/mve.md (mve_vbrsrq_n_f<mode>): Rename into ...
(@mve_<mve_insn>q_n_f<mode>): ... this.
(mve_vbrsrq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vbrsrq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
(mve_vbrsrq_m_n_f<mode>): Rename into ...
(@mve_<mve_insn>q_m_n_f<mode>): ... this.

arm: [MVE intrinsics] add binary_imm32 shape

This patch adds the binary_imm32 shape description.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_imm32): New.
* config/arm/arm-mve-builtins-shapes.h (binary_imm32): New.

arm: [MVE intrinsics] rework vqshluq

Implement vqshluq using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vqshluq): New.
* config/arm/arm-mve-builtins-base.def (vqshluq): New.
* config/arm/arm-mve-builtins-base.h (vqshluq): New.
* config/arm/arm_mve.h (vqshluq): Remove.
(vqshluq_m): Remove.
(vqshluq_n_s8): Remove.
(vqshluq_n_s16): Remove.
(vqshluq_n_s32): Remove.
(vqshluq_m_n_s8): Remove.
(vqshluq_m_n_s16): Remove.
(vqshluq_m_n_s32): Remove.
(__arm_vqshluq_n_s8): Remove.
(__arm_vqshluq_n_s16): Remove.
(__arm_vqshluq_n_s32): Remove.
(__arm_vqshluq_m_n_s8): Remove.
(__arm_vqshluq_m_n_s16): Remove.
(__arm_vqshluq_m_n_s32): Remove.
(__arm_vqshluq): Remove.
(__arm_vqshluq_m): Remove.

arm: [MVE intrinsics] factorize vqshluq

Factorize vqshluq builtins so that they use parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (mve_insn): Add vqshlu.
(supf): Add VQSHLUQ_M_N_S, VQSHLUQ_N_S.
(VQSHLUQ_M_N, VQSHLUQ_N): New.
* config/arm/mve.md (mve_vqshluq_n_s<mode>): Change name into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vqshluq_m_n_s<mode>): Change name into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.

arm: [MVE intrinsics] add binary_lshift_unsigned shape

This patch adds the binary_lshift_unsigned shape description.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc
(binary_lshift_unsigned): New.
* config/arm/arm-mve-builtins-shapes.h
(binary_lshift_unsigned): New.

arm: [MVE intrinsics] rework vrmlaldavhaq vrmlaldavhaxq vrmlsldavhaq vrmlsldavhaxq

Implement vrmlaldavhaq, vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq
using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vrmlaldavhaq)
(vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq): New.
* config/arm/arm-mve-builtins-base.def (vrmlaldavhaq)
(vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq): New.
* config/arm/arm-mve-builtins-base.h (vrmlaldavhaq)
(vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq): New.
* config/arm/arm-mve-builtins-functions.h: Handle vrmlaldavhaq,
vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq.
* config/arm/arm_mve.h (vrmlaldavhaq): Remove.
(vrmlaldavhaxq): Remove.
(vrmlsldavhaq): Remove.
(vrmlsldavhaxq): Remove.
(vrmlaldavhaq_p): Remove.
(vrmlaldavhaxq_p): Remove.
(vrmlsldavhaq_p): Remove.
(vrmlsldavhaxq_p): Remove.
(vrmlaldavhaq_s32): Remove.
(vrmlaldavhaq_u32): Remove.
(vrmlaldavhaxq_s32): Remove.
(vrmlsldavhaq_s32): Remove.
(vrmlsldavhaxq_s32): Remove.
(vrmlaldavhaq_p_s32): Remove.
(vrmlaldavhaq_p_u32): Remove.
(vrmlaldavhaxq_p_s32): Remove.
(vrmlsldavhaq_p_s32): Remove.
(vrmlsldavhaxq_p_s32): Remove.
(__arm_vrmlaldavhaq_s32): Remove.
(__arm_vrmlaldavhaq_u32): Remove.
(__arm_vrmlaldavhaxq_s32): Remove.
(__arm_vrmlsldavhaq_s32): Remove.
(__arm_vrmlsldavhaxq_s32): Remove.
(__arm_vrmlaldavhaq_p_s32): Remove.
(__arm_vrmlaldavhaq_p_u32): Remove.
(__arm_vrmlaldavhaxq_p_s32): Remove.
(__arm_vrmlsldavhaq_p_s32): Remove.
(__arm_vrmlsldavhaxq_p_s32): Remove.
(__arm_vrmlaldavhaq): Remove.
(__arm_vrmlaldavhaxq): Remove.
(__arm_vrmlsldavhaq): Remove.
(__arm_vrmlsldavhaxq): Remove.
(__arm_vrmlaldavhaq_p): Remove.
(__arm_vrmlaldavhaxq_p): Remove.
(__arm_vrmlsldavhaq_p): Remove.
(__arm_vrmlsldavhaxq_p): Remove.

arm: [MVE intrinsics] factorize vrmlaldavhaq vrmlaldavhaxq vrmlsldavhaq vrmlsldavhaxq

Factorize vrmlaldavhaq, vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq
builtins so that they use the same parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_VRMLxLDAVHAxQ)
(MVE_VRMLxLDAVHAxQ_P): New.
(mve_insn): Add vrmlaldavha, vrmlaldavhax, vrmlsldavha,
vrmlsldavhax.
(supf): Add VRMLALDAVHAXQ_P_S, VRMLALDAVHAXQ_S, VRMLSLDAVHAQ_P_S,
VRMLSLDAVHAQ_S, VRMLSLDAVHAXQ_P_S, VRMLSLDAVHAXQ_S,
VRMLALDAVHAQ_P_S.
* config/arm/mve.md (mve_vrmlaldavhaq_<supf>v4si)
(mve_vrmlaldavhaxq_sv4si, mve_vrmlsldavhaxq_sv4si)
(mve_vrmlsldavhaq_sv4si): Merge into ...
(@mve_<mve_insn>q_<supf>v4si): ... this.
(mve_vrmlaldavhaq_p_sv4si, mve_vrmlaldavhaq_p_uv4si)
(mve_vrmlaldavhaxq_p_sv4si, mve_vrmlsldavhaq_p_sv4si)
(mve_vrmlsldavhaxq_p_sv4si): Merge into ...
(@mve_<mve_insn>q_p_<supf>v4si): ... this.

arm: [MVE intrinsics] rework vqdmullbq vqdmulltq

Implement vqdmullbq, vqdmulltq using the new MVE builtins framework.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-base.cc (vqdmullbq, vqdmulltq): New.
* config/arm/arm-mve-builtins-base.def (vqdmullbq, vqdmulltq):
New.
* config/arm/arm-mve-builtins-base.h (vqdmullbq, vqdmulltq): New.
* config/arm/arm_mve.h (vqdmulltq): Remove.
(vqdmullbq): Remove.
(vqdmullbq_m): Remove.
(vqdmulltq_m): Remove.
(vqdmulltq_s16): Remove.
(vqdmulltq_n_s16): Remove.
(vqdmullbq_s16): Remove.
(vqdmullbq_n_s16): Remove.
(vqdmulltq_s32): Remove.
(vqdmulltq_n_s32): Remove.
(vqdmullbq_s32): Remove.
(vqdmullbq_n_s32): Remove.
(vqdmullbq_m_n_s32): Remove.
(vqdmullbq_m_n_s16): Remove.
(vqdmullbq_m_s32): Remove.
(vqdmullbq_m_s16): Remove.
(vqdmulltq_m_n_s32): Remove.
(vqdmulltq_m_n_s16): Remove.
(vqdmulltq_m_s32): Remove.
(vqdmulltq_m_s16): Remove.
(__arm_vqdmulltq_s16): Remove.
(__arm_vqdmulltq_n_s16): Remove.
(__arm_vqdmullbq_s16): Remove.
(__arm_vqdmullbq_n_s16): Remove.
(__arm_vqdmulltq_s32): Remove.
(__arm_vqdmulltq_n_s32): Remove.
(__arm_vqdmullbq_s32): Remove.
(__arm_vqdmullbq_n_s32): Remove.
(__arm_vqdmullbq_m_n_s32): Remove.
(__arm_vqdmullbq_m_n_s16): Remove.
(__arm_vqdmullbq_m_s32): Remove.
(__arm_vqdmullbq_m_s16): Remove.
(__arm_vqdmulltq_m_n_s32): Remove.
(__arm_vqdmulltq_m_n_s16): Remove.
(__arm_vqdmulltq_m_s32): Remove.
(__arm_vqdmulltq_m_s16): Remove.
(__arm_vqdmulltq): Remove.
(__arm_vqdmullbq): Remove.
(__arm_vqdmullbq_m): Remove.
(__arm_vqdmulltq_m): Remove.

arm: [MVE intrinsics] factorize vqdmullbq vqdmulltq

Factorize vqdmullbq, vqdmulltq builtins so that they use the same
parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/iterators.md (MVE_VQDMULLxQ, MVE_VQDMULLxQ_M)
(MVE_VQDMULLxQ_M_N, MVE_VQDMULLxQ_N): New.
(mve_insn): Add vqdmullb, vqdmullt.
(supf): Add VQDMULLBQ_S, VQDMULLBQ_M_S, VQDMULLBQ_M_N_S,
VQDMULLBQ_N_S, VQDMULLTQ_S, VQDMULLTQ_M_S, VQDMULLTQ_M_N_S,
VQDMULLTQ_N_S.
* config/arm/mve.md (mve_vqdmullbq_n_s<mode>)
(mve_vqdmulltq_n_s<mode>): Merge into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vqdmullbq_s<mode>, mve_vqdmulltq_s<mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vqdmullbq_m_n_s<mode>, mve_vqdmulltq_m_n_s<mode>): Merge into
...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
(mve_vqdmullbq_m_s<mode>, mve_vqdmulltq_m_s<mode>): Merge into ...
(@mve_<mve_insn>q_m_<supf><mode>): ... this.

arm: [MVE intrinsics] add binary_widen_opt_n shape

This patch adds the binary_widen_opt_n shape description.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

gcc/
* config/arm/arm-mve-builtins-shapes.cc (binary_widen_opt_n): New.
* config/arm/arm-mve-builtins-shapes.h (binary_widen_opt_n): New.

RISC-V: Suppress unused parameter warning in riscv-common.cc

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_select_multilib_by_abi):
Drop unused parameter.
(riscv_select_multilib): Ditto.
(riscv_compute_multilib): Update call site of
riscv_select_multilib_by_abi and riscv_select_multilib_by_abi.

libgomp testsuite: Generalize 'lang_library_path' into a list of 'lang_library_paths'

..., and use that for libquadmath, too.

libgomp/
* testsuite/lib/libgomp.exp (libgomp_target_compile): Generalize
'lang_library_path' into a list of 'lang_library_paths'.
* testsuite/libgomp.c++/c++.exp: Adjust.
* testsuite/libgomp.oacc-c++/c++.exp: Likewise.
* testsuite/libgomp.fortran/fortran.exp: Adjust.  Use that for
libquadmath, too.
* testsuite/libgomp.oacc-fortran/fortran.exp: Likewise.

libgomp testsuite: Get rid of 'lang_test_file_found'

Instead, 'return' early from the '*.exp' files that we're not able to test.
Also, change 'puts' into 'verbose -log'.  While re-indenting the previous
'if { $lang_test_file_found } { [...] }' code, also simplify 'ld_library_path'
setup.

libgomp/
* testsuite/lib/libgomp.exp (libgomp_target_compile): Don't look
at 'lang_test_file_found'.
* testsuite/libgomp.c++/c++.exp: Don't set and use it, and instead
'return' early if not able to test.  Simplify 'ld_library_path' setup.
* testsuite/libgomp.fortran/fortran.exp: Likewise.
* testsuite/libgomp.oacc-c++/c++.exp: Likewise.
* testsuite/libgomp.oacc-fortran/fortran.exp: Likewise.

libgomp C++, Fortran testsuites: Resolve 'lang_test_file_found' first

libgomp/
* testsuite/libgomp.c++/c++.exp: Resolve 'lang_test_file_found'
first.
* testsuite/libgomp.fortran/fortran.exp: Likewise.
* testsuite/libgomp.oacc-c++/c++.exp: Likewise.
* testsuite/libgomp.oacc-fortran/fortran.exp: Likewise.

libgomp testsuite: Localize 'lang_[...]' etc.

..., instead of letting them bleed into the next '*.exp' file, requiring
clean-up there.

libgomp/
* testsuite/libgomp.c++/c++.exp: Localize 'lang_[...]' etc.
* testsuite/libgomp.c/c.exp: Likewise.
* testsuite/libgomp.fortran/fortran.exp: Likewise.
* testsuite/libgomp.graphite/graphite.exp: Likewise.
* testsuite/libgomp.oacc-c++/c++.exp: Likewise.
* testsuite/libgomp.oacc-c/c.exp: Likewise.
* testsuite/libgomp.oacc-fortran/fortran.exp: Likewise.

RISC-V: Fix fail of vmv-imm-rv64.c in rv32

After update local codebase to the trunk. I realize there is one more
fail in RV32.
After this patch, all fails of RVV are cleaned up.
Thanks.

FAIL: gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c -O3 -ftree-vectorize
(test for excess errors)
Excess errors:
cc1: error: ABI requires '-march=rv32'

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: Add ABI

Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai>

RISC-V: Add basic vec_init for VLS RVV auto-vectorization

typedef int8_t vnx16qi __attribute__((vector_size (16)));

typedef int8_t vnx16qi __attribute__ ((vector_size (16)));
typedef int8_t vnx32qi __attribute__ ((vector_size (32)));
typedef int8_t vnx64qi __attribute__ ((vector_size (64)));
typedef int8_t vnx128qi __attribute__ ((vector_size (128)));

__attribute__ ((noipa)) void
f_vnx128qi (int8_t a, int8_t b, int8_t c, int8_t d, int8_t e, int8_t f,
int8_t g, int8_t h, int8_t *out)
{
  vnx128qi v
    = {a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h,
       a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h,
       a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h,
       a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h,
       a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h,
       a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h,
       a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h,
       a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h};
  *(vnx128qi *) out = v;
}

This patch codegen:
f_vnx128qi:
        andi    a1,a1,0xff
        andi    a0,a0,0xff
        slli    a1,a1,8
        andi    a2,a2,0xff
        or      a1,a1,a0
        slli    a2,a2,16
        andi    a3,a3,0xff
        or      a2,a2,a1
        slli    a3,a3,24
        andi    a4,a4,0xff
        or      a3,a3,a2
        slli    a4,a4,32
        andi    a5,a5,0xff
        or      a4,a4,a3
        slli    a5,a5,40
        andi    a6,a6,0xff
        or      a5,a5,a4
        slli    a6,a6,48
        or      a6,a6,a5
        vsetvli a5,zero,e64,m8,ta,ma
        ld      a5,0(sp)
        slli    a7,a7,56
        or      a7,a7,a6
        vmv.v.x v8,a7
        vs8r.v  v8,0(a5)
        ret

We support more optimizations cases in the future. But they are not
included in this patch.

Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:

* config/riscv/autovec.md (vec_init<mode><vel>): New pattern.
* config/riscv/riscv-protos.h (expand_vec_init): New function.
* config/riscv/riscv-v.cc (class rvv_builder): New class.
(rvv_builder::can_duplicate_repeating_sequence_p): New function.
(rvv_builder::get_merged_repeating_sequence): Ditto.
(expand_vector_init_insert_elems): Ditto.
(expand_vec_init): Ditto.
* config/riscv/vector-iterators.md: New attribute.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/rvv.exp:
* gcc.target/riscv/rvv/autovec/vls-vlmax/insert-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/insert-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/insert-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-6.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: New test.

RISC-V: Reorganize binary autovec testcases

1. This patch is moving binary autovec testcases into binop directory to
   make it
easier to maintain.

2. Current binary autovec only tested in LMUL = 1, enable testing in
   LMUL = 2/4/8.

Tested on both rv32/rv64, with no fails in RVV.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/shift-run-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/shift-run-template.h: ...here.
* gcc.target/riscv/rvv/autovec/shift-run.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/shift-run.c: ...here.
* gcc.target/riscv/rvv/autovec/shift-rv32gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/shift-rv64gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/shift-scalar-run.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: ...here.
* gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/shift-scalar-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h: ...here.
* gcc.target/riscv/rvv/autovec/shift-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/shift-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vadd-run-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vadd-run-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vadd-run.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vadd-run.c: ...here.
* gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vadd-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vadd-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vand-run-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vand-run-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vand-run.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vand-run.c: ...here.
* gcc.target/riscv/rvv/autovec/vand-rv32gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vand-rv64gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vand-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vand-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vdiv-run-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vdiv-run-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vdiv-run.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: ...here.
* gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vdiv-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vdiv-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vmax-run-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vmax-run-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vmax-run.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vmax-run.c: ...here.
* gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vmax-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vmax-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vmin-run-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vmin-run-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vmin-run.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vmin-run.c: ...here.
* gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vmin-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vmin-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vmul-run-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vmul-run-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vmul-run.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vmul-run.c: ...here.
* gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vmul-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vmul-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vor-run-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vor-run-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vor-run.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vor-run.c: ...here.
* gcc.target/riscv/rvv/autovec/vor-rv32gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vor-rv64gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vor-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vor-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vrem-run-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vrem-run-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vrem-run.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vrem-run.c: ...here.
* gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vrem-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vrem-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vsub-run-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vsub-run-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vsub-run.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vsub-run.c: ...here.
* gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vsub-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vsub-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vxor-run-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vxor-run-template.h: ...here.
* gcc.target/riscv/rvv/autovec/vxor-run.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vxor-run.c: ...here.
* gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: ...here.
* gcc.target/riscv/rvv/autovec/vxor-template.h: Moved to...
* gcc.target/riscv/rvv/autovec/binop/vxor-template.h: ...here.
* gcc.target/riscv/rvv/rvv.exp: Add autovec LMUL = 2/4/8 for binary.

Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai>

RISC-V: Fix RVV binary auto-vectorizaiton test fails

In rv32:
FAIL: gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c -O3 -ftree-vectorize
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vmin-run.c -O3 -ftree-vectorize (test
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c -O3 -ftree-vectorize
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vand-run.c -O3 -ftree-vectorize (test
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vrem-run.c -O3 -ftree-vectorize (test
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c -O3 -ftree-vectorize
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vmul-run.c -O3 -ftree-vectorize (test
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/shift-run.c -O3 -ftree-vectorize
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c -O3 -ftree-vectorize
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vand-rv64gcv.c -O3 -ftree-vectorize
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vdiv-run.c -O3 -ftree-vectorize (test
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c -O3 -ftree-vectorize
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vor-run.c -O3 -ftree-vectorize (test
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/shift-rv64gcv.c -O3 -ftree-vectorize
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/shift-scalar-run.c -O3
-ftree-vectorize (test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c -O3 -ftree-vectorize
(test for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vmax-run.c -O3 -ftree-vectorize (test
for excess errors)
FAIL: gcc.target/riscv/rvv/autovec/vor-rv64gcv.c -O3 -ftree-vectorize
(test for excess errors)

In rv64:
FAIL: gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c -O3 -ftree-vectorize
(test for excess errors)

Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai>
gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/shift-run.c: Fix fail.
* gcc.target/riscv/rvv/autovec/shift-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/shift-scalar-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/vand-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/vand-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/vdiv-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/vmax-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/vmin-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/vmul-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/vor-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/vor-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/vrem-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/vxor-run.c: Ditto.
* gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c: Ditto.

rs6000: Change ilp32 target check for scalar-extract-sig and scalar-insert-exp test cases

gcc/testsuite/
* gcc.target/powerpc/bfp/scalar-extract-sig-2.c: Replace ilp32 check
with dg-skip-if has_arch_ppc64.
* gcc.target/powerpc/bfp/scalar-insert-exp-2.c: Likewise.
* gcc.target/powerpc/bfp/scalar-insert-exp-5.c: Likewise.

rs6000: Change mode and insn condition for scalar insert exp instruction

gcc/
* config/rs6000/rs6000-builtins.def
(__builtin_vsx_scalar_insert_exp): Replace bif-pattern from xsiexpdp
to xsiexpdp_di.
(__builtin_vsx_scalar_insert_exp_dp): Replace bif-pattern from
xsiexpdpf to xsiexpdpf_di.
* config/rs6000/vsx.md (xsiexpdp): Rename to...
(xsiexpdp_<mode>): ..., set the mode of second operand to GPR and
replace TARGET_64BIT with TARGET_POWERPC64.
(xsiexpdpf): Rename to...
(xsiexpdpf_<mode>): ..., set the mode of second operand to GPR and
replace TARGET_64BIT with TARGET_POWERPC64.

gcc/testsuite/
* gcc.target/powerpc/bfp/scalar-insert-exp-0.c: Replace lp64 check
with has_arch_ppc64.
* gcc.target/powerpc/bfp/scalar-insert-exp-1.c: Likewise.
* gcc.target/powerpc/bfp/scalar-insert-exp-12.c: Likewise.
* gcc.target/powerpc/bfp/scalar-insert-exp-13.c: Likewise.
* gcc.target/powerpc/bfp/scalar-insert-exp-3.c: Likewise.
* gcc.target/powerpc/bfp/scalar-insert-exp-4.c: Likewise.

rs6000: Change mode and insn condition for scalar extract sig instruction

gcc/
* config/rs6000/rs6000-builtins.def
(__builtin_vsx_scalar_extract_sig): Set return type to const signed
long long.
* config/rs6000/vsx.md (xsxsigdp): Replace TARGET_64BIT with
TARGET_POWERPC64.

gcc/testsuite/
* gcc.target/powerpc/bfp/scalar-extract-sig-0.c: Replace lp64 check
with has_arch_ppc64.
* gcc.target/powerpc/bfp/scalar-extract-sig-1.c: Likewise.
* gcc.target/powerpc/bfp/scalar-extract-sig-6.c: Likewise.

rs6000: Change mode and insn condition for scalar extract exp instruction

gcc/
* config/rs6000/rs6000-builtins.def
(__builtin_vsx_scalar_extract_exp): Set return type to const signed
int and set its bif-pattern to xsxexpdp_si, move it from power9-64
to power9 catalog.
* config/rs6000/vsx.md (xsxexpdp): Rename to ...
(xsxexpdp_<mode>): ..., set mode of operand 0 to GPR and remove
TARGET_64BIT check.
* doc/extend.texi (scalar_extract_exp): Remove 64-bit environment
requirement when it has a 64-bit argument.

gcc/testsuite/
* gcc.target/powerpc/bfp/scalar-extract-exp-0.c: Remove lp64 check.
* gcc.target/powerpc/bfp/scalar-extract-exp-1.c: Likewise.
* gcc.target/powerpc/bfp/scalar-extract-exp-2.c: Delete as the case
is invalid now.
* gcc.target/powerpc/bfp/scalar-extract-exp-6.c: Remove lp64 check.

Var-Tracking: Typedef pointer_mux<tree_node, rtx_def> as decl_or_value

The decl_or_value is defined as void * before this PATCH. It will take
care of both the tree_node and rtx_def. Unfortunately, given a void
pointer cannot tell the input is tree_node or rtx_def.

Then we have some implicit structure layout requirement similar as
below. Or we will touch unreasonable bits when cast void * to tree_node
or rtx_def.

+--------+-----------+----------+
| offset | tree_node | rtx_def  |
+--------+-----------+----------+
|      0 | code: 16  | code: 16 | <- require the same location and bitssize
+--------+-----------+----------+
|     16 | ...       | mode: 8  |
+--------+-----------+----------+
| ...                           |
+--------+-----------+----------+
|     24 | ...       | ...      |
+--------+-----------+----------+

This behavior blocks the PATCH that extend the rtx_def mode from 8 to
16 bits for running out of machine mode. This PATCH introduced the
pointer_mux to tell the input is tree_node or rtx_def, and decouple
the above implicit dependency.

Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored-By: Richard Sandiford <richard.sandiford@arm.com>
Co-Authored-By: Richard Biener <rguenther@suse.de>
Co-Authored-By: Jakub Jelinek <jakub@redhat.com>
gcc/ChangeLog:

* mux-utils.h: Add overload operator == and != for pointer_mux.
* var-tracking.cc: Included mux-utils.h for pointer_tmux.
(decl_or_value): Changed from void * to pointer_mux<tree_node, rtx_def>.
(dv_is_decl_p): Reconciled to the new type, aka pointer_mux.
(dv_as_decl): Ditto.
(dv_as_opaque): Removed due to unnecessary.
(struct variable_hasher): Take decl_or_value as compare_type.
(variable_hasher::equal): Diito.
(dv_from_decl): Reconciled to the new type, aka pointer_mux.
(dv_from_value): Ditto.
(attrs_list_member):  Ditto.
(vars_copy): Ditto.
(var_reg_decl_set): Ditto.
(var_reg_delete_and_set): Ditto.
(find_loc_in_1pdv): Ditto.
(canonicalize_values_star): Ditto.
(variable_post_merge_new_vals): Ditto.
(dump_onepart_variable_differences): Ditto.
(variable_different_p): Ditto.
(set_slot_part): Ditto.
(clobber_slot_part): Ditto.
(clobber_variable_part): Ditto.

Daily bump.

PR modula2/109810 ICE fix when an array is assigned by a larger string

This patch fixes an ICE when an array variable is assigned with
a string which exceeds the array size.  It improves the accuracy
of the virtual token used to indicate the error message.

gcc/m2/ChangeLog:

PR modula2/109810
* gm2-compiler/M2ALU.mod (ConvertConstToType): Use
PrepareCopyString in place of DoCopyString.
* gm2-compiler/M2GenGCC.def (DoCopyString): Rename to ...
(PrepareCopyString): ... this.
* gm2-compiler/M2GenGCC.mod (CodeStatement): Call CodeReturnValue
with a single parameter.  Call CodeXIndr with a single parameter.
(CodeReturnValue): Remove parameters and replace with a single
quadno.  Reimplement using PrepareCopyString.  Issue error
if the string exceeds designator space.
(DoCopyString): Reimplement and rename to ...
(PrepareCopyString): ... this.
(CodeXIndr): Remove parameters and replace with a single
quadno.  Reimplement using PrepareCopyString.  Issue error
if the string exceeds designator space.
(CodeBecomes): Remove parameters and replace with a single
quadno.  Reimplement using PrepareCopyString.  Issue error
if the string exceeds designator space.
* gm2-compiler/M2Quads.def (BuildReturn): Rename parameter to
tokreturn.
* gm2-compiler/M2Quads.mod (BuildReturn): Rename parameter to
tokreturn.  Rename tokno to tokcombined.

gcc/testsuite/ChangeLog:

PR modula2/109810
* gm2/pim/fail/highice.mod: New test.

Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>

c++: 'mutable' subobject of constexpr variable [PR109745]

r13-2701-g7107ea6fb933f1 made us correctly accept during constexpr
evaluation 'mutable' member accesses of objects constructed during
that evaluation, while continuing to reject such accesses for constexpr
objects constructed outside of that evaluation, by considering the
CONSTRUCTOR_MUTABLE_POISON flag during cxx_eval_component_reference.

However, this flag is set only for the outermost CONSTRUCTOR of a
constexpr variable initializer, so if we're accessing a 'mutable' member
of a nested CONSTRUCTOR, the flag won't be set and we won't reject the
access.  This can lead to us accepting invalid code, as in the first
testcase, or even wrong code generation due to our speculative constexpr
evaluation, as in the second and third testcase.

This patch fixes this by setting CONSTRUCTOR_MUTABLE_POISON recursively
rather than only on the outermost CONSTRUCTOR.

PR c++/109745

gcc/cp/ChangeLog:

* typeck2.cc (poison_mutable_constructors): Define.
(store_init_value): Use it instead of setting
CONSTRUCTOR_MUTABLE_POISON directly.

gcc/testsuite/ChangeLog:

* g++.dg/cpp0x/constexpr-mutable4.C: New test.
* g++.dg/cpp0x/constexpr-mutable5.C: New test.
* g++.dg/cpp1y/constexpr-mutable2.C: New test.

libstdc++: Use RAII types in strtod-based std::from_chars implementation

This adds auto_locale and auto_ferounding types to use RAII for changing
and restoring the local and floating-point environment when using strtod
to implement std::from_chars.

The destructors for the RAII objects run slightly later than the
previous statements that restored the locale/fenv, but the differences
are just some trivial assignments and an isinf call.

Reviewed-by: Patrick Palka <ppalka@redhat.com>
libstdc++-v3/ChangeLog:

* src/c++17/floating_from_chars.cc [USE_STRTOD_FOR_FROM_CHARS]
(auto_locale, auto_ferounding): New class types.
(from_chars_impl): Use auto_locale and auto_ferounding.

libstdc++: Fix chrono::hh_mm_ss::subseconds() [PR109772]

I borked the logic in r13-4526-g5329e1a8e1480d so that the selected
partial specialization of hh_mm_ss::__subseconds might not be able to
represent the correct number of subseconds. This can result in a
truncated value being stored for the subseconds, e.g., 4755859375 gets
truncated to 460892079 because the correct value doesn't fit in
uint_least32_t.

Instead of checking whether the maximum value of the incoming duration
type can be represented, we would need to check whether that maximum value
can be represented after being converted to the correct precision type:

       template<typename _Tp>
         static constexpr bool __fits
           = duration_cast<precision>(_Duration::max()).count()
               <= duration_values<_Tp>::max();

However, this can fail to compile, due to integer overflow in the
constexpr multiplications. Instead, we could limit the check to the case
where the incoming duration has the same period as the precision, where
no conversion is needed and so no overflow can happen. But that seems of
very limited value, as it would only benefit specializations like
hh_mm_ss<duration<int, std::pico>>, which can only represent a
time-of-day between -00:00:00.0215 and +00:00:00.0215 measured in
picoseconds!

Additionally, the hh_mm_ss::__subseconds partial specializations do not
have disjoint constraints, so that some hh_mm_ss specializations result
in ambiguities tying to match a __subseconds partial specialization.

The most practical fix is to just stop using the __fits variable
template in the constraints of the partial specializations. This fixes
the truncated values by not selecting an inappropriate partial
specialization, and fixes the ambiguous match by ensuring the
constraints are disjoint.

Fixing this changes the layout of some specializations, so is an ABI
change. It only affects specializations that have a small (less than
64-bit) representation type and either a very small period (e.g. like
the picosecond specialization above) or a non-power-of-ten period like
ratio<1, 1024>.  For example both hh_mm_ss<duration<int, std::pico>> and
hh_mm_ss<duration<int, ratio<1, 1024>> are affected (increasing from 16
bytes to 24 on x86_64), but hh_mm_ss<duration<int, ratio<1, 1000>> and
hh_mm_ss<duration<long, ratio<1, 1024>> are not affected.

libstdc++-v3/ChangeLog:

PR libstdc++/109772
* include/std/chrono (hh_mm_ss::__fits): Remove variable
template.
(hh_mm_ss::__subseconds): Remove __fits from constraints.
* testsuite/std/time/hh_mm_ss/109772.cc: New test.
* testsuite/std/time/hh_mm_ss/1.cc: Adjust expected size for
hh_mm_ss<duration<int, std::pico>>.