Uros Bizjak [Tue, 5 Jan 2021 13:42:29 +0000 (14:42 +0100)]
i386: Prevent spurious FP exceptions with _mm_cvt{,t}ps_pi32 [PR98522]
Prevent spurious FP exceptions with _mm_cvt{,t}ps_pi32 for TARGET_MMX_WITH_SSE
by clearing the top 64 bytes of the input XMM register.
2021-01-05 Uroš Bizjak <ubizjak@gmail.com>
gcc/
PR target/98522
* config/i386/sse.md (sse_cvtps2pi): Redefine as define_insn_and_split.
Clear the top 64 bytes of the input XMM register.
(sse_cvttps2pi): Ditto.
gcc/testsuite
PR target/98522
* gcc.target/i386/pr98522.c: New test.
Nathan Sidwell [Tue, 5 Jan 2021 13:18:50 +0000 (05:18 -0800)]
[c++]: Improve module-decl diagnostics [PR 98327]
The diagnostic for a misplaced module decl was essentially 'computer
says no', which isn't the most helpful. This adjusts it to indicate
what would be acceptable.
gcc/cp/
* parser.c (cp_parser_module_declaration): Alter diagnostic
text to say where is permissable.
gcc/testsuite/
* g++.dg/modules/mod-decl-1.C: Adjust.
* g++.dg/modules/p0713-2.C: Adjust.
* g++.dg/modules/p0713-3.C: Adjust.
H.J. Lu [Fri, 1 Jan 2021 13:30:34 +0000 (05:30 -0800)]
x86: Cast to unsigned short first for _mm_extract_pi16
_mm_extract_pi16 is intrinsic for pextrw, which should be zero-extended,
not sign-extended.
gcc/
PR target/98495
* config/i386/xmmintrin.h (_mm_extract_pi16): Cast to unsigned
short first.
gcc/testsuite/
PR target/98495
* gcc.target/i386/pr98495-1.c: New test.
* gcc.target/i386/pr98495-2.c: New test.
* gcc.target/i386/pr98495-3.c: New test.
* gcc.target/i386/pr98495-4.c: New test.
* gcc.target/i386/pr98495-5.c: New test.
gcc/ChangeLog
PR target/98461
* config/i386/sse.md (*sse2_pmovskb_zexthisi): New
define_insn_and_split for zero_extend of subreg HI of pmovskb
result.
(*sse2_pmovskb_zexthisi): Add new combine splitters for
zero_extend of not of subreg HI of pmovskb result.
gcc/testsuite/ChangeLog
* gcc.target/i386/sse2-pr98461-2.c: New test.
explow, aarch64: Fix force-Pmode-to-mem for ILP32 [PR97269]
This patch fixes a mode/rtx mismatch for ILP32 targets in:
mem = force_const_mem (ptr_mode, imm);
where imm can be Pmode rather than ptr_mode.
The patch uses convert_memory_address to convert the Pmode address
to ptr_mode before the call. However, immediate addresses can in
general contain unspecs, and convert_memory_address wasn't set up
to handle those.
The patch therefore adds some generic unspec handling to
convert_memory_address_addr_space_1. As the comment says, we can add
a target hook if this behaviour turns out to be wrong for some targets.
But I think what the patch does is a strict improvement over the status
quo: without it, we would try to force the unspec into a register,
but nevertheless wrap the result in a (const ...). That in turn
would be invalid rtl and seems bound to generate an ICE later.
I tested the explow.c part using -fstack-protector with local hacks
to force SYMBOL_FORCE_TO_MEM for UNSPEC_SALT_ADDR.
Fixes c-c++-common/torture/pr57945.c and various other tests.
gcc/
PR target/97269
* explow.c (convert_memory_address_addr_space_1): Handle UNSPECs
nested in CONSTs.
* config/aarch64/aarch64.c (aarch64_expand_mov_immediate): Use
convert_memory_address to convert symbolic immediates to ptr_mode
before forcing them to memory.
recog: Fix a constrain_operands corner case [PR97144]
aarch64's *add<mode>3_poly_1 has a pattern with the constraints:
"=...,r,&r"
"...,0,rk"
"...,Uai,Uat"
i.e. the penultimate alternative requires operands 0 and 1 to match,
but the final alternative does not allow them to match.
The register allocators dealt with this correctly, and so used
different input and output registers for instructions with Uat
operands. However, constrain_operands carried the penultimate
alternative's matching rule over to the final alternative,
so it would essentially ignore the earlyclobber. This in turn
allowed postreload to convert a correct Uat pairing into an
incorrect one.
The fix is simple: recompute the matching information for each
alternative.
gcc/
PR rtl-optimization/97144
* recog.c (constrain_operands): Initialize matching_operand
for each alternative, rather than only doing it once.
gcc/testsuite/
PR rtl-optimization/97144
* gcc.c-torture/compile/pr97144.c: New test.
* gcc.target/aarch64/sve/pr97144.c: Likewise.
In the PR, fwprop was changing a call instruction and tripped
an assert when trying to update a list of call clobbers.
There are two ways we could handle this: remove the call clobber
and then add it back, or assume that the clobber will stay in its
current place.
At the moment we don't have enough information to safely move
calls around, so the second approach seems simpler and more
efficient.
vect: Fix missing alias checks for 128-bit SVE [PR98371]
On AArch64, the vectoriser tries various ways of vectorising with both
SVE and Advanced SIMD and picks the best one. All other things being
equal, it prefers earlier attempts over later attempts.
The way this works currently is that, once it has a successful
vectorisation attempt A, it analyses all other attempts as epilogue
loops of A:
/* When pick_lowest_cost_p is true, we should in principle iterate
over all the loop_vec_infos that LOOP_VINFO could replace and
try to vectorize LOOP_VINFO under the same conditions.
E.g. when trying to replace an epilogue loop, we should vectorize
LOOP_VINFO as an epilogue loop with the same VF limit. When trying
to replace the main loop, we should vectorize LOOP_VINFO as a main
loop too.
However, autovectorize_vector_modes is usually sorted as follows:
- Modes that naturally produce lower VFs usually follow modes that
naturally produce higher VFs.
- When modes naturally produce the same VF, maskable modes
usually follow unmaskable ones, so that the maskable mode
can be used to vectorize the epilogue of the unmaskable mode.
This order is preferred because it leads to the maximum
epilogue vectorization opportunities. Targets should only use
a different order if they want to make wide modes available while
disparaging them relative to earlier, smaller modes. The assumption
in that case is that the wider modes are more expensive in some
way that isn't reflected directly in the costs.
There should therefore be few interesting cases in which
LOOP_VINFO fails when treated as an epilogue loop, succeeds when
treated as a standalone loop, and ends up being genuinely cheaper
than FIRST_LOOP_VINFO. */
However, the vectoriser can normally elide alias checks for epilogue
loops, on the basis that the main loop should do them instead.
Converting an epilogue loop to a main loop can therefore cause the alias
checks to be skipped. (It probably also unfairly penalises the original
loop in the cost comparison, given that one loop will have alias checks
and the other won't.)
As the comment says, we should in principle analyse each vector mode
twice: once as a main loop and once as an epilogue. However, doing
that up-front would be quite expensive. This patch instead goes for a
compromise: if an epilogue loop for mode M2 seems better than a main
loop for mode M1, re-analyse with M2 as the main loop.
The patch fixes dg.torture.exp=pr69719.c when testing with
-msve-vector-bits=128.
gcc/
PR tree-optimization/98371
* tree-vect-loop.c (vect_reanalyze_as_main_loop): New function.
(vect_analyze_loop): If an epilogue loop appears to be cheaper
than the main loop, re-analyze it as a main loop before adopting
it as a main loop.
Rainer Orth [Tue, 5 Jan 2021 10:32:31 +0000 (11:32 +0100)]
build: libcody: Link with -lsocket -lnsl if necessary [PR98316]
With the introduction of C++20 modules and libcody, cc1plus and
cc1objplus gained a dependency on the socket functions. Before those
were merged into libc in Solaris 11.4, one needed to link with -lsocket -lnsl
on Solaris, so that merge broke the Solaris 11.3 build.
While we already have 4 different checks for those libraries in the
tree, I decided to import autoconf-archive's AX_LIB_SOCKET_NSL macro
instead. At the same time, the patch only links libcody and the
networking libs where needed (cc1plus, cc1objplus).
Bootstrapped without regressions on i386-pc-solaris2.11 (Solaris 11.3
and 11.4), sparc-sun-solaris2.11, and x86_64-pc-linux-gnu.
Jakub Jelinek [Tue, 5 Jan 2021 09:57:52 +0000 (10:57 +0100)]
simplify-rtx: Optimize (x - 1) * y + y [PR98334]
We don't try to optimize for signed x, y (int) (x - 1U) * y + y
into x * y, we can't do that with signed x * y, because the former
is well defined for INT_MIN and -1, while the latter is not.
We could perhaps optimize it during isel or some very late optimization
where we'd turn magically flag_wrapv, but we don't do that yet.
This patch optimizes it in simplify-rtx.c, such that we can optimize
it during combine.
2021-01-05 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/98334
* simplify-rtx.c (simplify_context::simplify_binary_operation_1):
Optimize (X - 1) * Y + Y to X * Y or (X + 1) * Y - Y to X * Y.
David Malcolm [Tue, 5 Jan 2021 00:20:32 +0000 (19:20 -0500)]
analyzer: fix ICE with -fsanitize=undefined [PR98293]
-fsanitize=undefined with calls to nonnull functions
creates struct __ubsan_nonnull_arg_data instances
with CONSTRUCTORs for RECORD_TYPEs with NULL index values.
The analyzer was mistakenly using INTEGER_CST for these
fields, leading to ICEs.
Fix the issue by iterating through the fields in the type
for such cases, imitating similar logic in varasm.c's
output_constructor.
gcc/analyzer/ChangeLog:
PR analyzer/98293
* store.cc (binding_map::apply_ctor_to_region): When "index" is
NULL, iterate through the fields for RECORD_TYPEs, rather than
creating an INTEGER_CST index.
gcc/testsuite/ChangeLog:
PR analyzer/98293
* gcc.dg/analyzer/pr98293.c: New test.
vect, aarch64: Fix alignment units for IFN_MASK* [PR95401]
The IFN_MASK* functions take two leading arguments: a load or
store pointer and a “cookie”. The type of the cookie is the
type of the access for TBAA purposes (like for MEM_REFs)
while the value of the cookie is the alignment of the access.
This PR was caused by a disagreement about whether the alignment
is measured in bits or bytes.
It looks like this goes back to PR68786, which made the
vectoriser create its own cookie argument rather than reusing
the one created by ifcvt. The alignment value of the new cookie
was measured in bytes (as needed by set_ptr_info_alignment)
while the existing code expected it to be measured in bits.
The folds I added for IFN_MASK_LOAD and STORE then made
things worse.
gcc/
PR tree-optimization/95401
* config/aarch64/aarch64-sve-builtins.cc
(gimple_folder::load_store_cookie): Use bits rather than bytes
for the alignment argument to IFN_MASK_LOAD and IFN_MASK_STORE.
* gimple-fold.c (gimple_fold_mask_load_store_mem_ref): Likewise.
* tree-vect-stmts.c (vectorizable_store): Likewise.
(vectorizable_load): Likewise.
gcc/testsuite/
PR tree-optimization/95401
* g++.dg/vect/pr95401.cc: New test.
* g++.dg/vect/pr95401a.cc: Likewise.
Jakub Jelinek [Mon, 4 Jan 2021 13:36:06 +0000 (14:36 +0100)]
loop-niter: Recognize popcount idioms even with char, short and __int128 [PR95771]
As the testcase shows, we punt unnecessarily on popcount loop idioms if
the type is smaller than int or larger than long long.
Smaller type than int can be handled by zero-extending the argument to
unsigned int, and types twice as long as long long by doing
__builtin_popcountll on both halves of the __int128.
2020-01-04 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/95771
* tree-ssa-loop-niter.c (number_of_iterations_popcount): Handle types
with precision smaller than int's precision and types with precision
twice as large as long long. Formatting fixes.
docs: Fix wording describing the hwaddress sanitizer
The original documentation added to mention the clash between
-fsanitize=address and -fsanitize=hwaddress used confusing wording trying
to say that -fsanitize=hwaddress is only available on AArch64.
It read as if -fsanitize=address were only supported on AArch64.
This patch fixes that wording by being more explicit.
in the 64-bit vst[234] functions. The zero was forced into a
register at expand time, and we relied on combine to fuse the
zero and combine back together into a single combinez pattern.
The problem is that the zero could be hoisted before combine
gets a chance to do its thing.
gcc/
PR target/89057
* config/aarch64/aarch64-simd.md (aarch64_combine<mode>): Accept
aarch64_simd_reg_or_zero for operand 2. Use the combinez patterns
to handle zero operands.
gcc/testsuite/
PR target/89057
* gcc.target/aarch64/pr89057.c: New test.
The expansions of the svprf[bhwd] instructions weren't taking
advantage of the immediate addressing mode.
gcc/
* config/aarch64/aarch64.c (offset_6bit_signed_scaled_p): New function.
(offset_6bit_unsigned_scaled_p): Fix typo in comment.
(aarch64_sve_prefetch_operand_p): Accept MUL VLs in the range
[-32, 31].
gcc/testsuite/
* gcc.target/aarch64/sve/acle/asm/prfb.c: Test for a MUL VL range of
[-32, 31].
* gcc.target/aarch64/sve/acle/asm/prfh.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/prfw.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/prfd.c: Likewise.
Bernd Edlinger [Sun, 13 Dec 2020 07:24:57 +0000 (08:24 +0100)]
Fix -save-temp leaking lto files in /tmp
When linking with -flto and -save-temps, various
temporary files are created in /tmp.
The same happens when invoking the driver with @file
parameter, and using -L or -I options.
* collect-utils.c (collect_execute): Check dumppfx.
* collect2.c (maybe_run_lto_and_relink, do_link): Pass atsuffix
to collect_execute.
(do_link): Add new parameter atsuffix.
(main): Handle -dumpdir option. Skip one argument for
-o, -isystem and -B options.
* gcc.c (make_at_file): New helper function.
(close_at_file): Use it.
Iain Sandoe [Thu, 31 Dec 2020 14:51:56 +0000 (14:51 +0000)]
Darwin : Adjust defaults for the linker.
Ideally, the linker will be queried for its version and that will be
used to determine capabilities that cannot be discovered from
reasonable configuration testing.
When building cross tools, this might not be possible, and we have
strategies for providing useful defaults. These are adjusted here to
refect current choices.
gcc/ChangeLog:
* config/darwin.h (MIN_LD64_NO_COAL_SECTS): Adjust.
Amend handling for LD64_VERSION fallback defaults.
The darwinN.h headers (with the sole exception of darwin7.h,
which contains a target macro definition) now only contain
values that set fall-backs for cross-compilations, these can
be provided from the config.gcc script which means we no longer
need the darwinN.h - so delete them.
gcc/ChangeLog:
* config.gcc: Compute default version information
from the configured target. Likewise defaults for
ld64.
* config/darwin10.h: Removed.
* config/darwin12.h: Removed.
* config/darwin9.h: Removed.
* config/rs6000/darwin8.h: Removed.
Iain Sandoe [Thu, 31 Dec 2020 09:31:04 +0000 (09:31 +0000)]
Darwin, Simplify headers 3/5 : Delete dead code.
Darwin defines ASM_OUTPUT_ALIGNED_DECL_COMMON which is used in
preference to ASM_OUTPUT_ALIGNED_COMMON, which makes the latter
definition dead code. Remove this.
There is no need to make the LINK_GCC_C_SEQUENCE_SPEC conditional on
configuration parameters, it is adequately conditionalized on the
macosx-version-min.
gcc/ChangeLog:
* config/darwin10.h (LINK_GCC_C_SEQUENCE_SPEC): Move from
here...
* config/darwin.h (LINK_GCC_C_SEQUENCE_SPEC): ... to here.
Iain Sandoe [Wed, 30 Dec 2020 16:56:12 +0000 (16:56 +0000)]
Darwin, Simplify headers 0/5 : Move spec for Darwin 10 unwind stub [NFC].
The darwinN.h headers were (presumably) introduced to allow specs to be
adjusted when there was no mmacosx-version-min handling, or that was
considered unreliable.
We have version-specific specs for the values that have configuration
data, and the version is set in the driver (so may be considered
reliably present).
Some of the 'darwinN.h' content has become dead code, and the reminder
is either conditionalised on version information (or is setting values
used as fall-backs in cross-compilations).
With the changes needed for Darwin20 / macOS 11 the 'darwnN.h' headers
are now too unwieldy to be useful - so this series moves the relevant
specs definitons to the common 'darwin.h' header and then finally uses
the config.gcc script to supply the fall-back defaults for cross-
compilations.
We can then delete all but the main header, since the darwinN.h are
unused.
This change moves a spec from darwin10.h to the main darwin.h
target header.
gcc/ChangeLog:
* config/darwin10.h (LINK_GCC_C_SEQUENCE_SPEC): Move the spec
for the Darwin10 unwinder stub from here ...
* config/darwin.h (LINK_COMMAND_SPEC_A): ... to here.
Iain Sandoe [Wed, 30 Dec 2020 10:36:52 +0000 (10:36 +0000)]
Darwin : Adjust defaults for current bootstrap constraints.
The toolchain now requires a C++11 compiler to bootstrap and
none of the older Darwin toolchains which were based on stabs
debugging are suitable. We can simplify the debug setup now.
gcc/ChangeLog:
* config/darwin.h (DSYMUTIL_SPEC): Default to DWARF
(ASM_DEBUG_SPEC):Only define if the assembler supports
stabs.
(PREFERRED_DEBUGGING_TYPE): Default to DWARF.
(DARWIN_PREFER_DWARF): Define.
* config/darwin9.h (PREFERRED_DEBUGGING_TYPE): Remove.
(DARWIN_PREFER_DWARF): Likewise
(DSYMUTIL_SPEC): Likewise.
(COLLECT_RUN_DSYMUTIL): Likewise.
(ASM_DEBUG_SPEC): Likewise.
(ASM_DEBUG_OPTION_SPEC): Likewise.
Harald Anlauf [Fri, 1 Jan 2021 17:55:41 +0000 (18:55 +0100)]
PR fortran/96381 - invalid read in gfc_find_derived_vtab
An invalid declaration of a CLASS instance can lead to an internal state
with inconsistent attributes during parsing that needs to be handled with
sufficient care when processing subsequent statements. Avoid a lookup of
the vtab entry for such cases.
gcc/fortran/ChangeLog:
* class.c (gfc_find_vtab): Add check on attribute is_class.
Joel Brobecker [Fri, 1 Jan 2021 00:38:05 +0000 (21:38 -0300)]
compile gcc.target/arm/{pr78255-2.c,memset-inline-2.c} with -mno-long-calls
If the target is configured such that -mlong-call is passed
by default, the function calls these tests are trying to detect
by scanning the assembly file are performed using long calls,
like so:
This change adds -mno-long-calls to the list of compiler options
to make sure we generate short call code, allowing the assembly
matching to pass.
This is added unconditionally to the dg-options (as opposed to using
dg-additional-options) because this test is already specific to ARM
targets, and -mno-long-calls is available on all ARM targets.
for gcc/testsuite/ChangeLog
* gcc.target/arm/memset-inline-2.c: Add -mno-long-calls to
the test's dg-options.
* gcc.target/arm/pr78255-2.c: Likewise.
Joel Brobecker [Fri, 1 Jan 2021 04:54:58 +0000 (01:54 -0300)]
gcc.dg/intmax_t-1.c compiles without error on VxWorks 7 SR06x0
This test currently fails on VxWorks 7 SR06x0 targets when in kernel
mode, because it expects a discrepancy between built-in and system
intmax_t for all VxWorks targets when in kernel mode. Fortunately,
this has now been fixed when targetting VxWorks 7 SR06x0, so this
commit adjusts the "dg-error" condition to exclude newer versions of
VxWorks 7.
for gcc/testsuite/ChangeLog
* gcc.dg/intmax_t-1.c: Do not expect an error on *-*-vxworks7r*
targets.
Alexandre Oliva [Fri, 1 Jan 2021 00:38:24 +0000 (21:38 -0300)]
-mno-long-calls for arm/no_unique_address tests
The implicit -mlong-calls from our vxworks configurations makes the
tail-call instructions differ from those expected by the
no_unique_address tests in gcc.target/arm.
This patch adds -mno-long-calls to the compilation commands, so that
we generate the expected sequences.
Alexandre Oliva [Fri, 1 Jan 2021 00:38:23 +0000 (21:38 -0300)]
-mno-long-calls for arm/headmerge tests
The headmerge tests pass a constant to conditional calls, so that the
same constant is always passed to a function, though it's a different
function depending on which path is taken.
The test checks that the constant appears only once in the assembly
output, as a means to verify that the insns setting up the argument
are unified: they appear as separate insns up to jump2, where
crossjump identifies a common prefix to all conditional paths and
unifies them.
Alas, with -mlong-calls, that we enable in our arm-vxworks
configurations, the argument register is loaded after loading the
callee address into another register. Since each path calls a
different function, there's no common initial code sequence for
crossjump to unify, and the argument register set up remains separate,
so the test fails.
Though it would surely be desirable for the compiler to perform the
unification of the argument register setting up, this patch merely
avoids the effects of -mlong-calls, with an explicit -mno-long-calls.
Alexandre Oliva [Fri, 1 Jan 2021 00:38:22 +0000 (21:38 -0300)]
-mno-long-calls for expected regalloc in arm/fp16-aapcs-2.c test
The implicit -mlong-calls used in our arm-vxworks configurations
changes the register allocation patterns in the arm/fp16-aapcs-2.c
test: r3 ends up used in the long-call sequence, and we end up using
ip as a temporary, which doesn't match the expected mov patterns.
This patch adds an explicit -mno-long-calls for the generated code to
match the expectation.
for gcc/testsuite/ChangeLog
* gcc.target/arm/fp16-aapcs-2.c: Use -mno-long-calls.
unsigned long long x = ...;
char y = (char) (x << 37);
The overwidening pattern realised that only the low 8 bits
of x << 37 are needed, but then tried to turn that into:
unsigned long long x = ...;
char y = (char) x << 37;
which gives an out-of-range shift. In this case y can simply
be replaced by zero, but as the comment in the patch says,
it's kind-of awkward to do that in the middle of vectorisation.
Most of the overwidening stuff is about keeping operations
as narrow as possible, which is important for vectorisation
but could be counter-productive for scalars (especially on
RISC targets). In contrast, optimising y to zero in the above
feels like an independent optimisation that would benefit scalar
code and that should happen before vectorisation.
gcc/
PR tree-optimization/98302
* tree-vect-patterns.c (vect_determine_precisions_from_users): Make
sure that the precision remains greater than the shift count.
gcc/testsuite/
PR tree-optimization/98302
* gcc.dg/vect/pr98302.c: New test.
vect: Fix bogus alignment assumption in alias checks [PR94994]
This PR is about a case in which the vectoriser was feeding
incorrect alignment information to tree-data-ref.c, leading
to incorrect runtime alias checks. The alignment was taken
from the TREE_TYPE of the DR_REF, which in this case was a
COMPONENT_REF with a normally-aligned type. However, the
underlying MEM_REF was only byte-aligned.
This patch uses dr_alignment to calculate the (byte) alignment
instead, just like we do when creating vector MEM_REFs.
gcc/
PR tree-optimization/94994
* tree-vect-data-refs.c (vect_vfa_align): Use dr_alignment.
gcc/testsuite/
PR tree-optimization/94994
* gcc.dg/vect/pr94994.c: New test.
genmodes: Update GET_MODE_MASK when changing NUNITS [PR98214]
The static GET_MODE_MASKs for SVE vectors are based on the
static precisions, which in turn are based on 128-bit SVE.
The precisions are later updated based on -msve-vector-bits
(usually to become variable length), but the GET_MODE_MASK
stayed the same. This caused combine to fold:
(*_extract:DI (subreg:DI (reg:VNxMM R) 0) ...)
to zero because the extracted bits appeared to be insignificant.
gcc/
PR rtl-optimization/98214
* genmodes.c (emit_insn_modes_h): Emit a definition of CONST_MODE_MASK.
(emit_mode_mask): Treat mode_mask_array as non-constant if adj_nunits.
(emit_mode_adjustments): Update GET_MODE_MASK when updating
GET_MODE_NUNITS.
* machmode.h (mode_mask_array): Use CONST_MODE_MASK.
Jakub Jelinek [Thu, 31 Dec 2020 10:06:56 +0000 (11:06 +0100)]
wide-int: Fix wi::to_mpz [PR98474]
The following testcase is miscompiled, because niter analysis miscomputes
the number of iterations to 0.
The problem is that niter analysis uses mpz_t (wonder why, wouldn't
widest_int do the same job?) and when wi::to_mpz is called e.g. on the
TYPE_MAX_VALUE of __uint128_t, it initializes the mpz_t result with wrong
value.
wi::to_mpz has code to handle negative wide_ints in signed types by
inverting all bits, importing to mpz and complementing it, which is fine,
but doesn't handle correctly the case when the wide_int's len (times
HOST_BITS_PER_WIDE_INT) is smaller than precision when wi::neg_p.
E.g. the 0xffffffffffffffffffffffffffffffff TYPE_MAX_VALUE is represented
in wide_int as 0xffffffffffffffff len 1, and wi::to_mpz would create
0xffffffffffffffff mpz_t value from that.
This patch handles it by adding the needed -1 host wide int words (and has
also code to deal with precision that aren't multiple of
HOST_BITS_PER_WIDE_INT).
2020-12-31 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/98474
* wide-int.cc (wi::to_mpz): If wide_int has MSB set, but type
is unsigned and excess negative, append set bits after len until
precision.
Jakub Jelinek [Thu, 31 Dec 2020 09:20:39 +0000 (10:20 +0100)]
fold-const: Avoid (cast) ((cast2) x p+ y) folding for -fsanitize=alignment [PR98206]
The following testcase is diagnosed by UBSan as invalid, even when it is
valid.
We have a derived type Base2 at offset 1 with alignment 1 and do:
(const Derived &) ((const Base2 *) this + -1)
but the folder before ubsan in the FE gets a chance to instrument it
optimizes that into:
(const Derived &) this + -1
and so we require that this has 8-byte alignment which Derived class needs.
Fixed by avoiding such an optimization when -fsanitize=alignment is in
effect if it would affect the alignments (and guarded with !in_gimple_form
because we don't really care during GIMPLE, though pointer conversions are
useless then and so such folding isn't needed very much during GIMPLE).
2020-12-31 Jakub Jelinek <jakub@redhat.com>
PR c++/98206
* fold-const.c: Include asan.h.
(fold_unary_loc): Don't optimize (ptr_type) (((ptr_type2) x) p+ y)
into ((ptr_type) x) p+ y if sanitizing alignment in GENERIC and
ptr_type points to type with higher alignment than ptr_type2.
Jakub Jelinek [Thu, 31 Dec 2020 09:19:06 +0000 (10:19 +0100)]
reassoc: Optimize x > 0x1fff || y > 0x1fff into (x | y) > 0x1fff [PR56719]
The following patch adds an optimization mentioned in PR56719 #c8.
We already have the x != 0 && y != 0 && z != 0 into (x | y | z) != 0
and x != -1 && y != -1 && y != -1 into (x & y & z) != -1
optimizations, this patch just extends that to
x < C && y < C && z < C for power of two constants C into
(x | y | z) < C (for unsigned comparisons).
I didn't want to create too many buckets (there can be TYPE_PRECISION such
constants), so the patch instead just uses one buckets for all such
constants and loops over that bucket up to TYPE_PRECISION times.
2020-12-31 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/56719
* tree-ssa-reassoc.c (optimize_range_tests_cmp_bitwise): Also optimize
x < C && y < C && z < C when C is a power of two constant into
(x | y | z) < C.
Iain Buclaw [Thu, 31 Dec 2020 00:05:01 +0000 (01:05 +0100)]
d: Mangled Symbols now back reference types and identifiers
Symbols with extern(D) linkage are now mangled using back references to
types and identifiers if these occur more than once in the mangled name
as emitted before. This reduces symbol length, especially with chained
expressions of templated functions with Voldemort return types.
For example, the average symbol length of the 127000+ symbols created by
a libphobos unittest build is reduced by a factor of about 3, while the
longest symbol shrinks from 416133 to 1142 characters.
Iain Buclaw [Wed, 23 Dec 2020 17:04:47 +0000 (18:04 +0100)]
d: Give the result of evaluated expressions a location
CST trees that were converted back to a D front-end AST node lost all
location information of the original expression. Now this is propagated
on to the literal expression.
gcc/d/ChangeLog:
* d-tree.h (d_eval_constant_expression): Add location argument.
* d-builtins.cc (d_eval_constant_expression): Give generated constants
a proper file location.
* d-compiler.cc (Compiler::paintAsType): Pass expression location to
d_eval_constant_expression.
* d-frontend.cc (eval_builtin): Likewise.
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