The lfdpx, stdpx, lfdp and stfdp instructions work on a register pair. The
register pair test must only be applied to these instructions in the
dis_fp_pair() function.
Petar Jovanovic [Mon, 13 Feb 2017 16:15:24 +0000 (16:15 +0000)]
mips64: do correct 32-bit comparison for Iop_CmpNE32
Make sure that we take into account 32-bit size of values in comparison
on MIPS64-platforms. This is done either by sign extending these values
before comparison or sign extending xored values (depending on what
comparison we do). This should avoid false-positives like the one
reported in BZ #341481.
Patch based on code provided by Crestez Dan Leonard and Tamara Vlahovic.
Petar Jovanovic [Fri, 10 Feb 2017 17:58:40 +0000 (17:58 +0000)]
mips: rewrite mips_irgen_load_and_add32|64 and code around it
Make sure that mips_irgen_load_and_add32 gets both expected value and
new value, so the function code makes more sense and does load/store in
a atomic way.
Julian Seward [Mon, 16 Jan 2017 05:14:24 +0000 (05:14 +0000)]
dis_neon_data_3same: don't silently accept invalid instructions. Instead,
"return False" for any instruction not accepted by this function. Also,
add a few switch default backstops.
Carl Love [Mon, 7 Nov 2016 19:41:30 +0000 (19:41 +0000)]
Fix xxsel parsing error.
The xxsel instruction uses part of the standard opc2 field to specify
a additional operand or other values. A subset of the field is used for
the actual opcode. The masking and array lookup was getting confused by
bits in the the additional operand field. The arrays were split so only
the opcodes that should be found for a given mask is in the array. This
also speeds up the search as you are not searching through values that
cannot match. The small groups of opcodes for a couple of the masks are
now done in a case statement as that is probably faster then doing an array
look up.
Julian Seward [Wed, 19 Oct 2016 16:57:11 +0000 (16:57 +0000)]
Allow early writeback of SP base register in "strd rD, [sp, #-16]" so
as to avoid Memcheck complaining about writes below SP. Previously
this was allowed only for the #-8 case. n-i-bz.
Carl Love [Tue, 18 Oct 2016 15:52:09 +0000 (15:52 +0000)]
Fix PPC BE in 32-bit mode.
The 64-bit compares are not supported in 32-bit mode. Change the 64-bit
compares to 32-bit compares when doing byte compares. Add routine for
doing V128 GT compare using 32-bit compares.
The clean caller support was missing for 32-bit mode
Update the expected output file jm_vec_isa_2_07.stdout.exp
Carl Love [Fri, 7 Oct 2016 22:53:52 +0000 (22:53 +0000)]
ISA 3.0 BE fixes for various new instructions
This is an additional commit to fix issues found with the
new Power ISA 3.0 instructions for BE mode. The instructions
fixed in this patch include: lxvl, lxvx, lxvwsx, lxvh8x, lxvh16x,
stxvx, stxvh8x, stxvh16x, lxsibzx, lxsihzx, xscvqpdp, xscvqpdp0,
xvcvsphp.
Carl Love [Mon, 3 Oct 2016 15:30:46 +0000 (15:30 +0000)]
Fix rounding mode check and instruction stxvl
In BE mode, the function FPU_rounding_mode_isOdd() has the assert
vassert(mode->Iex.Const.con->Ico.U8 == 0x8);
The value was set using mkU32 but in BE mode the U8 maps to the upper
bits in the memory location not the lower bits. The comparison was
fixed by changing the .U8 to .U32 to be consistent with how the field
was set.
The stxvl instruction called the 64-bit NOT not the 128-bit NOT when
calculating the store_val.
The stxvx instruction the temp word values were initialized I32 not I64.
Not sure why this wasn't caught on LE.
Julian Seward [Fri, 19 Aug 2016 11:47:59 +0000 (11:47 +0000)]
Add a dummy initialisation and a dummy path to avoid warnings with gcc -Og.
Neither are actually necessary, but gcc's flow analysis at -Og is weaker than
at -O or above and so it produces false warnings here. No functional change.
Most of these instructions required adding a new Iop as they could not
be emulated with existing Iops. In some cases, some of the above instrctions
could be emulated using another instruction from the above list.
Most of the instructions add support for 128-bit instructions. There are a
number of helper functions that check a values for zero, infinity, NaN, etc.
for various sizes. The new 128-bit instructions require a new version of these
existing functions for a 128-bit operand. Rather then adding another size
specific version of these functions, the existing size specific functions were
replaced with a single function that takes the size of operand to be operated
on. There are some additional helper functions that are added to support
the size independent version of these functions.
Note this is the last of the 5 patches required to complete the ISA 3.0
support.
Julian Seward [Wed, 3 Aug 2016 11:53:11 +0000 (11:53 +0000)]
arm32 backend stuff needed to support IR artefacts resulting from
guest support of 32-bit V8 crypto instructions:
* add new pseudo-instruction ARMin_VXferQ, to move values between
two D regs and a Q reg, in either direction. Use this to implement
Iop_64HLtoV128 much more efficiently than before, and to implement
Iop_V128HIto64 and Iop_V128to64.
* Generate code for helper calls in which have four or more
(32-bit) word-sized arguments and a V128 return value.
These require passing arguments on the stack.
dis_neon_data_3same: for the case A==12, don't silently produce invalid IR
which then causes the sanity checker to abort the run. Instead synthesise
a SIGILL in the normal way.
If an instruction can't be decoded, print the first 10 bytes at RSP
rather than 8. 8 is not enough to disambiguate the instruction in
some situations, in particular where there is a control immediate byte
at the end of the instruction.
dis_pc_relative, case 0x002: remove a path that cannot be taken. That
stops gcc -Og complaining. It complains because at that relatively
low level of optimisation, its flow analysis is apparently too weak to
see that the removed path cannot be taken and so it complains
(wrongly) about a possibly uninitialised use of |result|. No
functional change.
Carl Love [Mon, 13 Jun 2016 17:27:03 +0000 (17:27 +0000)]
Fix mtfsfi usage of W bit. (isa2.05,ppc64)
Fix mtfsfi usage of W bit.
The Wbit field was added in ISA 2.05, allowing updates to the 'other'
half of the 64-bit FPSCR field.
Logic and Support for that bit is in place, but a 'reserved field
must contain zeros' check was not updated, preventing the desired
path from being taken.
Bugzilla 362894
Signed-off-by: Will Schmidt <will_schmidt@vnet.ibm.com>
Patch reviewed and verified by: Carl Love <cel@ibm.com>
Petar Jovanovic [Sat, 21 May 2016 00:05:34 +0000 (00:05 +0000)]
mips: allow building code with -mfpxx
Some recent GCC-based toolchains and Debian as a distribution enable the
flag -mpfxx by default. -mfpxx implies -mno-odd-spreg, so use of odd-
numbered single-precision floating-point registers has to be avoided in
Valgrind inline assembly in that case.
Carl Love [Tue, 26 Apr 2016 19:52:56 +0000 (19:52 +0000)]
Power PC Fix V bit error in 128-bit BCD add and subtract instructions
The original code was using the bcdadd / bcdsub instruction on the operand
shadow bits to calculate the shadow bits for the result. This introduced
non-zero bits shadow bits in the result. The shadow bits for these
instructions should be set to all valid or all invalid. If one of the
argument shadow bits was one, then all of the shadow bits of the result should
be one. Otherwise the result shadow bits should be zero.
This patch fixes the above bug in memcheck/mc_translate.c
Fixing the above bug broke the v-bit test. The issue is the v-bit tester
assumes the shadow bits for the operands of a given Iop can be set to one
for testing purposes. The implementation of the bcdadd and bcdsub was passing
a constant value for the variable ps. The ps value is an argument to the
instruction that specifies how to set the sign code of the result. The
implementation of the instructions was changed to issue the instruction with
ps=0. Then the result of the instruction is updated in the VEX code if ps=1.
This changed also results in cleaning up the vbit test code.
This patch also fixes the issues with the v-bit test program.
Carl Love [Tue, 29 Mar 2016 21:27:20 +0000 (21:27 +0000)]
Power PC Add support for ISA 3.0, part 1
The Floating-point condition code bits FPCC is bits[15:12] of the FPSCR.
The instructions fcmpu, fcmpo, dcmpu, dcmpq, dtstdc, dtstdcq, xscmpodq
and xscmpudq set the FPCC bits in addition to the BE field of the CC
register. This support is needed by the ISA 3.0 instructions to be added.
Carl Love [Tue, 16 Feb 2016 21:20:24 +0000 (21:20 +0000)]
128bit modulo and carry instruction fix
This patch fixes an issue with caculating the carry to the next 32-bit
chunk for the 128-bit add and subract instructions: vaddcuq, vadduqm,
vsubcuq, vsubuqm, vaddecuq, vaddeuqm, vsubecuq, vsubeuqm
Carl Love [Tue, 3 Nov 2015 17:44:55 +0000 (17:44 +0000)]
Add ISA 2.07 vbit test support
The ISA 2.07 support adds new Iops as well as support for some existing
Iops. None of these Iops have been enabled in the vbit tester. This commit
adds the needed support to the files VEX/priv/ir_inject and VEX/pub/libvex.h.
These changes add support for additional immediate operands.
There are additional changes to the memcheck files to complete the ISA 2.07
support.
Florian Krohm [Fri, 16 Oct 2015 17:26:22 +0000 (17:26 +0000)]
Give typeOfPrimop external linkage. This allows us to simplify
memcheck/tests/vbit-test which used to have local copies of certain
functions from ir_defs.c
Mark Wielaard [Thu, 1 Oct 2015 12:31:19 +0000 (12:31 +0000)]
Don't advertise RDRAND in cpuid for Core-i7-4910-like avx2 machine.
Bug#353370. In amd64g_dirtyhelper_CPUID_avx2 we set the RDRAND bit
but we don't implement support for RDRAND. Turn the bit off so programs
don't try to use RDRAND when running under valgrind.
Carl Love [Mon, 21 Sep 2015 21:46:46 +0000 (21:46 +0000)]
Fix, Add support for the Power PC Program Priority Register
Commit r3189 had a typo in it. In function LibVEX_GuestPPC64_initialise()
the value of vex_state->guest_PSPB is initialized to 0x0. The intention was
for it to be initialized to 0x100. This commit fixes the typo.
The original commit message:
Added the Program Priority Register (PPR), support to read and write it
via the mfspr and mtspr instructions as well as the special OR instruction
No Op instructions. The setting of the PPR is dependent on the value in
the Problem State Priority Boost register. Basic support for this register
was added. Not all of the PSPB register functionality was added.
Carl Love [Wed, 16 Sep 2015 22:26:59 +0000 (22:26 +0000)]
Add support for the Power PC Program Priority Register
Added the Program Priority Register (PPR), support to read and write it
via the mfspr and mtspr instructions as well as the special OR instruction
No Op instructions. The setting of the PPR is dependent on the value in
the Problem State Priority Boost register. Basic support for this register
was added. Not all of the PSPB register functionality was added.
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