Steve Ellcey [Fri, 5 May 2017 17:00:46 +0000 (17:00 +0000)]
invoke.texi (-fopt-info): Explicitly say order of options included in -fopt-info does not matter.
2017-05-05 Steve Ellcey <sellcey@cavium.com>
* doc/invoke.texi (-fopt-info): Explicitly say order of options
included in -fopt-info does not matter.
* doc/optinfo.texi (-fopt-info): Fix description of default
behavour. Explicitly say order of options included in -fopt-info
does not matter.
[ARM] Allow combination of aprofile and rmprofile multilibs
2017-05-05 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config.gcc: Allow combinations of aprofile and rmprofile values for
--with-multilib-list.
* config/arm/t-multilib: New file.
* config/arm/t-aprofile: Remove initialization of MULTILIB_*
variables. Remove setting of ISA and floating-point ABI in
MULTILIB_OPTIONS and MULTILIB_DIRNAMES. Set architecture and FPU in
MULTI_ARCH_OPTS_A and MULTI_ARCH_DIRS_A rather than MULTILIB_OPTIONS
and MULTILIB_DIRNAMES respectively. Add comment to introduce all
matches. Add architecture matches for marvel-pj4 and generic-armv7-a
CPU options.
* config/arm/t-rmprofile: Likewise except for the matches changes.
* doc/install.texi (--with-multilib-list): Document the combination of
aprofile and rmprofile values and warn about pitfalls in doing that.
Wilco Dijkstra [Fri, 5 May 2017 16:18:17 +0000 (16:18 +0000)]
Float to int moves currently generate inefficient code due to hacks used in the movsi and movdi patterns.
Float to int moves currently generate inefficient code due to
hacks used in the movsi and movdi patterns. The 'r = w' variant
uses '*' which tells the register allocator to ignore it.
As a result the float to int moves typically spill to the stack,
which is extremely inefficient.
gcc/
* config/aarch64/aarch64.md (movsi_aarch64): Remove '*' from r=w.
(movdi_aarch64): Likewise.
Jakub Jelinek [Fri, 5 May 2017 16:02:44 +0000 (18:02 +0200)]
re PR tree-optimization/80632 (error: invalid PHI argument with -O2)
PR tree-optimization/80632
* tree-switch-conversion.c (struct switch_conv_info): Add target_vop
field.
(build_arrays): Initialize it for virtual phis.
(fix_phi_nodes): Use it for virtual phis.
Jakub Jelinek [Fri, 5 May 2017 15:43:22 +0000 (17:43 +0200)]
re PR tree-optimization/80558 (VRP not handling x & -2 well)
PR tree-optimization/80558
* tree-vrp.c (extract_range_from_binary_expr_1): Optimize
[x, y] op z into [x op, y op z] for op & or | if conditions
are met.
Andre Vieira [Fri, 5 May 2017 15:41:28 +0000 (15:41 +0000)]
[ARM] PR71607: Fix ICE when loading constant
2017-05-05 Andre Vieira <andre.simoesdiasvieira@arm.com>
Prakhar Bahuguna <prakhar.bahuguna@arm.com>
gcc/
PR target/71607
* config/arm/arm.md (use_literal_pool): Remove.
(64-bit immediate split): No longer takes cost into consideration
if arm_disable_literal_pool is enabled.
* config/arm/arm.c (arm_tls_referenced_p): Add diagnostic if TLS is
used when arm_disable_literal_pool is enabled.
(arm_max_const_double_inline_cost): Remove use of
arm_disable_literal_pool.
(push_minipool_fix): Add assert.
(arm_reorg): Add return if arm_disable_literal_pool is enabled.
* config/arm/vfp.md (no_literal_pool_df_immediate): New.
(no_literal_pool_sf_immediate): New.
2017-05-05 Andre Vieira <andre.simoesdiasvieira@arm.com>
Thomas Preud'homme <thomas.preudhomme@arm.com>
Prakhar Bahuguna <prakhar.bahuguna@arm.com>
Wilco Dijkstra [Fri, 5 May 2017 09:40:01 +0000 (09:40 +0000)]
Code scheduling for Cortex-A53 isn't as good as it could be.
Code scheduling for Cortex-A53 isn't as good as it could be. It turns out
code runs faster overall if we place loads and stores with a dependency
closer together. To achieve this effect, this patch adds a bypass between
cortex_a53_load1 and cortex_a53_load*/cortex_a53_store* if the result of an
earlier load is used in an address calculation. This significantly improved
benchmark scores in a proprietary benchmark suite.
gcc/
* config/arm/aarch-common.c (arm_early_load_addr_dep_ptr):
New function.
(arm_early_store_addr_dep_ptr): Likewise.
* config/arm/aarch-common-protos.h
(arm_early_load_addr_dep_ptr): Add prototype.
(arm_early_store_addr_dep_ptr): Likewise.
* config/arm/cortex-a53.md: Add new bypasses.
Jakub Jelinek [Fri, 5 May 2017 07:35:13 +0000 (09:35 +0200)]
tree.c (next_type_uid): Change type to unsigned.
* tree.c (next_type_uid): Change type to unsigned.
(type_hash_canon): Decrement back next_type_uid if
freeing a type node with the highest TYPE_UID. For INTEGER_TYPEs
also ggc_free TYPE_MIN_VALUE, TYPE_MAX_VALUE and TYPE_CACHED_VALUES
if possible.
Wilco Dijkstra [Thu, 4 May 2017 17:52:03 +0000 (17:52 +0000)]
Many supported cores use the AUTOPREFETCHER_WEAK setting which tries to order...
Many supported cores use the AUTOPREFETCHER_WEAK setting which tries
to order loads and stores to improve streaming performance. Since significant
gains were reported in http://patchwork.ozlabs.org/patch/534469/ it seems
like a good idea to enable this setting too for -mcpu=generic. Since the
weak model only keeps the order if it doesn't make the schedule worse, it
should not impact performance adversely on cores that don't show a gain.
Wilco Dijkstra [Thu, 4 May 2017 17:49:19 +0000 (17:49 +0000)]
Set jump alignment to 4 for Cortex cores as it reduces codesize by 0.4% on...
Set jump alignment to 4 for Cortex cores as it reduces codesize by 0.4% on
average with no obvious performance difference. See original discussion of
the overheads of various alignments:
https://gcc.gnu.org/ml/gcc-patches/2016-06/msg02075.html.
gcc/
* config/aarch64/aarch64.c (cortexa35_tunings): Set jump alignment to 4.
(cortexa53_tunings): Likewise.
(cortexa57_tunings): Likewise.
(cortexa72_tunings): Likewise.
(cortexa73_tunings): Likewise.
Wilco Dijkstra [Thu, 4 May 2017 17:43:43 +0000 (17:43 +0000)]
With -mcpu=generic the loop alignment is currently 4.
With -mcpu=generic the loop alignment is currently 4. All but one of the
supported cores use 8 or higher. Since using 8 provides performance gains
on several cores, it is best to use that by default. As discussed in [1],
the jump alignment has no effect on performance, yet has a relatively high
codesize cost [2], so setting it to 4 is best. This gives a 0.2% overall
codesize improvement as well as performance gains in several benchmarks.
gcc/
* config/aarch64/aarch64.c (generic_tunings): Set jump alignment to 4.
Set loop alignment to 8.
Wilco Dijkstra [Thu, 4 May 2017 17:05:28 +0000 (17:05 +0000)]
All cores which add a cpu_addrcost_table use a non-zero value for HI and TI...
All cores which add a cpu_addrcost_table use a non-zero value for
HI and TI mode shifts (a non-zero value for general indexing also
applies to all shifts). Given this, it makes no sense to use a
different setting in generic_addrcost_table. So change it so that
all supported cores, including -mcpu=generic, now generate the same:
int f(short *p, short *q, long x) { return p[x] + q[x]; }
Martin Jambor [Thu, 4 May 2017 16:19:20 +0000 (18:19 +0200)]
[PR 80622] Treat const pools as initialized in SRA
2017-05-04 Martin Jambor <mjambor@suse.cz>
PR tree-optimization/80622
* tree-sra.c (comes_initialized_p): New function.
(build_accesses_from_assign): Only set write lazily when
comes_initialized_p is false.
(analyze_access_subtree): Use comes_initialized_p.
(propagate_subaccesses_across_link): Assert !comes_initialized_p
instead of testing for PARM_DECL.
Kyrylo Tkachov [Thu, 4 May 2017 16:14:37 +0000 (16:14 +0000)]
[AArch64] Accept more addressing modes for PRFM
* config/aarch64/aarch64.md (prefetch); Adjust predicate and
constraint on operand 0 to allow more general addressing modes.
Adjust output template.
* config/aarch64/aarch64.c (aarch64_address_valid_for_prefetch_p):
New function.
* config/aarch64/aarch64-protos.h
(aarch64_address_valid_for_prefetch_p): Declare prototype.
* config/aarch64/constraints.md (Dp): New address constraint.
* config/aarch64/predicates.md (aarch64_prefetch_operand): New
predicate.
* gcc.target/aarch64/prfm_imm_offset_1.c: New test.
Jan Hubicka [Thu, 4 May 2017 13:57:35 +0000 (15:57 +0200)]
ipa-cp.c (perform_estimation_of_a_value): Drop base_time parameter; update use of estimate_ipcp_clone_size_and_time.
* ipa-cp.c (perform_estimation_of_a_value): Drop base_time parameter;
update use of estimate_ipcp_clone_size_and_time.
(estimate_local_effects): Update use of
estimate_ipcp_clone_size_and_time and perform_estimation_of_a_value.
* ipa-inline.h (estimate_ipcp_clone_size_and_time): Update prototype.
* ipa-inline-analysis.c (estimate_ipcp_clone_size_and_time):
Return nonspecialized time.
Richard Biener [Thu, 4 May 2017 13:29:08 +0000 (13:29 +0000)]
tree-ssa-alias.c (get_continuation_for_phi): Improve looking for the last VUSE which def dominates the PHI.
2017-05-04 Richard Biener <rguenther@suse.de>
* tree-ssa-alias.c (get_continuation_for_phi): Improve looking
for the last VUSE which def dominates the PHI. Directly call
maybe_skip_until.
(get_continuation_for_phi_1): Remove.
For the reasons explained in PR77536, niter_for_unrolled_loop assumes 5
iterations in the absence of profiling information, although it doesn't
increase beyond the estimate for the original loop. This left a hole in
which the new estimate could be less than the old one but still greater
than the limit imposed by CEIL (nb_iterations_upper_bound, unroll factor).
2017-05-04 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* tree-ssa-loop-manip.c (niter_for_unrolled_loop): Add commentary
to explain the use of truncating division. Cap the number of
iterations to the maximum given by nb_iterations_upper_bound,
if defined.
gcc/testsuite/
* gcc.dg/vect/vect-profile-1.c: New test.
This patch adds support for purecode to ARMv8-M Baseline, in addition to
the existing support for ARMv7-M and ARMv8-M Mainline.
2017-05-04 Prakhar Bahuguna <prakhar.bahuguna@arm.com>
Andre Simoes Dias Vieira <andre.simoesdiasvieira@arm.com>
gcc/
* config/arm/arm.md (movsi): Change TARGET_32BIT to TARGET_HAVE_MOVT.
(movt splitter): Likewise.
* config/arm/arm.c (arm_option_check_internal): Change arm_arch_thumb2
to TARGET_HAVE_MOVT, and merge with -mslow-flash-data check.
(const_ok_for_arm): Change else to else if (TARGET_THUMB2) and add else
block for Thumb-1 with MOVT.
(thumb2_legitimate_address_p): Move code block ...
(can_avoid_literal_pool_for_label_p): ... into this new function.
(thumb1_legitimate_address_p): Add check for TARGET_HAVE_MOVT and
literal pool.
(thumb_legitimate_constant_p): Add conditional on TARGET_HAVE_MOVT
* doc/invoke.texi (-mpure-code): Change "ARMv7-M targets" for
"M-profile targets with the MOVT instruction".
gcc/testsuite/
* gcc.target/arm/pure-code/pure-code.exp: Add conditional for
check_effective_target_arm_thumb1_movt_ok.
Co-Authored-By: Andre Vieira <andre.simoesdiasvieira@arm.com>
From-SVN: r247585
The GCC documentation in section 6.60.8 ARM Floating Point Status and
Control Intrinsics states that the FPSCR register can be read and
written to using the intrinsics __builtin_arm_get_fpscr and
__builtin_arm_set_fpscr. However, these are misnamed within GCC itself
and these intrinsic names are not recognised.
This patch corrects the intrinsic names to match the documentation, and
adds tests to verify these intrinsics generate the correct
instructions.
gcc/
* gcc/config/arm/arm-builtins.c (arm_init_builtins): Rename
__builtin_arm_ldfscr to __builtin_arm_get_fpscr, and rename
__builtin_arm_stfscr to __builtin_arm_set_fpscr.
gcc/testsuite/
* gcc.target/arm/fpscr.c: New file.
Richard Biener [Thu, 4 May 2017 09:08:01 +0000 (09:08 +0000)]
tree.c (array_at_struct_end_p): Handle arrays at struct end with flexarrays more conservatively.
2017-05-04 Richard Biener <rguenther@suse.de>
* tree.c (array_at_struct_end_p): Handle arrays at struct
end with flexarrays more conservatively. Refactor and treat
arrays of arrays or aggregates more strict. Fix
VIEW_CONVERT_EXPR handling. Remove allow_compref argument.
* tree.c (array_at_struct_end_p): Adjust prototype.
* emit-rtl.c (set_mem_attributes_minus_bitpos): Adjust.
* gimple-fold.c (get_range_strlen): Likewise.
* tree-chkp.c (chkp_may_narrow_to_field): Likewise.
* brig-builtins.def: Added a builtin for class_f64.
* builtin-types.def: Added a builtin type needed by class_f64.
* brigfrontend/brig-code-entry-handler.cc
(brig_code_entry_handler::build_address_operand): Fix a bug
with reg+offset addressing on 32b segments. In large mode,
the offset is treated as 32bits unless it's global, readonly or
kernarg address space.
* rt/workitems.c: Removed a leftover comment.
* rt/arithmetic.c (__hsail_class_f32, __hsail_class_f64): Fix the
check for signaling/non-signalling NaN. Add class_f64 default
implementation.
Martin Jambor [Wed, 3 May 2017 16:48:20 +0000 (18:48 +0200)]
Use call_summary in ipa-prop and ipa-cp
2017-05-03 Martin Jambor <mjambor@suse.cz>
* ipa-prop.h (ipa_edge_args): Make a class. Mark with for_user GTY
tag. Added a default constructor and a destructor.
(ipa_edge_args_sum_t): New class;
(ipa_edge_args_sum): Declare.
(ipa_edge_args_vector): Remove declaration.
(IPA_EDGE_REF): Use ipa_edge_args_sum.
(ipa_free_edge_args_substructures): Remove declaration.
(ipa_check_create_edge_args): Use ipa_edge_args_sum.
(ipa_edge_args_info_available_for_edge_p): Likewise.
* ipa-prop.c (ipa_edge_args_vector): Removed.
(edge_removal_hook_holder): Likewise.
(edge_duplication_hook_holder): Likewise.
(ipa_edge_args_sum): New variable.
(ipa_propagate_indirect_call_infos): Test ipa_edge_args_sum instead of
ipa_edge_args_vector.
(ipa_free_edge_args_substructures): Likewise.
(ipa_free_all_edge_args): Free ipa_edge_args_sum instead of
ipa_edge_args_vector.
(ipa_edge_removal_hook): Turned into method
ipa_edge_args_sum_t::remove.
(ipa_edge_duplication_hook): Turned into method
ipa_edge_args_sum_t::duplicate.
(ipa_register_cgraph_hooks): Create ipa_edge_args_sum instead of
registering edge hooks.
(ipa_unregister_cgraph_hooks): Do not unregister edge hooks.
* ipa-inline-analysis.c (estimate_function_body_sizes): Test
ipa_edge_args_sum instead of ipa_edge_args_vector.
* ipa-profile.c (ipa_profile): Likewise.
Martin Jambor [Wed, 3 May 2017 16:41:39 +0000 (18:41 +0200)]
call_summary to keep info about cgraph_edges
2017-05-03 Martin Jambor <mjambor@suse.cz>
* symbol-summary.h (function_summary): New method exists.
(function_summary::symtab_removal): Deallocate through release.
(call_summary): New class.
(gt_ggc_mx): New overload.
(gt_pch_nx): Likewise.
(gt_pch_nx): Likewise.
Jeff Law [Wed, 3 May 2017 16:33:45 +0000 (10:33 -0600)]
re PR tree-optimization/78496 (Missed opportunities for jump threading)
PR tree-optimization/78496
* tree-vrp.c (simplify_cond_using_ranges_1): Renamed
from simplify_cond_using_ranges. Split off code to walk
backwards through casts into ...
(simplify_cond_using_ranges_2): New function.
(simplify_stmt_using_ranges): Call simplify_cond_using_ranges_1.
(execute_vrp): After identifying jump threads, call
simplify_cond_using_ranges_2.
PR tree-optimization/78496
* gcc.dg/tree-ssa/ssa-thread-15.c: New test.
David Malcolm [Wed, 3 May 2017 13:11:21 +0000 (13:11 +0000)]
New fix-it printer
The existing fix-it printer can lead to difficult-to-read output
when fix-it hints are near each other. For example, in a recent
patch to add fix-it hints to the C++ frontend's -Wold-style-cast,
e.g. for:
foo *f = (foo *)ptr->field;
^~~~~
the fix-it hints:
replace the open paren with "const_cast<"
replace the close paren with "> ("
insert ")" after the "ptr->field"
class rich_location consolidates adjacent fix-it hints, which helps
somewhat, but the underlying problem is that the existing printer
simply walks through the list of hints printing them, starting newlines
as necessary.
This patch reimplements fix-it printing by introducing a planning
stage: a new class line_corrections "plans" how to print the
fix-it hints affecting a line, generating a vec of "correction"
instances. Hints that are sufficiently close to each other are
consolidated at this stage.
This leads to the much more reasonable output for the above case:
where the 3 hints are consolidated into one "correction" at printing.
gcc/ChangeLog:
* diagnostic-show-locus.c (struct column_range): New struct.
(get_affected_columns): New function.
(get_printed_columns): New function.
(struct correction): New struct.
(correction::ensure_capacity): New function.
(correction::ensure_terminated): New function.
(struct line_corrections): New struct.
(line_corrections::~line_corrections): New dtor.
(line_corrections::add_hint): New function.
(layout::print_trailing_fixits): Reimplement in terms of the new
classes.
(selftest::test_overlapped_fixit_printing): New function.
(selftest::diagnostic_show_locus_c_tests): Call it.
Nathan Sidwell [Wed, 3 May 2017 12:15:05 +0000 (12:15 +0000)]
Canonicalize canonical type hashing
Canonicalize canonical type hashing
gcc/
* tree.h (type_hash_canon_hash): Declare.
* tree.c (type_hash_list, attribute_hash_list): Move into
type_hash_canon_hash.
(build_type_attribute_qual_variant): Break out hash code calc into
type_hash_canon_hash.
(type_hash_canon_hash): New. Generic type hash computation.
(build_range_type_1, build_array_type_1, build_function_type)
build_method_type_directly, build_offset_type, build_complex_type,
make_vector_type): Call it.
gcc/c-family/
* c-common.c (complete_array_type): Use type_hash_canon.
(--This line, and those below, will be ignored--
M gcc/tree.c
M gcc/tree.h
M gcc/c-family/ChangeLog
M gcc/c-family/c-common.c
M gcc/ChangeLog
Richard Biener [Wed, 3 May 2017 11:01:06 +0000 (11:01 +0000)]
tree-vect-data-refs.c (vect_enhance_data_refs_alignment): When all DRs have unknown misaligned do not always peel when...
2017-05-03 Richard Biener <rguenther@suse.de>
* tree-vect-data-refs.c (vect_enhance_data_refs_alignment):
When all DRs have unknown misaligned do not always peel
when there is a store but apply the same costing model as if
there were only loads.
* gcc.dg/vect/costmodel/x86_64/costmodel-alignpeel.c: New testcase.
[ARM] Set mode for success result of atomic compare and swap
2017-05-03 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* config/arm/iterators.md (CCSI): New mode iterator.
(arch): New mode attribute.
* config/arm/sync.md (atomic_compare_and_swap<mode>_1): Rename into ...
(atomic_compare_and_swap<CCSI:arch><NARROW:mode>_1): This and ...
(atomic_compare_and_swap<CCSI:arch><SIDI:mode>_1): This. Use CCSI
code iterator for success result mode.
* config/arm/arm.c (arm_expand_compare_and_swap): Adapt code to use
the corresponding new insn generators.
Jakub Jelinek [Wed, 3 May 2017 07:49:43 +0000 (09:49 +0200)]
re PR tree-optimization/79472 (x86-64: Switch table generation fails if default case has different code)
PR tree-optimization/79472
* tree-switch-conversion.c (struct switch_conv_info): Add
contiguous_range and default_case_nonstandard fields.
(collect_switch_conv_info): Compute contiguous_range and
default_case_nonstandard fields, don't clear final_bb if
contiguous_range and only the default case doesn't have the required
structure.
(check_all_empty_except_final): Set default_case_nonstandard instead
of failing if contiguous_range and the default case doesn't have empty
block.
(check_final_bb): Add SWTCH argument, don't fail if contiguous_range
and only the default case doesn't have the required constants. Skip
virtual phis.
(gather_default_values): Skip virtual phis. Allow non-NULL CASE_LOW
if default_case_nonstandard.
(build_constructors): Build constant 1 just once. Assert that default
values aren't inserted in between cases if contiguous_range. Skip
virtual phis.
(build_arrays): Skip virtual phis.
(prune_bbs): Add DEFAULT_BB argument, don't remove that bb.
(fix_phi_nodes): Don't add e2f phi arg if default_case_nonstandard.
Handle virtual phis.
(gen_inbound_check): Handle default_case_nonstandard case.
(process_switch): Adjust check_final_bb caller. Call
gather_default_values with the first non-default case instead of
default case if default_case_nonstandard.
* gcc.dg/tree-ssa/vrp40.c: Add -fno-tree-switch-conversion to dg-options.
* gcc.dg/tree-ssa/vrp113.c: New test.
* gcc.dg/tree-ssa/cswtch-3.c: New test.
* gcc.dg/tree-ssa/cswtch-4.c: New test.
* gcc.dg/tree-ssa/cswtch-5.c: New test.
David Malcolm [Tue, 2 May 2017 19:03:56 +0000 (19:03 +0000)]
Support fix-it hints that add new lines
Previously fix-it hints couldn't contain newlines. This is
due to the need to print something user-readable for them
within diagnostic-show-locus, and for handling them within
edit-context for printing diffs and regenerating content.
This patch enables limited support for fix-it hints with newlines,
for suggesting adding new lines.
Such a fix-it hint must have exactly one newline character, at the
end of the content. It must be an insertion at the beginning of
a line (so that e.g. fix-its that split a pre-existing line are
still rejected).
They are printed by diagnostic-show-locus with a '+' in the
left-hand margin, like this:
test.c:42:4: note: suggest adding 'break;' here
+ break;
case 'b':
^~~~~~~~~
and the printer injects "spans" if the insertion location is not
near the primary range of the diagnostic e.g.:
test.c:4:2: note: unrecognized 'putchar'; suggest including '<stdio.h>'
test.c:1:1:
+#include <stdio.h>
test.c:4:2:
putchar (ch);
^~~~~~~
gcc/ChangeLog:
* diagnostic-show-locus.c
(layout::should_print_annotation_line_p): Make private.
(layout::print_annotation_line): Make private.
(layout::annotation_line_showed_range_p): Make private.
(layout::show_ruler): Make private.
(layout::print_source_line): Make private. Pass in line and
line_width, rather than calling location_get_source_line. Drop
returned value.
(layout::print_leading_fixits): New method.
(layout::print_any_fixits): Rename to...
(layout::print_trailing_fixits): ...this, and make private.
Don't print newline fixits.
(diagnostic_show_locus): Move logic for printing one row into...
(layout::print_line): ...this new function. Move the
location_get_source_line call and error-handling from
print_source_line to here. Call print_leading_fixits, and rename
print_any_fixits to print_trailing_fixits.
(selftest::test_fixit_insert_containing_newline): Update now that
newlines are partially supported.
(selftest::test_fixit_insert_containing_newline_2): New test.
(selftest::test_fixit_replace_containing_newline): Update comments.
(selftest::diagnostic_show_locus_c_tests): Call the new test.
* edit-context.c (class added_line): New class.
(class edited_line): Describe newline handling in comment.
(edited_line::actually_edited_p): New method.
(edited_line::print_content): Delete redundant decl.
(edited_line::m_predecessors): New field.
(edited_file::print_content): Call edited_line::print_content.
(edited_file::print_diff): Update to support newlines.
(edited_file::print_diff_hunk): Likewise.
(edited_file::print_run_of_changed_lines): New function.
(edited_file::print_diff_line): Convert to...
(print_diff_line): ...this.
(edited_file::get_effective_line_count): New function.
(edited_line::edited_line): Initialize new field m_predecessors.
(edited_line::~edited_line): Clean up m_predecessors.
(edited_line::apply_fixit): Handle newlines.
(edited_line::get_effective_line_count): New function.
(edited_line::print_content): New function.
(edited_line::print_diff_lines): New function.
(selftest::test_applying_fixits_insert_containing_newline): New
test.
(selftest::test_applying_fixits_replace_containing_newline): New
test.
(selftest::insert_line): New function.
(selftest::test_applying_fixits_multiple_lines): Add example of
inserting a line.
(selftest::edit_context_c_tests): Call the new tests.
gcc/testsuite/ChangeLog:
* gcc.dg/plugin/diagnostic-test-show-locus-bw.c
(test_fixit_insert_newline): New function.
* gcc.dg/plugin/diagnostic-test-show-locus-color.c
(test_fixit_insert_newline): New function.
* gcc.dg/plugin/diagnostic-test-show-locus-generate-patch.c
(test_fixit_insert_newline): New function.
* gcc.dg/plugin/diagnostic-test-show-locus-parseable-fixits.c
(test_fixit_insert_newline): New function.
* gcc.dg/plugin/diagnostic_plugin_test_show_locus.c
(test_show_locus): Handle test_fixit_insert_newline.
libcpp/ChangeLog:
* include/line-map.h (class rich_location): Update description of
newline handling.
(class fixit_hint): Likewise.
(fixit_hint::ends_with_newline_p): New decl.
* line-map.c (rich_location::maybe_add_fixit): Support newlines
in fix-it hints that are insertions of single lines at the start
of a line. Don't consolidate into such fix-it hints.
(fixit_hint::ends_with_newline_p): New method.
* tree-ssa-loop-ivopts.c (get_computation_aff_1): New.
(get_computation_aff): Reorder parameters. Use get_computation_aff_1.
(get_computation_at, rewrite_use_address): Update use of
get_computation_aff.
Martin Jambor [Tue, 2 May 2017 12:49:55 +0000 (14:49 +0200)]
[PR 78687] Set SRA grp_write lazily
2017-05-02 Martin Jambor <mjambor@suse.cz>
PR tree-optimization/78687
* tree-sra.c (access): New field parent.
(process_subtree_disqualification): New function.
(disqualify_candidate): Call it.
(build_accesses_from_assign): Reset write flag if creating an
assighnment link.
(build_access_subtree): Fill in parent field and also prpagate
down grp_write flag.
(create_artificial_child_access): New parameter set_grp_write, set
grp_write to its value.
(propagate_subaccesses_across_link): Also propagate grp_write flag
values.
(propagate_all_subaccesses): Push the closest parent back to work
queue if add_access_to_work_queue returned true.
projects / thirdparty / gcc.git / log
