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8 months agolibstdc++: Do not define _Insert_base::try_emplace before C++17
Jonathan Wakely [Fri, 8 Nov 2024 13:58:23 +0000 (13:58 +0000)] 
libstdc++: Do not define _Insert_base::try_emplace before C++17

This is not a reserved name in C++11 and C++14, so must not be defined.

Also use the appropriate feature test macros for the try_emplace members
of the Debug Mode maps.

libstdc++-v3/ChangeLog:

* include/bits/hashtable_policy.h (_Insert_base::try_emplace):
Do not define for C++11 and C++14.
* include/debug/map.h (try_emplace): Use feature test macro.
* include/debug/unordered_map (try_emplace): Likewise.
* testsuite/17_intro/names.cc: Define try_emplace before C++17.

(cherry picked from commit b66a57c0ad300b293ebd366bc29f44f2ddb65c69)

8 months agoi386: Add new model number for Arrow Lake
Haochen Jiang [Mon, 11 Nov 2024 02:52:33 +0000 (10:52 +0800)] 
i386: Add new model number for Arrow Lake

gcc/ChangeLog:

* common/config/i386/cpuinfo.h (get_intel_cpu): Add new model
number for Arrow Lake.

8 months agoDaily bump.
GCC Administrator [Mon, 11 Nov 2024 00:21:46 +0000 (00:21 +0000)] 
Daily bump.

8 months agoDaily bump.
GCC Administrator [Sun, 10 Nov 2024 00:22:20 +0000 (00:22 +0000)] 
Daily bump.

8 months agoDaily bump.
GCC Administrator [Sat, 9 Nov 2024 16:07:50 +0000 (16:07 +0000)] 
Daily bump.

8 months agoarm: Fix ICE on arm_mve.h pragma without MVE types [PR117408]
Torbjörn SVENSSON [Fri, 1 Nov 2024 16:47:48 +0000 (17:47 +0100)] 
arm: Fix ICE on arm_mve.h pragma without MVE types [PR117408]

Starting with r14-435-g00d97bf3b5a, doing `#pragma arm "arm_mve.h"
false` or `#pragma arm "arm_mve.h" true` without first doing
`#pragma arm "arm_mve_types.h"` causes GCC to ICE.

gcc/ChangeLog:

PR target/117408
* config/arm/arm-mve-builtins.cc(handle_arm_mve_h): Detect if MVE
types is missing and if so, return error.

gcc/testsuite/ChangeLog:

PR target/117408
* gcc.target/arm/mve/pr117408-1.c: New test.
* gcc.target/arm/mve/pr117408-2.c: Likewise.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
(cherry picked from commit 8b04f60f88079c41b5cb1bf3b7c798703cceea18)

9 months agohppa: Don't use '%' operator in base14_operand
John David Anglin [Fri, 8 Nov 2024 21:54:48 +0000 (16:54 -0500)] 
hppa: Don't use '%' operator in base14_operand

Division is slow on hppa and mode sizes are powers of 2.  So, we
can use '&' operator to check displacement alignment.

2024-11-08  John David Anglin  <danglin@gcc.gnu.org>

gcc/ChangeLog:

* config/pa/predicates.md (base14_operand): Use '&' operator
instead of '%' to check displacement alignment.

9 months agohppa: Fix handling of secondary reloads involving a SUBREG
John David Anglin [Fri, 8 Nov 2024 21:34:41 +0000 (16:34 -0500)] 
hppa: Fix handling of secondary reloads involving a SUBREG

This is fairly subtle.

When handling spills for SUBREG arguments in pa_emit_move_sequence,
alter_subreg may be called.  It in turn calls adjust_address_1 and
change_address_1.  change_address_1 calls pa_legitimate_address_p
to validate the new spill address.  change_address_1 generates an
internal compiler error if the address is not valid.  We need to
allow 14-bit displacements for all modes when reload_in_progress
is true and strict is false to prevent the internal compiler error.

SUBREGs are only used with the general registers, so the spill
should result in an integer access.  14-bit displacements are okay
for integer loads and stores but not for floating-point loads and
stores.

Potentially, the change could break the handling of spills for the
floating point-registers but I believe these are handled separately
in pa_emit_move_sequence.

This change fixes the build of symmetrica-3.0.1+ds.

2024-11-08  John David Anglin  <danglin@gcc.gnu.org>

gcc/ChangeLog:

PR target/117443
* config/pa/pa.cc (pa_legitimate_address_p): Allow any
14-bit displacement when reload is in progress and strict
is false.

9 months agoAArch64: backport Neoverse and Cortex CPU definitions
Tamar Christina [Fri, 8 Nov 2024 18:12:32 +0000 (18:12 +0000)] 
AArch64: backport Neoverse and Cortex CPU definitions

This is a conservative backport of a few core definitions backporting only the
core definitions and mapping them to their closest cost model that exist on the
branches.

gcc/ChangeLog:

* config/aarch64/aarch64-cores.def (cortex-a725, cortex-x925,
neoverse-n3, neoverse-v3, neoverse-v3ae): New.
* config/aarch64/aarch64-tune.md: Regenerate
* doc/invoke.texi: Document them.

9 months agoaarch64: Fix gcc.target/aarch64/sme2/acle-asm/bfmlslb_f32.c
Richard Sandiford [Fri, 8 Nov 2024 14:07:47 +0000 (14:07 +0000)] 
aarch64: Fix gcc.target/aarch64/sme2/acle-asm/bfmlslb_f32.c

I missed a search-and-replace on this test, meaning that it was
duplicating bfmlalb_f32.c.

gcc/testsuite/
* gcc.target/aarch64/sme2/acle-asm/bfmlslb_f32.c: Replace bfmla*
with bfmls*

(cherry picked from commit 156f536d54b2f6f41de4719f9b3a8a33273a51a9)

9 months agoaarch64: Make PSEL dependent on SME rather than SME2
Richard Sandiford [Fri, 8 Nov 2024 14:07:47 +0000 (14:07 +0000)] 
aarch64: Make PSEL dependent on SME rather than SME2

The svpsel_lane intrinsics were wrongly classified as SME2+ only,
rather than as base SME intrinsics.  They should always be available
in streaming mode.

gcc/
* config/aarch64/aarch64-sve2.md (@aarch64_sve_psel<BHSD_BITS>)
(*aarch64_sve_psel<BHSD_BITS>_plus): Require TARGET_STREAMING
rather than TARGET_STREAMING_SME2.

gcc/testsuite/
* gcc.target/aarch64/sme2/acle-asm/psel_lane_b16.c: Move to...
* gcc.target/aarch64/sme/acle-asm/psel_lane_b16.c: ...here.
* gcc.target/aarch64/sme2/acle-asm/psel_lane_b32.c: Move to...
* gcc.target/aarch64/sme/acle-asm/psel_lane_b32.c: ...here.
* gcc.target/aarch64/sme2/acle-asm/psel_lane_b64.c: Move to...
* gcc.target/aarch64/sme/acle-asm/psel_lane_b64.c: ...here.
* gcc.target/aarch64/sme2/acle-asm/psel_lane_b8.c: Move to...
* gcc.target/aarch64/sme/acle-asm/psel_lane_b8.c: ...here.
* gcc.target/aarch64/sme2/acle-asm/psel_lane_c16.c: Move to...
* gcc.target/aarch64/sme/acle-asm/psel_lane_c16.c: ...here.
* gcc.target/aarch64/sme2/acle-asm/psel_lane_c32.c: Move to...
* gcc.target/aarch64/sme/acle-asm/psel_lane_c32.c: ...here.
* gcc.target/aarch64/sme2/acle-asm/psel_lane_c64.c: Move to...
* gcc.target/aarch64/sme/acle-asm/psel_lane_c64.c: ...here.
* gcc.target/aarch64/sme2/acle-asm/psel_lane_c8.c: Move to...
* gcc.target/aarch64/sme/acle-asm/psel_lane_c8.c: ...here.

(cherry picked from commit afd3887262edbdd5d7be5f34658432fd3046a168)

9 months agoaarch64: Restrict FCLAMP to SME2
Richard Sandiford [Fri, 8 Nov 2024 14:07:46 +0000 (14:07 +0000)] 
aarch64: Restrict FCLAMP to SME2

There are two sets of patterns for FCLAMP: one set for single registers
and one set for multiple registers.  The multiple-register set was
correctly gated on SME2, but the single-register set only required SME.
This doesn't matter for ACLE usage, since the intrinsic definitions
are correctly gated.  But it does matter for automatic generation of
FCLAMP from separate minimum and maximum operations (either ACLE
intrinsics or autovectorised code).

gcc/
* config/aarch64/aarch64-sve2.md (@aarch64_sve_fclamp<mode>)
(*aarch64_sve_fclamp<mode>_x): Require TARGET_STREAMING_SME2
rather than TARGET_STREAMING_SME.

gcc/testsuite/
* gcc.target/aarch64/sme/clamp_3.c: Force sme2
* gcc.target/aarch64/sme/clamp_4.c: Likewise.
* gcc.target/aarch64/sme/clamp_5.c: New test.

(cherry picked from commit f5962839d6e0c3115931e68d938d9a0cd7a383b1)

9 months agoaarch64: Fix folding of degenerate svwhilele case [PR117045]
Richard Sandiford [Fri, 8 Nov 2024 14:07:46 +0000 (14:07 +0000)] 
aarch64: Fix folding of degenerate svwhilele case [PR117045]

The svwhilele folder mishandled the degenerate case in which
the second argument is the maximum integer.  In that case,
the result is all-true regardless of the first parameter:

  If the second scalar operand is equal to the maximum signed integer
  value then a condition which includes an equality test can never fail
  and the result will be an all-true predicate.

This is because the conceptual "increment the first operand
by 1 after each element" is done modulo the range of the operand.
The GCC code was instead treating it as infinite precision.
whilele_5.c even had a test for the incorrect behaviour.

The easiest fix seemed to be to handle that case specially before
doing constant folding.  This also copes with variable first operands.

gcc/
PR target/116999
PR target/117045
* config/aarch64/aarch64-sve-builtins-base.cc
(svwhilelx_impl::fold): Check for WHILELTs of the minimum value
and WHILELEs of the maximum value.  Fold them to all-false and
all-true respectively.

gcc/testsuite/
PR target/116999
PR target/117045
* gcc.target/aarch64/sve/acle/general/whilele_5.c: Fix bogus
expected result.
* gcc.target/aarch64/sve/acle/general/whilele_11.c: New test.
* gcc.target/aarch64/sve/acle/general/whilele_12.c: Likewise.

(cherry picked from commit 50e7c51b0a0e9dc1d93f829016ae743b4f2e5070)

9 months agoaarch64: Fix SVE ACLE gimple folds for C++ LTO [PR116629]
Richard Sandiford [Fri, 8 Nov 2024 14:07:45 +0000 (14:07 +0000)] 
aarch64: Fix SVE ACLE gimple folds for C++ LTO [PR116629]

The SVE ACLE code has two ways of handling overloaded functions.
One, used by C, is to define a single dummy function for each unique
overloaded name, with resolve_overloaded_builtin then resolving calls
to real non-overloaded functions.  The other, used by C++, is to
define a separate function for each individual overload.

The builtins harness assigns integer function codes programmatically.
However, LTO requires it to use the same assignment for every
translation unit, regardless of language.  This means that C++ TUs
need to create (unused) slots for the C overloads and that C TUs
need to create (unused) slots for the C++ overloads.

In many ways, it doesn't matter whether the LTO frontend itself
uses the C approach or the C++ approach to defining overloaded
functions, since the LTO frontend never has to resolve source-level
overloading.  However, the C++ approach of defining a separate
function for each overload means that C++ calls never need to
be redirected to a different function.  Calls to an overload
can appear in the LTO dump and survive until expand.  In contrast,
calls to C's dummy overload functions are resolved by the front
end and never survive to LTO (or expand).

Some optimisations work by moving between sibling functions, such as _m
to _x.  If the source function is an overload, the expected destination
function is too.  The LTO frontend needs to define C++ overloads if it
wants to do this optimisation properly for C++.

The PR is about a tree checking failure caused by trying to use a
stubbed-out C++ overload in LTO.  Dealing with that by detecting the
stub (rather than changing which overloads are defined) would have
turned this from an ice-on-valid to a missed optimisation.

In future, it would probably make sense to redirect overloads to
non-overloaded functions during gimple folding, in case that exposes
more CSE opportunities.  But it'd probably be of limited benefit, since
it should be rare for code to mix overloaded and non-overloaded uses of
the same operation.  It also wouldn't be suitable for backports.

gcc/
PR target/116629
* config/aarch64/aarch64-sve-builtins.cc
(function_builder::function_builder): Use direct overloads for LTO.

gcc/testsuite/
PR target/116629
* gcc.target/aarch64/sve/acle/general/pr106326_2.c: New test.

(cherry picked from commit fee3adbac055c3ff2649fed866c66d44ebfcbe90)

9 months agoaarch64: Rename svpext to svpext_lane [PR116371]
Richard Sandiford [Fri, 8 Nov 2024 14:07:45 +0000 (14:07 +0000)] 
aarch64: Rename svpext to svpext_lane [PR116371]

When implementing the SME2 ACLE, I somehow missed off the _lane
suffix on svpext.

gcc/
PR target/116371
* config/aarch64/aarch64-sve-builtins-sve2.h (svpext): Rename to...
(svpext_lane): ...this.
* config/aarch64/aarch64-sve-builtins-sve2.cc (svpext_impl): Rename
to...
(svpext_lane_impl): ...this and update instantiation accordingly.
* config/aarch64/aarch64-sve-builtins-sve2.def (svpext): Rename to...
(svpext_lane): ...this.

gcc/testsuite/
PR target/116371
* gcc.target/aarch64/sme2/acle-asm/pext_c16.c,
gcc.target/aarch64/sme2/acle-asm/pext_c16_x2.c,
gcc.target/aarch64/sme2/acle-asm/pext_c32.c,
gcc.target/aarch64/sme2/acle-asm/pext_c32_x2.c,
gcc.target/aarch64/sme2/acle-asm/pext_c64.c,
gcc.target/aarch64/sme2/acle-asm/pext_c64_x2.c,
gcc.target/aarch64/sme2/acle-asm/pext_c8.c,
gcc.target/aarch64/sme2/acle-asm/pext_c8_x2.c: Replace with...
* gcc.target/aarch64/sme2/acle-asm/pext_lane_c16.c,
gcc.target/aarch64/sme2/acle-asm/pext_lane_c16_x2.c,
gcc.target/aarch64/sme2/acle-asm/pext_lane_c32.c,
gcc.target/aarch64/sme2/acle-asm/pext_lane_c32_x2.c,
gcc.target/aarch64/sme2/acle-asm/pext_lane_c64.c,
gcc.target/aarch64/sme2/acle-asm/pext_lane_c64_x2.c,
gcc.target/aarch64/sme2/acle-asm/pext_lane_c8.c,
gcc.target/aarch64/sme2/acle-asm/pext_lane_c8_x2.c: ...these new tests,
testing for svpext_lane instead of svpext.

(cherry picked from commit cc2d29e5f4434a3fd4e0dd93ea4f9857a0309201)

9 months agotestsuite: arm: Use check-function-bodies in epilog-1.c test
Torbjörn SVENSSON [Thu, 7 Nov 2024 19:09:48 +0000 (20:09 +0100)] 
testsuite: arm: Use check-function-bodies in epilog-1.c test

Update test case for armv8.1-m.main that supports conditional
arithmetic.

armv7-m:
        push    {r4, lr}
        ldr     r4, .L6
        ldr     r4, [r4]
        lsls    r4, r4, #29
        it      mi
        addmi   r2, r2, #1
        bl      bar
        movs    r0, #0
        pop     {r4, pc}

armv8.1-m.main:
        push    {r3, r4, r5, lr}
        ldr     r4, .L5
        ldr     r5, [r4]
        tst     r5, #4
        csinc   r2, r2, r2, eq
        bl      bar
        movs    r0, #0
        pop     {r3, r4, r5, pc}

gcc/testsuite/ChangeLog:

* gcc.target/arm/epilog-1.c: Use check-function-bodies.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
(cherry picked from commit ec86e87439b4a5cf73da6f318757f3561f9f278a)

9 months agotestsuite: arm: Use effective-target arm_libc_fp_abi for pr68620.c test
Torbjörn SVENSSON [Wed, 6 Nov 2024 06:12:14 +0000 (07:12 +0100)] 
testsuite: arm: Use effective-target arm_libc_fp_abi for pr68620.c test

This fixes reported regression at
https://linaro.atlassian.net/browse/GNU-1407.

gcc/testsuite/ChangeLog:

* gcc.target/arm/pr68620.c: Use effective-target
arm_libc_fp_abi.
* lib/target-supports.exp: Define effective-target
arm_libc_fp_abi.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
Co-authored-by: Richard Earnshaw <rearnsha@arm.com>
(cherry picked from commit dc5d559494656c17c4faa99f398047b7d0c33adc)

9 months agotestsuite: arm: Allow vst1.32 instruction in pr40457-2.c
Torbjörn SVENSSON [Thu, 7 Nov 2024 17:05:19 +0000 (18:05 +0100)] 
testsuite: arm: Allow vst1.32 instruction in pr40457-2.c

When building the test case with neon, the 'vst1.32' instruction is used
instead of 'strd'. Allow both variants to make the test pass.

gcc/testsuite/ChangeLog:

* gcc.target/arm/pr40457-2.c: Add vst1.32 as an allowed
instruction.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
(cherry picked from commit 636b8aeacd182351313381636ecbf8dcef1ee45a)

9 months agotestsuite: arm: Use effective-target for pr84556.cc test
Torbjörn SVENSSON [Wed, 6 Nov 2024 09:28:34 +0000 (10:28 +0100)] 
testsuite: arm: Use effective-target for pr84556.cc test

Using "dg-do run" with a selector overrides the default selector set by
vect.exp that picks between "dg-do run" and "dg-do compile" based on the
target's support for simd operations for Arm targets.
The actual selection of default operation is performed in
check_vect_support_and_set_flags.

gcc/testsuite/ChangeLog:

* g++.dg/vect/pr84556.cc: Change from "dg-do run" with selector
to instead use dg-require-effective-target with the same
selector.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
(cherry picked from commit 85c3d944800257248ab48cdc75c2c02fadf63c73)

9 months agotestsuite: arm: Use effective-target for nomve_fp_1 test
Torbjörn SVENSSON [Thu, 31 Oct 2024 18:11:57 +0000 (19:11 +0100)] 
testsuite: arm: Use effective-target for nomve_fp_1 test

Test uses MVE, so add effective-target arm_fp requirement.

gcc/testsuite/ChangeLog:

* g++.target/arm/mve/general-c++/nomve_fp_1.c: Use
effective-target arm_fp.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
(cherry picked from commit e8886406fac50f80a521a4100a80517e50e1c388)

9 months agoaarch64: Add support for FUJITSU-MONAKA (-mcpu=fujitsu-monaka) CPU
Yuta Mukai [Thu, 7 Nov 2024 22:09:39 +0000 (22:09 +0000)] 
aarch64: Add support for FUJITSU-MONAKA (-mcpu=fujitsu-monaka) CPU

This patch adds initial support for FUJITSU-MONAKA CPU.
The cost model will be corrected in the future.

2024-11-07  Yuta Mukai  <mukai.yuta@fujitsu.com>

gcc/ChangeLog:

* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add fujitsu-monaka.
* config/aarch64/aarch64-tune.md: Regenerate.
* config/aarch64/aarch64.cc: Include fujitsu-monaka tuning model.
* doc/invoke.texi: Document -mcpu=fujitsu-monaka.
* config/aarch64/tuning_models/fujitsu_monaka.h: New file.

9 months agoi386: Modify regexp of pr117304-1.c
Hu, Lin1 [Thu, 7 Nov 2024 02:13:15 +0000 (10:13 +0800)] 
i386: Modify regexp of pr117304-1.c

Since the test doesn't care if the hint is correct,
modify the regexp of the hint part to avoid future
changes to the hint that would cause the test to fail.

gcc/testsuite/ChangeLog:

* gcc.target/i386/pr117304-1.c: Modify regexp.

(cherry picked from commit 4473cf8409f4db19ad91bd784e32dc54eccf02a3)

9 months agoi386: Add OPTION_MASK_ISA2_EVEX512 for some AVX512 instructions.
Hu, Lin1 [Tue, 5 Nov 2024 07:49:57 +0000 (15:49 +0800)] 
i386: Add OPTION_MASK_ISA2_EVEX512 for some AVX512 instructions.

gcc/ChangeLog:

PR target/117304
* config/i386/i386-builtin.def: Add OPTION_MASK_ISA2_EVEX512 for some
AVX512 512-bits instructions.

gcc/testsuite/ChangeLog:

PR target/117304
* gcc.target/i386/pr117304-1.c: New test.

(cherry picked from commit 8ac694ae67e24a798dce368587bed4c40b90fbc0)

9 months agoDaily bump.
GCC Administrator [Thu, 7 Nov 2024 00:24:55 +0000 (00:24 +0000)] 
Daily bump.

9 months agoAArch64: rename the SVE2 psel intrinsics to psel_lane [PR116371]
Tamar Christina [Mon, 14 Oct 2024 12:58:09 +0000 (13:58 +0100)] 
AArch64: rename the SVE2 psel intrinsics to psel_lane [PR116371]

The psel intrinsics. similar to the pext, should be name psel_lane.  This
corrects the naming.

gcc/ChangeLog:

PR target/116371
* config/aarch64/aarch64-sve-builtins-sve2.cc (class svpsel_impl):
Renamed to ...
(class svpsel_lane_impl): ... This and adjust initialization.
* config/aarch64/aarch64-sve-builtins-sve2.def (svpsel): Renamed to ...
(svpsel_lane): ... This.
* config/aarch64/aarch64-sve-builtins-sve2.h (svpsel): Renamed to
svpsel_lane.

gcc/testsuite/ChangeLog:

PR target/116371
* gcc.target/aarch64/sme2/acle-asm/psel_b16.c,
gcc.target/aarch64/sme2/acle-asm/psel_b32.c,
gcc.target/aarch64/sme2/acle-asm/psel_b64.c,
gcc.target/aarch64/sme2/acle-asm/psel_b8.c,
gcc.target/aarch64/sme2/acle-asm/psel_c16.c,
gcc.target/aarch64/sme2/acle-asm/psel_c32.c,
gcc.target/aarch64/sme2/acle-asm/psel_c64.c,
gcc.target/aarch64/sme2/acle-asm/psel_c8.c: Renamed to....
* gcc.target/aarch64/sme2/acle-asm/psel_lane_b16.c,
gcc.target/aarch64/sme2/acle-asm/psel_lane_b32.c,
gcc.target/aarch64/sme2/acle-asm/psel_lane_b64.c,
gcc.target/aarch64/sme2/acle-asm/psel_lane_b8.c,
gcc.target/aarch64/sme2/acle-asm/psel_lane_c16.c,
gcc.target/aarch64/sme2/acle-asm/psel_lane_c32.c,
gcc.target/aarch64/sme2/acle-asm/psel_lane_c64.c,
gcc.target/aarch64/sme2/acle-asm/psel_lane_c8.c: ... These.

(cherry picked from commit 306834b7f74ab61160f205e04f5bf35b71f9ec52)

9 months agoc++: Defer -fstrong-eval-order processing to template instantiation time [PR117158]
Simon Martin [Wed, 6 Nov 2024 05:54:57 +0000 (06:54 +0100)] 
c++: Defer -fstrong-eval-order processing to template instantiation time [PR117158]

Since r10-3793-g1a37b6d9a7e57c, we ICE upon the following valid code
with -std=c++17 and above

=== cut here ===
struct Base {
  unsigned int *intarray;
};
template <typename T> struct Sub : public Base {
  bool Get(int i) {
    return (Base::intarray[++i] == 0);
  }
};
=== cut here ===

The problem is that from c++17 on, we use -fstrong-eval-order and need
to wrap the array access expression into a SAVE_EXPR. We do so at
template declaration time, and end up calling contains_placeholder_p
with a SCOPE_REF, that it does not handle well.

This patch fixes this by deferring the wrapping into SAVE_EXPR to
instantiation time for templates, when the SCOPE_REF will have been
turned into a COMPONENT_REF.

PR c++/117158

gcc/cp/ChangeLog:

* typeck.cc (cp_build_array_ref): Only wrap array expression
into a SAVE_EXPR at template instantiation time.

gcc/testsuite/ChangeLog:

* g++.dg/cpp1z/eval-order13.C: New test.
* g++.dg/parse/crash77.C: New test.

(cherry picked from commit b1d92aeb8583c8d1491c97703680c5fb88ed1fe4)

9 months agoDaily bump.
GCC Administrator [Wed, 6 Nov 2024 00:24:00 +0000 (00:24 +0000)] 
Daily bump.

9 months agoc++: reference variable as default targ [PR101463]
Patrick Palka [Tue, 5 Nov 2024 20:18:26 +0000 (15:18 -0500)] 
c++: reference variable as default targ [PR101463]

Here during default template argument substitution we wrongly consider
the (substituted) default arguments v and vt<int> as value-dependent
which ultimately leads to deduction failure for the calls.

The bogus value_dependent_expression_p result aside, I noticed
type_unification_real during default targ substitution keeps track of
whether all previous targs are known and non-dependent, as is the case
for these calls.  And in such cases it should be safe to avoid checking
dependence of the substituted default targ and just assume it's not.
This patch implements this optimization for GCC 14, which lets us accept
both testcases by sidestepping the value_dependent_expression_p issue
altogether.  (Note that for GCC 15 we fixed this differently, see
r15-3038-g5348e3cb9bc99d.)

PR c++/101463

gcc/cp/ChangeLog:

* pt.cc (type_unification_real): Avoid checking dependence of
a substituted default template argument if we can assume it's
non-dependent.

gcc/testsuite/ChangeLog:

* g++.dg/cpp1z/nontype6.C: New test.
* g++.dg/cpp1z/nontype6a.C: New test.

Reviewed-by: Jason Merrill <jason@redhat.com>
9 months agotestsuite: arm: Use effective-target for pr68620 and pr78041 tests
Torbjörn SVENSSON [Thu, 31 Oct 2024 18:00:36 +0000 (19:00 +0100)] 
testsuite: arm: Use effective-target for pr68620 and pr78041 tests

gcc/testsuite/ChangeLog:

* gcc.target/arm/pr68620.c: Use effective-target arm_neon.
* gcc.target/arm/pr78041.c: Use effective-target arm_arch_v7a.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
(cherry picked from commit c7518891483e2aa558390ffeab4a19ba747814d6)

9 months agotestsuite: arm: Use effective-target for pr98636.c test
Torbjörn SVENSSON [Fri, 1 Nov 2024 10:11:26 +0000 (11:11 +0100)] 
testsuite: arm: Use effective-target for pr98636.c test

The test case assumes that -mfp16-format=alternative is accepted for the
target, but not all targets support this flag. One such target is
Cortex-M85 that does support FP16, but not the alternative format.

gcc/testsuite/ChangeLog:

* gcc.target/arm/pr98636.c: Use effective-target
arm_fp16_alternative.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
(cherry picked from commit 4602f628f723688a10c14ab20bd013ba7a825dab)

9 months agoc++: allow array mem-init with -fpermissive [PR116634]
Jason Merrill [Mon, 4 Nov 2024 22:48:46 +0000 (17:48 -0500)] 
c++: allow array mem-init with -fpermissive [PR116634]

We've accidentally accepted this forever (at least as far back as 4.7), but
it's always been ill-formed; this was PR59465.  And we didn't accept it for
scalar types.  But rather than switch to a hard error for this code, let's
give a permerror so affected code can continue to work with -fpermissive.

PR c++/116634

gcc/cp/ChangeLog:

* init.cc (can_init_array_with_p): Allow PR59465 case with
permerror.

gcc/testsuite/ChangeLog:

* g++.dg/diagnostic/aggr-init1.C: Expect warning with -fpermissive.
* g++.dg/init/array62.C: Adjust diagnostic.
* g++.dg/init/array63.C: Adjust diagnostic.
* g++.dg/init/array64.C: Adjust diagnostic.

(cherry picked from commit 3545aab00152ed3db1d7ce6ca4e1671dde276980)

9 months agoFortran: Fix regressions with intent(out) class[PR115070, PR115348].
Paul Thomas [Tue, 5 Nov 2024 15:54:45 +0000 (15:54 +0000)] 
Fortran: Fix regressions with intent(out) class[PR115070, PR115348].

2024-11-05  Paul Thomas  <pault@gcc.gnu.org>

gcc/fortran
PR fortran/115070
PR fortran/115348
* trans-expr.cc (gfc_trans_class_init_assign): If all the
components of the default initializer are null for a scalar,
build an empty statement to prevent prior declarations from
disappearing.

gcc/testsuite/
PR fortran/115070
* gfortran.dg/ieee/pr115070.f90: New test.

PR fortran/115348
* gfortran.dg/pr115348.f90: New test.

9 months agoDaily bump.
GCC Administrator [Tue, 5 Nov 2024 00:24:42 +0000 (00:24 +0000)] 
Daily bump.

9 months agoDon't call invert on VARYING.
Andrew MacLeod [Sat, 2 Nov 2024 14:26:24 +0000 (10:26 -0400)] 
Don't call invert on VARYING.

When all cases go to one label and resul in a VARYING value, we can't
invert that value to remove all values from the default case. Simply
check for this case and set the default to UNDEFINED.

PR tree-optimization/117398
gcc/
* gimple-range-edge.cc (gimple_outgoing_range::calc_switch_ranges):
Check for VARYING and don't call invert () on it.

gcc/testsuite/
* gcc.dg/pr117398.c: New.

9 months agotestsuite: arm: Use effective-target for memset-inline* tests
Torbjörn SVENSSON [Thu, 24 Oct 2024 08:40:27 +0000 (10:40 +0200)] 
testsuite: arm: Use effective-target for memset-inline* tests

As these tests are set to execute and require neon hardware to do so,
add the missing dg-require-effective-target arm_neon_hw.

gcc/testsuite/ChangeLog:

* gcc.target/arm/memset-inline-4.c: Use effective-target
arm_neon_hw.
* gcc.target/arm/memset-inline-5.c: Likewise.
* gcc.target/arm/memset-inline-6.c: Likewise.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
9 months agotestsuite: arm: Force hard ABI for pr51534.c test
Torbjörn SVENSSON [Thu, 31 Oct 2024 17:54:30 +0000 (18:54 +0100)] 
testsuite: arm: Force hard ABI for pr51534.c test

The test case is written in a way that it should be using hard float
ABI, but the use of -mfloat-abi=hard could be overriden by
dg-add-options arm_neon. Ensure that -mfloat-abi=hard is always after.

gcc/testsuite/ChangeLog:

* gcc.target/arm/pr51534.c: Ensure -mfloat-abi=hard is used.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
(cherry picked from commit e995866cff2866512cd3af24b6ca27a5782aca1f)

9 months agotestsuite: arm: Use effective-target for data-intrinsics-assembly test
Torbjörn SVENSSON [Sat, 19 Oct 2024 17:55:51 +0000 (19:55 +0200)] 
testsuite: arm: Use effective-target for data-intrinsics-assembly test

The expected assembler in the test case assumes -marm, so explicily
require it.

gcc/testsuite/ChangeLog:

* gcc.target/arm/acle/data-intrinsics-assembly.c: Use
effective-target arm_arch_v6_arm.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
(cherry picked from commit 7b2e6e6be6fdb3cbb2e21e190a981731b322bf4f)

9 months agotestsuite: arm: Relax cbranch tests to accept inverted branches
Torbjörn SVENSSON [Sat, 19 Oct 2024 15:54:59 +0000 (17:54 +0200)] 
testsuite: arm: Relax cbranch tests to accept inverted branches

Similar to PR113502, but for non-aarch64 test.
The test started to fail after r14-7243-gafac1bd3365.

gcc/testsuite/ChangeLog:

* gcc.target/arm/vect-early-break-cbranch.c: Ignore exact
branch.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
(cherry picked from commit d56d2f3102ada3d68eaa318de4b6d1a17d9cd74d)

9 months agoada: Fix crash on default value with nested iterated component associations
Eric Botcazou [Wed, 16 Oct 2024 07:05:55 +0000 (09:05 +0200)] 
ada: Fix crash on default value with nested iterated component associations

The problem is that the freeze node for the type of the element ends up in
the component list of the record type declared with the default value.

gcc/ada/ChangeLog:

PR ada/113036
* freeze.adb (Freeze_Expression): Deal with freezing actions coming
from within nested internal loops present in spec expressions.

9 months agoada: Fix crash on real literal in declare expression of expression function
Eric Botcazou [Mon, 20 May 2024 12:33:14 +0000 (14:33 +0200)] 
ada: Fix crash on real literal in declare expression of expression function

The problem is that the freeze node of the type to which the real literal
is resolved is placed inside the expression function instead of outside.

gcc/ada/

* freeze.adb (Freeze_Expression): Also attach pending freeze nodes
to the parent in the case of an internal block in a spec expression.

9 months agoUpdate bitwise_or op_range.
Andrew MacLeod [Thu, 31 Oct 2024 18:07:00 +0000 (14:07 -0400)] 
Update bitwise_or op_range.

If the LHS of a bitwise OR is positive, then so are both operands when
using op1_range or op2_range.

gcc/
* range-op.cc (operator_bitwise_or::op1_range): If LHS is signed
positive, so are both operands.

gcc/testsuite
* g++.dg/cpp23/attr-assume-opt.C (f2b): Alternate flow test.

9 months agoReimplement 'assume' processing pass.
Andrew MacLeod [Fri, 1 Nov 2024 16:46:39 +0000 (12:46 -0400)] 
Reimplement 'assume' processing pass.

Rework the assume pass to work properly and fail conservatively when it
does.  Also move it to its own file.

PR tree-optimization/117287
gcc/
* Makefile.in (IBJS): Add tree-assume.o
* gimple-range.cc (assume_query::assume_range_p): Remove.
(assume_query::range_of_expr): Remove.
(assume_query::assume_query): Move to tree-assume.cc.
(assume_query::~assume_query): Remove.
(assume_query::calculate_op): Move to tree-assume.cc.
(assume_query::calculate_phi): Likewise.
(assume_query::check_taken_edge): Remove.
(assume_query::calculate_stmt): Move to tree-assume.cc.
(assume_query::dump): Remove.
* gimple-range.h (class assume_query): Move to tree-assume.cc
* tree-assume.cc: New
* tree-vrp.cc (struct pass_data_assumptions): Move to tree-assume.cc.
(class pass_assumptions): Likewise.
(make_pass_assumptions): Likewise.

gcc/testsuite/
* g++.dg/cpp23/pr117287-attr.C: New.

9 months agoMake fur_edge accessible.
Andrew MacLeod [Fri, 1 Nov 2024 14:56:54 +0000 (10:56 -0400)] 
Make fur_edge accessible.

Move the decl of fur_edge out of the source file into the header file.

* gimple-range-fold.cc (class fur_edge): Relocate from here.
(fur_edge::fur_edge): Also move to:
* gimple-range-fold.h (class fur_edge): Relocate to here.
(fur_edge::fur_edge): Likewise.

9 months agolibstdc++: Fix up 117406.cc test [PR117406]
Jakub Jelinek [Mon, 4 Nov 2024 11:29:01 +0000 (12:29 +0100)] 
libstdc++: Fix up 117406.cc test [PR117406]

Christophe mentioned in bugzilla that the test FAILs on aarch64,
I'm not including <climits> and use INT_MAX.
Apparently during my testing I got it because the test preinclude
-include bits/stdc++.h
and that includes <climits>, dunno why that didn't happen on aarch64.
In any case, either I can add #include <climits>, or because the
test already has #include <limits> I've changed uses of INT_MAX
with std::numeric_limits<int>::max(), that should be the same thing.
But if you prefer
 #include <climits>
I can surely add that instead.

2024-11-04  Jakub Jelinek  <jakub@redhat.com>

PR libstdc++/117406
* testsuite/26_numerics/headers/cmath/117406.cc: Use
std::numeric_limits<int>::max() instead of INT_MAX.

(cherry picked from commit afcbf4dd27c147eb7d8f84e1a41c021eddec777e)

9 months agolibstdc++: Fix up std::{,b}float16_t std::{ilogb,l{,l}r{ound,int}} [PR117406]
Jakub Jelinek [Sat, 2 Nov 2024 17:48:54 +0000 (18:48 +0100)] 
libstdc++: Fix up std::{,b}float16_t std::{ilogb,l{,l}r{ound,int}} [PR117406]

These overloads incorrectly cast the result of the float __builtin_*
to _Float or __gnu_cxx::__bfloat16_t.  For std::ilogb that changes
behavior for the INT_MAX return because that isn't representable in
either of the floating point formats, for the others it is I think
just a very inefficient hop from int/long/long long to std::{,b}float16_t
and back.  I mean for the round/rint cases, either the argument is small
and then the return value should be representable in the floating point
format too, or it is too large that the argument is already integral
and then it should just return the argument with the round trips.
Too large value is unspecified unlike ilogb.

2024-11-02  Jakub Jelinek  <jakub@redhat.com>

PR libstdc++/117406
* include/c_global/cmath (std::ilogb(_Float16), std::llrint(_Float16),
std::llround(_Float16), std::lrint(_Float16), std::lround(_Float16)):
Don't cast __builtin_* return to _Float16.
(std::ilogb(__gnu_cxx::__bfloat16_t),
std::llrint(__gnu_cxx::__bfloat16_t),
std::llround(__gnu_cxx::__bfloat16_t),
std::lrint(__gnu_cxx::__bfloat16_t),
std::lround(__gnu_cxx::__bfloat16_t)): Don't cast __builtin_* return to
__gnu_cxx::__bfloat16_t.
* testsuite/26_numerics/headers/cmath/117406.cc: New test.

(cherry picked from commit 36a9e2b22596711455e702ea5a5a3f26e145321c)

9 months agoexpand: Fix up expansion of VIEW_CONVERT_EXPR to BITINT_TYPE [PR117354]
Jakub Jelinek [Thu, 31 Oct 2024 09:52:56 +0000 (10:52 +0100)] 
expand: Fix up expansion of VIEW_CONVERT_EXPR to BITINT_TYPE [PR117354]

The following testcase ICEs, because when trying to expand the
VIEW_CONVERT_EXPR operand which is SSA_NAME defined to
V32QI or V4DI MEM_REF which is aligned just to 8 bytes we force
it as unaligned into a register, but then try to call extract_bit_field
from the V32QI or V4DI register to BLKmode.  extract_bit_field doesn't
obviously support BLKmode extraction and so ICEs.

The second hunk fixes the ICE by not calling extract_bit_field when
it can't handle it, the last if will handle it properly by storing
it to memory and using BLKmode access to the copy.

The first hunk is an optimization, if mode is BLKmode, by setting
inner_reference_p argument to expand_expr_real we avoid the
expand_misaligned_mem_ref calls which load it from memory into a register.

2024-10-31  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/117354
* expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Pass
true as inner_reference_p argument to expand_expr_real if
mode is BLKmode.  Don't call extract_bit_field if mode is BLKmode.

* gcc.dg/bitint-113.c: New test.

(cherry picked from commit b39f62ff739e9ffea0e6485667f15b985f8cd63d)

9 months agofunction: Call do_pending_stack_adjust in assign_parms [PR117296]
Jakub Jelinek [Wed, 30 Oct 2024 08:59:22 +0000 (09:59 +0100)] 
function: Call do_pending_stack_adjust in assign_parms [PR117296]

Functions called by assign_parms call emit_block_move in two places,
so on some targets can be expanded as calls and can result in pending
stack adjustment.

Now, during expansion we normally call do_pending_stack_adjust at the end
of expansion of each basic block or before emitting code that will branch
and/or has labels, and when emitting labels we assert that there are no
pending stack adjustments.

assign_parms is expanded before the first basic block and if the first
basic block starts with a label and at least one of those emit_block_move
calls resulted in the need of pending stack adjustments, we ICE when
emitting that label.

The following patch fixes that by calling do_pending_stack_adjust after
after the assign_parms potential emit_block_move calls.

2024-10-30  Jakub Jelinek  <jakub@redhat.com>

PR target/117296
* function.cc (assign_parms): Call do_pending_stack_adjust.

* gcc.target/i386/pr117296.c: New test.

(cherry picked from commit fccef0c4ed0119ac53940bdb3838052339cf14a2)

9 months agolibstdc++: Use if consteval rather than if (std::__is_constant_evaluated()) for ...
Jakub Jelinek [Tue, 29 Oct 2024 10:14:12 +0000 (11:14 +0100)] 
libstdc++: Use if consteval rather than if (std::__is_constant_evaluated()) for {,b}float16_t nextafter [PR117321]

The nextafter_c++23.cc testcase fails to link at -O0.
The problem is that eventhough std::__is_constant_evaluated() has
always_inline attribute, that at -O0 just means that we inline the
call, but its result is still assigned to a temporary which is tested
later, nothing at -O0 propagates that false into the if and optimizes
away the if body.  And the __builtin_nextafterf16{,b} calls are meant
to be used solely for constant evaluation, the C libraries don't
define nextafterf16 these days.

As __STDCPP_FLOAT16_T__ and __STDCPP_BFLOAT16_T__ are predefined right
now only by GCC, not by clang which doesn't implement the extended floating
point types paper, and as they are predefined in C++23 and later modes only,
I think we can just use if consteval which is folded already during the FE
and the body isn't included even at -O0.  I've added a feature test for
that just in case clang implements those and implements those in some weird
way.  Note, if (__builtin_is_constant_evaluted()) would work correctly too,
that is also folded to false at gimplification time and the corresponding
if block not emitted at all.  But for -O0 it can't be wrapped into a helper
inline function.

2024-10-29  Jakub Jelinek  <jakub@redhat.com>

PR libstdc++/117321
* include/c_global/cmath (nextafter(_Float16, _Float16)): Use
if consteval rather than if (std::__is_constant_evaluated()) around
the __builtin_nextafterf16 call.
(nextafter(__gnu_cxx::__bfloat16_t, __gnu_cxx::__bfloat16_t)): Use
if consteval rather than if (std::__is_constant_evaluated()) around
the __builtin_nextafterf16b call.
* testsuite/26_numerics/headers/cmath/117321.cc: New test.

(cherry picked from commit 5e247ac0c28b9a2662f99c4a5420c5f7c2d0c6bd)

9 months agoAdd regression test
Eric Botcazou [Mon, 4 Nov 2024 10:15:15 +0000 (11:15 +0100)] 
Add regression test

This is for the latest fix made to Selected_Length_Checks in Checks.

gcc/testsuite
* gnat.dg/specs/array7.ads: New test.

9 months agoada: Fix internal error on concatenation of discriminant-dependent component
Eric Botcazou [Fri, 16 Aug 2024 14:03:30 +0000 (16:03 +0200)] 
ada: Fix internal error on concatenation of discriminant-dependent component

This only occurs with optimization enabled, but the expanded code is always
wrong because it reuses the formal parameter of an initialization procedure
associated with a discriminant (a discriminal in GNAT parlance) outside of
the initialization procedure.

gcc/ada/

* checks.adb (Selected_Length_Checks.Get_E_Length): For a
component of a record with discriminants and if the expression is
a selected component, try to build an actual subtype from its
prefix instead of from the discriminal.

9 months agoDaily bump.
GCC Administrator [Mon, 4 Nov 2024 00:22:56 +0000 (00:22 +0000)] 
Daily bump.

9 months agoDaily bump.
GCC Administrator [Sun, 3 Nov 2024 00:22:12 +0000 (00:22 +0000)] 
Daily bump.

9 months agoDaily bump.
GCC Administrator [Sat, 2 Nov 2024 00:25:44 +0000 (00:25 +0000)] 
Daily bump.

9 months agoi386: Do not allow pointer conversion for CMPccXADD intrin under -O0
Haochen Jiang [Fri, 1 Nov 2024 07:59:47 +0000 (15:59 +0800)] 
i386: Do not allow pointer conversion for CMPccXADD intrin under -O0

The pointer conversion to wider type under macro would not consider
whether the higher bit is cleaned or not. It will lead to unexpected
cmp result.

After this change, it will throw an incompatible pointer type error just
like -O2 does currently.

gcc/ChangeLog:

* config/i386/cmpccxaddintrin.h (_cmpccxadd_epi32): Do not do
type conversion for pointer.
(_cmpccxadd_epi64): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/cmpccxadd-1b.c: New test.

9 months agoFortran: Fix ICE with structure constructor in data statement [PR79685]
Paul Thomas [Fri, 25 Oct 2024 16:59:03 +0000 (17:59 +0100)] 
Fortran: Fix ICE with structure constructor in data statement [PR79685]

2024-10-25  Paul Thomas  <pault@gcc.gnu.org>

gcc/fortran
PR fortran/79685
* decl.cc (match_data_constant): Find the symtree instead of
the symbol so the use renamed symbols are found. Pass this and
the derived type to gfc_match_structure_constructor.
* match.h: Update prototype of gfc_match_structure_contructor.
* primary.cc (gfc_match_structure_constructor): Remove call to
gfc_get_ha_sym_tree and use caller supplied symtree instead.

gcc/testsuite/
PR fortran/79685
* gfortran.dg/use_rename_13.f90: New test.

(cherry picked from commit 6cb1da72cac166bd3b005c0430557b68b9761da5)

9 months ago[APX PPX] Avoid generating unmatched pushp/popp in pro/epilogue
Hongyu Wang [Wed, 7 Feb 2024 06:42:58 +0000 (14:42 +0800)] 
[APX PPX] Avoid generating unmatched pushp/popp in pro/epilogue

According to APX spec, the pushp/popp pairs should be matched,
otherwise the PPX hint cannot take effect and cause performance loss.

In the ix86_expand_epilogue, there are several optimizations that may
cause the epilogue using mov to restore the regs. Check if PPX applied
and prevent usage of mov/leave in the epilogue. Also do not use PPX
for eh_return.

gcc/ChangeLog:

* config/i386/i386.cc (ix86_expand_prologue): Set apx_ppx_used
flag in m.fs with TARGET_APX_PPX && !crtl->calls_eh_return.
(ix86_emit_save_regs): Emit ppx is available only when
TARGET_APX_PPX && !crtl->calls_eh_return.
(ix86_expand_epilogue): Don't restore reg using mov when
apx_ppx_used flag is true.
* config/i386/i386.h (struct machine_frame_state):
Add apx_ppx_used flag.

gcc/testsuite/ChangeLog:

* gcc.target/i386/apx-ppx-2.c: New test.
* gcc.target/i386/apx-ppx-3.c: Likewise.

(cherry picked from commit 8e72b1bb3896f6e8d4f4679cbcfbc2a8212d04f9)

9 months agoDaily bump.
GCC Administrator [Fri, 1 Nov 2024 00:24:47 +0000 (00:24 +0000)] 
Daily bump.

9 months agors6000: ROP - Do not disable shrink-wrapping for leaf functions [PR114759]
Peter Bergner [Tue, 18 Jun 2024 22:42:45 +0000 (17:42 -0500)] 
rs6000: ROP - Do not disable shrink-wrapping for leaf functions [PR114759]

Only disable shrink-wrapping when using -mrop-protect when we know we
will be emitting the ROP-protect hash instructions (ie, non-leaf functions).

2024-06-17  Peter Bergner  <bergner@linux.ibm.com>

gcc/
PR target/114759
* config/rs6000/rs6000.cc (rs6000_override_options_after_change): Move
the disabling of shrink-wrapping from here....
* config/rs6000/rs6000-logue.cc (rs6000_emit_prologue): ...to here.

gcc/testsuite/
PR target/114759
* gcc.target/powerpc/pr114759-1.c: New test.

(cherry picked from commit 0451bc503da9c858e9f1ddfb8faec367c2e032c8)

9 months agoaarch64: Forbid F64MM permutes in streaming mode
Richard Sandiford [Thu, 31 Oct 2024 19:52:46 +0000 (19:52 +0000)] 
aarch64: Forbid F64MM permutes in streaming mode

The current code was based on an early version of the SME spec,
which allowed the .Q forms of TRN1, TRN2, UZP1, UZP2, ZIP1, and ZIP2
to be used in streaming mode.  We should now forbid them instead;
see https://developer.arm.com/documentation/ddi0602/2024-09/SVE-Instructions/TRN1--TRN2--vectors---Interleave-even-or-odd-elements-from-two-vectors-?lang=en
and the corresponding entries for the others.

gcc/
* config/aarch64/aarch64-sve-builtins-base.def (svtrn1q, svtrn2q)
(svuzp1q, svuzp2q, svzip1q, svzip2q): Require SM_OFF.

gcc/testsuite/
* g++.target/aarch64/sve/aarch64-ssve.exp: Add tests for trn[12]q,
uzp[12].c, and zip[12]q.
* gcc.target/aarch64/sve/acle/asm/trn1q_bf16.c: Skip for
STREAMING_COMPATIBLE.
* gcc.target/aarch64/sve/acle/asm/trn1q_f16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn1q_f32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn1q_f64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn1q_s16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn1q_s32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn1q_s64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn1q_s8.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn1q_u16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn1q_u32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn1q_u64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn1q_u8.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn2q_bf16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn2q_f16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn2q_f32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn2q_f64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn2q_s16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn2q_s32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn2q_s64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn2q_s8.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn2q_u16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn2q_u32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn2q_u64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/trn2q_u8.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp1q_bf16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp1q_f16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp1q_f32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp1q_f64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp1q_s16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp1q_s32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp1q_s64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp1q_s8.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp1q_u16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp1q_u32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp1q_u64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp1q_u8.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp2q_bf16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp2q_f16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp2q_f32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp2q_f64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp2q_s16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp2q_s32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp2q_s64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp2q_s8.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp2q_u16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp2q_u32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp2q_u64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/uzp2q_u8.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip1q_bf16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip1q_f16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip1q_f32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip1q_f64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip1q_s16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip1q_s32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip1q_s64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip1q_s8.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip1q_u16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip1q_u32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip1q_u64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip1q_u8.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip2q_bf16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip2q_f16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip2q_f32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip2q_f64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip2q_s16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip2q_s32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip2q_s64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip2q_s8.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip2q_u16.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip2q_u32.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip2q_u64.c: Likewise.
* gcc.target/aarch64/sve/acle/asm/zip2q_u8.c: Likewise.

(cherry picked from commit e8fa15ea01439bccf15ae9b9a4d63ac92586c2c5)

9 months agoFix function multiversioning dispatcher link error with LTO
Yangyu Chen [Thu, 31 Oct 2024 19:52:45 +0000 (19:52 +0000)] 
Fix function multiversioning dispatcher link error with LTO

We forgot to apply DECL_EXTERNAL to __init_cpu_features_resolver decl. When
building with LTO, the linker cannot find the
__init_cpu_features_resolver.lto_priv* symbol, causing the link error.

This patch gets this fixed by adding DECL_EXTERNAL to the decl. To avoid used
but never defined warning for this symbol, we also mark TREE_PUBLIC to the decl.
We should also mark the decl having hidden visibility. And fix the attribute in
the same way for __aarch64_cpu_features identifier.

Minimal steps to reproduce the bug:

echo '__attribute__((target_clones("default", "aes"))) void func1() { }' > 1.c
echo '__attribute__((target_clones("default", "aes"))) void func2() { }' > 2.c
echo 'void func1();void func2();int main(){func1();func2();return 0;}' > main.c
gcc -flto -c 1.c 2.c
gcc -flto main.c 1.o 2.o

Fixes: 0cfde688e213 ("[aarch64] Add function multiversioning support")
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
gcc/ChangeLog:

* config/aarch64/aarch64.cc (dispatch_function_versions): Adding
DECL_EXTERNAL, TREE_PUBLIC and hidden DECL_VISIBILITY to
__init_cpu_features_resolver and __aarch64_cpu_features.

(cherry picked from commit 875279ff3ee3b4135401286b8378087a24fd0f8d)

9 months agoDaily bump.
GCC Administrator [Thu, 31 Oct 2024 00:22:52 +0000 (00:22 +0000)] 
Daily bump.

9 months agojit: fix leak of pending_assemble_externals_set [PR117275]
David Malcolm [Wed, 30 Oct 2024 20:11:41 +0000 (16:11 -0400)] 
jit: fix leak of pending_assemble_externals_set [PR117275]

My recent r15-4580-g779c0390e3b57d fix for resetting state in
varasm.cc introduced some noise to "make selftest-valgrind" and,
presumably, a memory leak in libgccjit:

==2462086== 160 (56 direct, 104 indirect) bytes in 1 blocks are definitely lost in loss record 248 of 352
==2462086==    at 0x5270E7D: operator new(unsigned long) (vg_replace_malloc.c:342)
==2462086==    by 0x1D1EB89: init_varasm_once() (varasm.cc:6806)
==2462086==    by 0x181C845: backend_init() (toplev.cc:1826)
==2462086==    by 0x181D41A: do_compile() (toplev.cc:2193)
==2462086==    by 0x181D99C: toplev::main(int, char**) (toplev.cc:2371)
==2462086==    by 0x378391D: main (main.cc:39)

Fixed thusly.

gcc/ChangeLog:
PR jit/117275
* varasm.cc (process_pending_assemble_externals): Reset
pending_assemble_externals_set to nullptr after deleting it.
(varasm_cc_finalize): Delete pending_assemble_externals_set.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>
(cherry picked from commit 7f41203f08b9948c1c636dc9d66571121c6c7793)
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
9 months agojit: reset state in varasm.cc [PR117275]
David Malcolm [Wed, 30 Oct 2024 20:11:40 +0000 (16:11 -0400)] 
jit: reset state in varasm.cc [PR117275]

PR jit/117275 reports various jit test failures seen on
powerpc64le-unknown-linux-gnu due to hitting this assertion
in varasm.cc on the 2nd compilation in a process:

#2  0x00007ffff63e67d0 in assemble_external_libcall (fun=0x7ffff2a4b1d8)
    at ../../src/gcc/varasm.cc:2650
2650          gcc_assert (!pending_assemble_externals_processed);
(gdb) p pending_assemble_externals_processed
$1 = true

We're not properly resetting state in varasm.cc after a compile
for libgccjit.

Fixed thusly.

gcc/ChangeLog:
PR jit/117275
* toplev.cc (toplev::finalize): Call varasm_cc_finalize.
* varasm.cc (varasm_cc_finalize): New.
* varasm.h (varasm_cc_finalize): New decl.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>
(cherry picked from commit 779c0390e3b57d1eebd41bbfe43d1f329c91de6c)
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
9 months agotestsuite, jit: fix test-error-pr63969-missing-driver.c
David Malcolm [Wed, 30 Oct 2024 20:11:40 +0000 (16:11 -0400)] 
testsuite, jit: fix test-error-pr63969-missing-driver.c

jit.dg/test-error-pr63969-missing-driver.c tries to break PATH and
verify that an error is generated when using an external driver.

However it does this by unsetting PATH, and so the test could
accidentally find the driver if the system supplies a default and the
driver happens to be installed in that path (reported as rhbz#2318021).

Fix the test by instead setting PATH to a bogus value.

gcc/testsuite/ChangeLog:
* jit.dg/test-error-pr63969-missing-driver.c (create_code): When
breaking PATH, use setenv with a bogus value, rather than
unsetenv, in case the system uses a default path that contains
the driver binary.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>
(cherry picked from commit f8dcb559e615dbb4557a23363f9532a3544a7241)
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
9 months agoaarch64: Assume alias conflict if common address reg changes [PR116783]
Alex Coplan [Wed, 30 Oct 2024 13:46:12 +0000 (13:46 +0000)] 
aarch64: Assume alias conflict if common address reg changes [PR116783]

As the PR shows, pair fusion was tricking memory_modified_in_insn_p into
returning false when a common base register (in this case, x1) was
modified between the mem and the store insn.  This lead to wrong code as
the accesses really did alias.

To avoid this sort of problem, this patch avoids invoking RTL alias
analysis altogether (and assume an alias conflict) if the two insns to
be compared share a common address register R, and the insns see different
definitions of R (i.e. it was modified in between).

This is a backport (but not a straight cherry pick) of
r15-4518-gc0e54ce1999ccf2241f74c5188b11b92e5aedc1f.

gcc/ChangeLog:

PR rtl-optimization/116783
* config/aarch64/aarch64-ldp-fusion.cc
(def_walker::cand_addr_uses): New.
(def_walker::def_walker): Add parameter for candidate address
uses.
(def_walker::alias_conflict_p): Declare.
(def_walker::addr_reg_conflict_p): New.
(def_walker::conflict_p): New.
(store_walker::store_walker): Add parameter for candidate
address uses and pass to base ctor.
(store_walker::conflict_p): Rename to ...
(store_walker::alias_conflict_p): ... this.
(load_walker::load_walker): Add parameter for candidate
address uses and pass to base ctor.
(load_walker::conflict_p): Rename to ...
(load_walker::alias_conflict_p): ... this.
(ldp_bb_info::try_fuse_pair): Collect address register
uses for candidate insns and pass down to alias walkers.

gcc/testsuite/ChangeLog:

PR rtl-optimization/116783
* g++.dg/torture/pr116783.C: New test.

9 months agoFix ICE due to subreg:us_truncate.
liuhongt [Tue, 29 Oct 2024 09:09:39 +0000 (02:09 -0700)] 
Fix ICE due to subreg:us_truncate.

Force_operand issues an ICE when input
is (subreg:DI (us_truncate:V8QI)), it's probably because it's an
invalid rtx, So refine backend patterns for that.

gcc/ChangeLog:

PR target/117318
* config/i386/sse.md (*avx512vl_<code>v2div2qi2_mask_store_1):
Rename to ..
(avx512vl_<code>v2div2qi2_mask_store_1): .. this.
(avx512vl_<code>v2div2qi2_mask_store_2): Change to
define_expand.
(*avx512vl_<code><mode>v4qi2_mask_store_1): Rename to ..
(avx512vl_<code><mode>v4qi2_mask_store_1): .. this.
(avx512vl_<code><mode>v4qi2_mask_store_2): Change to
define_expand.
(*avx512vl_<code><mode>v8qi2_mask_store_1): Rename to ..
(avx512vl_<code><mode>v8qi2_mask_store_1): .. this.
(avx512vl_<code><mode>v8qi2_mask_store_2): Change to
define_expand.
(*avx512vl_<code><mode>v4hi2_mask_store_1): Rename to ..
(avx512vl_<code><mode>v4hi2_mask_store_1): .. this.
(avx512vl_<code><mode>v4hi2_mask_store_2): Change to
define_expand.
(*avx512vl_<code>v2div2hi2_mask_store_1): Rename to ..
(avx512vl_<code>v2div2hi2_mask_store_1): .. this.
(avx512vl_<code>v2div2hi2_mask_store_2): Change to
define_expand.
(*avx512vl_<code>v2div2si2_mask_store_1): Rename to ..
(avx512vl_<code>v2div2si2_mask_store_1): .. this.
(avx512vl_<code>v2div2si2_mask_store_2): Change to
define_expand.
(*avx512f_<code>v8div16qi2_mask_store_1): Rename to ..
(avx512f_<code>v8div16qi2_mask_store_1): .. this.
(avx512f_<code>v8div16qi2_mask_store_2): Change to
define_expand.

gcc/testsuite/ChangeLog:

* gcc.target/i386/pr117318.c: New test.

(cherry picked from commit bc0eeccf27a084461a2d5661e23468350acb43da)

9 months agoDaily bump.
GCC Administrator [Wed, 30 Oct 2024 00:23:39 +0000 (00:23 +0000)] 
Daily bump.

9 months agoFix miscompilation of function containing __builtin_unreachable
Eric Botcazou [Tue, 29 Oct 2024 20:40:34 +0000 (21:40 +0100)] 
Fix miscompilation of function containing __builtin_unreachable

This is a wrong-code generation on the SPARC for a function containing
a call to __builtin_unreachable caused by the delay slot scheduling pass,
and more specifically the find_end_label function which has these lines:

  /* Otherwise, see if there is a label at the end of the function. If there
     is, it must be that RETURN insns aren't needed, so that is our return
     label and we don't have to do anything else.  */

The comment was correct 20 years ago but no longer is nowadays in the
presence of RTL epilogues and calls to __builtin_unreachable, so the
patch just removes the associated two lines of code:

  else if (LABEL_P (insn))
    *plabel = as_a <rtx_code_label *> (insn);

and otherwise contains just adjustments to the commentary.

gcc/
PR rtl-optimization/117327
* reorg.cc (find_end_label): Do not return a dangling label at the
end of the function and adjust commentary.

gcc/testsuite/
* gcc.c-torture/execute/20241029-1.c: New test.

9 months agors6000: Fix PTImode handling in power8 swap optimization pass [PR116415]
Peter Bergner [Fri, 23 Aug 2024 16:45:40 +0000 (11:45 -0500)] 
rs6000: Fix PTImode handling in power8 swap optimization pass [PR116415]

Our power8 swap optimization pass has some special handling for optimizing
swaps of TImode variables.  The test case reported in bugzilla uses a call
to  __atomic_compare_exchange, which introduces a variable of PTImode and
that does not get the same treatment as TImode leading to wrong code
generation.  The simple fix is to treat PTImode identically to TImode.

2024-08-23  Peter Bergner  <bergner@linux.ibm.com>

gcc/
PR target/116415
* config/rs6000/rs6000.h (TI_OR_PTI_MODE): New define.
* config/rs6000/rs6000-p8swap.cc (rs6000_analyze_swaps): Use it to
handle PTImode identically to TImode.

gcc/testsuite/
PR target/116415
* gcc.target/powerpc/pr116415.c: New test.

(cherry picked from commit 6e68c3df1540c5bafbb47343698bf4e270333fdb)

9 months agoDaily bump.
GCC Administrator [Tue, 29 Oct 2024 00:23:02 +0000 (00:23 +0000)] 
Daily bump.

9 months agotestsuite: add testcase for fixed PR107467
Sam James [Mon, 21 Oct 2024 11:11:42 +0000 (12:11 +0100)] 
testsuite: add testcase for fixed PR107467

PR107467 ended up being fixed by the fix for PR115110, but let's
add the testcase on top.

gcc/testsuite/ChangeLog:
PR tree-optimization/107467
PR middle-end/115110

* g++.dg/lto/pr107467_0.C: New test.

(cherry picked from commit 4e09ae37dbe0a10f48490214f50ff733cc92280a)

9 months agoRevert "testsuite: add testcase for fixed PR107467"
Sam James [Mon, 28 Oct 2024 17:06:37 +0000 (17:06 +0000)] 
Revert "testsuite: add testcase for fixed PR107467"

This reverts commit 2f0d109bd871d11b5b93468f271aa6dc34ef88d8.

9 months agotestsuite: add testcase for fixed PR107467
Sam James [Mon, 21 Oct 2024 11:11:42 +0000 (12:11 +0100)] 
testsuite: add testcase for fixed PR107467

PR107467 ended up being fixed by the fix for PR115110, but let's
add the testcase on top.

gcc/testsuite/ChangeLog:
PR tree-optimization/107467
PR middle-end/115110

* g++.dg/lto/pr107467_0.C: New test.

9 months agoDaily bump.
GCC Administrator [Mon, 28 Oct 2024 00:22:21 +0000 (00:22 +0000)] 
Daily bump.

9 months agotestsuite: Sanitize pacbti test cases for Cortex-M
Torbjörn SVENSSON [Tue, 3 Sep 2024 09:23:57 +0000 (11:23 +0200)] 
testsuite: Sanitize pacbti test cases for Cortex-M

Some of the test cases were scanning for "bti", but it would,
incorrectly, match the ".arch_extenssion pacbti".

gcc/testsuite/ChangeLog:

* gcc.target/arm/bti-1.c: Check for asm instructions starting
with a tab.
* gcc.target/arm/bti-2.c: Likewise.
* gcc.target/arm/pac-1.c: Likewise.
* gcc.target/arm/pac-2.c: Likewise.
* gcc.target/arm/pac-3.c: Likewise.
* gcc.target/arm/pac-4.c: Likewise.
* gcc.target/arm/pac-6.c: Likewise.
* gcc.target/arm/pac-7.c: Likewise.
* gcc.target/arm/pac-8.c: Likewise.
* gcc.target/arm/pac-9.c: Likewise.
* gcc.target/arm/pac-10.c: Likewise.
* gcc.target/arm/pac-11.c: Likewise.
* gcc.target/arm/pac-15.c: Likewise.
* gcc.target/arm/pac-sibcall.c: Likewise.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
Co-authored-by: Yvan ROUX <yvan.roux@foss.st.com>
(cherry picked from commit 6ad29a858bac7cf9e765925cf5f6945e20f085be)

9 months agoDaily bump.
GCC Administrator [Sun, 27 Oct 2024 00:23:03 +0000 (00:23 +0000)] 
Daily bump.

9 months agoDaily bump.
GCC Administrator [Sat, 26 Oct 2024 00:23:24 +0000 (00:23 +0000)] 
Daily bump.

9 months agoAssorted --disable-checking fixes [PR117249]
Jakub Jelinek [Fri, 25 Oct 2024 12:09:42 +0000 (14:09 +0200)] 
Assorted --disable-checking fixes [PR117249]

We have currently 3 different definitions of gcc_assert macro, one used most
of the time (unless --disable-checking) which evaluates the condition at
runtime and also checks it at runtime, then one for --disable-checking GCC 4.5+
which looks like
((void)(UNLIKELY (!(EXPR)) ? __builtin_unreachable (), 0 : 0))
and a fallback one
((void)(0 && (EXPR)))
Now, the last one actually doesn't evaluate any of the side-effects in the
argument, just quiets up unused var/parameter warnings.
I've tried to replace the middle definition with
({ [[assume (EXPR)]]; (void) 0; })
for compilers which support assume attribute and statement expressions
(surprisingly quite a few spots use gcc_assert inside of comma expressions),
but ran into PR117287, so for now such a change isn't being proposed.

The following patch attempts to move important side-effects from gcc_assert
arguments.

Bootstrapped/regtested on x86_64-linux and i686-linux with normal
--enable-checking=yes,rtl,extra, plus additionally I've attempted to do
x86_64-linux bootstrap with --disable-checking and gcc_assert changed to the
((void)(0 && (EXPR)))
version when --disable-checking.  That version ran into spurious middle-end
warnings
../../gcc/../include/libiberty.h:733:36: error: argument to ‘alloca’ is too large [-Werror=alloca-larger-than=]
../../gcc/tree-ssa-reassoc.cc:5659:20: note: in expansion of macro ‘XALLOCAVEC’
  int op_num = ops.length ();
  int op_normal_num = op_num;
  gcc_assert (op_num > 0);
  int stmt_num = op_num - 1;
  gimple **stmts = XALLOCAVEC (gimple *, stmt_num);
where we have gcc_assert exactly to work-around middle-end warnings.
Guess I'd need to also disable -Werror for this experiment, which actually
isn't a problem with unmodified system.h, because even for
--disable-checking we use the __builtin_unreachable at least in
stage2/stage3 and so the warnings aren't emitted, and even if it used
[[assume ()]]; it would work too because in stage2/stage3 we could again
rely on assume and statement expression support.

2024-10-25  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/117249
* tree-ssa-structalias.cc (insert_vi_for_tree): Move put calls out of
gcc_assert.
* lto-cgraph.cc (lto_symtab_encoder_delete_node): Likewise.
* gimple-ssa-strength-reduction.cc (get_alternative_base,
add_cand_for_stmt): Likewise.
* tree-eh.cc (add_stmt_to_eh_lp_fn): Likewise.
* except.cc (duplicate_eh_regions_1): Likewise.
* tree-ssa-reassoc.cc (insert_operand_rank): Likewise.
* config/nvptx/nvptx.cc (nvptx_expand_call): Use == rather than = in
gcc_assert.
* opts-common.cc (jobserver_info::disconnect): Call close outside of
gcc_assert and only check result in it.
(jobserver_info::return_token): Call write outside of gcc_assert and
only check result in it.
* genautomata.cc (output_default_latencies): Move j++ side-effect
outside of gcc_assert.
* tree-ssa-loop-ivopts.cc (get_alias_ptr_type_for_ptr_address): Use
== rather than = in gcc_assert.
* cgraph.cc (symbol_table::create_edge): Move ++edges_max_uid
side-effect outside of gcc_assert.

(cherry picked from commit e2a8772c9328960c625f5b95091d4312efa0e284)

9 months agoc++: Further fix for get_member_function_from_ptrfunc [PR117259]
Jakub Jelinek [Thu, 24 Oct 2024 10:56:19 +0000 (12:56 +0200)] 
c++: Further fix for get_member_function_from_ptrfunc [PR117259]

The following testcase shows that the previous get_member_function_from_ptrfunc
changes weren't sufficient and we still have cases where
-fsanitize=undefined with pointers to member functions can cause wrong code
being generated and related false positive warnings.

The problem is that save_expr doesn't always create SAVE_EXPR, it can skip
some invariant arithmetics and in the end it could be really large
expressions which would be evaluated several times (and what is worse, with
-fsanitize=undefined those expressions then can have SAVE_EXPRs added to
their subparts for -fsanitize=bounds or -fsanitize=null or
-fsanitize=alignment instrumentation).  Tried to just build1 a SAVE_EXPR
+ add TREE_SIDE_EFFECTS instead of save_expr, but that doesn't work either,
because cp_fold happily optimizes those SAVE_EXPRs away when it sees
SAVE_EXPR operand is tree_invariant_p.

So, the following patch instead of using save_expr or building SAVE_EXPR
manually builds a TARGET_EXPR.  Both types are pointers, so it doesn't need
to be destroyed in any way, but TARGET_EXPR is what doesn't get optimized
away immediately.

2024-10-24  Jakub Jelinek  <jakub@redhat.com>

PR c++/117259
* typeck.cc (get_member_function_from_ptrfunc): Use force_target_expr
rather than save_expr for instance_ptr and function.  Don't call it
for TREE_CONSTANT.

* g++.dg/ubsan/pr117259.C: New test.

(cherry picked from commit b25d3201b6338d9f71c64f524ca2974d9a1f38e8)

9 months agoasan: Fix up build_check_stmt gsi handling [PR117209]
Jakub Jelinek [Thu, 24 Oct 2024 10:45:34 +0000 (12:45 +0200)] 
asan: Fix up build_check_stmt gsi handling [PR117209]

gsi_safe_insert_before properly updates gsi_bb in gimple_stmt_iterator
in case it splits objects, but unfortunately build_check_stmt was in
some places (but not others) using a copy of the iterator rather than
the iterator passed from callers and so didn't propagate that to callers.
I guess it didn't matter much before when it was just using
gsi_insert_before as that really didn't change the iterator.
The !before_p case is apparently dead code, nothing is calling it with
before_p=false since around 4.9.

2024-10-24  Jakub Jelinek  <jakub@redhat.com>

PR sanitizer/117209
* asan.cc (maybe_cast_to_ptrmode): Formatting fix.
(build_check_stmt): Don't copy *iter into gsi, perform all
the updates on iter directly.

* gcc.dg/asan/pr117209.c: New test.

(cherry picked from commit 885143fa77599c44bfdd4e8e6b6987b7824db6ba)

9 months agoAdd regression test
Eric Botcazou [Fri, 25 Oct 2024 11:14:22 +0000 (13:14 +0200)] 
Add regression test

gcc/testsuite
PR ada/116551
* gnat.dg/specs/vfa3.ads: New test.

9 months agoada: Fix internal error on bit-packed array type with Volatile_Full_Access
Eric Botcazou [Wed, 11 Sep 2024 17:53:12 +0000 (19:53 +0200)] 
ada: Fix internal error on bit-packed array type with Volatile_Full_Access

The problem occurs when the component type is a record type with default
values for the initialization procedure of the (base) array type, because
the compiler is trying to generate a full access for a parameter of the
base array type, which does not make sense.

gcc/ada/ChangeLog:

PR ada/116551
* gcc-interface/trans.cc (node_is_atomic) <N_Identifier>: Return
false if the type of the entity is an unconstrained array type.
(node_is_volatile_full_access) <N_Identifier>: Likewise.

9 months agoAVR: target/116953 - Restore recog_data after calling jump_over_one_insn_p.
Georg-Johann Lay [Tue, 22 Oct 2024 09:51:44 +0000 (11:51 +0200)] 
AVR: target/116953 - Restore recog_data after calling jump_over_one_insn_p.

The previous fix for PR116953 is incomplete because references to
recog_data are escaping avr_out_sbxx_branch() in the form of %-operands
in the returned asm code template.  This patch reverts the previous fix,
and re-extracts the operands by means of extract_constrain_insn_cached()
after the call of jump_over_one_insn_p().

PR target/116953
gcc/
* config/avr/avr.cc (avr_out_sbxx_branch): Revert previous fix
for PR116953 (r15-4078).  Run extract_constrain_insn_cached
on the current insn after calling jump_over_one_insn_p.

(cherry picked from commit ca0ab7a0ac18911181e9161cfb8b87fb90039612)

9 months agoFortran: Simplify len_trim with array ref and fix mapping bug[PR84868].
Paul Thomas [Tue, 16 Jul 2024 14:56:44 +0000 (15:56 +0100)] 
Fortran: Simplify len_trim with array ref and fix mapping bug[PR84868].

2024-07-16  Paul Thomas  <pault@gcc.gnu.org>

gcc/fortran
PR fortran/84868
* simplify.cc (gfc_simplify_len_trim): If the argument is an
element of a parameter array, simplify all the elements and
build a new parameter array to hold the result, after checking
that it doesn't already exist.
* trans-expr.cc (gfc_get_interface_mapping_array) if a string
length is available, use it for the typespec.
(gfc_add_interface_mapping): Supply the se string length.

gcc/testsuite/
PR fortran/84868
* gfortran.dg/pr84868.f90: New test.

(cherry picked from commit 9f966b6a8ff0244dd6f8bf36d876799d5f9bbaee)

9 months agoc++: remove dg-warning [PR117274]
Jason Merrill [Thu, 24 Oct 2024 15:13:30 +0000 (11:13 -0400)] 
c++: remove dg-warning [PR117274]

This warning was added for GCC 15, don't expect it.

PR c++/117274
PR c++/117107

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/decomp10.C: Remove captured binding warning.

9 months agoDaily bump.
GCC Administrator [Thu, 24 Oct 2024 00:24:41 +0000 (00:24 +0000)] 
Daily bump.

9 months agoFix ICE due to isa mismatch for the builtins.
liuhongt [Tue, 22 Oct 2024 08:54:40 +0000 (01:54 -0700)] 
Fix ICE due to isa mismatch for the builtins.

gcc/ChangeLog:

PR target/117240
* config/i386/i386-builtin.def: Add avx/avx512f to vaes
ymm/zmm builtins.

gcc/testsuite/ChangeLog:

* gcc.target/i386/pr117240_avx.c: New test.
* gcc.target/i386/pr117240_avx512f.c: New test.

(cherry picked from commit 403e361d5aa620e77c9832578b2409a0fdd79d96)

9 months agoc-family: Fix up -Wsizeof-pointer-memaccess ICEs [PR117230]
Jakub Jelinek [Tue, 22 Oct 2024 18:30:41 +0000 (20:30 +0200)] 
c-family: Fix up -Wsizeof-pointer-memaccess ICEs [PR117230]

In the following testcases, we ICE on all 4 function calls.
The problem is using TYPE_PRECISION on vector types (but guess it
would be similarly problematic on structures/unions/arrays).
The test only differentiates between suggestion what to do, whether
to supply explicit size because sizeof (*p) for
{,{,un}signed }char *p is not very likely what the user want, or
dereferencing the pointer, so I think limiting that suggestion
to integral types is ok.

2024-10-22  Jakub Jelinek  <jakub@redhat.com>

PR c/117230
* c-warn.cc (sizeof_pointer_memaccess_warning): Only compare
TYPE_PRECISION of TREE_TYPE (type) to precision of char if
TREE_TYPE (type) is integral type.

* c-c++-common/Wsizeof-pointer-memaccess5.c: New test.

(cherry picked from commit 5fd1c0c1b6968d55e3f997d67a4c149edf20c012)

9 months agomatch.pd: Further fma negation fixes [PR116891]
Jakub Jelinek [Tue, 15 Oct 2024 17:38:46 +0000 (19:38 +0200)] 
match.pd: Further fma negation fixes [PR116891]

On Mon, Oct 14, 2024 at 08:53:29AM +0200, Jakub Jelinek wrote:
> >     PR middle-end/116891
> >     * match.pd ((negate (IFN_FNMS@3 @0 @1 @2)) -> (IFN_FMA @0 @1 @2)):
> >     Only enable for !HONOR_SIGN_DEPENDENT_ROUNDING.
>
> Guess it would be nice to have a testcase which FAILs without the patch and
> PASSes with it, but it can be added later.

I've added such a testcase now, and additionally found the fix only fixed
one of the 4 problematic similar cases.

Here is a patch which fixes the others too and adds the testcases.
fma-pr116891.c FAILed without your patch, FAILs with your patch too (but
only due to the bar/baz/qux checks) and PASSes with the patch.

2024-10-15  Jakub Jelinek  <jakub@redhat.com>

PR middle-end/116891
* match.pd ((negate (fmas@3 @0 @1 @2)) -> (IFN_FNMS @0 @1 @2)):
Only enable for !HONOR_SIGN_DEPENDENT_ROUNDING.
((negate (IFN_FMS@3 @0 @1 @2)) -> (IFN_FNMA @0 @1 @2)): Likewise.
((negate (IFN_FNMA@3 @0 @1 @2)) -> (IFN_FMS @0 @1 @2)): Likewise.

* gcc.dg/pr116891.c: New test.
* gcc.target/i386/fma-pr116891.c: New test.

(cherry picked from commit 4366f0c7e296ea0d7279343c9b0a1d597588a1da)

9 months agomiddle-end/116891 - fix (negate (IFN_FNMS@3 @0 @1 @2)) -> (IFN_FMA @0 @1 @2)
Richard Biener [Mon, 14 Oct 2024 06:11:22 +0000 (08:11 +0200)] 
middle-end/116891 - fix (negate (IFN_FNMS@3 @0 @1 @2)) -> (IFN_FMA @0 @1 @2)

Transforming -fma (-a, b, -c) to fma (a, b, c) is only valid when
not rounding towards -inf or +inf as the sign of the multiplication
changes.

PR middle-end/116891
* match.pd ((negate (IFN_FNMS@3 @0 @1 @2)) -> (IFN_FMA @0 @1 @2)):
Only enable for !HONOR_SIGN_DEPENDENT_ROUNDING.

(cherry picked from commit c53bd48c6920bc1f4039b6682aafbf414a600e47)

9 months agoDaily bump.
GCC Administrator [Wed, 23 Oct 2024 00:24:19 +0000 (00:24 +0000)] 
Daily bump.

9 months agoc++: non-dep structured binding decltype again [PR117107]
Jason Merrill [Tue, 22 Oct 2024 20:37:49 +0000 (16:37 -0400)] 
c++: non-dep structured binding decltype again [PR117107]

The patch for PR92687 handled the usual case of a decomp variable not being
in the table, but missed the case of there being nothing in the table yet.

PR c++/117107
PR c++/92687

gcc/cp/ChangeLog:

* decl.cc (lookup_decomp_type): Handle null table.

gcc/testsuite/ChangeLog:

* g++.dg/cpp2a/decomp10.C: New test.

(cherry picked from commit 71e13ea134b04562f8f2cdd9c4a55dbb0905f96a)

9 months agoc++/modules: Fix treatment of unnamed types [PR116929]
Nathaniel Shead [Thu, 23 May 2024 12:50:58 +0000 (22:50 +1000)] 
c++/modules: Fix treatment of unnamed types [PR116929]

In r14-9530 we relaxed "depending on type with no-linkage" errors for
declarations that could actually be accessed from different TUs anyway.
However, this also enabled it for unnamed types, which never work.

In a normal module interface, an unnamed type is TU-local by
[basic.link] p15.2, and so cannot be exposed or the program is
ill-formed.  We don't yet implement this checking but we should assume
that we will later; currently supporting this actually causes ICEs when
attempting to create the mangled name in some situations.

For a header unit, by [module.import] p5.3 it is unspecified whether two
TUs importing a header unit providing such a declaration are importing
the same header unit.  In this case, we would require name mangling
changes to somehow allow the (anonymous) type exported by such a header
unit to correspond across different TUs in the presence of other
anonymous declarations, so for this patch just assume that this case
would be an ODR violation instead.

PR c++/116929

gcc/cp/ChangeLog:

* tree.cc (no_linkage_check): Anonymous types can't be accessed
in a different TU.

gcc/testsuite/ChangeLog:

* g++.dg/modules/linkage-1_a.C: Remove anonymous type test.
* g++.dg/modules/linkage-1_b.C: Likewise.
* g++.dg/modules/linkage-1_c.C: Likewise.
* g++.dg/modules/linkage-2.C: Add note about anonymous types.

Signed-off-by: Nathaniel Shead <nathanieloshead@gmail.com>
Reviewed-by: Jason Merrill <jason@redhat.com>
(cherry picked from commit 0173dcce92baa62a74929814a75edb75eeab1a54)

9 months agotestsuite: arm: Use check-function-bodies in fp16-aapcs-* tests
Torbjörn SVENSSON [Sun, 20 Oct 2024 09:48:42 +0000 (11:48 +0200)] 
testsuite: arm: Use check-function-bodies in fp16-aapcs-* tests

Converted the tests to use check-function-bodies in order to ensure that
the sequence is correct.

gcc/testsuite/ChangeLog:

* gcc.target/arm/fp16-aapcs-1.c: Use check-function-bodies.
* gcc.target/arm/fp16-aapcs-2.c: Likewise.
* gcc.target/arm/fp16-aapcs-3.c: Likewise.
* gcc.target/arm/fp16-aapcs-4.c: Likewise.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
(cherry picked from commit 205515da82a2914d765e74ba73fd2765e1254112)

9 months agotestsuite: arm: Relax expected asm in bitfield* and union-2 tests
Torbjörn SVENSSON [Sun, 20 Oct 2024 08:28:32 +0000 (10:28 +0200)] 
testsuite: arm: Relax expected asm in bitfield* and union-2 tests

Below -O2, lsls/lsrs are prefered. For -O2 and above, lsl/lsr are
prefered.

gcc/testsuite/ChangeLog:

* gcc.target/arm/cmse/mainline/8_1m/bitfield-4.c: Allow lsl and
lsr instructions.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-6.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-8.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/bitfield-and-union.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/union-2.c: Likewise.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
(cherry picked from commit a79ca49b5ce0ad4738062572948e52485aa2da2b)

9 months agotestsuite: arm: Use check-function-bodies in cmse-5 tests
Torbjörn SVENSSON [Sun, 20 Oct 2024 09:20:43 +0000 (11:20 +0200)] 
testsuite: arm: Use check-function-bodies in cmse-5 tests

Converted the tests to use check-function-bodies in order to ensure that
the sequence is correct.
This also allows both APSR_nzcvq and APSR_nzcvqg as target selector does
not work when the -march and/or -mcpu overrides the target to test.

gcc/testsuite/ChangeLog:

* gcc.target/arm/cmse/mainline/8m/hard-sp/cmse-5.c: Use
check-function-bodies.
* gcc.target/arm/cmse/mainline/8m/hard/cmse-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8m/soft/cmse-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8m/softfp-sp/cmse-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8m/softfp/cmse-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard-sp/cmse-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/hard/cmse-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/soft/cmse-5.c: Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp-sp/cmse-5.c:
Likewise.
* gcc.target/arm/cmse/mainline/8_1m/softfp/cmse-5.c: Likewise.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
(cherry picked from commit 835ad52fbb9c8a0bb4e713deb6c99679d8b77d60)

9 months agotestsuite: Skip pr112305.c for -O[01] on simulators
Richard Sandiford [Tue, 22 Oct 2024 11:49:35 +0000 (12:49 +0100)] 
testsuite: Skip pr112305.c for -O[01] on simulators

gcc.dg/torture/pr112305.c contains an inner loop that executes
0x8000_0014 times and an outer loop that executes 5 times, giving about
10 billion total executions of the inner loop body.  At -O2 and above we
are able to remove the inner loop, but at -O1 we keep a no-op loop:

        dls     lr, r3
.L3:
        subs    r3, r3, #1
        le      lr, .L3

and at -O0 we of course don't optimise.

This can lead to long execution times on simulators, possibly
triggering a timeout.

gcc/testsuite
* gcc.dg/torture/pr112305.c: Skip at -O0 and -O1 for simulators.

(cherry picked from commit 4e80432c52a18b92899244e8ce3c243f560766a6)

9 months agolibstdc++: Implement LWG 3664 changes to ranges::distance
Patrick Palka [Sat, 5 Oct 2024 17:48:06 +0000 (13:48 -0400)] 
libstdc++: Implement LWG 3664 changes to ranges::distance

libstdc++-v3/ChangeLog:

* include/bits/ranges_base.h (__distance_fn::operator()):
Adjust iterator/sentinel overloads as per LWG 3664.
* testsuite/24_iterators/range_operations/distance.cc:
Test LWG 3664 example.

Reviewed-by: Jonathan Wakely <jwakely@redhat.com>
(cherry picked from commit 7c0d1e9f2a2f1d41d9eb755c36c871d92638c4b7)

9 months agolibstdc++/ranges: Implement various small LWG issues
Patrick Palka [Fri, 4 Oct 2024 14:01:39 +0000 (10:01 -0400)] 
libstdc++/ranges: Implement various small LWG issues

This implements the following small LWG issues:

  3848. adjacent_view, adjacent_transform_view and slide_view missing base accessor
  3851. chunk_view::inner-iterator missing custom iter_move and iter_swap
  3947. Unexpected constraints on adjacent_transform_view::base()
  4001. iota_view should provide empty
  4012. common_view::begin/end are missing the simple-view check
  4013. lazy_split_view::outer-iterator::value_type should not provide default constructor
  4035. single_view should provide empty
  4053. Unary call to std::views::repeat does not decay the argument
  4054. Repeating a repeat_view should repeat the view

libstdc++-v3/ChangeLog:

* include/std/ranges (single_view::empty): Define as per LWG 4035.
(iota_view::empty): Define as per LWG 4001.
(lazy_split_view::_OuterIter::value_type): Remove default
constructor and make other constructor private as per LWG 4013.
(common_view::begin): Disable non-const overload for simple
views as per LWG 4012.
(common_view::end): Likewise.
(adjacent_view::base): Define as per LWG 3848.
(adjacent_transform_view::base): Likewise.
(chunk_view::_InnerIter::iter_move): Define as per LWG 3851.
(chunk_view::_InnerIter::itep_swap): Likewise.
(slide_view::base): Define as per LWG 3848.
(repeat_view): Adjust deduction guide as per LWG 4053.
(_Repeat::operator()): Adjust single-parameter overload as per
LWG 4054.
* testsuite/std/ranges/adaptors/adjacent/1.cc: Verify existence
of base member function.
* testsuite/std/ranges/adaptors/adjacent_transform/1.cc: Likewise.
* testsuite/std/ranges/adaptors/chunk/1.cc: Test LWG 3851 example.
* testsuite/std/ranges/adaptors/slide/1.cc: Verify existence of
base member function.
* testsuite/std/ranges/iota/iota_view.cc: Test LWG 4001 example.
* testsuite/std/ranges/repeat/1.cc: Test LWG 4053/4054 examples.

Reviewed-by: Jonathan Wakely <jwakely@redhat.com>
(cherry picked from commit 20165d0107abd0f839f2519818b904f029f4ae55)

9 months agolibstdc++: Add some missing ranges feature-test macro tests
Patrick Palka [Thu, 22 Aug 2024 15:25:10 +0000 (11:25 -0400)] 
libstdc++: Add some missing ranges feature-test macro tests

libstdc++-v3/ChangeLog:

* testsuite/25_algorithms/contains/1.cc: Verify value of
__cpp_lib_ranges_contains.
* testsuite/25_algorithms/find_last/1.cc: Verify value of
__cpp_lib_ranges_find_last.
* testsuite/25_algorithms/iota/1.cc: Verify value of
__cpp_lib_ranges_iota.

Reviewed-by: Jonathan Wakely <jwakely@redhat.com>
(cherry picked from commit 8e0da56f18b3678beee9d2bae27e08a0e122573a)