Robin Dapp [Mon, 22 May 2023 18:41:59 +0000 (20:41 +0200)]
RISC-V: Allow all const_vec_duplicates as constants.
As we can always broadcast an integer constant to a vector register
allow them in riscv_const_insns. We need as many instructions as
it takes to generate the constant and one vmv.vx.
liuhongt [Mon, 6 Mar 2023 07:35:37 +0000 (15:35 +0800)]
Detect bswap + rotate for byte permutation in pass_bswap.
The patch doesn't handle:
1. cast64_to_32,
2. memory source with rsize < range.
gcc/ChangeLog:
PR middle-end/108938
* gimple-ssa-store-merging.cc (is_bswap_or_nop_p): New
function, cut from original find_bswap_or_nop function.
(find_bswap_or_nop): Add a new parameter, detect bswap +
rotate and save rotate result in the new parameter.
(bswap_replace): Add a new parameter to indicate rotate and
generate rotate stmt if needed.
(maybe_optimize_vector_constructor): Adjust for new rotate
parameter in the upper 2 functions.
(pass_optimize_bswap::execute): Ditto.
(imm_store_chain_info::output_merged_store): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr108938-1.c: New test.
* gcc.target/i386/pr108938-2.c: New test.
* gcc.target/i386/pr108938-3.c: New test.
* gcc.target/i386/pr108938-load-1.c: New test.
* gcc.target/i386/pr108938-load-2.c: New test.
Kyrylo Tkachov [Tue, 30 May 2023 09:41:02 +0000 (10:41 +0100)]
aarch64: Convert ADDLP and ADALP patterns to standard RTL codes
This patch converts the patterns for the integer widen and pairwise-add instructions
to standard RTL operations. The pairwise addition withing a vector can be represented
as an addition of two vec_selects, one selecting the even elements, and one selecting odd.
Thus for the intrinsic vpaddlq_s8 we can generate:
(set (reg:V8HI 92)
(plus:V8HI (vec_select:V8HI (sign_extend:V16HI (reg/v:V16QI 93 [ a ]))
(parallel [
(const_int 0 [0])
(const_int 2 [0x2])
(const_int 4 [0x4])
(const_int 6 [0x6])
(const_int 8 [0x8])
(const_int 10 [0xa])
(const_int 12 [0xc])
(const_int 14 [0xe])
]))
(vec_select:V8HI (sign_extend:V16HI (reg/v:V16QI 93 [ a ]))
(parallel [
(const_int 1 [0x1])
(const_int 3 [0x3])
(const_int 5 [0x5])
(const_int 7 [0x7])
(const_int 9 [0x9])
(const_int 11 [0xb])
(const_int 13 [0xd])
(const_int 15 [0xf])
]))))
Similarly for the accumulating forms where there's an extra outer PLUS for the accumulation.
We already have the handy helper functions aarch64_stepped_int_parallel_p and
aarch64_gen_stepped_int_parallel defined in aarch64.cc that we can make use of to define
the right predicate for the VEC_SELECT PARALLEL.
This patch allows us to remove some code iterators and the UNSPEC definitions for SADDLP and UADDLP.
UNSPEC_UADALP and UNSPEC_SADALP are retained because they are used by SVE2 patterns still.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_<sur>adalp<mode>): Delete.
(aarch64_<su>adalp<mode>): New define_expand.
(*aarch64_<su>adalp<mode><vczle><vczbe>_insn): New define_insn.
(aarch64_<su>addlp<mode>): Convert to define_expand.
(*aarch64_<su>addlp<mode><vczle><vczbe>_insn): New define_insn.
* config/aarch64/iterators.md (UNSPEC_SADDLP, UNSPEC_UADDLP): Delete.
(ADALP): Likewise.
(USADDLP): Likewise.
* config/aarch64/predicates.md (vect_par_cnst_even_or_odd_half): Define.
Kyrylo Tkachov [Tue, 30 May 2023 09:36:46 +0000 (10:36 +0100)]
aarch64: Reimplement v(r)hadd and vhsub intrinsics with RTL codes
This patch reimplements the MD patterns for the UHADD,SHADD,UHSUB,SHSUB,URHADD,SRHADD instructions using
standard RTL operations rather than unspecs. The correct RTL representations involves widening
the inputs before adding them and halving, followed by a truncation back to the original mode.
An unfortunate wart in the patch is that we end up having very similar expanders for the intrinsics
through the aarch64_<su>h<ADDSUB:optab><mode> and aarch64_<su>rhadd<mode> names and the standard names
for the vector averaging optabs <su>avg<mode>3_floor and <su>avg<mode>3_ceil.
I'd like to reuse <su>avg<mode>3_ceil for the intrinsics builtin as well but our scheme
in aarch64-simd-builtins.def and aarch64-builtins.cc makes it awkward by only allowing mappings
of entries in aarch64-simd-builtins.def to:
0 - CODE_FOR_aarch64_<name><mode>
1-9 - CODE_FOR_<name><mode><1-9>
10 - CODE_FOR_<name><mode>
whereas here we want a string after the <mode> i.e. CODE_FOR_uavg<mode>3_ceil.
This patch adds a bit of remapping logic in aarch64-builtins.cc before the construction of the
builtin info that remaps the CODE_FOR_* definitions in aarch64-simd-builtins.def to the
optab-derived ones. CODE_FOR_aarch64_srhaddv4si gets remapped to CODE_FOR_avgv4si3_ceil, for example.
It's a bit specific to this case, but this solution requires the least invasive changes while avoiding
having duplicate expanders just for the sake of a different pattern name.
Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
gcc/ChangeLog:
* config/aarch64/aarch64-builtins.cc (VAR1): Move to after inclusion of
aarch64-builtin-iterators.h. Add definition to remap shadd, uhadd,
srhadd, urhadd builtin codes for standard optab ones.
* config/aarch64/aarch64-simd.md (<u>avg<mode>3_floor): Rename to...
(<su_optab>avg<mode>3_floor): ... This. Expand to RTL codes rather than
unspec.
(<u>avg<mode>3_ceil): Rename to...
(<su_optab>avg<mode>3_ceil): ... This. Expand to RTL codes rather than
unspec.
(aarch64_<su>hsub<mode>): New define_expand.
(aarch64_<sur>h<addsub><mode><vczle><vczbe>): Split into...
(*aarch64_<su>h<ADDSUB:optab><mode><vczle><vczbe>_insn): ... This...
(*aarch64_<su>rhadd<mode><vczle><vczbe>_insn): ... And this.
Kyrylo Tkachov [Tue, 30 May 2023 08:56:29 +0000 (09:56 +0100)]
stor-layout, aarch64: Express SRA intrinsics with RTL codes
This patch expresses the intrinsics for the SRA and RSRA instructions with
standard RTL codes rather than relying on UNSPECs.
These instructions perform a vector shift right plus accumulate with an
optional rounding constant addition for the RSRA variant.
There are a number of interesting points:
* The scalar-in-SIMD-registers variant for DImode SRA e.g. ssra d0, d1, #N
is left using the UNSPECs. Expressing it as a DImode plus+shift led to all
kinds of trouble as it started matching the existing define_insns for
"add x0, x0, asr #N" instructions and adding the SRA form as an extra
alternative required a significant amount of deduplication of iterators and
things still didn't work out well. I decided not to tackle that case in
this patch. It can be attempted later.
* For the RSRA variants that add a rounding constant (1 << (shift-1)) the
addition is notionally performed in a wider mode than the input types so that
overflow is handled properly. In RTL this can be represented with an appropriate
extend operation followed by a truncate back to the original modes.
However for 128-bit input modes such as V4SI we don't have appropriate modes
defined for this widening i.e. we'd need a V4DI mode to represent the
intermediate widened result. This patch defines such modes for
V16HI,V8SI,V4DI,V2TI. These will come handy in the future too as we have
more Advanced SIMD instruction that have similar intermediate widening
semantics.
* The above new modes led to a problem with stor-layout.cc. The new modes only
exist for the sake of the RTL optimisers understanding the semantics of the
instruction but are not indended to be moved to and from register or memory,
assigned to types, used as TYPE_MODE or participate in auto-vectorisation.
This is expressed in aarch64 by aarch64_classify_vector_mode returning zero
for these new modes. However, the code in stor-layout.cc:<mode_for_vector>
explicitly doesn't check this when picking a TYPE_MODE due to modes being made
potentially available later through target switching (PR38240).
This led to these modes being picked as TYPE_MODE for declarations such as:
typedef int16_t vnx8hi __attribute__((vector_size (32))) when 256-bit
fixed-length SVE modes are available and vector_type_mode later struggling
to rectify this.
This issue is addressed with the new target hook
TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P that is intended to check if a
vector mode can be used in any legal target attribute configuration of the
port, as opposed to the existing TARGET_VECTOR_MODE_SUPPORTED_P that checks
only the initial target configuration. This allows a simple adjustment in
stor-layout.cc that still disqualifies these limited modes early on while
allowing consideration of modes that can be turned on in the future with
target attributes.
Bootstrapped and tested on aarch64-none-linux-gnu.
gcc/ChangeLog:
* config/aarch64/aarch64-modes.def (V16HI, V8SI, V4DI, V2TI): New modes.
* config/aarch64/aarch64-protos.h (aarch64_const_vec_rnd_cst_p):
Declare prototype.
(aarch64_const_vec_rsra_rnd_imm_p): Likewise.
* config/aarch64/aarch64-simd.md (*aarch64_simd_sra<mode>): Rename to...
(aarch64_<sra_op>sra_n<mode>_insn): ... This.
(aarch64_<sra_op>rsra_n<mode>_insn): New define_insn.
(aarch64_<sra_op>sra_n<mode>): New define_expand.
(aarch64_<sra_op>rsra_n<mode>): Likewise.
(aarch64_<sur>sra_n<mode>): Rename to...
(aarch64_<sur>sra_ndi): ... This.
* config/aarch64/aarch64.cc (aarch64_classify_vector_mode): Add
any_target_p argument.
(aarch64_extract_vec_duplicate_wide_int): Define.
(aarch64_const_vec_rsra_rnd_imm_p): Likewise.
(aarch64_const_vec_rnd_cst_p): Likewise.
(aarch64_vector_mode_supported_any_target_p): Likewise.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
* config/aarch64/iterators.md (UNSPEC_SRSRA, UNSPEC_URSRA): Delete.
(VSRA): Adjust for the above.
(sur): Likewise.
(V2XWIDE): New mode_attr.
(vec_or_offset): Likewise.
(SHIFTEXTEND): Likewise.
* config/aarch64/predicates.md (aarch64_simd_rsra_rnd_imm_vec): New
predicate.
* doc/tm.texi (TARGET_VECTOR_MODE_SUPPORTED_P): Adjust description to
clarify that it applies to current target options.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Document.
* doc/tm.texi.in: Regenerate.
* stor-layout.cc (mode_for_vector): Check
vector_mode_supported_any_target_p when iterating through vector modes.
* target.def (TARGET_VECTOR_MODE_SUPPORTED_P): Adjust description to
clarify that it applies to current target options.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Define.
Eric Botcazou [Fri, 7 Apr 2023 16:03:16 +0000 (18:03 +0200)]
ada: Fix internal error on qualified aggregate with storage model
It comes from a small oversight in get_storage_model_access.
gcc/ada/
* gcc-interface/trans.cc (node_is_component): Remove parentheses.
(node_is_type_conversion): New predicate.
(get_atomic_access): Use it.
(get_storage_model_access): Likewise and look into the parent to
find a component if it returns true.
(present_in_lhs_or_actual_p): Likewise.
Eric Botcazou [Fri, 7 Apr 2023 13:51:16 +0000 (15:51 +0200)]
ada: Add missing guards for degenerate storage models
gcc/ada/
* gcc-interface/trans.cc (Attribute_to_gnu) <Attr_Size>: Check that
the storage model has Copy_From before instantiating loads for it.
<Attr_Length>: Likewise.
<Attr_Bit_Position>: Likewise.
(gnat_to_gnu) <N_Indexed_Component>: Likewise.
<N_Slice>: Likewise.
Marc Poulhiès [Mon, 3 Apr 2023 14:36:13 +0000 (16:36 +0200)]
ada: Fix incorrect copies being used with 'Address
When using 'Address on an object with a size clause, gigi would end up
creating a copy and using its address instead of the one of the original
object, leading to incorrect behavior. Remove the conversion (that
triggers the copy) when 'Address is applied to a declaration.
gcc/ada/
* gcc-interface/trans.cc (Attribute_to_gnu): Also strip conversion
in case of DECL.
Eric Botcazou [Mon, 13 Mar 2023 22:01:54 +0000 (23:01 +0100)]
ada: Fix bogus Storage_Error on dynamic array with static zero length
This works around the limitations present for the support of arrays in the
middle-end by clearing the TREE_OVERFLOW flag for arrays with zero length.
gcc/ada/
* gcc-interface/decl.cc (gnat_to_gnu_entity) <E_Array_Type>: Use a
local variable for the GNAT index type.
<E_Array_Subtype>: Likewise. Call Is_Null_Range on the bounds and
force the zero on TYPE_SIZE and TYPE_SIZE_UNIT if it returns true.
Eric Botcazou [Wed, 22 Feb 2023 16:22:11 +0000 (17:22 +0100)]
ada: Minor generic tweaks left and and right
No functional changes.
gcc/ada/
* gcc-interface/decl.cc (gnat_to_gnu_entity) <E_Variable>: Replace
integer_zero_node with null_pointer_node for pointer types.
* gcc-interface/trans.cc (gnat_gimplify_expr) <NULL_EXPR>: Likewise.
* gcc-interface/utils.cc (maybe_pad_type): Do not attempt to make a
packable type from a fat pointer type.
* gcc-interface/utils2.cc (build_atomic_load): Use a local variable.
(build_atomic_store): Likewise.
Eric Botcazou [Wed, 25 Jan 2023 14:59:19 +0000 (15:59 +0100)]
ada: Adjust again the implementation of storage models
The code generator must now be prepared to translate assignment statements
to objects allocated with a storage model and that are not initialized yet.
gcc/ada/
* gcc-interface/trans.cc (Attribute_to_gnu) <Attr_Size>: Tweak.
(gnat_to_gnu) <N_Assignment_Statement>: Declare a local variable.
For a target with a storage model, use the Actual_Designated_Subtype
to compute the size if it is present.
Eric Botcazou [Tue, 24 Jan 2023 09:26:00 +0000 (10:26 +0100)]
ada: Simplify the implementation of storage models
As the additional temporaries required by the semantics of nonnative storage
models are now created by the front-end, in particular for actual parameters
and assignment statements, the corresponding code in gigi can be removed.
gcc/ada/
* gcc-interface/trans.cc (Call_to_gnu): Remove code implementing the
by-copy semantics for actuals with nonnative storage models.
(gnat_to_gnu) <N_Assignment_Statement>: Remove code instantiating a
temporary for assignments between nonnative storage models.
Eric Botcazou [Wed, 18 Jan 2023 23:37:18 +0000 (00:37 +0100)]
ada: Make use of Cannot_Be_Superflat flag on N_Range nodes
gcc/ada/
* gcc-interface/decl.cc (range_cannot_be_superflat): Return true
immediately if Cannot_Be_Superflat is set.
* gcc-interface/misc.cc (gnat_post_options): Do not override the
-Wstringop-overflow setting.
Eric Botcazou [Mon, 17 Apr 2023 13:19:06 +0000 (15:19 +0200)]
ada: Small cleanups and fixes in expansion of aggregates
This streamlines the handling of qualified expressions in the expansion of
aggregates and plugs a couple of loopholes that may cause memory leaks.
gcc/ada/
* exp_aggr.adb (Build_Array_Aggr_Code): Move the declaration of Typ
to the beginning.
(Initialize_Array_Component): Test the unqualified version of the
expression for the nested array case.
(Initialize_Ctrl_Array_Component): Do not duplicate the expression
here. Do the pattern matching of the unqualified version of it.
(Gen_Assign): Call Unqualify to compute Expr_Q and use Expr_Q in
subsequent pattern matching.
(Initialize_Ctrl_Record_Component): Do the pattern matching of the
unqualified version of the aggregate.
(Build_Record_Aggr_Code): Call Unqualify.
(Convert_Aggr_In_Assignment): Likewise.
(Convert_Aggr_In_Object_Decl): Likewise.
(Component_OK_For_Backend): Likewise.
(Is_Delayed_Aggregate): Likewise.
Eric Botcazou [Wed, 12 Apr 2023 17:49:05 +0000 (19:49 +0200)]
ada: Fix wrong expansion of array aggregate with noncontiguous choices
This extends an earlier fix done for the others choice of an array aggregate
to all the choices of the aggregate, since the same sharing issue may happen
when the choices are not contiguous.
gcc/ada/
* exp_aggr.adb (Build_Array_Aggr_Code.Get_Assoc_Expr): Duplicate the
expression here instead of...
(Build_Array_Aggr_Code): ...here.
Eric Botcazou [Fri, 14 Apr 2023 09:14:47 +0000 (11:14 +0200)]
ada: Fix internal error on array constant in expression function
This happens when the peculiar check emitted by Check_Large_Modular_Array
is applied to an object whose actual subtype is an itype with dynamic size,
because the first reference to the itype in the expanded code may turn out
to be within the raise statement, which is problematic for the eloboration
of this itype by the code generator at library level.
gcc/ada/
* freeze.adb (Check_Large_Modular_Array): Fix head comment, use
Standard_Long_Long_Integer_Size directly and generate a reference
just before the raise statement if the Etype of the object is an
itype declared in an open scope.
Eric Botcazou [Thu, 13 Apr 2023 21:11:38 +0000 (23:11 +0200)]
ada: Fix fallout of recent fix for missing finalization
The original fix makes it possible to create transient scopes around return
statements in more cases, but it overlooks that transient scopes are reused
and, in particular, that they can be promoted to secondary stack management.
gcc/ada/
* exp_ch7.adb (Find_Enclosing_Transient_Scope): Return the index in
the scope table instead of the scope's entity.
(Establish_Transient_Scope): If an enclosing scope already exists,
do not set the Uses_Sec_Stack flag on it if the node to be wrapped
is a return statement which requires secondary stack management.
Joel Brobecker [Wed, 12 Apr 2023 15:03:55 +0000 (08:03 -0700)]
ada: Add System.Traceback.Symbolic.Module_Name support on AArch64 Linux
This commit changes the runtime on aarch64-linux to use the Linux
version of s-tsmona.adb, so as to add support for this functionality
on aarch64-linux.
gcc/ada/
* Makefile.rtl: Use libgnat/s-tsmona__linux.adb on
aarch64-linux. Link libgnat with -ldl, as the use of
s-tsmona__linux.adb requires it.
Piotr Trojanek [Tue, 11 Apr 2023 22:19:23 +0000 (00:19 +0200)]
ada: Only build access-to-subprogram wrappers when expander is active
For access-to-subprogram types with Pre/Post aspects we create a wrapper
routine that evaluates these aspects. Spec of this wrapper was created
always, while its body was only created when expansion was enabled.
Now we only create these wrappers when expansion is enabled. In
particular, we don't create them in GNATprove mode; instead, GNATprove
picks the Pre/Post expressions directly from the aspects.
gcc/ada/
* exp_ch3.adb
(Build_Access_Subprogram_Wrapper_Body): Build wrapper body if requested
by routine that builds wrapper spec.
* sem_ch3.adb
(Analyze_Full_Type_Declaration): Only build wrapper when expander is
active.
(Build_Access_Subprogram_Wrapper):
Remove special-case for GNATprove.
ada: Ensure Default_Stack_Size is greater than Minimum_Stack_Size
The Default_Stack_Size function does not check that the binder specified
default stack size is greater than the minimum stack size for the runtime.
This can result in tasks using default stack sizes less than the minimum
stack size because the Adjust_Storage_Size only adjusts storages sizes for
tasks that explicitly specify a storage size. To avoid this, the binder
specified default stack size is round up to the minimum stack size if
required.
gcc/ada/
* libgnat/s-parame.adb: Check that Default_Stack_Size >=
Minimum_Stack_size.
* libgnat/s-parame__rtems.adb: Ditto.
* libgnat/s-parame__vxworks.adb: Check that Default_Stack_Size >=
Minimum_Stack_size and use the proper Minimum_Stack_Size if
Stack_Check_Limits is enabled.
Eric Botcazou [Tue, 11 Apr 2023 10:15:22 +0000 (12:15 +0200)]
ada: Fix visibility error with DIC or Type_Invariant aspect on generic type
The compiler fails to capture global references during the analysis of the
aspect on the generic type because it analyzes a copy of the expression.
gcc/ada/
* exp_util.adb (Build_DIC_Procedure_Body.Add_Own_DIC): When inside
a generic unit, preanalyze the expression directly.
(Build_Invariant_Procedure_Body.Add_Own_Invariants): Likewise.
Lili Cui [Tue, 30 May 2023 05:47:47 +0000 (05:47 +0000)]
Handle FMA friendly in reassoc pass
Make some changes in reassoc pass to make it more friendly to fma pass later.
Using FMA instead of mult + add reduces register pressure and insruction
retired.
There are mainly two changes
1. Put no-mult ops and mult ops alternately at the end of the queue, which is
conducive to generating more fma and reducing the loss of FMA when breaking
the chain.
2. Rewrite the rewrite_expr_tree_parallel function to try to build parallel
chains according to the given correlation width, keeping the FMA chance as
much as possible.
With the patch applied
On ICX:
507.cactuBSSN_r: Improved by 1.7% for multi-copy .
503.bwaves_r : Improved by 0.60% for single copy .
507.cactuBSSN_r: Improved by 1.10% for single copy .
519.lbm_r : Improved by 2.21% for single copy .
no measurable changes for other benchmarks.
On aarch64
507.cactuBSSN_r: Improved by 1.7% for multi-copy.
503.bwaves_r : Improved by 6.00% for single-copy.
no measurable changes for other benchmarks.
TEST1:
float
foo (float a, float b, float c, float d, float *e)
{
return *e + a * b + c * d ;
}
For "-Ofast -mfpmath=sse -mfma" GCC generates:
vmulss %xmm3, %xmm2, %xmm2
vfmadd132ss %xmm1, %xmm2, %xmm0
vaddss (%rdi), %xmm0, %xmm0
ret
With this patch GCC generates:
vfmadd213ss (%rdi), %xmm1, %xmm0
vfmadd231ss %xmm2, %xmm3, %xmm0
ret
Juzhe-Zhong [Tue, 30 May 2023 02:20:19 +0000 (10:20 +0800)]
RISC-V: Add floating-point to integer conversion RVV auto-vectorization support
Even though we can't support floating-point operations which are
depending
on FRM yet, (for example vfadd support is blocked) since the RVV
intrinsic doc is not updated
and we can't support mode switching for this.
We can support floating-point to integer conversion now since it's not
depending on FRM and
we don't need mode switching support for this ('rtz' conversions
independent FRM).
* config/riscv/autovec.md (<optab><mode><vconvert>2): New pattern.
* config/riscv/iterators.md: New attribute.
* config/riscv/vector-iterators.md: New attribute.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv32gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-rv64gcv.c: New test.
* gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-template.h: New test.
Notice there is warning:
../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning:
comparison between signed and unsigned integer expressions
[-Wsign-compare]
if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning:
comparison between signed and unsigned integer expressions
[-Wsign-compare]
else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
../../../riscv-gcc/gcc/config/riscv/riscv.md: In function ‘rtx_def*
gen_anddi3(rtx, rtx, rtx)’:
../../../riscv-gcc/gcc/config/riscv/riscv.md:1356:32: warning:
comparison between signed and unsigned integer expressions
[-Wsign-compare]
if (INTVAL (operands[2]) == GET_MODE_MASK (HImode))
../../../riscv-gcc/gcc/config/riscv/riscv.md:1358:37: warning:
comparison between signed and unsigned integer expressions
[-Wsign-compare]
else if (INTVAL (operands[2]) == GET_MODE_MASK (SImode))
* config/riscv/autovec.md (fnma<mode>4): New pattern.
(*fnma<mode>): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: New test.
before patch:
ConEmv_imm_imm_reg:
addi a5,a0,-1000
li a0,10
th.mvnez a0,zero,a5
th.mveqz a1,zero,a5
or a0,a0,a1
ret
after patch:
ConEmv_imm_imm_reg:
addi a5,a0,-1000
li a0,10
th.mvnez a0,a1,a5
ret
Signed-off-by: Die Li <lidie@eswincomputing.com>
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_conditional_move_onesided):
Delete.
(riscv_expand_conditional_move): Reuse the TARGET_SFB_ALU expand
process for TARGET_XTHEADCONDMOV
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadcondmov-indirect-rv32.c: Update the output.
* gcc.target/riscv/xtheadcondmov-indirect-rv64.c: Likewise.
Jivan Hakobyan [Mon, 29 May 2023 13:55:29 +0000 (07:55 -0600)]
RISC-V: Use extension instructions instead of bitwise "and"
In the case where the target supports extension instructions,
it is preferable to use that instead of doing the same in other ways.
For the following case
void foo (unsigned long a, unsigned long* ptr) {
ptr[0] = a & 0xffffffffUL;
ptr[1] &= 0xffffffffUL;
}
GCC generates
foo:
li a5,-1
srli a5,a5,32
and a0,a0,a5
sd a0,0(a1)
ld a4,8(a1)
and a5,a4,a5
sd a5,8(a1)
ret
but it will be profitable to generate this one
foo:
zext.w a0,a0
sd a0,0(a1)
lwu a5,8(a1)
sd a5,8(a1)
ret
This patch fixes mentioned issue.
It supports HI -> DI, HI->SI and SI -> DI extensions.
gcc/ChangeLog:
* config/riscv/riscv.md (and<mode>3): New expander.
(*and<mode>3) New pattern.
* config/riscv/predicates.md (arith_operand_or_mode_mask): New
predicate.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/and-extend-1.c: New test
* gcc.target/riscv/and-extend-2.c: New test
Pan Li [Thu, 25 May 2023 02:58:49 +0000 (10:58 +0800)]
RISC-V: Using merge approach to optimize repeating sequence in vec_init
This patch would like to optimize the VLS vector initialization like
repeating sequence. From the vslide1down to the vmerge with a simple
cost model, aka every instruction only has 1 cost.
Given code with -march=rv64gcv_zvl256b --param riscv-autovec-preference=fixed-vlmax
typedef int64_t vnx32di __attribute__ ((vector_size (256)));
__attribute__ ((noipa)) void
f_vnx32di (int64_t a, int64_t b, int64_t *out)
{
vnx32di v = {
a, b, a, b, a, b, a, b,
a, b, a, b, a, b, a, b,
a, b, a, b, a, b, a, b,
a, b, a, b, a, b, a, b,
};
*(vnx32di *) out = v;
}
Before this patch:
vslide1down.vx (x31 times)
After this patch:
li a5,-1431654400
addi a5,a5,-1365
li a3,-1431654400
addi a3,a3,-1366
slli a5,a5,32
add a5,a5,a3
vsetvli a4,zero,e64,m8,ta,ma
vmv.v.x v8,a0
vmv.s.x v0,a5
vmerge.vxm v8,v8,a1,v0
vs8r.v v8,0(a2)
Since we dont't have SEW = 128 in vec_duplicate, we can't combine ab into
SEW = 128 element and then broadcast this big element.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (enum insn_type): New type.
* config/riscv/riscv-v.cc (RVV_INSN_OPERANDS_MAX): New macro.
(rvv_builder::can_duplicate_repeating_sequence_p): Align the referenced
class member.
(rvv_builder::get_merged_repeating_sequence): Ditto.
(rvv_builder::repeating_sequence_use_merge_profitable_p): New function
to evaluate the optimization cost.
(rvv_builder::get_merge_scalar_mask): New function to get the merge
mask.
(emit_scalar_move_insn): New function to emit vmv.s.x.
(emit_vlmax_integer_move_insn): New function to emit vlmax vmv.v.x.
(emit_nonvlmax_integer_move_insn): New function to emit nonvlmax
vmv.v.x.
(get_repeating_sequence_dup_machine_mode): New function to get the dup
machine mode.
(expand_vector_init_merge_repeating_sequence): New function to perform
the optimization.
(expand_vec_init): Add this vector init optimization.
* config/riscv/riscv.h (BITS_PER_WORD): New macro.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c: New test.
Martin Jambor [Mon, 29 May 2023 09:51:28 +0000 (11:51 +0200)]
MAINTAINERS file: Replace spaces with tabs
This change, separating Benjamin's name and email address with tabs
rather than spaces, makes contrib/check-MAINTAINERS.py script happy
about our MAINTAINERS file again.
Eric Botcazou [Mon, 29 May 2023 07:45:57 +0000 (09:45 +0200)]
Fix artificial overflow during GENERIC folding
The Ada compiler gives a bogus warning:
storage_offset1.ads:16:52: warning: Constraint_Error will be raised at run
time [enabled by default]
Ironically enough, this occurs because of an intermediate conversion to an
unsigned type which is supposed to hide overflows but is counter-productive
for constants because TREE_OVERFLOW is always set for them, so it ends up
setting a bogus TREE_OVERFLOW when converting back to the original type.
The fix simply redirects INTEGER_CSTs to the other, direct path without the
intermediate conversion to the unsigned type.
gcc/
* match.pd ((T)P - (T)(P + A) -> -(T) A): Avoid artificial overflow
on constants.
gcc/testsuite/
* gnat.dg/specs/storage_offset1.ads: New test.
Cedric Landet [Fri, 31 Mar 2023 12:05:37 +0000 (14:05 +0200)]
ada: Set g-spogwa as a GNATRTL_SOCKETS_OBJS
g-spogwa.adb is the body of the procedure GNAT.Sockets.Poll.G_Wait.
This is a socket specific procedure. It should only be built for
systems that support sockets.
gcc/ada/
* Makefile.rtl: Move g-spogwa$(objext) from GNATRTL_NONTASKING_OBJS
to GNATRTL_SOCKETS_OBJS
Eric Botcazou [Sat, 8 Apr 2023 16:29:16 +0000 (18:29 +0200)]
ada: Fix memory leak in expression function returning Big_Integer
We fail to establish a transient scope around the return statement because
the function returns a controlled type, but this is no longer problematic
because controlled types are no longer returned on the secondary stack.
gcc/ada/
* exp_ch7.adb (Establish_Transient_Scope.Find_Transient_Context):
Bail out for a simple return statement only if the transient scope
and the function both require secondary stack management, or else
if the function is a thunk.
* sem_res.adb (Resolve_Call): Do not create a transient scope when
the call is the expression of a simple return statement.
ada: Use Code_Address attribute to determine subprogram addresses
The runtime used label addresses to determine the code address of
subprograms because the subprogram's canonical address on some targets
is a descriptor or a stub. Simplify the code by using the Code_Address
attribute instead, which is designed to return the code address of a
subprogram. This also works around a current GNAT-LLVM limitation where
the address of a label is incorrectly calculated when using -O1. As a
result, we can now build a-except.adb and g-debpoo.adb at -O1 again with
GNAT-LLVM.
gcc/ada/
* libgnat/a-excach.adb (Call_Chain): Replace
Code_Address_For_AAA/ZZZ functions with AAA/ZZZ'Code_Address.
* libgnat/a-except.adb (Code_Address_For_AAA/ZZZ): Delete.
(AAA/ZZZ): New null procedures.
* libgnat/g-debpoo.adb
(Code_Address_For_Allocate_End): Delete.
(Code_Address_For_Deallocate_End): Delete.
(Code_Address_For_Dereference_End): Delete.
(Allocate): Remove label and use Code_Address attribute to
determine subprogram addresses.
(Dellocate): Likewise.
(Dereference): Likewise.
(Allocate_End): Convert to null procedure.
(Dellocate_End): Likewise.
(Dereference_End): Likewise.
Eric Botcazou [Sat, 8 Apr 2023 10:43:54 +0000 (12:43 +0200)]
ada: Call idiomatic routine in Expand_Simple_Function_Return
In the primary stack case, Insert_Actions is invoked when the expression is
being rewritten, whereas Insert_List_Before_And_Analyze is invoked in the
secondary stack case. The former is idiomatic, the latter is not.
gcc/ada/
* exp_ch6.adb (Expand_Simple_Function_Return): Call Insert_Actions
consistently when rewriting the expression.
Eric Botcazou [Fri, 7 Apr 2023 17:17:20 +0000 (19:17 +0200)]
ada: Fix wrong finalization for loop on indexed container
The problem is that a transient temporary created for the constant indexing
of the container is finalized almost immediately after its creation.
gcc/ada/
* exp_util.adb (Is_Finalizable_Transient.Is_Indexed_Container):
New predicate to detect a temporary created to hold the result of
a constant indexing on a container.
(Is_Finalizable_Transient.Is_Iterated_Container): Adjust a couple
of obsolete comments.
(Is_Finalizable_Transient): Return False if Is_Indexed_Container
returns True on the object.
Eric Botcazou [Fri, 7 Apr 2023 07:16:12 +0000 (09:16 +0200)]
ada: Fix bogus error on conditional expression with only user-defined literals
This implements the recursive resolution of conditional expressions whose
dependent expressions are (all) user-defined literals the same way it is
implemented for operators.
gcc/ada/
* sem_res.adb (Has_Applicable_User_Defined_Literal): Make it clear
that the predicate also checks the node itself.
(Try_User_Defined_Literal): Move current implementation to...
Deal only with literals, named numbers and conditional expressions
whose dependent expressions are literals or named numbers.
(Try_User_Defined_Literal_For_Operator): ...this. Remove multiple
return False statements and put a single one at the end.
(Resolve): Call Try_User_Defined_Literal instead of directly
Has_Applicable_User_Defined_Literal for all nodes. Call
Try_User_Defined_Literal_For_Operator for operator nodes.
Piotr Trojanek [Fri, 7 Apr 2023 11:55:09 +0000 (13:55 +0200)]
ada: Fix crash on semi-recursive call in access-to-subprogram contract
Calls to access-to-subprogram from its own pre/post aspects are rejected
as illegal, e.g.:
type F is access function (X : Natural) return Boolean with
Pre => F.all (X);
but they caused an assertion failure in detection of recursive calls.
Now they are properly recognized as recursive, but the error is
suppressed, because it has been already posted at the call node.
gcc/ada/
* sem_res.adb (Invoked_With_Different_Arguments): Use Get_Called_Entity,
which properly deals with calls via an access-to-subprogram; fix
inconsistent use of a Call object declared in enclosing subprogram.
Piotr Trojanek [Sun, 2 Apr 2023 12:47:49 +0000 (14:47 +0200)]
ada: Attach pre/post on access-to-subprogram to internal subprogram type
Aspects Pre/Post that annotate access-to-subprogram type were attached
to the source entity (whose kind is either E_Access_Subprogram_Type or
E_Access_Protected_Subprogram_Type). However, it is more convenient to
attach them to the internal entity (whose kind is E_Subprogram_Type), so
that both Pre/Post aspects and First_Formal/Next_Formal chain are
attached to the same entity, just like for ordinary subprograms.
The drawback of having the Post aspect attached to an internal entity is
that name in prefixes of attribute Result no longer match the name of
entity where this Post aspect is attached. However, currently there is
no code that relies on this matching and, in general, there are fewer
routines that deal with attribute Result so they are easier to adapt
than the code that queries the Pre/Post aspects.
gcc/ada/
* contracts.adb
(Add_Pre_Post_Condition): Attach pre/post aspects to E_Subprogram_Type
entity.
(Analyze_Entry_Or_Subprogram_Contract): Adapt to use full type
declaration for a contract attached to E_Subprogram_Type entity.
* sem_prag.adb
(Analyze_Pre_Post_Condition): Add pre/post aspects to the designed type.
Piotr Trojanek [Wed, 5 Apr 2023 21:55:30 +0000 (23:55 +0200)]
ada: Cleanup detection of type support subprogram entities
Avoid repeated calls to Get_TSS_Name. Code cleanup related to handling
of dispatching operations in GNATprove; semantics is unaffected.
gcc/ada/
* exp_aggr.adb (Convert_Aggr_In_Allocator): Replace Get_TSS_Name
with a high-level Is_TSS.
* sem_ch6.adb (Check_Conformance): Replace DECLARE block and
nested IF with a call to Get_TSS_Name and a membership test.
(Has_Reliable_Extra_Formals): Refactor repeated calls to
Get_TSS_Name.
* sem_disp.adb (Check_Dispatching_Operation): Replace repeated
calls to Get_TSS_Name with a membership test.
Eric Botcazou [Tue, 4 Apr 2023 17:25:11 +0000 (19:25 +0200)]
ada: Fix internal error with pragma Compile_Time_{Warning,Error}
This happens when the pragmas are deferred to the back-end from an external
unit to the main unit that is generic, because the back-end does not compile
a main unit that is generic.
gcc/ada/
* sem_prag.adb (Process_Compile_Time_Warning_Or_Error): Do not defer
anything to the back-end when the main unit is generic.
Eric Botcazou [Wed, 5 Apr 2023 18:43:54 +0000 (20:43 +0200)]
ada: Fix remaining failures in Roman Numbers test
The test is inspired from the example of user-defined literals given in the
Ada 2022 RM. Mixed Arabic numbers/Roman numbers computations are rejected
because the second resolution pass would try to resolve Arabic numbers only
as user-defined literals.
gcc/ada/
* sem_res.adb (Try_User_Defined_Literal): For arithmetic operators,
also accept operands whose type is covered by the resolution type.
Eric Botcazou [Mon, 3 Apr 2023 08:53:30 +0000 (10:53 +0200)]
ada: Fix wrong finalization for call to BIP function in conditional expression
This happens when the call is a dependent expression of the conditional
expression, and the conditional expression is either the expression of a
simple return statement or the return expression of an expression function.
The reason is that the special processing of "tail calls" for BIP functions,
i.e. calls that are the expression of simple return statements or the return
expression of expression functions, is not applied.
This change makes sure that it is applied by distributing the simple return
statements enclosing conditional expressions into the dependent expressions
of the conditional expressions in almost all cases. As a side effect, this
elides a temporary in the nonlimited by-reference case, as well as a pair of
calls to Adjust/Finalize in the nonlimited controlled case.
gcc/ada/
* exp_ch4.adb (Expand_N_Case_Expression): Distribute simple return
statements enclosing the conditional expression into the dependent
expressions in almost all cases.
(Expand_N_If_Expression): Likewise.
(Process_Transient_In_Expression): Adjust to the above distribution.
* exp_ch6.adb (Expand_Ctrl_Function_Call): Deal with calls in the
dependent expressions of a conditional expression.
* sem_ch6.adb (Analyze_Function_Return): Deal with the rewriting of
a simple return statement during the resolution of its expression.
Marc Poulhiès [Mon, 27 Mar 2023 14:47:04 +0000 (16:47 +0200)]
ada: Fix crash on vector initialization
Initializing a vector using
Vec : V.Vector := [Some_Type'(Some_Abstract_Type with F => 0)];
may crash the compiler. The expander marks the N_Extension_Aggregate for
delayed expansion which never happens and incorrectly ends up in gigi.
The delayed expansion is needed for nested aggregates, which the
original code is testing for, but container aggregates are handled
differently.
Such assignments to container aggregates are later transformed into
procedure calls to the procedures named in the Aggregate aspect
definition, for which the delayed expansion is not required/expected.
gcc/ada/
* exp_aggr.adb (Convert_To_Assignments): Do not mark node for
delayed expansion if parent type has the Aggregate aspect.
* sem_util.adb (Is_Container_Aggregate): Move...
* sem_util.ads (Is_Container_Aggregate): ... here and make it
public.
Eric Botcazou [Mon, 3 Apr 2023 15:11:11 +0000 (17:11 +0200)]
ada: Repair support for user-defined literals in arithmetic operators
It was partially broken to fix a regression in error reporting, because the
fix was applied to the first pass of resolution instead of the second pass,
as needs to be done for user-defined literals.
gcc/ada/
* sem_ch4.ads (Unresolved_Operator): New procedure.
* sem_ch4.adb (Has_Possible_Literal_Aspects): Rename into...
(Has_Possible_User_Defined_Literal): ...this. Tidy up.
(Operator_Check): Accept again unresolved operators if they have a
possible user-defined literal as operand. Factor out the handling
of the general error message into...
(Unresolved_Operator): ...this new procedure.
* sem_res.adb (Resolve): Be prepared for unresolved operators on
entry in Ada 2022 or later. If they are still unresolved on exit,
call Unresolved_Operator to give the error message.
(Try_User_Defined_Literal): Tidy up.
If the Default_Component_Value aspect is specified for an array type, then
specifying Initialize_Scalars or Normalize_Scalars should have no effect
on the default initialization of an object of the array type.
gcc/ada/
* exp_ch3.adb
(Expand_N_Object_Declaration.Default_Initialize_Object): Add test for
specified Default_Component_Value aspect when deciding whether
either Initialize_Scalars or Normalize_Scalars impacts default
initialization of an array object.
Javier Miranda [Mon, 3 Apr 2023 17:15:47 +0000 (17:15 +0000)]
ada: Crash on aggregate for tagged record with discriminants
The frontend may crash processing an aggregate initializing
a derived tagged record type that has discriminants.
gcc/ada/
* sem_aggr.adb
(Resolve_Record_Aggregate): For aggregates of derived tagged
record types with discriminants, when collecting components
from ancestors, pass to subprogram Gather_Components the
parent type. Required to report errors on wrong aggregate
components.
Piotr Trojanek [Wed, 29 Mar 2023 14:21:01 +0000 (16:21 +0200)]
ada: Fix retrieval of spec entity from entry body entity
When retrieving entities of subprogram spec we only handled functions
and procedures, but not entries. This had no consequences, because we
then only applied checks to functions, but still is worth a cleanup, so
the code is easier to adapt for access-to-subprogram entities as well.
Piotr Trojanek [Mon, 3 Apr 2023 14:54:39 +0000 (16:54 +0200)]
ada: Restore parent link for both lists and nodes in class-wide condition
When preanalysing class-wide conditions, we restore "Function (Object)"
to its original "Object.Function" notation. This requires the Parent
links to be fixed. We did it for nodes; now we do it for lists as well.
This patch is enough to fix assertion failure in CCG and to make the
tree well-connected. Perhaps there is a more elegant solution, but that
remains to be investigated.
gcc/ada/
* contracts.adb (Fix_Parent): Fir part both for lists and nodes.
Eric Botcazou [Sat, 1 Apr 2023 19:57:21 +0000 (21:57 +0200)]
ada: Fix spurious error on nested instantiations with generic renaming
The problem is that the renaming slightly changes the form of a global
reference that was saved during the analysis of a generic package, and
that is sufficient to fool the code adjusting global references during
the instantiation.
gcc/ada/
* sem_ch12.adb (Copy_Generic_Node): Test the original node kind
for the sake of consistency. For identifiers and other entity
names and operators, accept an expanded name as associated node.
Replace "or" with "or else" in condtion and fix its formatting.
Piotr Trojanek [Fri, 31 Mar 2023 12:40:10 +0000 (14:40 +0200)]
ada: Simplify removal of formals from the scope
Calls to Install_Formals are typically enclosed by Push_Scope/End_Scope.
There were just two such calls that instead used Pop_Scope, but most
likely that was by mistake.
Cleanup related to handling of class-wide contracts. Behavior appears to
be unaffected.
gcc/ada/
* contracts.adb (Remove_Formals): Remove.
(Preanalyze_Condition): Replace Pop_Scope with End_Scope.
* sem_ch13.adb (Build_Discrete_Static_Predicate): Replace
Pop_Scope with End_Scope; enclose Install_Formals within
Push_Scope/End_Scope.
Javier Miranda [Wed, 29 Mar 2023 18:48:19 +0000 (18:48 +0000)]
ada: Spurious error on string interpolation
The frontend reports spurious errors on operators found in
interpolated string literals.
gcc/ada/
* scans.ads (Inside_Interpolated_String_Expression): New variable.
* par-ch2.adb (P_Interpolated_String_Literal): Set/clear new
variable when parsing interpolated string expressions.
* scng.adb (Set_String): Skip processing operator symbols when we
arescanning an interpolated string literal.
ada: Add QNX specific version of System.Parameters
The QNX runtimes used the default implementation of
System.Parameters that defines a default stack size
of 2 MB. The QNX specific version uses the QNX default
stack size of 256 KB instead.
gcc/ada/
* Makefile.rtl (QNX): Use s-parame__qnx.adb for s-parame.adb.
* libgnat/s-parame__qnx.adb: Add QNX specific version of
System.Parameters.
Yannick Moy [Thu, 30 Mar 2023 13:07:09 +0000 (15:07 +0200)]
ada: Restore SPARK_Mode On for numerical functions
GNATprove has ad-hoc support for the standard numerical functions, which
consists in emitting an unprovable preconditions on cases which could
lead to an overflow. These functions are thus valid to call from SPARK
code.
gcc/ada/
* libgnat/a-ngelfu.ads: Restore SPARK_Mode from context.
Marc Poulhiès [Wed, 22 Mar 2023 09:43:07 +0000 (10:43 +0100)]
ada: Fix restoration of parent link
When resetting the parent link after having restored the selected
component node, the assertion used was incorrectly triggered when the
traversal hits the members of the parameters association list, as in:
This.Some_Func (Param1, Param2).Dispatching_Call
When restoring the selected component for Dispatching_Call, the
assertion was wrongly triggered when passed Param1 and Param2.
Piotr Trojanek [Wed, 29 Mar 2023 08:03:29 +0000 (10:03 +0200)]
ada: Analyze pre/post on access-to-subprogram without a wrapper
Aspects Pre/Post attached to an access-to-subprogram type were relocated
to a spec of a wrapper subprogram and analyzed there; the body of the
wrapper was only created with expansion enabled. However, there were
several problems with this approach.
When switch -gnat2022 was missing, we didn't relocate the Pre/Post
aspects to wrapper and complained that their placement is incorrect
(because we wrongly assumed that relocation is unconditional). Now we
gently inform, that these aspects are Ada 2022 features that require
-gnat20222 switch.
When switch -gnata was missing, we entirely bypassed analysis of the
Pre/Post aspects on access-to-subprogram. This was unlike for Pre/Post
aspects on subprograms, which are checked for legality regardless of the
-gnata switch.
Finally, in the GNATprove backend we were picking the Pre/Post contract
on an access-to-subprogram type from the wrapper, which was awkward as
otherwise we had to ignore the wrapper specs and special-case for their
missing bodies. In general, it is cleaner for GNATprove to extract the
aspect expressions from where they originally appear and not from
various expansion artifacts like access-to-subprogram wrappers (but the
same applies to predication functions, type invariant procedures and
default initialization procedures).
Now we analyze the Pre/Post aspects on the types where they are
originally attached, regardless of the -gnata switch. Once we adapt
GNATprove to pick the aspect expression from there, we will stop
creating the wrapper spec when expansion is disabled.
gcc/ada/
* contracts.adb
(Add_Pre_Post_Condition): Adapt to handle pre/post of an
access-to-subprogram type.
(Analyze_Type_Contract): Analyze pre/post of an
access-to-subprogram.
* contracts.ads
(Analyze_Type_Contract): Adapt comment.
* sem_ch3.adb
(Build_Access_Subprogram_Wrapper): Copy pre/post aspects to
wrapper spec and keep it on the type.
* sem_prag.adb
(Analyze_Pre_Post_Condition): Expect pre/post aspects on
access-to-subprogram and complain if they appear without -gnat2022
switch.
(Analyze_Pre_Post_Condition_In_Decl_Part): Adapt to handle
pre/post on an access-to-subprogram type entity.
* sem_attr.adb (Analyze_Attribute_Old_Result): Likewise.
(Result): Likewise.
Juzhe-Zhong [Mon, 29 May 2023 04:52:36 +0000 (12:52 +0800)]
RISC-V: Remove redundant printf of abs-run.c
Notice that this testcase cause unexpected fail:
FAIL: gcc.target/riscv/rvv/autovec/unop/abs-run.c (test for excess
errors)
Excess errors:
/work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
warning: implicit declaration of function 'printf'
[-Wimplicit-function-declaration]
/work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
warning: incompatible implicit declaration of built-in function 'printf'
[-Wbuiltin-declaration-mismatch]
/work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
warning: incompatible implicit declaration of built-in function 'printf'
[-Wbuiltin-declaration-mismatch]
/work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
warning: incompatible implicit declaration of built-in function 'printf'
[-Wbuiltin-declaration-mismatch]
/work/home/jzzhong/work/rvv-opensource/software/host/toolchain/gcc/riscv-gcc/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-run.c:22:7:
warning: incompatible implicit declaration of built-in function 'printf'
[-Wbuiltin-declaration-mismatch]
* config/riscv/autovec.md (fma<mode>4): New pattern.
(*fma<mode>): Ditto.
* config/riscv/riscv-protos.h (enum insn_type): New enum.
(emit_vlmax_ternary_insn): New function.
* config/riscv/riscv-v.cc (emit_vlmax_ternary_insn): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/rvv.exp: Add ternary tests
* gcc.target/riscv/rvv/autovec/ternop/ternop-1.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-2.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop-3.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: New test.
* gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: New test.
Juzhe-Zhong [Mon, 29 May 2023 03:01:32 +0000 (11:01 +0800)]
RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM
Currently mode switching incorrect codegen for the following case:
void fn (void);
void f (void * in, void *out, int32_t x, int n, int m)
{
for (int i = 0; i < n; i++) {
vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
fn ();
v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
__riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
}
}
Pan Li [Thu, 25 May 2023 11:56:40 +0000 (19:56 +0800)]
RISC-V: Add ZVFHMIN extension to the -march= option
This patch would like to add new sub extension (aka ZVFHMIN) to the
-march= option. To make it simple, only the sub extension itself is
involved in this patch, and the underlying FP16 related RVV intrinsic
API depends on the TARGET_ZVFHMIN.
The Zvfhmin extension depends on the Zve32f extension. You can locate
more information about ZVFHMIN from below spec doc.
liuhongt [Thu, 25 May 2023 08:14:14 +0000 (16:14 +0800)]
Split notl + pbraodcast + pand to pbroadcast + pandn more modes.
r12-5595-gc39d77f252e895306ef88c1efb3eff04e4232554 adds 2 splitter to
transform notl + pbroadcast + pand to pbroadcast + pandn for
VI124_AVX2 which leaves out all DI-element-size ones as
well as all 512-bit ones.
This patch extend the splitter to VI_AVX2 which will handle DImode for
AVX2, and V64QImode,V32HImode,V16SImode,V8DImode for AVX512.
gcc/ChangeLog:
PR target/100711
* config/i386/sse.md (*andnot<mode>3): Extend below splitter
to VI_AVX2 to cover more modes.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr100711-2.c: Add v4di/v2di testcases.
* gcc.target/i386/pr100711-3.c: New test.
liuhongt [Mon, 22 May 2023 02:41:50 +0000 (10:41 +0800)]
Disable avoid_false_dep_for_bmi for atom and icelake(and later) core processors.
lzcnt/tzcnt has been fixed since skylake, popcnt has been fixed since
icelake. At least for icelake and later intel Core processors, the
errata tune is not needed. And the tune isn't need for ATOM either.
gcc/ChangeLog:
* config/i386/x86-tune.def (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI):
Remove ATOM and ICELAKE(and later) core processors.
Martin Uecker [Fri, 26 May 2023 09:19:01 +0000 (11:19 +0200)]
c: -Wstringop-overflow for parameters with forward-declared sizes
Warnings from -Wstringop-overflow do not appear for parameters declared
as VLAs when the bound refers to a parameter forward declaration. This
is fixed by splitting the loop that passes through parameters into two,
first only recording the positions of all possible size expressions
and then processing the parameters.
PR c/109970
gcc/c-family:
* c-attribs.cc (build_attr_access_from_parms): Split loop to first
record all parameters.
projects / thirdparty / gcc.git / log
