Jason Merrill [Fri, 30 Aug 2024 20:02:10 +0000 (16:02 -0400)]
c++: support C++11 attributes in C++98
I don't see any reason why we can't allow the [[]] attribute syntax in C++98
mode with a pedwarn just like many other C++11 features. In fact, we
already do support it in some places in the grammar, but not in places that
check cp_nth_tokens_can_be_std_attribute_p.
Let's also follow the C front-end's lead in only warning about them when
-pedantic.
It still isn't necessary for this function to guard against Objective-C
message passing syntax; we handle that with tentative parsing in
cp_parser_statement, and we don't call this function in that context anyway.
gcc/cp/ChangeLog:
* parser.cc (cp_nth_tokens_can_be_std_attribute_p): Don't check
cxx_dialect.
* error.cc (maybe_warn_cpp0x): Only complain about C++11 attributes
if pedantic.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/gen-attrs-1.C: Also run in C++98 mode.
* g++.dg/cpp0x/gen-attrs-11.C: Likewise.
* g++.dg/cpp0x/gen-attrs-13.C: Likewise.
* g++.dg/cpp0x/gen-attrs-15.C: Likewise.
* g++.dg/cpp0x/gen-attrs-75.C: Don't expect C++98 warning after
__extension__.
This is a new attempt to fix PR116080. The previous try was reverted
because it just broke a bunch of tests, hiding the problem.
- musttail behaves differently than tailcall at -O0. Some of the test
run at -O0, so add separate effective target tests for musttail.
- New effective target tests need to use unique file names
to make dejagnu caching work
- Change the tests to use new targets
- Add a external_musttail test to check for target's ability
to do tail calls between translation units. This covers some powerpc
ABIs.
gcc/testsuite/ChangeLog:
PR testsuite/116080
* c-c++-common/musttail1.c: Use musttail target.
* c-c++-common/musttail12.c: Use struct_musttail target.
* c-c++-common/musttail2.c: Use musttail target.
* c-c++-common/musttail3.c: Likewise.
* c-c++-common/musttail4.c: Likewise.
* c-c++-common/musttail7.c: Likewise.
* c-c++-common/musttail8.c: Likewise.
* g++.dg/musttail10.C: Likewise. Replace powerpc checks with
external_musttail.
* g++.dg/musttail11.C: Use musttail target.
* g++.dg/musttail6.C: Use musttail target. Replace powerpc
checks with external_musttail.
* g++.dg/musttail9.C: Use musttail target.
* lib/target-supports.exp: Add musttail, struct_musttail,
external_musttail targets. Remove optimization for musttail.
Use unique file names for musttail.
David Malcolm [Tue, 3 Sep 2024 19:11:06 +0000 (15:11 -0400)]
pretty-print: split up pretty_printer::format into subroutines
The body of pretty_printer::format is almost 500 lines long,
mostly comprising two distinct phases.
This patch splits it up so that there are explicit subroutines
for the two different phases, reducing the scope of various
locals, and making it easier to e.g. put a breakpoint on phase 2.
No functional change intended.
gcc/ChangeLog:
* pretty-print-markup.h (pp_markup::context::context): Drop
params "buf" and "chunk_idx", initializing m_buf from pp.
(pp_markup::context::m_chunk_idx): Drop field.
* pretty-print.cc (pretty_printer::format): Convert param
from a text_info * to a text_info &. Split out phase 1
and phase 2 into subroutines...
(format_phase_1): New, from pretty_printer::format.
(format_phase_2): Likewise.
* pretty-print.h (pretty_printer::format): Convert param
from a text_info * to a text_info &.
(pp_format): Update for above change. Assert that text_info is
non-null.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
David Malcolm [Tue, 3 Sep 2024 19:10:56 +0000 (15:10 -0400)]
pretty-print: naming cleanups
This patch is a followup to r15-3311-ge31b6176996567 making some
cleanups to pretty-printing to reflect those changes:
- renaming "chunk_info" to "pp_formatted_chunks"
- renaming "cur_chunk_array" to "m_cur_fomatted_chunks"
- rewording/clarifying comments
and taking the opportunity to add a "m_" prefix to all fields of
output_buffer.
No functional change intended.
gcc/analyzer/ChangeLog:
* analyzer-logging.cc (logger::logger): Prefix all output_buffer
fields with "m_".
gcc/c-family/ChangeLog:
* c-ada-spec.cc (dump_ada_node): Prefix all output_buffer fields
with "m_".
* c-pretty-print.cc (pp_c_integer_constant): Likewise.
(pp_c_integer_constant): Likewise.
(pp_c_floating_constant): Likewise.
(pp_c_fixed_constant): Likewise.
gcc/c/ChangeLog:
* c-objc-common.cc (print_type): Prefix all output_buffer fields
with "m_".
gcc/cp/ChangeLog:
* error.cc (type_to_string): Prefix all output_buffer fields with
"m_".
(append_formatted_chunk): Likewise. Rename "chunk_info" to
"pp_formatted_chunks" and field cur_chunk_array with
m_cur_formatted_chunks.
gcc/fortran/ChangeLog:
* error.cc (gfc_move_error_buffer_from_to): Prefix all
output_buffer fields with "m_".
(gfc_diagnostics_init): Likewise.
gcc/ChangeLog:
* diagnostic.cc (diagnostic_set_caret_max_width): Prefix all
output_buffer fields with "m_".
* dumpfile.cc (emit_any_pending_textual_chunks): Likewise.
(emit_any_pending_textual_chunks): Likewise.
* gimple-pretty-print.cc (gimple_dump_bb_buff): Likewise.
* json.cc (value::dump): Likewise.
* pretty-print-format-impl.h (class chunk_info): Rename to...
(class pp_formatted_chunks): ...this. Add friend
class output_buffer. Update comment near end of decl to show
the pp_formatted_chunks instance on the chunk_obstack.
(pp_formatted_chunks::pop_from_output_buffer): Delete decl.
(pp_formatted_chunks::on_begin_quote): Delete decl that should
have been removed in r15-3311-ge31b6176996567.
(pp_formatted_chunks::on_end_quote): Likewise.
(pp_formatted_chunks::m_prev): Update for renaming.
* pretty-print.cc (output_buffer::output_buffer): Prefix all
fields with "m_". Rename "cur_chunk_array" to
"m_cur_formatted_chunks".
(output_buffer::~output_buffer): Prefix all fields with "m_".
(output_buffer::push_formatted_chunks): New.
(output_buffer::pop_formatted_chunks): New.
(pp_write_text_to_stream): Prefix all output_buffer fields with
"m_".
(pp_write_text_as_dot_label_to_stream): Likewise.
(pp_write_text_as_html_like_dot_to_stream): Likewise.
(chunk_info::append_formatted_chunk): Rename to...
(pp_formatted_chunks::append_formatted_chunk): ...this.
(chunk_info::pop_from_output_buffer): Delete.
(pretty_printer::format): Update leading comment to mention
pushing pp_formatted_chunks, and to reflect changes in r15-3311-ge31b6176996567. Prefix all output_buffer fields with
"m_".
(pp_output_formatted_text): Update leading comment to mention
popping a pp_formatted_chunks, and to reflect the changes in r15-3311-ge31b6176996567. Prefix all output_buffer fields with
"m_" and rename "cur_chunk_array" to "m_cur_formatted_chunks".
Replace call to chunk_info::pop_from_output_buffer with a call to
output_buffer::pop_formatted_chunks.
(pp_flush): Prefix all output_buffer fields with "m_".
(pp_really_flush): Likewise.
(pp_clear_output_area): Likewise.
(pp_append_text): Likewise.
(pretty_printer::remaining_character_count_for_line): Likewise.
(pp_newline): Likewise.
(pp_character): Likewise.
(pp_markup::context::push_back_any_text): Likewise.
* pretty-print.h (class chunk_info): Rename to...
(class pp_formatted_chunks): ...this.
(class output_buffer): Delete unimplemented rule-of-5 members.
(output_buffer::push_formatted_chunks): New decl.
(output_buffer::pop_formatted_chunks): New decl.
(output_buffer::formatted_obstack): Rename to...
(output_buffer::m_formatted_obstack): ...this.
(output_buffer::chunk_obstack): Rename to...
(output_buffer::m_chunk_obstack): ...this.
(output_buffer::obstack): Rename to...
(output_buffer::m_obstack): ...this.
(output_buffer::cur_chunk_array): Rename to...
(output_buffer::m_cur_formatted_chunks): ...this.
(output_buffer::stream): Rename to...
(output_buffer::m_stream): ...this.
(output_buffer::line_length): Rename to...
(output_buffer::m_line_length): ...this.
(output_buffer::digit_buffer): Rename to...
(output_buffer::m_digit_buffer): ...this.
(output_buffer::flush_p): Rename to...
(output_buffer::m_flush_p): ...this.
(output_buffer_formatted_text): Prefix all output_buffer fields
with "m_".
(output_buffer_append_r): Likewise.
(output_buffer_last_position_in_text): Likewise.
(pretty_printer::set_output_stream): Likewise.
(pp_scalar): Likewise.
(pp_wide_int): Likewise.
* tree-pretty-print.cc (dump_generic_node): Likewise.
(dump_generic_node): Likewise.
(pp_double_int): Likewise.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
Jan Hubicka [Tue, 3 Sep 2024 16:20:34 +0000 (18:20 +0200)]
Zen5 tuning part 4: update reassocation width
Zen5 has 6 instead of 4 ALUs and the integer multiplication can now execute in
3 of them. FP units can do 2 additions and 2 multiplications with latency 2
and 3. This patch updates reassociation width accordingly. This has potential
of increasing register pressure but unlike while benchmarking znver1 tuning
I did not noticed this actually causing problem on spec, so this patch bumps
up reassociation width to 6 for everything except for integer vectors, where
there are 4 units with typical latency of 1.
Jonathan Wakely [Mon, 2 Sep 2024 11:16:49 +0000 (12:16 +0100)]
libstdc++: Fix error handling in fs::hard_link_count for Windows
The recent change to use auto_win_file_handle for
std::filesystem::hard_link_count caused a regression. The
std::error_code argument should be cleared if no error occurs, but this
no longer happens. Add a call to ec.clear() in fs::hard_link_count to
fix this.
Also change the auto_win_file_handle class to take a reference to the
std::error_code and set it if an error occurs, to slightly simplify the
control flow in the fs::equiv_files function.
libstdc++-v3/ChangeLog:
* src/c++17/fs_ops.cc (auto_win_file_handle): Add error_code&
member and set it if CreateFileW or GetFileInformationByHandle
fails.
(fs::equiv_files) [_GLIBCXX_FILESYSTEM_IS_WINDOWS]: Simplify
control flow.
(fs::hard_link_count) [_GLIBCXX_FILESYSTEM_IS_WINDOWS]: Clear ec
on success.
* testsuite/27_io/filesystem/operations/hard_link_count.cc:
Check error handling.
Jonathan Wakely [Mon, 2 Sep 2024 10:29:13 +0000 (11:29 +0100)]
libstdc++: Specialize std::disable_sized_sentinel_for for std::move_iterator [PR116549]
LWG 3736 added a partial specialization of this variable template for
two std::move_iterator types. This is needed for the case where the
types satisfy std::sentinel_for and are subtractable, but do not model
the semantics requirements of std::sized_sentinel_for.
libstdc++-v3/ChangeLog:
PR libstdc++/116549
* include/bits/stl_iterator.h (disable_sized_sentinel_for):
Define specialization for two move_iterator types, as per LWG
3736.
* testsuite/24_iterators/move_iterator/lwg3736.cc: New test.
Jan Hubicka [Tue, 3 Sep 2024 14:26:16 +0000 (16:26 +0200)]
Zen5 tuning part 3: scheduler tweaks
this patch adds support for new fussion in znver5 documented in the
optimization manual:
The Zen5 microarchitecture adds support to fuse reg-reg MOV Instructions
with certain ALU instructions. The following conditions need to be met for
fusion to happen:
- The MOV should be reg-reg mov with Opcode 0x89 or 0x8B
- The MOV is followed by an ALU instruction where the MOV and ALU destination register match.
- The ALU instruction may source only registers or immediate data. There cannot be any memory source.
- The ALU instruction sources either the source or dest of MOV instruction.
- If ALU instruction has 2 reg sources, they should be different.
- The following ALU instructions can fuse with an older qualified MOV instruction:
ADD ADC AND XOR OP SUB SBB INC DEC NOT SAL / SHL SHR SAR
(I assume OP is OR)
I also increased issue rate from 4 to 6. Theoretically znver5 can do more, but
with our model we can't realy use it.
Increasing issue rate to 8 leads to infinite loop in scheduler.
Finally, I also enabled fuse_alu_and_branch since it is supported by
znver5 (I think by earlier zens too).
New fussion pattern moves quite few instructions around in common code:
@@ -2210,13 +2210,13 @@
.cfi_offset 3, -32
leaq 63(%rsi), %rbx
movq %rbx, %rbp
+ shrq $6, %rbp
+ salq $3, %rbp
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
- shrq $6, %rbp
- movq %rsi, 8(%rsp)
- salq $3, %rbp
movq %rbp, %rdi
+ movq %rsi, 8(%rsp)
call _Znwm
movq 8(%rsp), %rsi
movl $0, 8(%r12)
@@ -2224,8 +2224,8 @@
movq %rax, (%r12)
movq %rbp, 32(%r12)
testq %rsi, %rsi
- movq %rsi, %rdx
cmovns %rsi, %rbx
+ movq %rsi, %rdx
sarq $63, %rdx
shrq $58, %rdx
sarq $6, %rbx
which should help decoder bandwidth and perhaps also cache, though I was not
able to measure off-noise effect on SPEC.
gcc/ChangeLog:
* config/i386/i386.h (TARGET_FUSE_MOV_AND_ALU): New tune.
* config/i386/x86-tune-sched.cc (ix86_issue_rate): Updat for znver5.
(ix86_adjust_cost): Add TODO about znver5 memory latency.
(ix86_fuse_mov_alu_p): New.
(ix86_macro_fusion_pair_p): Use it.
* config/i386/x86-tune.def (X86_TUNE_FUSE_ALU_AND_BRANCH): Add ZNVER5.
(X86_TUNE_FUSE_MOV_AND_ALU): New tune;
Jonathan Wakely [Wed, 28 Aug 2024 12:07:47 +0000 (13:07 +0100)]
libstdc++: Simplify std::any to fix -Wdeprecated-declarations warning
We don't need to use std::aligned_storage in std::any. We just need a
POD type of the right size. The void* union member already ensures the
alignment will be correct. Avoiding std::aligned_storage means we don't
need to suppress a -Wdeprecated-declarations warning.
libstdc++-v3/ChangeLog:
* include/experimental/any (experimental::any::_Storage): Use
array of unsigned char instead of deprecated
std::aligned_storage.
* include/std/any (any::_Storage): Likewise.
* testsuite/20_util/any/layout.cc: New test.
Dhruv Chawla [Mon, 26 Aug 2024 05:39:19 +0000 (11:09 +0530)]
libstdc++: Add missing feature-test macro in various headers
version.syn#2 requires various headers to define
__cpp_lib_allocator_traits_is_always_equal. Currently, only <memory> was
defining this macro. Implement fixes for the other headers as well.
Jan Hubicka [Tue, 3 Sep 2024 13:07:41 +0000 (15:07 +0200)]
Zen5 tuning part 2: disable gather and scatter
We disable gathers for zen4. It seems that gather has improved a bit compared
to zen4 and Zen5 optimization manual suggests "Avoid GATHER instructions when
the indices are known ahead of time. Vector loads followed by shuffles result
in a higher load bandwidth." however the situation seems to be more
complicated.
gather is 5-10% loss on parest benchmark as well as 30% loss on sparse dot
products in TSVC. Curiously enough breaking these out into microbenchmark
reversed the situation and it turns out that the performance depends on
how indices are distributed. gather is loss if indices are sequential,
neutral if they are random and win for some strides (4, 8).
This seems to be similar to earlier zens, so I think (especially for
backporting znver5 support) that it makes sense to be conistent and disable
gather unless we work out a good heuristics on when to use it. Since we
typically do not know the indices in advance, I don't see how that can be done.
I opened PR116582 with some examples of wins and loses
gcc/ChangeLog:
* config/i386/x86-tune.def (X86_TUNE_USE_GATHER_2PARTS): Disable for
ZNVER5.
(X86_TUNE_USE_SCATTER_2PARTS): Disable for ZNVER5.
(X86_TUNE_USE_GATHER_4PARTS): Disable for ZNVER5.
(X86_TUNE_USE_SCATTER_4PARTS): Disable for ZNVER5.
(X86_TUNE_USE_GATHER_8PARTS): Disable for ZNVER5.
(X86_TUNE_USE_SCATTER_8PARTS): Disable for ZNVER5.
H.J. Lu [Tue, 27 Aug 2024 20:11:39 +0000 (13:11 -0700)]
ipa: Don't disable function parameter analysis for fat LTO
Update analyze_parms not to disable function parameter analysis for
-ffat-lto-objects. Tested on x86-64, there are no differences in zstd
with "-O2 -flto=auto" -g "vs -O2 -flto=auto -g -ffat-lto-objects".
PR ipa/116410
* ipa-modref.cc (analyze_parms): Always analyze function parameter
for LTO.
Jeff Law [Tue, 3 Sep 2024 12:45:30 +0000 (06:45 -0600)]
[PR target/115921] Improve reassociation for rv64
As Jovan pointed out in pr115921, we're not reassociating expressions like this
on rv64:
(x & 0x3e) << 12
It generates something like this:
li a5,258048
slli a0,a0,12
and a0,a0,a5
We have a pattern that's designed to clean this up. Essentially reassociating
the operations so that we don't need to load the constant resulting in
something like this:
andi a0,a0,63
slli a0,a0,12
That pattern wasn't working for certain constants due to its condition. The
condition is trying to avoid cases where this kind of reassociation would
hinder shadd generation on rv64. That condition was just written poorly.
This patch tightens up that condition in a few ways. First, there's no need to
worry about shadd cases if ZBA is not enabled. Second we can't use shadd if
the shift value isn't 1, 2 or 3. Finally rather than open-coding one of the
tests, we can use an existing operand predicate.
The net is we'll start performing this transformation in more cases on rv64
while still avoiding reassociation if it would spoil shadd generation.
PR target/115921
gcc/
* config/riscv/riscv.md (reassociate bitwise ops): Tighten test for
cases we do not want reassociate.
gcc/testsuite/
* gcc.target/riscv/pr115921.c: New test.
Jan Hubicka [Tue, 3 Sep 2024 11:38:33 +0000 (13:38 +0200)]
Zen5 tuning part 1: avoid FMA chains
testing matrix multiplication benchmarks shows that FMA on a critical chain
is a perofrmance loss over separate multiply and add. While the latency of 4
is lower than multiply + add (3+2) the problem is that all values needs to
be ready before computation starts.
While on znver4 AVX512 code fared well with FMA, it was because of the split
registers. Znver5 benefits from avoding FMA on all widths. This may be different
with the mobile version though.
On naive matrix multiplication benchmark the difference is 8% with -O3
only since with -Ofast loop interchange solves the problem differently.
It is 30% win, for example, on S323 from TSVC:
LTO/WPA: Ensure that output_offload_tables only writes table once [PR116535]
When ltrans was written concurrently, e.g. via -flto=N (N > 1, assuming
sufficient partiations, e.g., via -flto-partition=max), output_offload_tables
wrote the output tables once per fork.
Richard Biener [Tue, 3 Sep 2024 07:23:20 +0000 (09:23 +0200)]
tree-optimization/116575 - avoid ICE with SLP mask_load_lane
The following avoids performing re-discovery with single lanes in
the attempt to for the use of mask_load_lane as rediscovery will
fail since a single lane of a mask load will appear permuted which
isn't supported.
PR tree-optimization/116575
* tree-vect-slp.cc (vect_analyze_slp): Properly compute
the mask argument for vect_load/store_lanes_supported.
When the load is masked for now avoid rediscovery.
The intrin for non-optimized got a typo in mask type, which will cause
the high bits of __mmask32 being unexpectedly zeroed.
The test does not fail under O0 with current 1b since the testcase is
wrong. We need to include avx512-mask-type.h after SIZE is defined, or
it will always be __mmask8. That problem also happened in AVX10.2 testcases.
I will write a seperate patch to fix that.
gcc/ChangeLog:
* config/i386/avx512fp16intrin.h
(_mm512_mask_fpclass_ph_mask): Correct mask type to __mmask32.
(_mm512_fpclass_ph_mask): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx512fp16-vfpclassph-1c.c: New test.
Jakub Jelinek [Tue, 3 Sep 2024 08:20:44 +0000 (10:20 +0200)]
lower-bitint: Fix up __builtin_{add,sub}_overflow{,_p} bitint lowering [PR116501]
The following testcase is miscompiled. The problem is in the last_ovf step.
The second operand has signed _BitInt(513) type but has the MSB clear,
so range_to_prec returns 512 for it (i.e. it fits into unsigned
_BitInt(512)). Because of that the last step actually doesn't need to get
the most significant bit from the second operand, but the code was deciding
what to use purely from TYPE_UNSIGNED (type1) - if unsigned, use 0,
otherwise sign-extend the last processed bit; but that in this case was set.
We don't want to treat the positive operand as if it was negative regardless
of the bit below that precision, and precN >= 0 indicates that the operand
is in the [0, inf) range.
2024-09-03 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/116501
* gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
In the last_ovf case, use build_zero_cst operand not just when
TYPE_UNSIGNED (typeN), but also when precN >= 0.
Eric Botcazou [Fri, 23 Aug 2024 15:06:00 +0000 (17:06 +0200)]
ada: Add kludge for quirk of ancient 32-bit ABIs to previous change
Some ancient 32-bit ABIs, most notably that of x86/Linux, misalign double
scalars in record types, so comparing DECL_ALIGN with TYPE_ALIGN directly
may give the wrong answer for them.
gcc/ada/
* gcc-interface/trans.cc (addressable_p) <COMPONENT_REF>: Add kludge
to cope with ancient 32-bit ABIs.
Eric Botcazou [Fri, 23 Aug 2024 07:44:06 +0000 (09:44 +0200)]
ada: Plug loophole exposed by previous change
The change causes more temporaries to be created at call sites for unaligned
actual parameters, thus revealing that the machinery does not properly deal
with unconstrained nominal subtypes for them.
gcc/ada/
* gcc-interface/trans.cc (create_temporary): Deal with types whose
size is self-referential by allocating the maximum size.
Eric Botcazou [Thu, 22 Aug 2024 19:18:15 +0000 (21:18 +0200)]
ada: Fix internal error with Atomic Volatile_Full_Access object
The initial implementation of the GNAT aspect/pragma Volatile_Full_Access
made it incompatible with Atomic, because it was not decided whether the
read-modify-write sequences generated by Volatile_Full_Access would need
to be implemented atomically when Atomic was also specified, which would
have required a compare-and-swap primitive from the target architecture.
But Ada 2022 introduced Full_Access_Only and retrofitted it into Atomic
in the process, answering the above question by the negative, so the
incompatibility between Volatile_Full_Access and Atomic was lifted in
Ada 2012 as well, unfortunately without adjusting the implementation.
gcc/ada/
* gcc-interface/trans.cc (get_atomic_access): Deal specifically with
nodes that are both Atomic and Volatile_Full_Access in Ada 2012.
Eric Botcazou [Tue, 20 Aug 2024 20:59:58 +0000 (22:59 +0200)]
ada: Pass unaligned record components by copy in calls on all platforms
This has historically been done only on platforms requiring the strict
alignment of memory references, but this can arguably be considered as
being mandated by the language on all of them.
gcc/ada/
* gcc-interface/trans.cc (addressable_p) <COMPONENT_REF>: Take into
account the alignment of the field on all platforms.
Marc Poulhiès [Fri, 9 Aug 2024 16:08:01 +0000 (18:08 +0200)]
ada: Simplify Note_Uplevel_Bound procedure
The procedure Note_Uplevel_Bound was implemented as a custom expression
tree walk. This change replaces this custom tree traversal by a more
idiomatic use of Traverse_Proc.
gcc/ada/
* exp_unst.adb (Check_Static_Type::Note_Uplevel_Bound): Refactor
to use the generic Traverse_Proc.
(Check_Static_Type): Adjust calls to Note_Uplevel_Bound as the
previous second parameter was unused, so removed.
Steve Baird [Wed, 21 Aug 2024 00:35:24 +0000 (17:35 -0700)]
ada: Transform Length attribute references for non-Strict overflow mode.
The non-strict overflow checking code does a better job of eliminating
overflow checks if given an expression consisting only of predefined
operators (including relationals), literals, identifiers, and conditional
expressions. If it is both feasible and useful, rewrite a
Length attribute reference as such an expression. "Feasible" means
"index type is same type as attribute reference type, so we can rewrite without
using type conversions". "Useful" means "Overflow_Mode is something other than
Strict, so there is value in making overflow check elimination easier".
gcc/ada/
* exp_attr.adb (Expand_N_Attribute_Reference): If it makes sense
to do so, then rewrite a Length attribute reference as an
equivalent conditional expression.
Eric Botcazou [Thu, 22 Aug 2024 20:54:02 +0000 (22:54 +0200)]
ada: Do not warn for partial access to Atomic Volatile_Full_Access objects
The initial implementation of the GNAT aspect/pragma Volatile_Full_Access
made it incompatible with Atomic, because it was not decided whether the
read-modify-write sequences generated by Volatile_Full_Access would need
to be implemented atomically when Atomic was also specified, which would
have required a compare-and-swap primitive from the target architecture.
But Ada 2022 introduced Full_Access_Only and retrofitted it into Atomic
in the process, answering the above question by the negative, so the
incompatibility between Volatile_Full_Access and Atomic was lifted in
Ada 2012 as well, but the implementation was not entirely adjusted.
In Ada 2012, it does not make sense to warn for the partial access to an
Atomic object if the object is also declared Volatile_Full_Access, since
the object will be accessed as a whole in this case (like in Ada 2022).
gcc/ada/
* sem_res.adb (Is_Atomic_Ref_With_Address): Rename into...
(Is_Atomic_Non_VFA_Ref_With_Address): ...this and adjust the
implementation to exclude Volatile_Full_Access objects.
(Resolve_Indexed_Component): Adjust to above renaming.
(Resolve_Selected_Component): Likewise.
Steve Baird [Mon, 19 Aug 2024 21:58:38 +0000 (14:58 -0700)]
ada: Reject illegal array aggregates as per AI22-0106.
Implement the new legality rules of AI22-0106 which (as discussed in the AI)
are needed to disallow constructs whose semantics would otherwise be poorly
defined.
gcc/ada/
* sem_aggr.adb (Resolve_Array_Aggregate): Implement the two new
legality rules of AI11-0106. Add code to avoid cascading error
messages.
Bob Duff [Thu, 22 Aug 2024 16:32:00 +0000 (12:32 -0400)]
ada: Fix Finalize_Storage_Only bug in b-i-p calls
Do not pass null for the Collection parameter when
Finalize_Storage_Only is in effect. If the collection
is null in that case, we will blow up later when we
deallocate the object.
gcc/ada/
* exp_ch6.adb (Add_Collection_Actual_To_Build_In_Place_Call):
Remove Finalize_Storage_Only from the code that checks whether to
pass null to the Collection parameter. Having done that, we don't
need to check for Is_Library_Level_Entity, because
No_Heap_Finalization requires that. And if we ever change
No_Heap_Finalization to allow nested access types, we will still
want to pass null. Note that the comment "Such a type lacks a
collection." is incorrect in the case of Finalize_Storage_Only;
such types have a collection.
Jennifer Schmitz [Fri, 30 Aug 2024 14:16:43 +0000 (07:16 -0700)]
SVE intrinsics: Fold constant operands for svmul.
This patch implements constant folding for svmul by calling
gimple_folder::fold_const_binary with tree_code MULT_EXPR.
Tests were added to check the produced assembly for different
predicates, signed and unsigned integers, and the svmul_n_* case.
The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression.
OK for mainline?
Jennifer Schmitz [Fri, 30 Aug 2024 14:03:49 +0000 (07:03 -0700)]
SVE intrinsics: Fold constant operands for svdiv.
This patch implements constant folding for svdiv:
The new function aarch64_const_binop was created, which - in contrast to
int_const_binop - does not treat operations as overflowing. This function is
passed as callback to vector_const_binop from the new gimple_folder
method fold_const_binary, if the predicate is ptrue or predication is _x.
From svdiv_impl::fold, fold_const_binary is called with TRUNC_DIV_EXPR as
tree_code.
In aarch64_const_binop, a case was added for TRUNC_DIV_EXPR to return 0
for division by 0, as defined in the semantics for svdiv.
Tests were added to check the produced assembly for different
predicates, signed and unsigned integers, and the svdiv_n_* case.
The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression.
OK for mainline?
Signed-off-by: Jennifer Schmitz <jschmitz@nvidia.com>
gcc/
* config/aarch64/aarch64-sve-builtins-base.cc (svdiv_impl::fold):
Try constant folding.
* config/aarch64/aarch64-sve-builtins.h: Declare
gimple_folder::fold_const_binary.
* config/aarch64/aarch64-sve-builtins.cc (aarch64_const_binop):
New function to fold binary SVE intrinsics without overflow.
(gimple_folder::fold_const_binary): New helper function for
constant folding of SVE intrinsics.
gcc/testsuite/
* gcc.target/aarch64/sve/const_fold_div_1.c: New test.
Jennifer Schmitz [Fri, 30 Aug 2024 13:56:52 +0000 (06:56 -0700)]
SVE intrinsics: Refactor const_binop to allow constant folding of intrinsics.
This patch sets the stage for constant folding of binary operations for SVE
intrinsics:
In fold-const.cc, the code for folding vector constants was moved from
const_binop to a new function vector_const_binop. This function takes a
function pointer as argument specifying how to fold the vector elements.
The intention is to call vector_const_binop from the backend with an
aarch64-specific callback function.
The code in const_binop for folding operations where the first operand is a
vector constant and the second argument is an integer constant was also moved
into vector_const_binop to to allow folding of binary SVE intrinsics where
the second operand is an integer (_n).
To allow calling poly_int_binop from the backend, the latter was made public.
The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression.
OK for mainline?
Signed-off-by: Jennifer Schmitz <jschmitz@nvidia.com>
gcc/
* fold-const.h: Declare vector_const_binop.
* fold-const.cc (const_binop): Remove cases for vector constants.
(vector_const_binop): New function that folds vector constants
element-wise.
(int_const_binop): Remove call to wide_int_binop.
(poly_int_binop): Add call to wide_int_binop.
Richard Biener [Mon, 2 Sep 2024 13:12:58 +0000 (15:12 +0200)]
Handle mixing REALPART/IMAGPART with other components in SLP groups
The following makes sure we handle a SLP load/store group from
a structure with complex and scalar members. This for example
happens in gcc.target/i386/pr106010-9a.c.
* tree-vect-slp.cc (vect_build_slp_tree_1): Handle mixing
all of handled components besides ARRAY_RANGE_REF, drop
handling of INDIRECT_REF.
Richard Biener [Mon, 2 Sep 2024 09:16:12 +0000 (11:16 +0200)]
Correctly handle store IFNs in vect_get_vector_types_for_stmt
Currently vect_get_vector_types_for_stmt only special-cases
IFN_MASK_STORE but there are now very many variants and simply
passing analysis without setting *VECTYPE will ICE duing SLP
discovery (noticed with IFN_SCATTER_STORE). The following
properly uses internal_store_fn_p. I also noticed we're
unnecessarily handing those again to determine the scalar type
but there should always be a data reference for them.
* tree-vect-stmts.cc (vect_get_vector_types_for_stmt):
Handle all internal_store_fn_p the same. Remove special-casing
for the scalar_type of IFN_MASK_STORE.
Levy Hsu [Mon, 26 Aug 2024 01:16:30 +0000 (10:46 +0930)]
i386: Support partial vectorized V2BF/V4BF plus/minus/mult/div/sqrt
This patch introduces new mode iterators and expands for the i386 architecture to support partial vectorization of bf16 operations using AVX10.2 instructions.
gcc/ChangeLog:
* config/i386/mmx.md (VBF_32_64): New mode iterator for partial vectorized V2BF/V4BF.
(<insn><mode>3): New define_expand for plusminusmultdiv.
(sqrt<mode>2): New define_expand for sqrt.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10_2-partial-bf-vector-fast-math-1.c: New test.
* gcc.target/i386/avx10_2-partial-bf-vector-operations-1.c: New test.
Before this patch:
10 │ sat_s_add_int64_t_fmt_1:
11 │ mv a5,a0
12 │ add a0,a0,a1
13 │ xor a1,a5,a1
14 │ not a1,a1
15 │ xor a4,a5,a0
16 │ and a1,a1,a4
17 │ blt a1,zero,.L5
18 │ ret
19 │ .L5:
20 │ srai a5,a5,63
21 │ li a0,-1
22 │ srli a0,a0,1
23 │ xor a0,a5,a0
24 │ ret
After this patch:
10 │ sat_s_add_int64_t_fmt_1:
11 │ add a2,a0,a1
12 │ xor a1,a0,a1
13 │ xor a5,a0,a2
14 │ srli a5,a5,63
15 │ srli a1,a1,63
16 │ xori a1,a1,1
17 │ and a5,a5,a1
18 │ srai a4,a0,63
19 │ li a3,-1
20 │ srli a3,a3,1
21 │ xor a3,a3,a4
22 │ neg a4,a5
23 │ and a3,a3,a4
24 │ addi a5,a5,-1
25 │ and a0,a2,a5
26 │ or a0,a0,a3
27 │ ret
The below test suites are passed for this patch:
1. The rv64gcv fully regression test.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_expand_ssadd): Add new func
decl for expanding ssadd.
* config/riscv/riscv.cc (riscv_gen_sign_max_cst): Add new func
impl to gen the max int rtx.
(riscv_expand_ssadd): Add new func impl to expand the ssadd.
* config/riscv/riscv.md (ssadd<mode>3): Add new pattern for
signed integer .SAT_ADD.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_arith_data.h: Add test data.
* gcc.target/riscv/sat_s_add-1.c: New test.
* gcc.target/riscv/sat_s_add-2.c: New test.
* gcc.target/riscv/sat_s_add-3.c: New test.
* gcc.target/riscv/sat_s_add-4.c: New test.
* gcc.target/riscv/sat_s_add-run-1.c: New test.
* gcc.target/riscv/sat_s_add-run-2.c: New test.
* gcc.target/riscv/sat_s_add-run-3.c: New test.
* gcc.target/riscv/sat_s_add-run-4.c: New test.
* gcc.target/riscv/scalar_sat_binary_run_xxx.h: New test.
YunQiang Su [Mon, 26 Aug 2024 00:45:36 +0000 (08:45 +0800)]
MIPS: Support vector reduc for MSA
We have SHF.fmt and HADD_S/U.fmt with MSA, which can be used for
vector reduc.
For min/max for U8/S8, we can
SHF.B W1, W0, 0xb1 # swap byte inner every half
MIN.B W1, W1, W0
SHF.H W2, W1, 0xb1 # swap half inner every word
MIN.B W2, W2, W1
SHF.W W3, W2, 0xb1 # swap word inner every doubleword
MIN.B W4, W3, W2
SHF.W W4, W4, 0x4e # swap the two doubleword
MIN.B W4, W4, W3
For plus of S8/U8, we can use HADD
HADD.H W0, W0, W0
HADD.W W0, W0, W0
HADD.D W0, W0, W0
SHF.W W1, W0, 0x4e # swap the two doubleword
ADDV.D W1, W1, W0
COPY_S.B T0, W1 # COPY_U.B for U8
We can do similar for S16/U16/S32/U32/S64/U64/FLOAT/DOUBLE.
gcc
* config/mips/mips-msa.md: (MSA_NO_HADD): we have HADD for
S8/U8/S16/U16/S32/U32 only.
(reduc_smin_scal_<mode>): New define pattern.
(reduc_smax_scal_<mode>): Ditto.
(reduc_umin_scal_<mode>): Ditto.
(reduc_umax_scal_<mode>): Ditto.
(reduc_plus_scal_<mode>): Ditto.
(reduc_plus_scal_v4si): Ditto.
(reduc_plus_scal_v8hi): Ditto.
(reduc_plus_scal_v16qi): Ditto.
(reduc_<optab>_scal_<mode>): Ditto.
* config/mips/mips-protos.h: New function mips_expand_msa_reduc.
* config/mips/mips.cc: New function mips_expand_msa_reduc.
* config/mips/mips.md: Define any_bitwise iterator.
30_threads/future/members/poll.cc has calibration code that, on
systems with very low clock resolution, may spuriously fail to run.
Even when it does run, low resolution and reasonable
timeouts limit severely the viability of increasing the loop counts so
as to reduce measurement noise, so we end up with very noisy results.
On various vxworks targets, high iteration count (low-noise)
measurements confirmed that some of the operations that we expected to
be up to 100x slower than the fastest ones can run a little slower
than that and, with significant noise, may seem to be even slower,
comparatively.
Bump the factors up to 200x, so that we have plenty of margin over
measured results.
for libstdc++-v3/ChangeLog
* testsuite/30_threads/future/members/poll.cc: Factor out
calibration, and run it unconditionally. Lower its
strictness. Bump wait_until_*'s slowness factor.
[libstdc++] [testsuite] avoid async.cc loss of precision [PR91486]
When we get to test_pr91486_wait_until(), we're about 10s past the
float_steady_clock epoch. This is enough for the 1s delta for the
timeout to come out slightly lower when the futex-less wait_until
converts the deadline from float_steady_clock to __clock_t. So we may
wake up a little too early, and end up looping one extra time to sleep
for e.g. another 954ns until we hit the deadline.
Each iteration calls float_steady_clock::now(), bumping the call_count
that we VERIFY() at the end of the subtest. Since we expect at most 3
calls, and we're going to have at the very least 3 on futex-less
targets (one in the test proper, one before wait_until_impl to compute
the deadline, and one after wait_until_impl to check whether the
deadline was hit), any such imprecision that causes an extra iteration
will reach 5 and cause the test to fail.
Initializing the epoch in the beginning of the test makes such
spurious fails due to loss of precision far less likely. I don't
suppose allowing for an extra couple of calls would be desirable.
While at that, I'm annotating unused status variables as such.
for libstdc++-v3/ChangeLog
PR libstdc++/91486
* testsuite/30_threads/async/async.cc
(test_pr91486_wait_for): Mark status as unused.
(test_pr91486_wait_until): Likewise. Initialize epoch later.
[testsuite] add linkonly to dg-additional-sources [PR115295]
The D testsuite shows it was a mistake to assume that
dg-additional-sources are never to be used for compilation tests.
Even if an output file is specified for compilation, extra module
files can be named and used in the compilation without being flagged
as errors.
Introduce a 'linkonly' flag for dg-additional-sources, and use it in
pr95401.cc and other vector tests that default to run, so that its
additional sources get discarded when vector tests downgrade to
compile-only. This reverts previous workarounds for this very
circumstance, that relied on being able to run vector tests anyway,
even after failing to detect runtime or hardware vector support.
Andrew Stubbs [Tue, 6 Aug 2024 16:00:21 +0000 (16:00 +0000)]
amdgcn: Remove TARGET_GCN5_PLUS
Now that GCN3 support is gone, TARGET_GCN5_PLUS always evaluates to true, so
we can make that code unconditional, and remove all the "else" cases.
The ISA features TARGET_GLOBAL_ADDRSPACE, TARGET_FLAT_OFFSETS,
TARGET_EXPLICIT_CARRY, and TARGET_MULTIPLY_IMMEDIATE, are similarly also
redundant and can be made unconditional.
The naming of the "gcc_version" attribute has been confusing since the "rdna"
attribute was added and this makes it worse, so it has been renamed to "cdna".
The add-with-carry assembler mnemonics no longer have two forms, so '%^' can be
removed.
Gaius Mulley [Mon, 2 Sep 2024 12:29:25 +0000 (13:29 +0100)]
PR modula2/116557 Remove physical address from the GPL header comment
This patch removes the physical address from all the header comments
in the m2 subdirectory. The physical address is replaced with the
text "You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>." instead.
Since r15-3254-g3f51f0dc88ec21c1ec79df694200f10ef85915f4
added scan-ltrans-rtl* variants to scanltranstree.exp, it no longer
makes sense to have "tree" in the name. This renames the file
accordingly and updates users.
libatomic/ChangeLog:
* testsuite/lib/libatomic.exp: Load scanltrans.exp instead of
scanltranstree.exp.
libgomp/ChangeLog:
* testsuite/lib/libgomp.exp: Load scanltrans.exp instead of
scanltranstree.exp.
libitm/ChangeLog:
* testsuite/lib/libitm.exp: Load scanltrans.exp instead of
scanltranstree.exp.
libphobos/ChangeLog:
* testsuite/lib/libphobos-dg.exp: Load scanltrans.exp instead of
scanltranstree.exp.
libvtv/ChangeLog:
* testsuite/lib/libvtv.exp: Load scanltrans.exp instead of
scanltranstree.exp.
gcc/testsuite/ChangeLog:
* gcc.dg-selftests/dg-final.exp: Load scanltrans.exp instead of
scanltranstree.exp.
* lib/gcc-dg.exp: Likewise.
* lib/scanltranstree.exp: Rename to ...
* lib/scanltrans.exp: ... this.
ASM_INPUT_P is so named because it causes the eventual rtl insn
pattern to be a top-level ASM_INPUT rather than an ASM_OPERANDS.
However, this name has caused confusion, partly due to earlier
documentation. The name also sounds related to ASM_INPUTS but
is for a different piece of state.
This patch renames it to ASM_BASIC_P, with the inverse meaning
an extended asm. ("Basic asm" is the term used in extend.texi.)
Eric Botcazou [Tue, 20 Aug 2024 15:40:41 +0000 (17:40 +0200)]
ada: Diagnose too large size clause on floating-point type
The problem is that the size clause changes the floating-point format used
for the type, but it must not when this format is the widest format that is
supported in hardware on the target. Instead a padding type must be built
and the associated warning given.
gcc/ada/
* gcc-interface/decl.cc (gnat_to_gnu_entity): Cap the Esize of a
floating-point type to the size of the widest format supported in
hardware if it is explicity defined.
ada: Fix standard output stream for gnatcmd output
Before this patch, the gnat command sent to standard error pieces of
information that are a better match for standard output. This patch
makes this information go to standard output.
gcc/ada/
* gnatcmd.adb (GNATCmd): Fix standard output stream.
Before this patch, the documentation of -gnaty0 used 0-based indexing
for column numbers while 1-based indexing is used everywhere else. This
patch makes this documentation use 1-based indexing, and also adds a
missing parenthesis.
gcc/ada/
* doc/gnat_ugn/building_executable_programs_with_gnat.rst: Fix
minor issues.
* gnat_ugn.texi: Regenerate.
Bob Duff [Sun, 18 Aug 2024 23:13:46 +0000 (19:13 -0400)]
ada: Documentation for generic type inference
...plus minor improvements to existing documentation.
gcc/ada/
* doc/gnat_rm/gnat_language_extensions.rst: I assume "extended set
of extensions" was a typo for "experimental set of extensions",
because "extended extensions" is repetitive and redundant. "in
addition" clarifies that the one subsumes the other. Add a
reminder at the start of each subsection about what switch/pragma
enables what extensions. Add new section about "Inference of
Dependent Types in Generic Instantiations".
* gnat_rm.texi: Regenerate.
Marc Poulhiès [Thu, 8 Aug 2024 11:36:37 +0000 (13:36 +0200)]
ada: Also reset scope for some nested declaration
When changing the scope for entities found in the entry body that is
mutated into a procedure, the compiler needs to look deeper than only
the top level entities as expansion may produce object declarations
which scopes are also the entry. For example, the tree after expansion
may look like:
procedure This_Is_An_Entry_Proc is
...
O1 : Typ := do
TMP1 : OTyp := ...;
...
in TMP1;
O1's scope needs to be reset to This_Is_An_Entry_Proc, but so does
TMP1's scope.
This change also fix a small oversight where
N_Implicit_Label_Declaration scope must be reset and its content
skipped.
gcc/ada/
* exp_ch9.adb (Reset_Scopes_To): Adjust comment.
(Reset_Scopes_To.Reset_Scope): Adjust the scope reset for object
declaration. In particular, visit the children nodes if any. Also
extend the handling of other declarations to
N_Implicit_Label_Declaration.
Jakub Jelinek [Mon, 2 Sep 2024 07:44:09 +0000 (09:44 +0200)]
ranger: Fix up range computation for CLZ [PR116486]
The initial CLZ gimple-range-op.cc implementation handled just the
case where second argument to .CLZ is equal to prec, but in
r15-1014 I've added also handling of the -1 case. As the following
testcase shows, incorrectly though for the case where the first argument
has [0,0] range. If the second argument is prec, then the result should
be [prec,prec] and that was handled correctly, but when the second argument
is -1, the result should be [-1,-1] but instead it was incorrectly computed
as [prec-1,prec-1] (when second argument is prec, mini is 0 and maxi is
prec, while when second argument is -1, mini is -1 and maxi is prec-1).
Fixed thusly (the actual handling is then similar to the CTZ [0,0] case).
2024-09-02 Jakub Jelinek <jakub@redhat.com>
PR middle-end/116486
* gimple-range-op.cc (cfn_clz::fold_range): If lh is [0,0]
and mini is -1, return [-1,-1] range rather than [prec-1,prec-1].
Richard Biener [Fri, 5 Jul 2024 08:35:08 +0000 (10:35 +0200)]
load and store-lanes with SLP
The following is a prototype for how to represent load/store-lanes
within SLP. I've for now settled with having a single load node
with multiple permute nodes acting as selection, one for each loaded lane
and a single store node fed from all stored lanes. For
for (int i = 0; i < 1024; ++i)
{
a[2*i] = b[2*i] + 7;
a[2*i+1] = b[2*i+1] * 3;
}
you have the following SLP graph where I explain how things are set
up and code-generated:
This is the load node, marked with ldst_lanes = true (the load
permutation is only accurate when taking into account the lane permute
in the selection nodes). It code generates
This scheme allows to leave code generation in vectorizable_load/store
mostly as-is.
While this should support both load-lanes and (masked) store-lanes
the decision to do either is done during SLP discovery time and
cannot be reversed without altering the SLP tree - as-is the SLP
tree is not usable for non-store-lanes on the store side, the
load side is OK representation-wise but will very likely fail
permute handling as the lowering to deal with the two input vector
restriction isn't done - but of course since the permute node is
marked as to be ignored that doesn't work out. So I've put
restrictions in place that fail vectorization if a load/store-lane
SLP tree is later classified differently by get_load_store_type.
I'll note that for example gcc.target/aarch64/sve/mask_struct_store_3.c
will not get SLP store-lanes used because the full store SLPs just
fine though we then fail to handle the "splat" load-permutation
the load permute lowering code currently doesn't consider it worth
lowering single loads from a group (or in this case not grouped loads).
The expectation is the target can handle this by two interleaves with
itself.
So what we see here is that while the explicit SLP representation is
helpful in some cases, in cases like this it would require changing
it when we make decisions how to vectorize. My idea is that this
all will change a lot when we re-do SLP discovery (for loops) and
when we get rid of non-SLP as I think vectorizable_* should be
allowed to alter the SLP graph during analysis.
The patch also removes the code cancelling SLP if we can use
load/store-lanes from the main loop vector analysis code and
re-implements it as re-discovering the SLP instance with
forced single-lane splits so SLP load/store-lanes scheme can be
used.
This is now done after SLP discovery and SLP pattern recog are
complete to not disturb the latter but per SLP instance instead
of being a global decision on the whole loop.
This is a behavioral change that for example shows in
gcc.dg/vect/slp-perm-6.c on ARM where we formerly used SLP permutes
but now a mix of SLP without permutes and load/store lanes. The
previous flaky heuristic is now flaky in a different way.
Testing on RISC-V and aarch64 reveal several testcases that require
adjustment as to now expect SLP even when load/store lanes are being
used. If in doubt I've adjusted them to the final expectation which
will lead to one or two new FAILs where we still do the SLP cancelling.
I have a followup that implements that while remaining in SLP that's
in final testing.
Note that gcc.dg/vect/slp-42.c and gcc.dg/vect/pr68445.c will FAIL
on aarch64 with SVE because for some odd reason vect_stridedN
is true for any N for check_effective_target_vect_fully_masked
targets but SVE cannot do ld8 while risc-v can.
I have not bothered to adjust target tests that now fail assembly-scan.
* tree-vectorizer.h (_slp_tree::ldst_lanes): New flag to mark
load, store and permute nodes.
* tree-vect-slp.cc (_slp_tree::_slp_tree): Initialize ldst_lanes.
(vect_build_slp_instance): For stores iff the target prefers
store-lanes discover single-lane sub-groups, do not perform
interleaving lowering but mark the node with ldst_lanes.
Also allow i == 0 - fatal failure - for splitting up a store group
when we're not doing single-lane discovery already.
(vect_lower_load_permutations): When the target supports
load lanes and the loads all fit the pattern split out
a single level of permutes only and mark the load and
permute nodes with ldst_lanes.
(vectorizable_slp_permutation_1): Handle the load-lane permute
forwarding of vector defs.
(vect_analyze_slp): After SLP pattern recog is finished see if
there are any SLP instances that would benefit from using
load/store-lanes and re-discover those with forced single lanes.
* tree-vect-stmts.cc (get_group_load_store_type): Support
load/store-lanes for SLP.
(vectorizable_store): Support SLP code generation for store-lanes.
(vectorizable_load): Support SLP code generation for load-lanes.
* tree-vect-loop.cc (vect_analyze_loop_2): Do not cancel SLP
when store-lanes can be used.
Richard Biener [Mon, 13 May 2024 12:57:01 +0000 (14:57 +0200)]
lower SLP load permutation to interleaving
The following emulates classical interleaving for SLP load permutes
that we are unlikely handling natively. This is to handle cases
where interleaving (or load/store-lanes) is the optimal choice for
vectorizing even when we are doing that within SLP. An example
would be
void foo (int * __restrict a, int * b)
{
for (int i = 0; i < 16; ++i)
{
a[4*i + 0] = b[4*i + 0] * 3;
a[4*i + 1] = b[4*i + 1] + 3;
a[4*i + 2] = (b[4*i + 2] * 3 + 3);
a[4*i + 3] = b[4*i + 3] * 3;
}
}
where currently the SLP store is merging four single-lane SLP
sub-graphs but none of the loads in it can be code-generated
with V4SImode vectors and a VF of four as the permutes would need
three vectors.
The patch introduces a lowering phase after SLP discovery but
before SLP pattern recognition or permute optimization that
analyzes all loads from the same dataref group and creates an
interleaving scheme starting from an unpermuted load.
What can be handled is power-of-two group size and a group size of
three. The possibility for doing the interleaving with a load-lanes
like instruction is done as followup.
For a group-size of three this is done by using
the non-interleaving fallback code which then creates at VF == 4 from
{ { a0, b0, c0 }, { a1, b1, c1 }, { a2, b2, c2 }, { a3, b3, c3 } }
the intermediate vectors { c0, c0, c1, c1 } and { c2, c2, c3, c3 }
to produce { c0, c1, c2, c3 }. This turns out to be more effective
than the scheme implemented for non-SLP for SSE and only slightly
worse for AVX512 and a bit more worse for AVX2. It seems to me that
this would extend to other non-power-of-two group-sizes though (but
the patch does not). Optimal schemes are likely difficult to lay out
in VF agnostic form.
I'll note that while the lowering assumes even/odd extract is
generally available for all vector element sizes (which is probably
a good assumption), it doesn't in any way constrain the other
permutes it generates based on target availability. Again difficult
to do in a VF agnostic way (but at least currently the vector type
is fixed).
I'll also note that the SLP store side merges lanes in a way
producing three-vector permutes for store group-size of three, so
the testcase uses a store group-size of four.
The patch has a fallback for when there are multi-lane groups
and the resulting permutes to not fit interleaving. Code
generation is not optimal when this triggers and might be
worse than doing single-lane group interleaving.
The patch handles gaps by representing them with NULL
entries in SLP_TREE_SCALAR_STMTS for the unpermuted load node.
The SLP discovery changes could be elided if we manually build the
load node instead.
SLP load nodes covering enough lanes to not need intermediate
permutes are retained as having a load-permutation and do not
use the single SLP load node for each dataref group. That's
something we might want to change, making load-permutation
something purely local to SLP discovery (but then SLP discovery
could do part of the lowering).
The patch misses CSEing intermediate generated permutes and
registering them with the bst_map which is possibly required
for SLP pattern detection in some cases - this re-spin of the
patch moves the lowering after SLP pattern detection.
* tree-vect-slp.cc (vect_build_slp_tree_1): Handle NULL stmt.
(vect_build_slp_tree_2): Likewise. Release load permutation
when there's a NULL in SLP_TREE_SCALAR_STMTS and assert there's
no actual permutation in that case.
(vllp_cmp): New function.
(vect_lower_load_permutations): Likewise.
(vect_analyze_slp): Call it.
* gcc.dg/vect/slp-11a.c: Expect SLP.
* gcc.dg/vect/slp-12a.c: Likewise.
* gcc.dg/vect/slp-51.c: New testcase.
* gcc.dg/vect/slp-52.c: New testcase.
[PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32.
Currently, in RV32, even with the D extension enabled, the cost of DFmode
register moves is still set to 'COSTS_N_INSNS (2)'. This results in the
'lower-subreg' pass splitting DFmode register moves into two SImode SUBREG
register moves, leading to the generation of many redundant instructions.
As an example, consider the following test case:
double foo (int t, double a, double b)
{
if (t > 0)
return a;
else
return b;
}
When compiling with -march=rv32imafdc -mabi=ilp32d, the following code is generated:
.cfi_startproc
addi sp,sp,-32
.cfi_def_cfa_offset 32
fsd fa0,8(sp)
fsd fa1,16(sp)
lw a4,8(sp)
lw a5,12(sp)
lw a2,16(sp)
lw a3,20(sp)
bgt a0,zero,.L1
mv a4,a2
mv a5,a3
.L1:
sw a4,24(sp)
sw a5,28(sp)
fld fa0,24(sp)
addi sp,sp,32
.cfi_def_cfa_offset 0
jr ra
.cfi_endproc
After adjust the DFmode register move's cost to 'COSTS_N_INSNS (1)', the
generated code is as follows, with a significant reduction in the number
of instructions.
.cfi_startproc
ble a0,zero,.L5
ret
.L5:
fmv.d fa0,fa1
ret
.cfi_endproc
gcc/
* config/riscv/riscv.cc (riscv_rtx_costs): Optimize the cost of the
DFmode register move for RV32.
gcc/testsuite/
* gcc.target/riscv/rv32-movdf-cost.c: New test.
Jeff Law [Mon, 2 Sep 2024 04:16:04 +0000 (22:16 -0600)]
[committed][PR rtl-optimization/116544] Fix test for promoted subregs
This is a small bug in the ext-dce code's handling of promoted subregs.
Essentially when we see a promoted subreg we need to make additional bit groups
live as various parts of the RTL path know that an extension of a suitably
promoted subreg can be trivially eliminated.
When I added support for dealing with this quirk I failed to account for the
larger modes properly and it ignored the case when the size of the inner object
was > 32 bits. Opps.
This does _not_ fix the outstanding x86 issue. That's caused by something
completely different and more concerning ;(
Bootstrapped and regression tested on x86. Obviously fixes the testcase on
riscv as well.
Pushing to the trunk.
PR rtl-optimization/116544
gcc/
* ext-dce.cc (ext_dce_process_uses): Fix thinko in promoted subreg
handling.
gcc/testsuite/
* gcc.dg/torture/pr116544.c: New test.
Levy Hsu [Mon, 2 Sep 2024 02:24:49 +0000 (10:24 +0800)]
i386: Support vec_cmp for V8BF/V16BF/V32BF in AVX10.2
gcc/ChangeLog:
* config/i386/i386-expand.cc (ix86_use_mask_cmp_p): Add BFmode
for int mask cmp.
* config/i386/sse.md (vec_cmp<mode><avx512fmaskmodelower>): New
vec_cmp expand for VBF modes.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10_2-512-bf-vector-cmpp-1.c: New test.
* gcc.target/i386/avx10_2-bf-vector-cmpp-1.c: Ditto.
Levy Hsu [Mon, 2 Sep 2024 02:24:45 +0000 (10:24 +0800)]
i386: Support vectorized BF16 add/sub/mul/div with AVX10.2 instructions
AVX10.2 introduces several non-exception instructions for BF16 vector.
Enable vectorized BF add/sub/mul/div operation by supporting standard
optab for them.
gcc/ChangeLog:
* config/i386/sse.md (div<mode>3): New expander for BFmode div.
(VF_BHSD): New mode iterator with vector BFmodes.
(<insn><mode>3<mask_name><round_name>): Change mode to VF_BHSD.
(mul<mode>3<mask_name><round_name>): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10_2-512-bf-vector-operations-1.c: New test.
* gcc.target/i386/avx10_2-bf-vector-operations-1.c: Ditto.
i386: Auto vectorize sdot_prod, usdot_prod, udot_prod with AVX10.2 instructions
gcc/ChangeLog:
* config/i386/sse.md (VI1_AVX512VNNIBW): New.
(VI2_AVX10_2): Ditto.
(sdot_prod<mode>): Add AVX10.2
to auto vectorize and combine 512 bit part.
(udot_prod<mode>): Ditto.
(sdot_prodv64qi): Removed.
(udot_prodv64qi): Ditto.
(usdot_prod<mode>): Add AVX10.2 to auto vectorize.
(udot_prod<mode>): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/vnniint16-auto-vectorize-2.c: Only define
TEST when not defined.
* gcc.target/i386/vnniint8-auto-vectorize-2.c: Ditto.
* gcc.target/i386/vnniint16-auto-vectorize-3.c: New test.
* gcc.target/i386/vnniint16-auto-vectorize-4.c: Ditto.
* gcc.target/i386/vnniint8-auto-vectorize-3.c: Ditto.
* gcc.target/i386/vnniint8-auto-vectorize-4.c: Ditto.
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_u_trunc-16.c: New test.
* gcc.target/riscv/sat_u_trunc-17.c: New test.
* gcc.target/riscv/sat_u_trunc-18.c: New test.
* gcc.target/riscv/sat_u_trunc-run-16.c: New test.
* gcc.target/riscv/sat_u_trunc-run-17.c: New test.
* gcc.target/riscv/sat_u_trunc-run-18.c: New test.
The below test is passed for this patch.
* The rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_u_trunc-10.c: New test.
* gcc.target/riscv/sat_u_trunc-11.c: New test.
* gcc.target/riscv/sat_u_trunc-12.c: New test.
* gcc.target/riscv/sat_u_trunc-run-10.c: New test.
* gcc.target/riscv/sat_u_trunc-run-11.c: New test.
* gcc.target/riscv/sat_u_trunc-run-12.c: New test.
Pan Li [Fri, 30 Aug 2024 03:01:37 +0000 (11:01 +0800)]
RISC-V: Add testcases for form 4 of unsigned vector .SAT_ADD IMM
This patch would like to add test cases for the unsigned vector .SAT_ADD
when one of the operand is IMM.
Form 4:
#define DEF_VEC_SAT_U_ADD_IMM_FMT_4(T, IMM) \
T __attribute__((noinline)) \
vec_sat_u_add_imm##IMM##_##T##_fmt_4 (T *out, T *in, unsigned limit) \
{ \
unsigned i; \
T ret; \
for (i = 0; i < limit; i++) \
{ \
out[i] = __builtin_add_overflow (in[i], IMM, &ret) == 0 ? ret : -1; \
} \
}
DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint64_t, 123)
The below test are passed for this patch.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-16.c: New test.
Pan Li [Fri, 30 Aug 2024 00:36:45 +0000 (08:36 +0800)]
RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM
This patch would like to add test cases for the unsigned vector .SAT_ADD
when one of the operand is IMM.
Form 3:
#define DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM) \
T __attribute__((noinline)) \
vec_sat_u_add_imm##IMM##_##T##_fmt_3 (T *out, T *in, unsigned limit) \
{ \
unsigned i; \
T ret; \
for (i = 0; i < limit; i++) \
{ \
out[i] = __builtin_add_overflow (in[i], IMM, &ret) ? -1 : ret; \
} \
}
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 123)
The below test are passed for this patch.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-9.c: New test.
Pan Li [Fri, 30 Aug 2024 06:07:12 +0000 (14:07 +0800)]
RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64
In previous, we have some specially handling for both the .SAT_ADD and
.SAT_SUB for unsigned int. There are similar to take care of SImode
in RV64 for zero extend. Thus refactor these two helper function
into one for possible code duplication.
The below test suite are passed for this patch.
* The rv64gcv fully regression test.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Merge
the zero_extend handing from func riscv_gen_unsigned_xmode_reg.
(riscv_gen_unsigned_xmode_reg): Remove.
(riscv_expand_ussub): Leverage riscv_gen_zero_extend_rtx
instead of riscv_gen_unsigned_xmode_reg.
Andrew Pinski [Sun, 1 Sep 2024 00:23:19 +0000 (17:23 -0700)]
slsr: Use simple_dce_from_worklist in SLSR [PR116554]
While working on a phiopt patch, it was noticed that
SLSR would leave around some unused ssa names. Let's
add simple_dce_from_worklist usage to SLSR to remove
the dead statements. This should give a small improvemnent
for passes afterwards.
Boostrapped and tested on x86_64.
gcc/ChangeLog:
PR tree-optimization/116554
* gimple-ssa-strength-reduction.cc: Include tree-ssa-dce.h.
(replace_mult_candidate): Add sdce_worklist argument, mark
the rhs1/rhs2 for maybe dceing.
(replace_unconditional_candidate): Add sdce_worklist argument,
Update call to replace_mult_candidate.
(replace_conditional_candidate): Add sdce_worklist argument,
update call to replace_mult_candidate.
(replace_uncond_cands_and_profitable_phis): Add sdce_worklist argument,
update call to replace_conditional_candidate,
replace_unconditional_candidate, and replace_uncond_cands_and_profitable_phis.
(replace_one_candidate): Add sdce_worklist argument, mark
the orig_rhs1/orig_rhs2 for maybe dceing.
(replace_profitable_candidates): Add sdce_worklist argument,
update call to replace_one_candidate and replace_profitable_candidates.
(analyze_candidates_and_replace): Call simple_dce_from_worklist and
update calls to replace_profitable_candidates, and
replace_uncond_cands_and_profitable_phis.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
testsuite: Prune compilation messages for modules tests
All testsuite compiler-calls pass default_target_compile in the
dejagnu installation (typically /usr/share/dejagnu/target.exp) which
also calls the dejagnu-installed prune_warnings.
Normally, tests using the dg framework (most or all tests these days)
compile and link by calling various wrappers that end up calling
dg-test in the dejagnu installation, typically installed as
/usr/share/dejagnu/dg.exp. That, besides the compiler call, also
calls ${tool}-dg-prune (g++-dg-prune) on the messages, which in turn
ends up calling prune_gcc_output in gcc/testsuite/lib/prune.exp. That
gcc-specific "pruning" function handles more cases than the dejagnu
prune_warnings, and also has updated patterns.
But, module_do_it in modules.exp calls the lower-level
${tool}_target_compile "directly", i.e. g++_target_compile defined in
gcc/testsuite/lib/g++.exp. That does not call ${tool}-dg-prune,
meaning those test-cases miss the gcc-specific pruning.
Noticed while testing a dejagnu update that handled the miniscule "in"
in the warning (line-breaks added below besides the original one after
"(void*)':")
"/path/to/cris-elf/bin/ld:
/gccobj/cris-elf/./libstdc++-v3/src/.libs/libstdc++.a(random.o): in
function `std::(anonymous namespace)::__libc_getentropy(void*)':
/gccsrc/libstdc++-v3/src/c++11/random.cc:183: warning: _getentropy is
not implemented and will always fail"
The line saying "in function" rather than "In function" (from the
binutils linker since 2018) is pruned by prune_gcc_output. The
prune_warnings in dejagnu-1.6.3 and earlier handles the second line
separately. It's an unfortunate wart that neither consumes the
delimiting line-break, leaving to the callers to prune residual empty
lines. See prune_warnings in dejagnu (default_target_compile and
dg-test) for those other line-break fixups, as alluded in the comment.
Roger Sayle [Sat, 31 Aug 2024 20:17:18 +0000 (14:17 -0600)]
i386: Support read-modify-write memory operands in STV.
This patch enables STV when the first operand of a TImode binary
logic operand (AND, IOR or XOR) is a memory operand, which is commonly
the case with read-modify-write instructions.
A different motivating example from the one given previously is:
__int128 m, p, q;
void foo() {
m ^= (p & q);
}
Currently with -O2 -mavx the RMW instructions are rejected by STV,
resulting in scalar code:
2024-08-31 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/i386/i386-features.cc (timode_scalar_to_vector_candidate_p):
Support the first operand of AND, IOR and XOR being MEM_P, i.e. a
read-modify-write insn.
gcc/testsuite/ChangeLog
* gcc.target/i386/movti-2.c: Change dg-options to -Os.
* gcc.target/i386/movti-4.c: Expected output of original movti-2.c.
Andrew Pinski [Sat, 31 Aug 2024 18:57:32 +0000 (11:57 -0700)]
libobjc: Add cast to void* to disable warning for casting between incompatible function types [PR89586]
Even though __objc_get_forward_imp returns an IMP type, it will be casted to a compatable function
type before calling it. So we adding a cast to `void*` will disable warning about the incompatible type.
Pushed after bootstrap/test on x86_64.
libobjc/ChangeLog:
PR libobjc/89586
* sendmsg.c (__objc_get_forward_imp): Add cast to `void*` before casting to IMP.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Georg-Johann Lay [Fri, 30 Aug 2024 17:38:30 +0000 (19:38 +0200)]
AVR: Run pass avr-fuse-add a second time after pass_cprop_hardreg.
gcc/
* config/avr/avr-passes.cc (avr_pass_fuse_add) <clone>: Override.
* config/avr/avr-passes.def (avr_pass_fuse_add): Run again
after pass_cprop_hardreg.
Georg-Johann Lay [Fri, 30 Aug 2024 17:38:30 +0000 (19:38 +0200)]
AVR: Tidy pass avr-fuse-add.
gcc/
* config/avr/avr-protos.h (avr_split_tiny_move): Rename to
avr_split_fake_addressing_move.
* config/avr/avr-passes.def: Same.
* config/avr/avr-passes.cc: Same.
(avr_pass_data_fuse_add) <tv_id>: Set to TV_MACH_DEP.
* config/avr/avr.md (split-lpmx): Remove a define_split. Such
splits are performed by avr_split_fake_addressing_move.
The 'torture' section of the coroutine tests is primarily about checking
correct operation of the generated code. It should, ideally, be possible
to run this part of the testsuite with '-Wall' and expect no fails. In
the case that we wish to test for a specific diagnostic (and that it does
not appear over a range of optimisation/debug conditions) then we should
make that explict (as done, for example, in pr109867.C).
The tests amended here have warnings because of unused entities; in many
cases those are relevant to the test, and so we just mark them with
__attribute__((__unused__)).
We amend the debug output in coro.h to avoid similar warnings when print
output is disabled (the default).
gcc/testsuite/ChangeLog:
* g++.dg/coroutines/coro.h: Use a variadic macro for PRINTF to
avoid unused warnings when output is disabled.
* g++.dg/coroutines/torture/co-await-04-control-flow.C: Avoid
unused warnings.
* g++.dg/coroutines/torture/co-ret-13-template-2.C: Likewise.
* g++.dg/coroutines/torture/exceptions-test-01-n4849-a.C: Likewise.
* g++.dg/coroutines/torture/local-var-04-hiding-nested-scopes.C:
Likewise.
* g++.dg/coroutines/torture/pr109867.C: Likewise.
Iain Sandoe [Sat, 31 Aug 2024 11:42:36 +0000 (12:42 +0100)]
testsuite, c++, coroutines: Correct a test intent.
The intention of the series of tests numberef pr95615-* is to
verify that entities created by the ramp and potentially needing
destruction are correctly handled when exceptions are thrown.
Because of a typo, one case was not being checked correctly (the
return object). This patch amends the check to test that the
returned object is properly deleted.
gcc/testsuite/ChangeLog:
* g++.dg/coroutines/torture/pr95615.inc: Check tha the
task object produced by get_return_object is correctly
deleted on exception.
Iain Sandoe [Tue, 27 Aug 2024 13:52:26 +0000 (14:52 +0100)]
c++, coroutines: Make and use a frame access helper.
In the review of earlier patches it was suggested that we might make
use of finish_class_access_expr instead of doing a lookup for the
member and then a build_class_access_expr call.
finish_class_access_expr does a lot more work than we need and ends
up calling build_class_access_expr anyway. So, instead, this patch
makes a new helper to do the lookup and build and uses that helper
everywhere except instances in the ramp function that we are going
to handle separately.
Andrew Pinski [Fri, 30 Aug 2024 17:36:24 +0000 (10:36 -0700)]
phiopt: Ignore some nop statements in heursics [PR116098]
The heurstics that was added for PR71016, try to search to see
if the conversion was being moved away from its definition. The problem
is the heurstics would stop if there was a non GIMPLE_ASSIGN (and already ignores
debug statements) and in this case we would have a GIMPLE_LABEL that was not
being ignored. So we should need to ignore GIMPLE_NOP, GIMPLE_LABEL and GIMPLE_PREDICT.
Note this is now similar to how gimple_empty_block_p behaves.
Note this fixes the wrong code that was reported by moving the VCE (conversion) out before
the phiopt/match could convert it into an bit_ior and move the VCE out with the VCE being
conditionally valid.
Bootstrapped and tested on x86_64-linux-gnu.
Also built and tested for aarch64-linux-gnu.
PR tree-optimization/116098
gcc/ChangeLog:
* tree-ssa-phiopt.cc (factor_out_conditional_operation): Ignore
nops, labels and predicts for heuristic for conversion with a constant.
gcc/testsuite/ChangeLog:
* c-c++-common/torture/pr116098-1.c: New test.
* gcc.target/aarch64/csel-1.c: New test.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
projects / thirdparty / gcc.git / log
