Abel Vesa [Wed, 8 Feb 2023 18:00:17 +0000 (20:00 +0200)]
phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs
Add the SM8550 both g4 and g3 configurations. In addition, there is a
new "lane shared" table that needs to be configured for g4, along with
the No-CSR list of resets. The no-CSR allows resetting the PHY without
actually dropping the PHY configuration. The no-CSR needs to be
deasserted only after the PHY has been configured and the PLL has
stabilized.
Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230208180020.2761766-9-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for
PCIE g4x2. Add the new lane shared PCIE specific offsets in a dedicated
header file.
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for
PCIE g4x2. Add the new qserdes TX RX PCIE specific offsets in a
dedicated header file.
Abel Vesa [Wed, 8 Feb 2023 18:00:13 +0000 (20:00 +0200)]
phy: qcom-qmp: pcs-pcie: Add v6 register offsets
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
UFS and PCIE g3x2. Add the new PCS PCIE specific offsets in a dedicated
header file.
Abel Vesa [Wed, 8 Feb 2023 18:00:10 +0000 (20:00 +0200)]
dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550
Document the QMP PCIe PHY compatible for SM8550.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230208180020.2761766-2-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
Stephen Boyd [Thu, 2 Feb 2023 21:53:29 +0000 (13:53 -0800)]
phy: qcom-qmp: Introduce Kconfig symbols for discrete drivers
Introduce a config option for each QMP PHY driver now that the QMP PHY
mega-driver has been split up into different modules. This allows kernel
configurators to limit the binary size of the kernel by only compiling
in the QMP PHY driver that they need.
Leave the old config QCOM_QMP in place and make it into a menuconfig so
that 'make olddefconfig' continues to work. Furthermore, set the default
of the new Kconfig symbols to be QCOM_QMP so that the transition is
smooth.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20230202215330.2152726-1-swboyd@chromium.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
usb: host: ohci-exynos: Convert to devm_of_phy_optional_get()
Use the new devm_of_phy_optional_get() helper instead of open-coding the
same operation.
As devm_of_phy_optional_get() returns NULL if either the PHY cannot be
found, or if support for the PHY framework is not enabled, it is no
longer needed to check for -ENODEV or -ENOSYS.
This lets us drop several checks for IS_ERR(), as phy_power_{on,off}()
handle NULL parameters fine.
usb: host: ehci-exynos: Convert to devm_of_phy_optional_get()
Use the new devm_of_phy_optional_get() helper instead of open-coding the
same operation.
As devm_of_phy_optional_get() returns NULL if either the PHY cannot be
found, or if support for the PHY framework is not enabled, it is no
longer needed to check for -ENODEV or -ENOSYS.
This lets us drop several checks for IS_ERR(), as phy_power_{on,off}()
handle NULL parameters fine.
net: fman: memac: Convert to devm_of_phy_optional_get()
Use the new devm_of_phy_optional_get() helper instead of open-coding the
same operation.
As devm_of_phy_optional_get() returns NULL if either the PHY cannot be
found, or if support for the PHY framework is not enabled, it is no
longer needed to check for -ENODEV or -ENOSYS.
Chunfeng Yun [Wed, 18 Jan 2023 08:43:41 +0000 (16:43 +0800)]
phy: mediatek: remove temporary variable @mask_
Remove the temporary @mask_, this may cause build warning when use clang
compiler for powerpc, but can't reproduce it when compile for arm64.
the build warning is caused by:
"warning: result of comparison of constant 18446744073709551615 with
expression of type (aka 'unsigned long') is always false
[-Wtautological-constant-out-of-range-compare]"
More information provided in below lore link.
After removing @mask_, there is a "CHECK:MACRO_ARG_REUSE" when run
checkpatch.pl, but due to @mask is constant, no reuse problem will happen.
Abel Vesa [Tue, 17 Jan 2023 22:41:47 +0000 (00:41 +0200)]
phy: qcom-qmp: pcs-ufs: Add v6 register offsets
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
UFS and PCIE g3x2. Add the new PCS UFS specific offsets in a dedicated
header file.
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB,
UFS and PCIE g3x2. Add the new qserdes TX RX but UFS specific offsets
in a dedicated header file.
Abel Vesa [Tue, 17 Jan 2023 22:41:43 +0000 (00:41 +0200)]
dt-bindings: phy: Add QMP UFS PHY comptible for SM8550
Document the QMP UFS PHY compatible for SM8550.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230117224148.1914627-2-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
Dmitry Baryshkov [Fri, 13 Jan 2023 21:21:38 +0000 (23:21 +0200)]
phy: qcom-qmp-usb: fix the regs layout table for sdx65 uniphy PHY
The sdx64 uniphy gen3x1 PHY references the qmp_v4_usb3phy_regs_layout
while the PHY itself uses v5 regs. While there are only minor
differences between v4 and v5 regs and none of them concerns registers
mentions in regs_layout, switch the PHY to use
qmp_v5_usb3phy_regs_layout, to remove possible confusion.
Dmitry Baryshkov [Fri, 13 Jan 2023 21:21:37 +0000 (23:21 +0200)]
phy: qcom-qmp-pcie: fix the regs layout table for sm8450 gen3x1 PHY
The sm8450 gen3x1 PHY references the pciephy_v4_regs_layout while the
PHY itself uses v5 regs. While there are only minor differences between
v4 and v5 regs and none of them concerns registers mentions in
regs_layout, switch the PHY to use pciephy_v5_regs_layout to remove
possible confusion.
Dmitry Baryshkov [Fri, 13 Jan 2023 21:21:02 +0000 (23:21 +0200)]
phy: qcom-qmp-combo: rework regs layout arrays
Use symbolic names for the values inside reg layout arrays. New register
names are added following the PCS register layout that is used by the
particular PHY.
Note: ipq8074 tables appear to use a mixture of v2 and v3 registers.
This might need additional fixes.
Dmitry Baryshkov [Fri, 13 Jan 2023 19:55:15 +0000 (21:55 +0200)]
phy: qualcomm: qmp-ufs: rename qmp_ufs_offsets_v5 to qmp_ufs_offsets
All currently known QMP UFS PHYs have the same offsets for register
sub-regions. Instead of using qmp_ufs_offsets_v5 for older generations
of PHYs, rename the offsets struct instance to remove _v5 suffix.
Sinthu Raja [Fri, 13 Jan 2023 15:06:15 +0000 (20:36 +0530)]
phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap
The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved
for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the
USB PHY that is integrated into the SerDes IP. The WIZ control register
has to be configured to support this lane swap feature.
The support for swapping lanes 2 and 3 is missing and therefore
add support to configure the control register to swap between
lanes 2 and 3 if PHY type is USB.
Sinthu Raja [Fri, 13 Jan 2023 15:06:14 +0000 (20:36 +0530)]
phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not specified
It's possible that the Type-C plug orientation on the DIR line will be
implemented through hardware design. In that situation, there won't be
an external GPIO line available, but the driver still needs to address
this since the DT won't use the typec-dir-gpios property.
Add code to handle LN10 Type-C swap if typec-dir-gpios property is not
specified in DT.
phy: qcom-qmp-ufs: Add HS G4 mode support to SC8280XP SoC
UFS PHY in SC8280XP SoC is capable of operating at HS G4 mode and the init
sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance
reusing the G4 init sequence of SM8350.
phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoC
UFS PHY in SM8450 SoC is capable of operating at HS G4 mode and the init
sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance
reusing the G4 init sequence of SM8350.
phy: qcom-qmp-ufs: Avoid setting HS G3 specific registers
SM8350 default init sequence sets some PCS registers to HS G3, thereby
disabling HS G4 mode. This has the effect on MPHY capability negotiation
between the host and the device during link startup and causes the
PA_MAXHSGEAR to G3 irrespective of device max gear.
Due to that, the agreed gear speed determined by the UFS core will become
G3 only and the platform won't run at G4.
So, let's remove setting these registers for SM8350 as like other G4
compatible platforms. One downside of this is that, when the board design
uses non-G4 compatible device, then MPHY will continue to run in the
default mode (G4) even if UFSHCD runs in G3. But this is the case for
other platforms as well.
phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC
UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the
required register settings using the tables_hs_g4 struct instance. This
also requires a separate qmp_phy_cfg for SM8250 instead of reusing SM8150.
phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 mode
Add separate tables_hs_g4 instance to allow the PHY driver to configure the
PHY in HS G4 mode. The individual SoC configs need to supply the Rx, Tx and
PCS register setting in tables_hs_g4 and the UFS driver can request the
Hs G4 mode by calling phy_set_mode_ext() with submode set to UFS_HS_G4.
phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode
Add separate tables_hs_b instance to allow the PHY driver to configure the
PHY in HS Series B mode. The individual SoC configs need to supply the
serdes register setting in tables_hs_b and the UFS driver can request the
Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B.
phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls struct
As done for Qcom PCIe PHY driver, let's move the register settings to the
common qmp_phy_cfg_tbls struct. This helps in adding any additional PHY
settings needed for functionalities like HS-G4 in the future by adding one
more instance of the qmp_phy_cfg_tbls.
Only MSM8996 is using "_ufs_" naming convention for PHY definitions instead
of "_ufsphy_" as like other SoCs. So to maintain the uniformity, let's
rename all of the definitions to use "_ufsphy_".
phy: qcom-qmp-ufs: Remove _tbl suffix from qmp_phy_init_tbl definitions
Following the other QMP PHY drivers like PCIe, let's remove the "_tbl"
suffix from the qmp_phy_init_tbl definitions. This helps in maintaining
the uniformity across all of the QMP PHY drivers.
Lux Aliaga [Sun, 8 Jan 2023 19:53:33 +0000 (16:53 -0300)]
phy: qcom-qmp: Add SM6125 UFS PHY support
The SM6125 UFS PHY is compatible with the one from SM6115. Add a
compatible for it and modify the config from SM6115 to make them
compatible with the SC8280XP binding
dt-bindings: phy: qcom,sc7180-qmp-usb3-dp-phy: correct clocks per variants
Different variants of Qualcomm USB3 DP PHY take different clocks
(according to upstream DTS and Linux driver):
sc7280-herobrine-crd.dtb: phy-wrapper@88e9000: clocks: [[43, 151], [39, 0], [43, 153]] is too short
sc7280-herobrine-crd.dtb: phy-wrapper@88e9000: clock-names:1: 'cfg_ahb' was expected
...
sm8250-hdk.dtb: phy@88e9000: clocks: [[46, 185], [44, 0], [46, 187]] is too short
sm8250-hdk.dtb: phy@88e9000: clock-names:1: 'cfg_ahb' was expected
dt-bindings: phy: qcom,qusb2: do not define properties in "if" block
It is more readable to define properties in top-level "properties:" and
restrict them (if needed) per compatible in the "if" block. Defining
properties in "if" block does not work correctly with
additionalProperties:false:
sc7180-trogdor-pazquel-lte-ti.dtb: phy@88e3000: 'qcom,bias-ctrl-value', 'qcom,charge-ctrl-value', 'qcom,hsdisc-trim-value',
'qcom,imp-res-offset-value', 'qcom,preemphasis-level', 'qcom,preemphasis-width' do not match any of the regexes: 'pinctrl-[0-9]+'
dt-bindings: phy: qcom,usb-snps-femto-v2: use fallback compatibles
Document SoC-specific compatibles with generic fallback (e.g.
qcom,usb-snps-hs-7nm-phy) already used in DTSI. Add SoC-specific
compatibles for PHY on SDX55 and SDX65.
This disallows usage of the qcom,usb-snps-hs-5nm-phy and
qcom,usb-snps-hs-7nm-phy generic compatibles alone. Do not touch
remaining two compatibles - qcom,usb-snps-femto-v2-phy and
qcom,sc8180x-usb-hs-phy - because there are no upstream users, so not
sure what was the intention for them.
This fixes warnings like:
sa8295p-adp.dtb: phy@88e5000: compatible: 'oneOf' conditional failed, one must be fixed:
['qcom,sc8280xp-usb-hs-phy', 'qcom,usb-snps-hs-5nm-phy'] is too long
'qcom,sc8280xp-usb-hs-phy' is not one of ['qcom,sm8150-usb-hs-phy', 'qcom,sm8250-usb-hs-phy', 'qcom,sm8350-usb-hs-phy', 'qcom,sm8450-usb-hs-phy']
'qcom,usb-snps-hs-7nm-phy' was expected
phy: renesas: r8a779f0-eth-serdes: Remove retry code in .init()
Remove retry code in r8a779f0_eth_serdes_init() because
r8a779f0_eth_serdes_chan_setting() was fixed so that no timeout
happened in the initializing procedure.
phy: renesas: r8a779f0-eth-serdes: Add .power_on() into phy_ops
Add r8a779f0_eth_serdes_power_on() to initialize the hardware for
each channel from the step 9 or later on the datasheet. In other words,
the procedure from the step 1 to 8 is for all channel and it is needed
once only. So, the .init() in any channel instance is called, this
driver initializes the hardware from step 1 to 8. And then, .power_on()
is called, this driver initializes the hardware from step 9 or later.
Bhupesh Sharma [Tue, 13 Dec 2022 12:28:43 +0000 (17:58 +0530)]
phy: qcom-qmp-usb: Add Qualcomm SM6115 / SM4250 USB3 PHY support
Enable SM6115 / SM4250 USB3 PHY support by adding the
qmp_phy_cfg data. Since this PHY is the same as the
one used on QCM2290, reuse the QCM2290 qmp_phy_cfg data
already available.
Bhupesh Sharma [Tue, 13 Dec 2022 12:28:42 +0000 (17:58 +0530)]
phy: qcom-qmp-usb: Fix QSERDES_V3_RX_UCDR_PI_CONTROLS init val
As per the Qualcomm QMP v3 PHY programming guide document,
QSERDES_V3_RX_UCDR_PI_CONTROLS configuration should be set to an
initial configuration value of 0x80.
Andre Przywara [Mon, 9 Jan 2023 01:22:23 +0000 (01:22 +0000)]
phy: sun4i-usb: Replace types with explicit quirk flags
So far we were assigning some crude "type" (SoC name, really) to each
Allwinner USB PHY model, then guarding certain quirks based on this.
This does not only look weird, but gets more or more cumbersome to
maintain.
Remove the bogus type names altogether, instead introduce flags for each
quirk, and explicitly check for them.
This improves readability, and simplifies future extensions.
Icenowy Zheng [Mon, 9 Jan 2023 01:22:21 +0000 (01:22 +0000)]
dt-bindings: phy: add binding document for Allwinner F1C100s USB PHY
Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs,
because it has only one OTG USB controller, no host-only OHCI/EHCI
controllers.
Add a binding document for it. Following the current situation of one
YAML file per SoC, this one is based on
allwinner,sun8i-v3s-usb-phy.yaml, but with OHCI/EHCI-related bits
removed. (The same driver in Linux, phy-sun4i-usb, covers all these
binding files now.)
Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20230109012223.4079299-2-andre.przywara@arm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Sing-Han Chen [Wed, 11 Jan 2023 11:04:49 +0000 (11:04 +0000)]
phy: tegra: xusb: Add Tegra234 support
Add support for the XUSB pad controller found on Tegra234 SoCs. It is
mostly similar to the same IP found on Tegra194, because most of
the Tegra234 XUSB PADCTL registers definition and programming sequence
are the same as Tegra194, Tegra234 XUSB PADCTL can share the same
driver with Tegra186 and Tegra194 XUSB PADCTL.
Introduce a new feature, USB2 HW tracking, for Tegra234.
The feature is to enable HW periodical PAD tracking which measure
and capture the electric parameters of USB2.0 PAD.
Signed-off-by: Sing-Han Chen <singhanc@nvidia.com> Co-developed-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20230111110450.24617-6-jonathanh@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Dmitry Baryshkov [Thu, 10 Nov 2022 19:22:48 +0000 (22:22 +0300)]
phy: qcom-qmp: move type-specific headers to particular driver
Remove QMP PHY type-specific headers inclusion from the common header
and move them to the specific PHY drivers to cleanup the namespaces used
by different drivers.
Dmitry Baryshkov [Thu, 10 Nov 2022 19:22:47 +0000 (22:22 +0300)]
phy: qcom-qmp-usb: fix regs layout arrays
Drop qcm2290_usb3phy_regs_layout, it is a duplicate of
qmp_v3_usb3phy_regs_layout. Introduce qmp_v5_usb3phy_regs_layout to be
used for sm8350 and sc8280xp.
Dmitry Baryshkov [Thu, 10 Nov 2022 19:22:46 +0000 (22:22 +0300)]
phy: qcom-qmp-usb: rework regs layout arrays
Use symbolic names for the values inside reg layout arrays. New register
names are added following the PCS register layout that is used by the
particular PHY.
Note: ipq8074 tables appear to use a mixture of v2 and v3 registers.
This might need additional fixes.
Dmitry Baryshkov [Thu, 10 Nov 2022 19:22:42 +0000 (22:22 +0300)]
phy: qcom-qmp-ufs: rework regs layout arrays
Use symbolic names for the values inside reg layout arrays. New register
names are added following the PCS register layout that is used by the
particular PHY.
Use symbolic names for the values inside reg layout arrays. New register
names are added following the PCS register layout that is used by the
particular PHY.
Note: ipq8074 tables appear to use a mixture of v2 and v3 registers.
This might need additional fixes.
Dmitry Baryshkov [Wed, 23 Nov 2022 10:44:41 +0000 (12:44 +0200)]
phy: qcom-qmp-ufs: provide symbol clocks
Register three UFS symbol clocks (ufs_rx_symbol_0_clk_src,
ufs_rx_symbol_1_clk_src ufs_tx_symbol_0_clk_src). Register OF clock
provider to let other devices link these clocks through the DT.
treewide: Convert del_timer*() to timer_shutdown*()
Due to several bugs caused by timers being re-armed after they are
shutdown and just before they are freed, a new state of timers was added
called "shutdown". After a timer is set to this state, then it can no
longer be re-armed.
The following script was run to find all the trivial locations where
del_timer() or del_timer_sync() is called in the same function that the
object holding the timer is freed. It also ignores any locations where
the timer->function is modified between the del_timer*() and the free(),
as that is not considered a "trivial" case.
This was created by using a coccinelle script and the following
commands:
Linus Torvalds [Fri, 23 Dec 2022 22:44:08 +0000 (14:44 -0800)]
Merge tag 'spi-fix-v6.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fix from Mark Brown:
"One driver specific change here which handles the case where a SPI
device for some reason tries to change the bus speed during a message
on fsl_spi hardware, this should be very unusual"
* tag 'spi-fix-v6.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
spi: fsl_spi: Don't change speed while chipselect is active
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