Swaraj Gaikwad [Mon, 15 Dec 2025 02:28:50 +0000 (02:28 +0000)]
drm/msm: Replace custom dumb_map_offset with generic helper
The msm driver implements a custom dumb_map_offset callback. This
implementation acquires the msm_gem_lock, but the underlying
drm_gem_create_mmap_offset() function is already thread-safe regarding
the VMA offset manager (it acquires the mgr->vm_lock internally).
Switching to the generic drm_gem_dumb_map_offset() helper provides
several benefits:
1. Removes the unnecessary locking overhead (locking leftovers).
2. Adds a missing check to reject mapping of imported objects, which is
invalid for dumb buffers.
3. Allows for the removal of the msm_gem_dumb_map_offset() wrapper and
the msm_gem_mmap_offset() helper function.
The logic from msm_gem_mmap_offset() has been inlined into
msm_ioctl_gem_info() to maintain functionality without the separate
helper.
This addresses the TODO:
"Documentation/gpu/todo.rst: Remove custom dumb_map_offset implementations"
Signed-off-by: Swaraj Gaikwad <swarajgaikwad1925@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/694727/
Message-ID: <20251215022850.12358-1-swarajgaikwad1925@gmail.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Dmitry Baryshkov [Fri, 21 Nov 2025 16:13:04 +0000 (18:13 +0200)]
drm/msm/a2xx: add A225 entry to catalog
Add catalog entry for Adreno A225.6 as present on MSM8960v3. Most of the
pieces were already contributed by Jonathan Marek in commit 21af872cd8c6
("drm/msm/adreno: add a2xx"), but weren't enabled because there was no
GPU entry.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689908/
Message-ID: <20251121-a225-v1-2-a1bab651d186@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Konrad Dybcio [Mon, 29 Dec 2025 20:47:39 +0000 (21:47 +0100)]
dt-bindings: display/msm/gpu: Straighten out reg-names on A619L/610/702
These GPUs have physically have the same regions as the base case
("main" + "cx_mem" + "cx_dbgc"). Remove the specific override.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org>
Patchwork: https://patchwork.freedesktop.org/patch/696547/
Message-ID: <20251229-topic-6115_2290_gpu_dbgc-v1-1-4a24d196389c@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Jie Zhang [Wed, 31 Dec 2025 08:45:25 +0000 (14:15 +0530)]
dt-bindings: display/msm/rgmu: Document A612 RGMU
RGMU a.k.a Reduced Graphics Management Unit is a small state machine
with the sole purpose of providing IFPC (Inter Frame Power Collapse)
support. Compared to GMU, it doesn't manage GPU clock, voltage
scaling, bw voting or any other functionalities. All it does is detect
an idle GPU and toggle the GDSC switch. As it doesn't access DDR space,
it doesn't require iommu.
So far, only Adreno 612 GPU has an RGMU core. Document it in
qcom,adreno-rgmu.yaml.
Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Patchwork: https://patchwork.freedesktop.org/patch/696679/
Message-ID: <20251231-qcs615-spin-2-v6-4-da87debf6883@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Wed, 31 Dec 2025 08:45:24 +0000 (14:15 +0530)]
dt-bindings: display/msm: gpu: Document A612 GPU
A612 GPU has a new IP called RGMU (Reduced Graphics Management Unit)
which replaces GMU. But it doesn't do clock or voltage scaling. So we
need the gpu core clock in the GPU node along with the power domain to
do clock and voltage scaling from the kernel. Update the bindings to
describe this GPU.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/696676/
Message-ID: <20251231-qcs615-spin-2-v6-3-da87debf6883@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
JSON Schema conditionals can become complex and error-prone when combined
with regex patterns. To improve readability and maintainability, replace
nested if-else blocks with a flattened structure using explicit enums.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/696674/
Message-ID: <20251231-qcs615-spin-2-v6-2-da87debf6883@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Wed, 31 Dec 2025 08:45:22 +0000 (14:15 +0530)]
drm/msm/a6xx: Retrieve gmu core range by index
Some GPUs like A612 doesn't use a named register range resource. This
is because the reg-name property is discouraged when there is just a
single resource.
To address this, retrieve the 'gmu' register range by its index. It is
always guaranteed to be at index 0.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/696673/
Message-ID: <20251231-qcs615-spin-2-v6-1-da87debf6883@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Rob Clark [Fri, 9 Jan 2026 15:37:29 +0000 (07:37 -0800)]
drm/msm: Fix GMEM_BASE for gen8
This should also be zero for gen8. This does change a7xx-gen1 to zero.
It was almost certainly incorrect before, but we have no such devices in
CI currently.
Fixes: 288a93200892 ("drm/msm/adreno: Introduce A8x GPU Support") Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/697779/
Message-ID: <20260109153730.130462-3-robin.clark@oss.qualcomm.com>
Johan Hovold [Sun, 21 Dec 2025 16:45:52 +0000 (17:45 +0100)]
drm/msm/a6xx: fix bogus hwcg register updates
The hw clock gating register sequence consists of register value pairs
that are written to the GPU during initialisation.
The a690 hwcg sequence has two GMU registers in it that used to amount
to random writes in the GPU mapping, but since commit 188db3d7fe66
("drm/msm/a6xx: Rebase GMU register offsets") they trigger a fault as
the updated offsets now lie outside the mapping. This in turn breaks
boot of machines like the Lenovo ThinkPad X13s.
Note that the updates of these GMU registers is already taken care of
properly since commit 40c297eb245b ("drm/msm/a6xx: Set GMU CGC
properties on a6xx too"), but for some reason these two entries were
left in the table.
Fixes: 5e7665b5e484 ("drm/msm/adreno: Add Adreno A690 support") Cc: stable@vger.kernel.org # 6.5 Cc: Bjorn Andersson <andersson@kernel.org> Cc: Konrad Dybcio <konradybcio@kernel.org> Signed-off-by: Johan Hovold <johan@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Fixes: 188db3d7fe66 ("drm/msm/a6xx: Rebase GMU register offsets")
Patchwork: https://patchwork.freedesktop.org/patch/695778/
Message-ID: <20251221164552.19990-1-johan@kernel.org> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Brian Masney [Thu, 8 Jan 2026 21:16:42 +0000 (16:16 -0500)]
drm/msm/dsi_phy_14nm: convert from divider_round_rate() to divider_determine_rate()
The divider_round_rate() function is now deprecated, so let's migrate
to divider_determine_rate() instead so that this deprecated API can be
removed.
Note that when the main function itself was migrated to use
determine_rate, this was mistakenly converted to:
req->rate = divider_round_rate(...)
This is invalid in the case when an error occurs since it can set the
rate to a negative value.
Fixes: cc41f29a6b04 ("drm/msm/dsi_phy_14nm: convert from round_rate() to determine_rate()") Signed-off-by: Brian Masney <bmasney@redhat.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/697613/ Link: https://lore.kernel.org/r/20260108-clk-divider-round-rate-v1-24-535a3ed73bf3@redhat.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Dmitry Baryshkov [Sun, 28 Dec 2025 04:02:29 +0000 (06:02 +0200)]
drm/msm/mdp5: drop support for MSM8998, SDM630 and SDM660
Currently MDP5 3.x (MSM8998, SDM630 and SDM660) platforms are support
by both DPU and MDP5 drivers. Support for them in the DPU driver is
mature enough, so it's no longer sensible to keep them enabled in the
MDP5 driver. Not to mention that MSM8998 never used an MDP5 compatible
string. Drop support for the MDP5 3.x genration inside the MDP5
driver and migrate those to the DPU driver only.
Note: this will break if one uses the DT generated before v6.3 as they
had only the generic, "qcom,mdp5" compatible string for SDM630 and
SDM660. However granted that we had two LTS releases inbetween I don't
think it is an issue.
Dmitry Baryshkov [Sun, 28 Dec 2025 04:02:28 +0000 (06:02 +0200)]
drm/msm/dpu: fix CMD panels on DPU 1.x - 3.x
DPU units before 4.x don't have a separate CTL_START IRQ to mark the
begin of the data transfer. In such a case, wait for the frame transfer
to complete rather than trying to wait for the CTL_START interrupt (and
obviously hitting the timeout).
Dmitry Baryshkov [Fri, 14 Nov 2025 03:43:39 +0000 (05:43 +0200)]
drm/msm/dpu: use standard functions in _dpu_format_populate_plane_sizes_ubwc()
The _dpu_format_populate_plane_sizes_ubwc() used MSM_MEDIA_ALIGN() and
MSM_MEDIA_ROUNDUP(), macros inherited from the previous implementation,
msm_media_info.h. Replace them with the standard Linux macros,
round_up() and DIV_ROUND_UP() respectively.
Dmitry Baryshkov [Fri, 14 Nov 2025 03:43:37 +0000 (05:43 +0200)]
drm/msm/dpu: drop redundant num_planes assignment in _dpu_format_populate_plane_sizes*()
Drop redundant layout->num_planes assignments, using the value assigned
from the formats table. RGB UBWC formats need special handling: they use
two planes (per the format table), but the uAPI defines plane[1] as
empty.
Move common bits of _dpu_format_populate_plane_sizes_ubwc() and
_linear() to dpu_format_populate_plane_sizes(), reducing unnecessary
duplication and simplifying code flow fror the UBWC function.
Dmitry Baryshkov [Fri, 14 Nov 2025 03:43:30 +0000 (05:43 +0200)]
drm/msm/disp: set num_planes, fetch_mode and tile_height in INTERLEAVED_RGB_FMT_TILED
All interleaved compressed RGB formats use only 2 planes,
MDP_FETCH_LINEAR and MDP_TILE_HEIGHT_UBWC. Specify num_planes,
fetch_mode and tile_height directly in the macro and remove unused
parameters.
Dmitry Baryshkov [Fri, 14 Nov 2025 03:43:29 +0000 (05:43 +0200)]
drm/msm/disp: set num_planes and fetch_mode in INTERLEAVED_RGB_FMT
All interleaved RGB formats use only 1 plane and MDP_FETCH_LINEAR.
Specify num_planes and fetch_mode directly in the macro and remove
unused parameters.
Dmitry Baryshkov [Fri, 14 Nov 2025 03:43:28 +0000 (05:43 +0200)]
drm/msm/disp: set num_planes to 1 for interleaved YUV formats
Interleaved YUV formats use only one plane for all pixel data. Specify
num_planes = 1 for those formats. This was left unnoticed since
_dpu_format_populate_plane_sizes_linear() overrides layout->num_planes.
Dan Carpenter [Thu, 8 Jan 2026 19:57:22 +0000 (22:57 +0300)]
drm/msm: remove some dead code
This is supposed to test for integer overflow but it is wrong and
unnecessary. The size_add()/mul() macros return SIZE_MAX when there is
an integer overflow. This code saves the SIZE_MAX to a u64 and then
tests if the result is greater than SIZE_MAX which it never will be.
Fortunately, when we try to allocate SIZE_MAX bytes the allocation
will fail. We even pass __GFP_NOWARN so the allocation fails
harmlessly and quietly.
Dale Whinham [Thu, 18 Dec 2025 00:19:32 +0000 (00:19 +0000)]
drm/msm/dp: Enable support for eDP v1.4+ link rates table
The MSM DRM driver currently does not support panels which report their
supported link rates via the SUPPORTED_LINK_RATES table.
For panels which do not offer the optional eDP v1.3 fallback via
MAX_LINK_RATE, this will cause a panel probe failure (e.g. Samsung
ATNA30DW01-1 as found in Microsoft Surface Pro 11).
Detect eDP v1.4 panels and parse the SUPPORTED_LINK_RATES table when
present.
Additionally, set the rate using LINK_RATE_SET instead of LINK_BW_SET,
but only if LINK_BW_SET hasn't already been written to.
Dmitry Baryshkov [Tue, 30 Dec 2025 07:17:57 +0000 (09:17 +0200)]
drm/msm/dpu: fix WD timer handling on DPU 8.x
Since DPU 8.x Watchdog timer settings were moved from the TOP to the
INTF block. Support programming the timer in the INTF block. Fixes tag
points to the commit which removed register access to those registers on
DPU 8.x+ (and which also should have added proper support for WD timer
on those devices).
Fixes: 43e3293fc614 ("drm/msm/dpu: add support for MDP_TOP blackhole") Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/696586/ Link: https://lore.kernel.org/r/20251230-intf-fix-wd-v6-2-98203d150611@oss.qualcomm.com
Teguh Sobirin [Tue, 30 Dec 2025 07:17:56 +0000 (09:17 +0200)]
drm/msm/dpu: Set vsync source irrespective of mdp top support
Since DPU 5.x the vsync source TE setup is split between MDP TOP and
INTF blocks. Currently all code to setup vsync_source is only executed
if MDP TOP implements the setup_vsync_source() callback. However on
DPU >= 8.x this callback is not implemented, making DPU driver skip all
vsync setup. Move the INTF part out of this condition, letting DPU
driver to setup TE vsync selection on all new DPU devices.
Mahadevan P [Thu, 1 Jan 2026 05:04:38 +0000 (10:34 +0530)]
drm/msm/disp/dpu: add merge3d support for sc7280
On SC7280 targets, display modes with a width greater than the
max_mixer_width (2400) are rejected during mode validation when
merge3d is disabled. This limitation exists because, without a
3D merge block, two layer mixers cannot be combined(non-DSC interface),
preventing large layers from being split across mixers. As a result,
higher resolution modes cannot be supported.
Enable merge3d support on SC7280 to allow combining streams from
two layer mixers into a single non-DSC interface. This capability
removes the width restriction and enables buffer sizes beyond the
2400-pixel limit.
Fixes: 591e34a091d1 ("drm/msm/disp/dpu1: add support for display for SC7280 target") Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/696713/ Link: https://lore.kernel.org/r/20260101-4k-v2-1-712ae3c1f816@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Ayushi Makhija [Sun, 4 Jan 2026 13:44:39 +0000 (19:14 +0530)]
dt-bindings: msm: dsi-controller-main: document the QCS8300 DSI CTRL
QCS8300 MDSS DSI controller reuses the same IP as SA8775P, with
identical register layout and programming model. Introduce a
QCS8300-specific compatible with a fallback to
`qcom,sa8775p-dsi-ctrl` to reflect this hardware reuse.
Ayushi Makhija [Sun, 4 Jan 2026 13:44:38 +0000 (19:14 +0530)]
dt-bindings: display: msm-dsi-phy-7nm: document the QCS8300 DSI PHY
QCS8300 uses the same 5nm MDSS DSI PHY IP as SA8775P, sharing
an identical register layout and programming model. Introduce a
QCS8300-specific compatible with a fallback to `qcom,sa8775p-dsi-phy-5nm`
to reflect this hardware reuse.
Evan Lambert [Wed, 24 Dec 2025 12:44:22 +0000 (12:44 +0000)]
drm/msm: Replace unsafe snprintf usage with scnprintf
The refill_buf function uses snprintf to append to a fixed-size buffer.
snprintf returns the length that would have been written, which can
exceed the remaining buffer size. If this happens, ptr advances beyond
the buffer and rem becomes negative. In the 2nd iteration, rem is
treated as a large unsigned integer, causing snprintf to write oob.
While this behavior is technically mitigated by num_perfcntrs being
locked at 5, it's still unsafe if num_perfcntrs were ever to change/a
second source was added.
Nikolay Kuratov [Thu, 11 Dec 2025 09:36:30 +0000 (12:36 +0300)]
drm/msm/dpu: Add missing NULL pointer check for pingpong interface
It is checked almost always in dpu_encoder_phys_wb_setup_ctl(), but in a
single place the check is missing.
Also use convenient locals instead of phys_enc->* where available.
Cc: stable@vger.kernel.org Fixes: d7d0e73f7de33 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback") Signed-off-by: Nikolay Kuratov <kniv@yandex-team.ru> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/693860/ Link: https://lore.kernel.org/r/20251211093630.171014-1-kniv@yandex-team.ru Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Randy Dunlap [Fri, 19 Dec 2025 18:46:38 +0000 (10:46 -0800)]
drm/msm: msm_iommu.c: fix all kernel-doc warnings
Correct or add kernel-doc comments to eliminate all warnings:
Warning: ../drivers/gpu/drm/msm/msm_iommu.c:381 expecting prototype for
alloc_pt(). Prototype was for msm_iommu_pagetable_alloc_pt() instead
Warning: ../drivers/gpu/drm/msm/msm_iommu.c:426 expecting prototype for
free_pt(). Prototype was for msm_iommu_pagetable_free_pt() instead
Randy Dunlap [Fri, 19 Dec 2025 18:46:37 +0000 (10:46 -0800)]
drm/msm: msm_gpu.h: fix all kernel-doc warnings
Correct or add kernel-doc comments to eliminate all warnings:
Warning: drivers/gpu/drm/msm/msm_gpu.h:119 Incorrect use of kernel-doc
format: * devfreq: devfreq instance
Warning: drivers/gpu/drm/msm/msm_gpu.h:125 Incorrect use of kernel-doc
format: * idle_freq:
Warning: drivers/gpu/drm/msm/msm_gpu.h:136 Incorrect use of kernel-doc
format: * boost_constraint:
Warning: drivers/gpu/drm/msm/msm_gpu.h:144 Incorrect use of kernel-doc
format: * busy_cycles: Last busy counter value, for calculating elapsed
busy
Warning: drivers/gpu/drm/msm/msm_gpu.h:156 Incorrect use of kernel-doc
format: * idle_work:
Warning: drivers/gpu/drm/msm/msm_gpu.h:163 Incorrect use of kernel-doc
format: * boost_work:
Warning: drivers/gpu/drm/msm/msm_gpu.h:170 struct member 'devfreq' not
described in 'msm_gpu_devfreq'
Warning: drivers/gpu/drm/msm/msm_gpu.h:170 struct member 'boost_freq' not
described in 'msm_gpu_devfreq'
Warning: drivers/gpu/drm/msm/msm_gpu.h:172 struct member 'devfreq' not
described in 'msm_gpu_devfreq'
Warning: drivers/gpu/drm/msm/msm_gpu.h:172 struct member 'lock' not
described in 'msm_gpu_devfreq'
Warning: drivers/gpu/drm/msm/msm_gpu.h:172 struct member 'governor' not
described in 'msm_gpu_devfreq'
Warning: drivers/gpu/drm/msm/msm_gpu.h:172 struct member 'we are
continuing to sample busyness and * adjust frequency while the GPU is
idle' not described in 'msm_gpu_devfreq'
Warning: drivers/gpu/drm/msm/msm_gpu.h:172 struct member 'boost_freq' not
described in 'msm_gpu_devfreq'
Warning: drivers/gpu/drm/msm/msm_gpu.h:172 struct member 'busy_cycles'
not described in 'msm_gpu_devfreq'
Warning: drivers/gpu/drm/msm/msm_gpu.h:172 struct member 'time' not
described in 'msm_gpu_devfreq'
Warning: drivers/gpu/drm/msm/msm_gpu.h:172 struct member 'idle_time' not
described in 'msm_gpu_devfreq'
Warning: drivers/gpu/drm/msm/msm_gpu.h:172 struct member 'idle_work' not
described in 'msm_gpu_devfreq'
Warning: drivers/gpu/drm/msm/msm_gpu.h:172 struct member 'boost_work' not
described in 'msm_gpu_devfreq'
Warning: drivers/gpu/drm/msm/msm_gpu.h:172 struct member 'suspended' not
described in 'msm_gpu_devfreq'
Warning: drivers/gpu/drm/msm/msm_gpu.h:472 No description found for
return value of 'msm_context_is_vmbind'
Warning: drivers/gpu/drm/msm/msm_gpu.h:476 struct member 'ref' not
described in 'msm_context'
Warning: drivers/gpu/drm/msm/msm_gpu.h:476 struct member 'elapsed_ns' not
described in 'msm_context'
Warning: drivers/gpu/drm/msm/msm_gpu.h:492 expecting prototype for
msm_context_is_vm_bind(). Prototype was for msm_context_is_vmbind()
instead
Warning: drivers/gpu/drm/msm/msm_gpu.h:523 No description found for
return value of 'msm_gpu_convert_priority'
Warning: drivers/gpu/drm/msm/msm_gpu.h:583 expecting prototype for
struct msm_gpu_submitqueues. Prototype was for struct msm_gpu_submitqueue
instead
Randy Dunlap [Fri, 19 Dec 2025 18:46:35 +0000 (10:46 -0800)]
drm/msm: msm_fence.h: fix all kernel-doc warnings
Correct or add kernel-doc comments to eliminate all warnings:
Warning: drivers/gpu/drm/msm/msm_fence.h:27 Incorrect use of kernel-doc
format: * last_fence:
Warning: drivers/gpu/drm/msm/msm_fence.h:36 Incorrect use of kernel-doc
format: * completed_fence:
Warning: drivers/gpu/drm/msm/msm_fence.h:44 Incorrect use of kernel-doc
format: * fenceptr:
Warning: drivers/gpu/drm/msm/msm_fence.h:65 Incorrect use of kernel-doc
format: * next_deadline_fence:
Warning: drivers/gpu/drm/msm/msm_fence.h:74 struct member 'dev' not
described in 'msm_fence_context'
Warning: drivers/gpu/drm/msm/msm_fence.h:74 struct member 'name' not
described in 'msm_fence_context'
Warning: drivers/gpu/drm/msm/msm_fence.h:74 struct member 'context' not
described in 'msm_fence_context'
Warning: drivers/gpu/drm/msm/msm_fence.h:74 struct member 'index' not
described in 'msm_fence_context'
Warning: drivers/gpu/drm/msm/msm_fence.h:74 struct member 'fence' not
described in 'msm_fence_context'
Warning: drivers/gpu/drm/msm/msm_fence.h:74 struct member 'there is no
remaining pending work */ uint32_t last_fence' not described in
'msm_fence_context'
Warning: drivers/gpu/drm/msm/msm_fence.h:74 struct member 'updated from the CPU after interrupt * from GPU */ uint32_t completed_fence' not described in 'msm_fence_context'
Warning: drivers/gpu/drm/msm/msm_fence.h:74 struct member 'fenceptr' not
described in 'msm_fence_context'
Warning: drivers/gpu/drm/msm/msm_fence.h:74 struct member 'spinlock' not
described in 'msm_fence_context'
Warning: drivers/gpu/drm/msm/msm_fence.h:74 struct member 'next_deadline'
not described in 'msm_fence_context'
Warning: drivers/gpu/drm/msm/msm_fence.h:74 struct member
'next_deadline_fence' not described in 'msm_fence_context'
Warning: drivers/gpu/drm/msm/msm_fence.h:74 struct member 'deadline_timer'
not described in 'msm_fence_context'
Warning: drivers/gpu/drm/msm/msm_fence.h:74 struct member 'deadline_work'
not described in 'msm_fence_context'
Randy Dunlap [Fri, 19 Dec 2025 18:46:34 +0000 (10:46 -0800)]
drm/msm/dpu: dpu_hw_wb.h: fix all kernel-doc warnings
Correct or add kernel-doc comments to eliminate all warnings:
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h:24 Cannot find
identifier on line: *
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h:57 struct member
'setup_roi' not described in 'dpu_hw_wb_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h:75 struct member
'caps' not described in 'dpu_hw_wb'
Randy Dunlap [Fri, 19 Dec 2025 18:46:33 +0000 (10:46 -0800)]
drm/msm/dpu: dpu_hw_vbif.h: fix all kernel-doc warnings
Correct or add kernel-doc comments to eliminate all warnings:
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h:19 Incorrect use of
kernel-doc format: * set_limit_conf - set transaction limit config
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h:29 Incorrect use of
kernel-doc format: * get_limit_conf - get transaction limit config
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h:39 Incorrect use of
kernel-doc format: * set_halt_ctrl - set halt control
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h:48 Incorrect use of
kernel-doc format: * get_halt_ctrl - get halt control
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h:57 Incorrect use of
kernel-doc format: * set_qos_remap - set QoS priority remap
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h:67 Incorrect use of
kernel-doc format: * set_mem_type - set memory type
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h:76 Incorrect use of
kernel-doc format: * clear_errors - clear any vbif errors
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h:88 Incorrect use of
kernel-doc format: * set_write_gather_en - set write_gather enable
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h:93 struct member
'limit' not described in 'dpu_hw_vbif_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h:93 struct member
'set_limit_conf' not described in 'dpu_hw_vbif_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h:93 struct member
'get_limit_conf' not described in 'dpu_hw_vbif_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h:93 struct member
'set_halt_ctrl' not described in 'dpu_hw_vbif_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h:93 struct member
'get_halt_ctrl' not described in 'dpu_hw_vbif_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h:93 struct member
'set_qos_remap' not described in 'dpu_hw_vbif_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h:93 struct member
'set_mem_type' not described in 'dpu_hw_vbif_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h:93 struct member
's' not described in 'dpu_hw_vbif_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h:93 struct member
'set_write_gather_en' not described in 'dpu_hw_vbif_ops'
Randy Dunlap [Fri, 19 Dec 2025 18:46:32 +0000 (10:46 -0800)]
drm/msm/dpu: dpu_hw_top.h: fix all kernel-doc warnings
Correct or add kernel-doc comments to eliminate all warnings:
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h:93 Incorrect use of
kernel-doc format: * setup_traffic_shaper() : Setup traffic shaper control
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h:101 Incorrect use of
kernel-doc format: * setup_clk_force_ctrl - set clock force control
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h:111 Incorrect use of
kernel-doc format: * get_danger_status - get danger status
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h:119 Incorrect use of
kernel-doc format: * setup_vsync_source - setup vsync source
configuration details
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h:127 Incorrect use of
kernel-doc format: * get_safe_status - get safe status
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h:135 Incorrect use of
kernel-doc format: * dp_phy_intf_sel - configure intf to phy mapping
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h:142 Incorrect use of
kernel-doc format: * intf_audio_select - select the external interface
for audio
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h:146 struct member
'setup_clk_force_ctrl' not described in 'dpu_hw_mdp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h:146 struct member
'get_danger_status' not described in 'dpu_hw_mdp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h:146 struct member
'setup_vsync_source' not described in 'dpu_hw_mdp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h:146 struct member
'get_safe_status' not described in 'dpu_hw_mdp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h:146 struct member
'dp_phy_intf_sel' not described in 'dpu_hw_mdp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h:146 struct member
'intf_audio_select' not described in 'dpu_hw_mdp_ops'
Randy Dunlap [Fri, 19 Dec 2025 18:46:31 +0000 (10:46 -0800)]
drm/msm/dpu: dpu_hw_sspp.h: fix all kernel-doc warnings
Modify non-kernel-doc comments to begin with "/*" instead of "/**".
Correct or add kernel-doc comments to eliminate all warnings:
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:17 missing initial
short description on line: * Flags
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:19 expecting
prototype for Flags(). Prototype was for DPU_SSPP_FLIP_LR() instead
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:26 This comment
starts with '/**', but isn't a kernel-doc comment.
* Component indices
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:47 cannot understand
function prototype: 'enum dpu_sspp_multirect_index'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:152 struct member
'dst_rect' not described in 'dpu_sw_pipe_cfg'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:174 struct member
'multirect_index' not described in 'dpu_sw_pipe'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:174 struct member
'multirect_mode' not described in 'dpu_sw_pipe'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:183 Incorrect use of
kernel-doc format: * setup_format - setup pixel format cropping
rectangle, flip
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:192 Incorrect use of
kernel-doc format: * setup_rects - setup pipe ROI rectangles
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:200 Incorrect use of
kernel-doc format: * setup_pe - setup pipe pixel extension
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:208 Incorrect use of
kernel-doc format: * setup_sourceaddress - setup pipe source addresses
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:216 Incorrect use of
kernel-doc format: * setup_csc - setup color space coversion
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:223 Incorrect use of
kernel-doc format: * setup_solidfill - enable/disable colorfill
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:231 Incorrect use of
kernel-doc format: * setup_multirect - setup multirect configuration
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:238 Incorrect use of
kernel-doc format: * setup_sharpening - setup sharpening
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:247 Incorrect use of
kernel-doc format: * setup_qos_lut - setup QoS LUTs
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:255 Incorrect use of
kernel-doc format: * setup_qos_ctrl - setup QoS control
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:263 Incorrect use of
kernel-doc format: * setup_clk_force_ctrl - setup clock force control
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:271 Incorrect use of
kernel-doc format: * setup_histogram - setup histograms
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:279 Incorrect use of
kernel-doc format: * setup_scaler - setup scaler
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:288 Incorrect use of
kernel-doc format: * setup_cdp - setup client driven prefetch
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:296 struct member
'setup_format' not described in 'dpu_hw_sspp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:296 struct member
'setup_rects' not described in 'dpu_hw_sspp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:296 struct member
'setup_pe' not described in 'dpu_hw_sspp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:296 struct member
'setup_sourceaddress' not described in 'dpu_hw_sspp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:296 struct member
'setup_csc' not described in 'dpu_hw_sspp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:296 struct member
'setup_solidfill' not described in 'dpu_hw_sspp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:296 struct member
'setup_multirect' not described in 'dpu_hw_sspp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:296 struct member
'setup_sharpening' not described in 'dpu_hw_sspp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:296 struct member
'setup_qos_lut' not described in 'dpu_hw_sspp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:296 struct member
'setup_qos_ctrl' not described in 'dpu_hw_sspp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:296 struct member
'setup_clk_force_ctrl' not described in 'dpu_hw_sspp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:296 struct member
'setup_histogram' not described in 'dpu_hw_sspp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:296 struct member
'setup_scaler' not described in 'dpu_hw_sspp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:296 struct member
'setup_cdp' not described in 'dpu_hw_sspp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h:320 struct member
'mdss_ver' not described in 'dpu_hw_sspp'
Randy Dunlap [Fri, 19 Dec 2025 18:46:30 +0000 (10:46 -0800)]
drm/msm/dpu: dpu_hw_pingpong.h: fix all kernel-doc warnings
Correct or add kernel-doc comments to eliminate all warnings:
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h:36 Cannot find
identifier on line: *
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h:46 Incorrect use
of kernel-doc format: * enables vysnc generation and sets up init value of
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h:53 Incorrect use
of kernel-doc format: * disables tear check block
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h:58 Incorrect use
of kernel-doc format: * read, modify, write to either set or clear
listening to external TE
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h:65 Incorrect use
of kernel-doc format: * Obtain current vertical line counter
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h:70 Incorrect use
of kernel-doc format: * Disable autorefresh if enabled
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h:75 Incorrect use
of kernel-doc format: * Setup dither matix for pingpong block
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h:80 Incorrect use
of kernel-doc format: * Enable DSC
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h:85 Incorrect use
of kernel-doc format: * Disable DSC
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h:90 Incorrect use
of kernel-doc format: * Setup DSC
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h:93 struct member
'connect_external_te' not described in 'dpu_hw_pingpong_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h:93 struct member
'disable_autorefresh' not described in 'dpu_hw_pingpong_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h:93 struct member
'enable_dsc' not described in 'dpu_hw_pingpong_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h:93 struct member
'disable_dsc' not described in 'dpu_hw_pingpong_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h:93 struct member
'setup_dsc' not described in 'dpu_hw_pingpong_ops'
Randy Dunlap [Fri, 19 Dec 2025 18:46:28 +0000 (10:46 -0800)]
drm/msm/dpu: dpu_hw_lm.h: fix all kernel-doc warnings
Correct or add kernel-doc comments to eliminate all warnings:
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h:27 Cannot find
identifier on line: *
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h:52 Incorrect use of
kernel-doc format: * Clear layer mixer to pipe configuration
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h:59 Incorrect use of
kernel-doc format: * Configure layer mixer to pipe configuration
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h:69 Incorrect use of
kernel-doc format: * setup_border_color : enable/disable border color
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h:76 Incorrect use of
kernel-doc format: * setup_misr: Enable/disable MISR
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h:81 Incorrect use of
kernel-doc format: * collect_misr: Read MISR signature
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h:84 struct member
'setup_mixer_out' not described in 'dpu_hw_lm_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h:84 struct member
'setup_blend_config' not described in 'dpu_hw_lm_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h:84 struct member
'setup_alpha_out' not described in 'dpu_hw_lm_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h:84 struct member
'clear_all_blendstages' not described in 'dpu_hw_lm_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h:84 struct member
'setup_blendstage' not described in 'dpu_hw_lm_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h:84 struct member
'setup_border_color' not described in 'dpu_hw_lm_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h:84 struct member
'setup_misr' not described in 'dpu_hw_lm_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h:84 struct member
'collect_misr' not described in 'dpu_hw_lm_ops'
Randy Dunlap [Fri, 19 Dec 2025 18:46:27 +0000 (10:46 -0800)]
drm/msm/dpu: dpu_hw_intf.h: fix all kernel-doc warnings
Correct or add kernel-doc comments to eliminate all warnings:
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h:76 duplicate section
name 'Return'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h:112 Incorrect use of
kernel-doc format: * Disable autorefresh if enabled
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h:118 struct member
'setup_timing_gen' not described in 'dpu_hw_intf_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h:118 struct member
'setup_prg_fetch' not described in 'dpu_hw_intf_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h:118 struct member
'enable_timing' not described in 'dpu_hw_intf_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h:118 struct member
'get_status' not described in 'dpu_hw_intf_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h:118 struct member
'get_line_count' not described in 'dpu_hw_intf_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h:118 struct member
'disable_autorefresh' not described in 'dpu_hw_intf_ops'
dpu_hw_intf.h:119: warning: Excess struct member 'get_vsync_info'
description in 'dpu_hw_intf_ops'
dpu_hw_intf.h:119: warning: Excess struct member 'setup_autorefresh'
description in 'dpu_hw_intf_ops'
dpu_hw_intf.h:119: warning: Excess struct member 'get_autorefresh'
description in 'dpu_hw_intf_ops'
Randy Dunlap [Fri, 19 Dec 2025 18:46:26 +0000 (10:46 -0800)]
drm/msm/dpu: dpu_hw_dspp.h: fix all kernel-doc warnings
Correct or add kernel-doc comments to eliminate all warnings:
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h:33 expecting prototype
for struct dpu_hw_pcc. Prototype was for struct dpu_hw_pcc_cfg instead
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h:42 Incorrect use of
kernel-doc format: * setup_pcc - setup dspp pcc
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h:48 struct member
'setup_pcc' not described in 'dpu_hw_dspp_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h:76 expecting prototype
for dpu_hw_dspp(). Prototype was for to_dpu_hw_dspp() instead
Randy Dunlap [Fri, 19 Dec 2025 18:46:25 +0000 (10:46 -0800)]
drm/msm/dpu: dpu_hw_dsc.h: fix all kernel-doc warnings
Correct or add kernel-doc comments to eliminate all warnings:
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h:23 Incorrect use of
kernel-doc format: * dsc_disable - disable dsc
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h:29 Incorrect use of
kernel-doc format: * dsc_config - configures dsc encoder
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h:41 Incorrect use of
kernel-doc format: * dsc_config_thresh - programs panel thresholds
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h:50 struct member
'dsc_disable' not described in 'dpu_hw_dsc_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h:50 struct member
'dsc_config' not described in 'dpu_hw_dsc_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h:50 struct member
'dsc_config_thresh' not described in 'dpu_hw_dsc_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h:50 struct member
'dsc_bind_pingpong_blk' not described in 'dpu_hw_dsc_ops'
Randy Dunlap [Fri, 19 Dec 2025 18:46:24 +0000 (10:46 -0800)]
drm/msm/dpu: dpu_hw_cwb.h: fix all kernel-doc warnings
Correct or add kernel-doc comments to eliminate all warnings:
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.h:30 Cannot find
identifier on line: *
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.h:61 expecting prototype
for dpu_hw_cwb(). Prototype was for to_dpu_hw_cwb() instead
Randy Dunlap [Fri, 19 Dec 2025 18:46:23 +0000 (10:46 -0800)]
drm/msm/dpu: dpu_hw_ctl.h: fix all kernel-doc warnings
Correct and add kernel-doc comments to eliminate all warnings:
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:18 cannot understand
function prototype: 'enum dpu_ctl_mode_sel'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:58 struct member 'wb'
not described in 'dpu_hw_intf_cfg'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:66 Incorrect use of
kernel-doc format: * kickoff hw operation for Sw controlled interfaces
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:73 Incorrect use of
kernel-doc format: * check if the ctl is started
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:80 Incorrect use of
kernel-doc format: * kickoff prepare is in progress hw operation for sw
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:88 Incorrect use of
kernel-doc format: * Clear the value of the cached pending_flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:96 Incorrect use of
kernel-doc format: * Query the value of the cached pending_flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:103 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:112 Incorrect use of
kernel-doc format: * OR in the given flushbits to the
cached pending_(wb_)flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:121 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_(cwb_)flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:130 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_(intf_)flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:139 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_(periph_)flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:148 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_(merge_3d_)flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:157 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:166 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:175 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:185 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_(dsc_)flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:194 Incorrect use of
kernel-doc format: * OR in the given flushbits to the cached
pending_(cdm_)flush_mask
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:202 Incorrect use of
kernel-doc format: * Write the value of the pending_flush_mask to hardware
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:208 Incorrect use of
kernel-doc format: * Read the value of the flush register
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:215 Incorrect use of
kernel-doc format: * Setup ctl_path interface config
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:223 Incorrect use of
kernel-doc format: * reset ctl_path interface config
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:244 Incorrect use of
kernel-doc format: * Set all blend stages to disabled
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:250 Incorrect use of
kernel-doc format: * Configure layer mixer to pipe configuration
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:262 Incorrect use of
kernel-doc format: * Set active pipes attached to this CTL
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:270 Incorrect use of
kernel-doc format: * Set active layer mixers attached to this CTL
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:277 struct member
'trigger_start' not described in 'dpu_hw_ctl_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:277 struct member
'is_started' not described in 'dpu_hw_ctl_ops'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:277 struct member
'trigger_pending' not described in 'dpu_hw_ctl_ops'
[many here]
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:319 struct member
'pending_periph_flush_mask' not described in 'dpu_hw_ctl'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:319 struct member
'pending_merge_3d_flush_mask' not described in 'dpu_hw_ctl'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:319 struct member
'pending_dspp_flush_mask' not described in 'dpu_hw_ctl'
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h:327 expecting
prototype for dpu_hw_ctl(). Prototype was for to_dpu_hw_ctl() instead
Randy Dunlap [Fri, 19 Dec 2025 18:46:22 +0000 (10:46 -0800)]
drm/msm/dpu: dpu_hw_cdm.h: fix all kernel-doc warnings
Correct and add kernel-doc comments to eliminate all warnings:
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h:91 Incorrect use of
kernel-doc format: * Enable the CDM module
Warning: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h:97 Incorrect use of
kernel-doc format: * Enable/disable the connection with pingpong
Randy Dunlap [Fri, 19 Dec 2025 18:46:21 +0000 (10:46 -0800)]
drm/msm/dp: fix all kernel-doc warnings
Correct and add kernel-doc comments to eliminate all warnings:
Warning: ../drivers/gpu/drm/msm/dp/dp_debug.h:31 expecting prototype for
msm_dp_debug_get(). Prototype was for msm_dp_debug_init() instead
Warning: ../drivers/gpu/drm/msm/dp/dp_drm.c:24 function parameter
'connector' not described in 'msm_dp_bridge_detect'
Warning: ../drivers/gpu/drm/msm/dp/dp_link.h:90 expecting prototype for
mdss_dp_test_bit_depth_to_bpp(). Prototype was for
msm_dp_link_bit_depth_to_bpp() instead
Warning: ../drivers/gpu/drm/msm/dp/dp_link.h:126 function parameter
'aux' not described in 'msm_dp_link_get'
Warning: ../drivers/gpu/drm/msm/dp/dp_link.h:126 function parameter
'dev' not described in 'msm_dp_link_get'
Warning: ../drivers/gpu/drm/msm/dp/dp_panel.h:70 function parameter
'bw_code' not described in 'is_link_rate_valid'
Warning: ../drivers/gpu/drm/msm/dp/dp_panel.h:84 expecting prototype for
msm_dp_link_is_lane_count_valid(). Prototype was for
is_lane_count_valid() instead
Randy Dunlap [Fri, 19 Dec 2025 18:46:20 +0000 (10:46 -0800)]
drm/msm/disp: mdp_format: fix all kernel-doc warnings
Correct and add kernel-doc comments to eliminate all warnings:
Warning: ../drivers/gpu/drm/msm/disp/mdp_format.h:27 This comment starts
with '/**', but isn't a kernel-doc comment.
Warning: ../drivers/gpu/drm/msm/disp/mdp_format.h:64 struct member
'bpc_a' not described in 'msm_format'
Warning: ../drivers/gpu/drm/msm/disp/mdp_format.h:64 struct member
'bpc_b_cb' not described in 'msm_format'
Warning: ../drivers/gpu/drm/msm/disp/mdp_format.h:64 struct member
'bpc_g_y' not described in 'msm_format'
Warning: ../drivers/gpu/drm/msm/disp/mdp_format.h:64 struct member
'bpc_r_cr' not described in 'msm_format'
Anna Maniscalco [Mon, 1 Dec 2025 18:14:36 +0000 (19:14 +0100)]
drm/msm: Fix a7xx per pipe register programming
GEN7_GRAS_NC_MODE_CNTL was only programmed for BR and not for BV pipe
but it needs to be programmed for both.
Program both pipes in hw_init and introducea separate reglist for it in
order to add this register to the dynamic reglist which supports
restoring registers per pipe.
Fixes: 91389b4e3263 ("drm/msm/a6xx: Add a pwrup_list field to a6xx_info") Cc: stable@vger.kernel.org Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Signed-off-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/691553/
Message-ID: <20251201-gras_nc_mode_fix-v3-1-92a8a10d91d0@gmail.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Alok Tiwari [Thu, 13 Nov 2025 08:28:31 +0000 (00:28 -0800)]
drm/msm/a6xx: move preempt_prepare_postamble after error check
Move the call to preempt_prepare_postamble() after verifying that
preempt_postamble_ptr is valid. If preempt_postamble_ptr is NULL,
dereferencing it in preempt_prepare_postamble() would lead to a crash.
This change avoids calling the preparation function when the
postamble allocation has failed, preventing potential NULL pointer
dereference and ensuring proper error handling.
Fixes: 50117cad0c50 ("drm/msm/a6xx: Use posamble to reset counters on preemption") Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com>
Patchwork: https://patchwork.freedesktop.org/patch/687659/
Message-ID: <20251113082839.3821867-1-alok.a.tiwari@oracle.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Neil Armstrong [Mon, 17 Nov 2025 14:51:35 +0000 (15:51 +0100)]
drm/msm: adreno: fix deferencing ifpc_reglist when not declared
On plaforms with an a7xx GPU not supporting IFPC, the ifpc_reglist
if still deferenced in a7xx_patch_pwrup_reglist() which causes
a kernel crash:
Unable to handle kernel NULL pointer dereference at virtual address 0000000000000008
...
pc : a6xx_hw_init+0x155c/0x1e4c [msm]
lr : a6xx_hw_init+0x9a8/0x1e4c [msm]
...
Call trace:
a6xx_hw_init+0x155c/0x1e4c [msm] (P)
msm_gpu_hw_init+0x58/0x88 [msm]
adreno_load_gpu+0x94/0x1fc [msm]
msm_open+0xe4/0xf4 [msm]
drm_file_alloc+0x1a0/0x2e4 [drm]
drm_client_init+0x7c/0x104 [drm]
drm_fbdev_client_setup+0x94/0xcf0 [drm_client_lib]
drm_client_setup+0xb4/0xd8 [drm_client_lib]
msm_drm_kms_post_init+0x2c/0x3c [msm]
msm_drm_init+0x1a4/0x228 [msm]
msm_drm_bind+0x30/0x3c [msm]
...
Check the validity of ifpc_reglist before deferencing the table
to setup the register values.
Fixes: a6a0157cc68e ("drm/msm/a6xx: Enable IFPC on Adreno X1-85") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/688944/
Message-ID: <20251117-topic-sm8x50-fix-a6xx-non-ifpc-v1-1-e4473cbf5903@linaro.org> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Document Adreno X2-85 GMU found in Glymur chipsets in the
dt-binding specification. It is very similar to Adreno 840
GMU with the additional requirement of RSCC HUB clock.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689032/
Message-ID: <20251118-kaana-gpu-support-v4-21-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:47 +0000 (14:20 +0530)]
dt-bindings: display/msm/gmu: Add Adreno 840 GMU
Document Adreno 840 GMU in the dt-binding specification.
Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689031/
Message-ID: <20251118-kaana-gpu-support-v4-20-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:46 +0000 (14:20 +0530)]
dt-bindings: arm-smmu: Add Kaanapali and Glymur GPU SMMU
Update the devicetree bindings to document the GPU SMMUs present in
Kaanapali and Glymur chipsets.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689028/
Message-ID: <20251118-kaana-gpu-support-v4-19-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:45 +0000 (14:20 +0530)]
drm/msm/a8xx: Add support for Adreno X2-85 GPU
Adreno X2-85 GPU is found in the next generation of Qualcomm's compute
series chipset called Snapdragon X2 Elite (a.k.a Glymur). It is based
on the new A8x slice architecture and features up to 4 slices. Due to
the wider 12 channel DDR support, there is higher DDR bandwidth available
than previous generation to improve performance.
Add a new entry in the catalog along with the necessary register
configurations to enable support for it.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689026/
Message-ID: <20251118-kaana-gpu-support-v4-18-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:44 +0000 (14:20 +0530)]
drm/msm/adreno: Do CX GBIF config before GMU start
GMU lies on the CX domain and accesses CX GBIF. So do CX GBIF
configurations before GMU wakes up. This was not a problem so far, but
A840 GPU is very sensitive to this requirement. Also, move these
registers to the catalog.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689024/
Message-ID: <20251118-kaana-gpu-support-v4-17-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:43 +0000 (14:20 +0530)]
drm/msm/a8xx: Add support for Adreno 840 GPU
Adreno 840 present in Kaanapali SoC is the second generation GPU in
A8x family. It comes in 2 variants with either 2 or 3 Slices. This is
in addition to the SKUs supported based on the GPU FMAX.
Add the necessary register configurations to the catalog and enable
support for it.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689022/
Message-ID: <20251118-kaana-gpu-support-v4-16-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:42 +0000 (14:20 +0530)]
drm/msm/adreno: Support AQE engine
AQE (Applicaton Qrisc Engine) is a dedicated core inside CP which aides
in Raytracing related workloads. Add support for loading the AQE firmware
and initialize the necessary registers.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689020/
Message-ID: <20251118-kaana-gpu-support-v4-15-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:41 +0000 (14:20 +0530)]
drm/msm/adreno: Introduce A8x GPU Support
A8x is the next generation of Adreno GPUs, featuring a significant
hardware design change. A major update to the design is the introduction
of Slice architecture. Slices are sort of mini-GPUs within the GPU which
are more independent in processing Graphics and compute workloads. Also,
in addition to the BV and BR pipe we saw in A7x, CP has more concurrency
with additional pipes.
From a software interface perspective, these changes have a significant
impact on the KMD side. First, the GPU register space has been extensively
reorganized. Second, to avoid a register space explosion caused by the
new slice architecture and additional pipes, many registers are now
virtualized, instead of duplicated as in A7x. KMD must configure an
aperture register with the appropriate slice and pipe ID before accessing
these virtualized registers.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689019/
Message-ID: <20251118-kaana-gpu-support-v4-14-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:40 +0000 (14:20 +0530)]
drm/msm/a6xx: Share dependency vote table with GMU
A8x GMU firmwares expect a separate vote table which describes the
relationship between the Gx rail and MxA rail (and possibly Cx rail).
Create this new vote table and implement the new HFI message which
allows passing vote tables to send this data to GMU.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689016/
Message-ID: <20251118-kaana-gpu-support-v4-13-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:39 +0000 (14:20 +0530)]
drm/msm/a6xx: Improve MX rail fallback in RPMH vote init
Current logic assumes that the voltage corners in both MxG and MxA are
always same. This is not true for recent targets. So, rework the rpmh init
sequence to probe and calculate the votes with the respective rails, ie,
GX rails should use MxG as secondary rail and Cx rail should use MxA as
the secondary rail.
Fixes: d6225e0cd096 ("drm/msm/adreno: Add support for X185 GPU") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689014/
Message-ID: <20251118-kaana-gpu-support-v4-12-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:38 +0000 (14:20 +0530)]
drm/msm/a8xx: Add support for A8x GMU
A8x GMU configurations are very similar to A7x. Unfortunately, there are
minor shuffling in the register offsets in the GMU CX register region.
So, update the driver to use the correct register offsets on A8x hw.
Some A8x GPUs have more than 16 powerlevels on GX domain and 4 on CX
domain. To accommodate this, increase the arrays' sizes which hold gx and
cx power levels.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689013/
Message-ID: <20251118-kaana-gpu-support-v4-11-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:37 +0000 (14:20 +0530)]
drm/msm/a6xx: Rebase GMU register offsets
GMU registers are always at a fixed offset from the GPU base address,
a consistency maintained at least within a given architecture generation.
In A8x family, the base address of the GMU has changed, but the offsets
of the gmu registers remain largely the same. To enable reuse of the gmu
code for A8x chipsets, update the gmu register offsets to be relative
to the GPU's base address instead of GMU's.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689010/
Message-ID: <20251118-kaana-gpu-support-v4-10-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:36 +0000 (14:20 +0530)]
drm/msm/a6xx: Sync latest register definitions
Sync the latest register definitions from Mesa which includes the
updates for A8x family.
Co-developed-by: Rob Clark <robin.clark@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689009/
Message-ID: <20251118-kaana-gpu-support-v4-9-86eeb8e93fb6@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:35 +0000 (14:20 +0530)]
drm/msm/adreno: Add MMU fault handler to adreno_gpu_func
Move MMU fault handler for each generation to adreno function list. This
will help to use common code for mmu pagefault handler registration between
a6x/a7x and a8x layer.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689007/
Message-ID: <20251118-kaana-gpu-support-v4-8-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:34 +0000 (14:20 +0530)]
drm/msm/adreno: Move gbif_halt() to adreno_gpu_func
Move the gbif halt fn to adreno_gpu_func so that we can call different
implementation from common code. This will come handy when we implement
A8x layer.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689005/
Message-ID: <20251118-kaana-gpu-support-v4-7-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:33 +0000 (14:20 +0530)]
drm/msm/adreno: Move adreno_gpu_func to catalogue
In A6x family (which is a pretty big one), there are separate
adreno_func definitions for each sub-generations. To streamline the
identification of the correct struct for a gpu, move it to the
catalogue and move the gpu_init routine to struct adreno_gpu_funcs.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689003/
Message-ID: <20251118-kaana-gpu-support-v4-6-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:32 +0000 (14:20 +0530)]
drm/msm/adreno: Common-ize PIPE definitions
Newer gen's introduce pipe enums which do not exist on older gens, but
the numeric values do not conflict. IOW, they are backward compatible.
So move its definition to adreno_common.xml.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689001/
Message-ID: <20251118-kaana-gpu-support-v4-5-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:31 +0000 (14:20 +0530)]
drm/msm/a6xx: Skip dumping SCRATCH registers
Crashdec doesn't require SCRATCH registers anymore for a6xx and newer
architectures. So skip dumping them during recovery.
Suggested-by: Rob Clark <rob.clark@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689000/
Message-ID: <20251118-kaana-gpu-support-v4-4-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:30 +0000 (14:20 +0530)]
drm/msm/a6xx: Fix the gemnoc workaround
Correct the register offset and enable this workaround for all A7x
and newer GPUs to match the recommendation. Also, downstream does this
w/a after moving the fence to allow mode. So do the same.
Fixes: dbfbb376b50c ("drm/msm/a6xx: Add A621 support") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/688997/
Message-ID: <20251118-kaana-gpu-support-v4-3-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Akhil P Oommen [Tue, 18 Nov 2025 08:50:29 +0000 (14:20 +0530)]
drm/msm/a6xx: Flush LRZ cache before PT switch
As per the recommendation, A7x and newer GPUs should flush the LRZ cache
before switching the pagetable. Update a6xx_set_pagetable() to do this.
While we are at it, sync both BV and BR before issuing a
CP_RESET_CONTEXT_STATE command, to match the downstream sequence.
Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/688995/
Message-ID: <20251118-kaana-gpu-support-v4-2-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Rob Clark [Tue, 18 Nov 2025 15:29:49 +0000 (07:29 -0800)]
drm/msm/registers: Fix encoding fields in 64b registers
Based on mesa commit 3f70b0578402 ("freedreno/registers: Fix encoding
fields in 64b registers"), but with some fixes to not skip emitting
interrupt enum values.
v2: Don't append "ull" to 32b reg MASK defines, to avoid printf format
conversion warnings all over the place
Co-developed-by: Connor Abbott <cwabbott0@gmail.com> Signed-off-by: Connor Abbott <cwabbott0@gmail.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/689141/
Message-ID: <20251118152952.226510-1-robin.clark@oss.qualcomm.com>
drm/msm: Wait for MMU devcoredump when waiting for GMU
If there is a flood of faults then the MMU can become saturated while it
waits for the kernel to process the first fault and resume it, so that
the GMU becomes blocked. This is mainly a problem when the kernel reads
the state of the GPU for a devcoredump, because this takes a while. If
we timeout waiting for the GMU, check if this has happened and retry
after we're finished.
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/664685/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Dmitry Baryshkov [Thu, 13 Nov 2025 20:40:50 +0000 (22:40 +0200)]
drm/msm/a2xx: stop over-complaining about the legacy firmware
If the rootfs have a legacy A200 firmware, currently the driver will
complain each time the hw is reinited (which can happen a lot). E.g.
with GL testsuite the hw is reinited after each test, spamming the
console.
Make sure that the message is printed only once: when we detect the
firmware that doesn't support protection.
Fixes: 302295070d3c ("drm/msm/a2xx: support loading legacy (iMX) firmware") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/688098/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Huiwen He [Wed, 12 Nov 2025 17:19:47 +0000 (01:19 +0800)]
drm/msm: fix missing NULL check after kcalloc in crashstate_get_bos()
The crashstate_get_bos() function allocates memory for `state->bos`
using kcalloc(), but the vmbind path does not check for allocation
failure before dereferencing it in the following drm_gpuvm_for_each_va()
loop. This could lead to a NULL pointer dereference if memory allocation
fails.
Fix this by wrapping the drm_gpuvm_for_each_va() loop with a NULL check
on state->bos, similar to the safety check in the non-vmbind path.
Fixes: af9aa6f316b3d ("drm/msm: Crashdump support for sparse") Signed-off-by: Huiwen He <hehuiwen@kylinos.cn>
Patchwork: https://patchwork.freedesktop.org/patch/687556/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Huiwen He [Wed, 12 Nov 2025 17:04:11 +0000 (01:04 +0800)]
drm/msm: Fix NULL pointer dereference in crashstate_get_vm_logs()
crashstate_get_vm_logs() did not check the return value of
kmalloc_array(). In low-memory situations, kmalloc_array() may return
NULL, leading to a NULL pointer dereference when the function later
accesses state->vm_logs.
Fix this by checking the return value of kmalloc_array() and setting
state->nr_vm_logs to 0 if allocation fails.
Fixes: 9edc52967cc7 ("drm/msm: Add VM logging for VM_BIND updates") Signed-off-by: Huiwen He <hehuiwen@kylinos.cn>
Patchwork: https://patchwork.freedesktop.org/patch/687555/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Jie Zhang [Thu, 6 Nov 2025 20:50:06 +0000 (02:20 +0530)]
drm/msm/a6xx: Add support for Adreno 612
Add support for Adreno 612 GPU found in SM6150/QCS615 chipsets.
A612 falls under ADRENO_6XX_GEN1 family and is a cut down version
of A615 GPU.
A612 has a new IP called Reduced Graphics Management Unit or RGMU
which is a small state machine which helps to toggle GX GDSC
(connected to CX rail) to implement IFPC feature. It doesn't support
any other features of a full fledged GMU like clock control, resource
voting to rpmh etc. So we need linux clock driver support like other
gmu-wrapper implementations to control gpu core clock and gpu GX gdsc.
This patch skips RGMU core initialization and act more like a
gmu-wrapper case.
Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/686212/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Rob Clark [Tue, 4 Nov 2025 22:02:45 +0000 (14:02 -0800)]
MAINTAINERS: Add Akhil as a reviewer for the Adreno driver
Akhil should be getting tagged to review GPU patches.
Cc: Akhil P Oommen <akhilpo@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Acked-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/685650/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
vm_op_enqueue() allocates an msm_vm_op struct with kmalloc,
but the return value is not checked for NULL value which
can be returned by kmalloc under low-memory conditions.
This can result in NULL pointer dereference when the pointer
is dereferenced.
Add NULL check after the allocation and propagate -ENOMEM back
to the caller in case of a failure.
Signed-off-by: Gopi Krishna Menon <krishnagopi487@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/678416/ Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Xiangxu Yin [Tue, 4 Nov 2025 01:33:24 +0000 (09:33 +0800)]
dt-bindings: display: msm: sm6150-mdss: Fix example indentation and OPP values
Improve the binding example by fixing indentation and adding missing
blank lines for better readability. Also correct the OPP clock values
to match the actual SM6150 DTS configuration.
SM6150 uses the same DisplayPort controller as SM8150, which is compatible
with SM8350. Add SM6150-specific compatible string for the DisplayPort
controller.
Add DisplayPort controller binding for Qualcomm SM6150 SoC.
SM6150 uses the same controller IP as SM8150.
Declare 'qcom,sm6150-dp' as a fallback compatible to
'qcom,sm8150-dp' and 'qcom,sm8350-dp' for consistency with existing
bindings and to ensure correct matching and future clarity.
Randy Dunlap [Tue, 11 Nov 2025 06:03:53 +0000 (22:03 -0800)]
drm/msm/disp: fix kernel-doc warnings
Fix all kernel-doc warnings in msm_disp_snapshot.h:
msm_disp_snapshot.h:53: warning: Function parameter or struct member
'blocks' not described in 'msm_disp_state'
msm_disp_snapshot.h:69: warning: Function parameter or struct member
'node' not described in 'msm_disp_state_block'
msm_disp_snapshot.h:69: warning: Excess struct member 'drm_dev' description
in 'msm_disp_state_block'
msm_disp_snapshot.h:95: warning: No description found for return value
of 'msm_disp_snapshot_state_sync'
msm_disp_snapshot.h:100: warning: bad line:
msm_disp_snapshot.h:117: warning: bad line:
msm_disp_snapshot.h:125: warning: bad line:
msm_disp_snapshot.h:142: warning: Excess function parameter 'name'
description in 'msm_disp_snapshot_add_block'
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