Liya Huang [Fri, 31 Jan 2025 00:52:43 +0000 (08:52 +0800)]
siemens: common: Make DDR_SI_TEST depend on TARGET_CAPRICORN
The DDR_SI_TEST config option is only relevant to the i.MX8 Capricorn
board.
Make DDR_SI_TEST depend on DDR_SI_TEST so that it does not show up
on other targets.
Tom Rini [Tue, 25 Feb 2025 17:11:32 +0000 (11:11 -0600)]
Merge patch series "Remove "saveenv" functionality from am57xx evms"
Anurag Dutta <a-dutta@ti.com> says:
Previously saved environment introduce discrepancies and may lead to
incompatibilities without default settings. This series removes the saved
environment functionality on am57xx evms so that the default configuration
is always loaded
Anurag Dutta [Sat, 8 Feb 2025 04:39:38 +0000 (10:09 +0530)]
configs: am57xx: Remove saved environments
Saved environments lead to inconsistencies leading to conflicts
with the default environment that U-boot should update during
development. Remove the previously saved environment so that
the default environment is always loaded.
Anurag Dutta [Sat, 8 Feb 2025 04:39:37 +0000 (10:09 +0530)]
configs: am57xx_hs: Remove saved environments
Saved environments cause inconsistencies leading to conflicts
with the default environment that U-boot should update during
development. Remove the previously saved environment so that
the default environment is always loaded.
Please pull the SoCFPGA changes for next from u-boot-socfpga, containing
boot support for the Altera SoCFPGA Agilex 5 platform in U-Boot. The
changes include:
1. Board-specific configurations and setup required to enable Agilex 5
operation in U-Boot.
2. Integration of cache coherency unit (CCU) initialization routine,
including CCU conguration in DT.
3. Clock, firewall (configured in DT), SMMU, low level initialization
specific to Agilex 5.
4. Integration of memory initialization routine, including DDR setup.
This patch set has been tested on Agilex 5 devkit with QSPI boot
(UBI/UBIFS) and RAM boot (TFTP & ARM DS debugger).
Automatically start watchdog timer for Agilex5. This
configuration is enabled by default in the Kconfig,
hence removing this configuration from Agilex5 defconfig.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Tien Fong Chee [Tue, 18 Feb 2025 08:35:09 +0000 (16:35 +0800)]
arm: socfpga: soc64: Add support for board_boot_order()
Add board_boot_order() to retrieve the list of boot devices from
spl-boot-order property in device tree. This board_boot_order()
would be used for all Intel SOC64 devices.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
arm: armv8: Improve SPL data save and restore implementation
Introduce a new symbol in the beginning of .data section in
the common ARMv8 linker script and use that as a reference
for data save and restore.
Previously, the code would rely on calculating the start of
the .data section address via data size, however, we observed
that the data size does not really reflect the SPL mapped
addresses.
In our case, the binman_sym section size was not included in
the data size, which will result in a wrong address for the
.data start section, which prevents us from properly saving
and restoring SPL data.
This approach skips the calculation for the starting address
of the .data section, and instead just defines the beginning
address of the .data section and calling the symbol as needed,
in which we think as a simpler and much more robust method.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
arm: socfpga: smc: Add memory coherency support to mailbox command
As cache is enabled in U-Boot and disabled in ATF(BL31). We need to
perform cache flush of buffers that are shared between U-Boot and
ATF using secure monitor calls.
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Tien Fong Chee [Tue, 18 Feb 2025 08:34:59 +0000 (16:34 +0800)]
arm: socfpga: agilex5: Add SMMU initialization
Allow non-secure accesses only with SMMU peripherals. This would protect
the content in DDR secure region from accidentally modified by SMMU
peripherals.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Tien Fong Chee [Thu, 8 Aug 2024 08:47:39 +0000 (16:47 +0800)]
arm: socfpga: agilex5: Enable cache flush for system memory cache in CCU
set/way instructions "dc cisw" which is used by the "dcache flush" command
only flushing CPU data caches from L1 -> L2 -> L3 to system memory cache in
cache coherency unit, hence this patch enables data flush from system
memory cache of CCU into DDR memory.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
These firewall configure settings are needed to disable firewall on
respective hardware component so both secure and non-secure transactions
are allowed.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
arm: socfpga: Add handoff data support for SoCFPGA Agilex5 device
Agilex5 supports both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and Agilex5 device.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
arm: socfpga: agilex5: Add warm reset mask for Agilex5
There are 5 L4 watchdogs and one SDM triggered warm reset bit
in Agilex5 reset manager "stat" register where bit 16:20 for L4
watchdogs. Assigning value 1 to these bits in the register address
will initiate SDM to trigger warm reset.
Introducing new warm reset mask for Agilex5 to trigger warm reset
to all five L4 watchdogs.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
drivers: clk: agilex5: Configure intosc as boot_clk source
Some customers prefer to minimize the use of external oscillators,
especially when using the FPGA first configuration mode.
By enabling the configuration of the HPS internal oscillator as
the boot_clk source instead of the default external oscillator,
(HPS_OSC_CLK) in non-secure boot scenarios, this allows them
to eliminate the need for an additional oscillator device and
a dedicated HPS pin, simplifying board layout and routing.
arm: socfpga: agilex5: Add new driver model for system manager in Agilex5
Initial creation of new system manager driver.
Add supports for the SOCFPGA System Manager Register block which
aggregates different peripheral function into one area.
On 64 bit ARM parts, the system manager only can be accessed during
EL3 mode, this driver model provide user the high level access
to system register and abstract user from low level access.
The base address of system manager can be retrieved
using DT framework through the System Manager driver.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com> Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Marek Vasut [Wed, 29 Jan 2025 11:15:54 +0000 (12:15 +0100)]
mmc: Fix size calculation for sector addressed MMC version 4
For eMMC v4 and newer that is smaller than 2 GiB, the JEDEC JESD84-B51
section 6.2.4 Configure partitions indicates that EXT_CSD SEC_COUNT
should not be used to determine device size, and instead device size
should be calculated from C_SIZE and C_SIZE_MULT.
This is not exactly accurate, the 2 GiB limit is not a hard line,
there are eMMC devices which are smaller than 2 GiB and still
require device size to be determined from EXT_CSD SEC_COUNT. The
hard line is instead OCR HCS bit, which indicates whether the device
is byte or sector addressed, the former applies to most devices
below 2 GiB, and the later applies mostly to devices above 2 GiB.
However, there are a couple of devices which are smaller than 2 GiB
and still set the OCR HCS bit to indicate they are sector addressed,
and therefore the size calculation for those devices should also
use EXT_CSD SEC_COUNT . Use mmc->high_capacity flag to discern the
devices instead of arbitrary 2 GiB limit. The mmc->high_capacity flag
reflects the OCR HCS bit state.
Fixes: 639b7827d1ca ("mmc: fix the condition for MMC version 4") Signed-off-by: Marek Vasut <marex@denx.de>
The length of buffers used to read inode tables, directory tables, and
reading a file are calculated as: number of blocks * block size, and
such plain multiplication is prone to overflowing (thus unsafe).
Replace it by __builtin_mul_overflow, i.e. safe math.
Signed-off-by: Joao Marcos Costa <joaomarcos.costa@bootlin.com>
Tom Rini [Sat, 22 Feb 2025 14:42:01 +0000 (08:42 -0600)]
Merge branch 'picasso' of https://source.denx.de/u-boot/custodians/u-boot-tegra
Branch contains bringup of Acer Iconia Tab A500 (codename picasso), a
Tegra 2 Android device with decent Linux kernel support. Ondevice tests
and U-Boot test suit all passed.
Tom Rini [Fri, 21 Feb 2025 14:34:34 +0000 (08:34 -0600)]
Merge patch series "Add preload_check_sign tool"
Paul HENRYS <paul.henrys_ext@softathome.com> says:
This serie of patches adds a new tool to authenticate files signed
with a preload header.
This tool is also used in the tests to actually verify the
authenticity of the file signed with such a preload header.
Tom Rini [Fri, 21 Feb 2025 14:24:49 +0000 (08:24 -0600)]
Merge branch 'fix-issues-and-update-pylint-version' into next
This merges a set of patches from myself and Simon Glass to resolve
various problems that the current version of pylint will report with our
codebase. After the problems are fixed, we update to the now current
version which is 3.3.4.
Udit Kumar [Thu, 13 Feb 2025 09:23:22 +0000 (14:53 +0530)]
remoteproc: k3-dsp: Flush D cache after loading firmware
Memory region used by remote cores was set to non-cached region but
commit 7c9c6e192580 ("arm: mach-k3: Merge initial memory maps") makes
all memory region as cached, unified across K3 devices.
This causes inconsistency while booting remote cores on devices, due to
cache incoherency between remote core and boot code.
So to make this operation coherent, cache the address and len while
loading ELF program headers to memory and flush that region in the next
cycle of load.
Paul HENRYS [Wed, 12 Feb 2025 09:31:24 +0000 (10:31 +0100)]
tools: Add preload_check_sign to authenticate images with a pre-load
preload_check_sign is added so that it can be used to authenticate images
signed with the pre-load signature supported by binman and U-Boot.
It could also be used to test the signature in binman tests signing
images with the pre-load.
Signed-off-by: Paul HENRYS <paul.henrys_ext@softathome.com>
Tom Rini [Wed, 12 Feb 2025 22:23:54 +0000 (16:23 -0600)]
test/py: Have test_usb.py raise an Exception with unsupported filesystems
With a newer pylint we get a warning about how offset could be used
before assigned. This is because when the underlying filesystem wasn't
one that is supported we would have runtime test failures. Address this
by raise'ing an Exception if fs is not supported.
Tom Rini [Wed, 12 Feb 2025 22:24:00 +0000 (16:24 -0600)]
test/py: Rework how test_ums.py handles (not) having write enabled
With a newer pylint version we get a warning about how mounted_test_fn
could be used before assignment. Evaluating the code, this can't happen
because we check for "not have_writable_fs_partition" and return before
moving to the part of the tests which use mounted_test_fn. However, we
should instead have this written so that we only try this part of the
test if have_writable_fs_partition is set, and this also fixes the
warning. As part of this we also move test_f and mounted_test_fn to the
section of code that already only does this if
have_writable_fs_partition is set.
Tom Rini [Wed, 12 Feb 2025 22:24:07 +0000 (16:24 -0600)]
test/py: Rework test_spi.py to assert we found output
When running a newer version of pylint it will complain that page_size
may be used before being assignment. Looking deeper what is going on is
that we could run in to the case where the regex we run for any of the
flash information fails but since we don't have a result, we don't check
it either. In the case of the rest of the numerical values we then have
some assignment (multiplying by some value) and so pylint doesn't
complain. Rework things to assert that each regex has a result and so
failure will stop the test and we won't have any use before assignment.
Tom Rini [Thu, 20 Feb 2025 22:14:53 +0000 (16:14 -0600)]
Merge patch series "FIT Image Boot Fixes for am57xx_hs_evm"
Anurag Dutta <a-dutta@ti.com> says:
The u-boot is unable to load the FIT image due to incorrect
boot arguments in case of am57_hs evm as can be seen in [1].
This series introduces multiple changes pertaining to several
environment variables and overlays that are responsible for
successful [2] loading of kernel image.
Sinthu Raja [Tue, 11 Feb 2025 09:49:30 +0000 (15:19 +0530)]
configs: omap5: Enable custom mmc boot to distroboot for AM57x
TI AM57x boards use a custom (though family common to TI boards) mechanism
for booting Linux. Add support to enable custom MMC boot as a default
option along with the distroboot approach.
Also, add supporting mmc boot environment variables which shall be used for
custom MMC boot
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Sinthu Raja [Tue, 11 Feb 2025 09:49:29 +0000 (15:19 +0530)]
include: configs: Override get_fit_config to get FIT config for AM57x
Kernel commit 837833a724b7 ("environment: ti: Add get_fit_config command
to get FIT config string") introduced "get_fit_config" in ti_armv7_common.h
to mangle the fdtfile name when used to select a config node from the OE
made FIT image. However, the ti_armv7_common.h is common for both K3 and
AM57xx platforms. AM57xx platforms' fdtfile name does not have '/' and
"conf-" prefix so the setexpr command fails and boot hangs.
Override the get_fit_config in AM57x specific config header to get the
correct FIT config name.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Daniel Schultz [Mon, 10 Feb 2025 15:25:48 +0000 (07:25 -0800)]
board: Phytec: phycore_am62x: Increase size for Image in SPI
Increase the maximum Image size from 23 MB to 26 MB by moving the
initramfs start address up. This gives us a bigger ranger to
provide kernel images which are not stripped down too much.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Daniel Schultz [Mon, 10 Feb 2025 15:25:47 +0000 (07:25 -0800)]
board: Phytec: phycore_am64x: Increase size for Image in SPI
Increase the maximum Image size from 23 MB to 26 MB by moving the
initramfs start address up. This gives us a bigger ranger to
provide kernel images which are not stripped down too much.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Enable ENV_IS_IN_SPI_FLASH to read the environment from the SPI
flash when booting from it. The oftree, kernel and ramdisk sizes
are located in this environment and therefore required to boot
an initramfs.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Enable ENV_IS_IN_SPI_FLASH to read the environment from the SPI
flash when booting from it. The oftree, kernel and ramdisk sizes
are located in this environment and therefore required to boot
an initramfs.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de> Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
configs: am62x_a53_usbdfu: enable USB MASS Storage command
The USB0 instance of USB on AM62 SoC when configured to operate in the
Gadget mode of operation can be used to mount an MMC/SD card on the USB
Host. Hence, enable support for the USB Mass Storage (ums) command.
Since this config fragment corresponds to USB DFU functionality which
configures the USB Controller in Gadget mode of operation, other SoCs
which include this fragment for DFU functionality can make use of the
USB MASS Storage functionality as well.
configs: j722s_evm_a53_defconfig: enable USB DFU support
The USB0 instance of USB on J722S SoC is a Designware USB Controller with
the same glue layer (wrapper) as AM62 SoC. In order to support USB DFU boot
and USB DFU flash with USB0, enable the corresponding glue layer driver.
configs: am62px_evm_a53_defconfig: enable USB DFU support
The config fragment "am62x_a53_usbdfu.config" which adds USB DFU support
for AM62x SoC is applicable to the AM62Px SoC as well. Hence, include it
in "am62px_evm_a53_defconfig" in order to enable support for USB DFU
flash and boot. Remove those configs from "am62px_evm_a53_defconfig" which
are present in the "am62x_a53_usbdfu.config" config fragment that is being
included.
board: ti: am62px: env: include environment for DFU Boot
Include the TI K3 DFU environment to support DFU Boot and DFU Flash.
Also add "usb" to the list of "boot_targets". While at it, add a newline
at the end of the file.
configs: am62ax_evm_a53_defconfig: enable USB DFU support
The config fragment "am62x_a53_usbdfu.config" which adds USB DFU support
for AM62x SoC is applicable to the AM62Ax SoC as well. Hence, include it
in "am62ax_evm_a53_defconfig" in order to enable support for USB DFU flash
and boot.
* create a parent device for all EFI block devices
* move lmb_map_update_notify() to EFI
* make efi_add_memory_map_pg() static
* remove comparisons to string literals from runtime
* ix potential deref-after-null
Other:
* avoid superfluous value check in lmb_map_update_notify()
* support more efi protocols in uuid_guid_get_str()
Please pull the fixes for rockchip platform:
- Fix for rk3399 bob and kevin
- Fix for sdram more than 4GB
- Fix for dwc_eth on rk356x/rk3588
- Fix for sdmmc access on rk33080rock-s9
When building with qemu_arm64_defconfig with CONFIG_CC_OPTIMIZE_FOR_DEBUG=y
and CONFIG_EFI_LOADER=n an error undefined reference to efi_add_memory_map_pg
occurs.
Move the EFI dependent part of lmb_map_update_notify() to the EFI
sub-system.
Reported-by: Liya Huang <1425075683@qq.com> Acked-by: Liya Huang <1425075683@qq.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
efi_driver: create a parent device for all EFI block devices
Up to now root has been the parent device for all block devices created via
calling ConnectController(). This does not work well together with the
implementation of bootstd.
Add a dummy parent device for all EFI block devices.
With this change EFI block devices are also accessible via commands like
'cat', 'load', and 'ls'.
Ilias Apalodimas [Fri, 14 Feb 2025 13:46:45 +0000 (15:46 +0200)]
efi_loader: remove comparisons to string literals from runtime
For EFI runtime services, we manage to preserve string literals
by placing the .efi_runtime section just before .data and preserving
it when marking the runtime memory by marking surrounding boottime
code as runtime. This is ok for now but will break if we update any
linker scripts and decouple .text and .runtime sections.
So let's define the strings we used to compare in the appropriate
section for runtime services
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tom Rini [Thu, 20 Feb 2025 00:49:47 +0000 (18:49 -0600)]
Merge patch series "bloblist: refactor xferlist and bloblist"
Tom Rini <trini@konsulko.com> says:
This small series separates "bloblist" and "standard passage" to allow
for these similar concepts to explore solutions to problems without
introduces breaking changes to the other.
Raymond Mao [Thu, 20 Feb 2025 00:02:20 +0000 (16:02 -0800)]
bloblist: kconfig for mandatory incoming standard passage
In previous commit, incoming standard passage is used by default
when initializing the bloblist, so explicitly BLOBLIST_PASSAGE is
no more needed.
Rename it as BLOBLIST_PASSAGE_MANDATORY to determine the behaviors
when an incoming transfer list does not exist or is invalid.
When it is selected, incoming standard passage is mandatory and
U-Boot will report an error when a valid incoming transfer list is
missing.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
Raymond Mao [Thu, 20 Feb 2025 00:02:19 +0000 (16:02 -0800)]
bloblist: refactor xferlist and bloblist
Refactor the xferlist to remove the relocating when bloblist passed
from the boot args.
Refactor bloblist init to use incoming standard passage by default
if a valid transfer list exists in the boot args.
For bloblist relocation, use the actual total size if it has a smaller
BLOBLIST_SIZE_RELOC.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org> Suggested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Jonas Karlman [Tue, 4 Feb 2025 21:38:43 +0000 (21:38 +0000)]
arm64: dts: rockchip: Fix sdmmc access on rk3308-rock-s0 v1.1 boards
BootROM leave GPIO4_D6 configured as SDMMC_PWREN function and DW MCI
driver set PRWEN high on MMC_POWER_UP and low on MMC_POWER_OFF.
Similarly U-Boot also set PRWEN high before accessing mmc.
However, HW revision prior to v1.2 must pull GPIO4_D6 low to access
sdmmc. For HW revision v1.2 the state of GPIO4_D6 has no impact.
Model an always-on active low fixed regulator using GPIO4_D6 to fix
use of sdmmc on older HW revisions of the board.
Jonas Karlman [Sun, 9 Feb 2025 23:27:56 +0000 (23:27 +0000)]
net: dwc_eth_qos_rockchip: Fix disable of RX/TX delay for RK3588
When rgmii-rxid/txid/id phy-mode is used the MAC should not add RX
and/or TX delay. Currently RX/TX delay is configured as enabled using
zero as delay value for the rgmii-rxid/txid/id modes.
Change to disable RX and/or TX delay and using zero as delay value.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 9 Feb 2025 23:27:55 +0000 (23:27 +0000)]
net: dwc_eth_qos_rockchip: Fix disable of RX/TX delay for RK356x
When rgmii-rxid/txid/id phy-mode is used the MAC should not add RX
and/or TX delay. Currently RX/TX delay is configured as enabled using
zero as delay value for the rgmii-rxid/txid/id modes.
Change to disable RX and/or TX delay and using zero as delay value.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 6 Jan 2025 21:39:42 +0000 (21:39 +0000)]
pinctrl: rockchip: rk3328: Fix pinmux for GPIO2-B and GPIO3-B pins
The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width,
correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is
recalculated so it remain unchanged. Add missing GPIO3-B1 to GPIO3-B7
pinmux data to rk3328_mux_recalced_data as mux register offset for these
pins does not follow rockchip convention.
This matches changes in following Linux commits:
- e8448a6c817c ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins")
- 5ef6914e0bf5 ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO3-B pins")
- 128f71fe014f ("pinctrl: rockchip: correct RK3328 iomux width flag for GPIO2-B pins")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 12 Jan 2025 22:27:29 +0000 (22:27 +0000)]
rockchip: rk3288: Use rk3288-cru.h from dts/upstream
clock/rk3288-cru.h in include/dt-bindings is almost identical to the
version in dts/upstream, remove the copy from include/dt-bindings to
only use the version from dts/upstream.
One clk, SCLK_MAC_PLL, is not part of the upstream bindings, this clk is
not used by upstream, in-tree or vendor DTs and can safely be dropped.
No functional change to board DTs is intended with this removal.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
projects / thirdparty / u-boot.git / log
