ada: Streamline propagation of controlled flags on types

The front-end maintains a set of 4 flags on (base) types that are used to
parameterize the implementation of controlled operations, and these flags
need to be propagated through composition and derivation.  This is done
on a per-flag basis in the current implementation with a few loopholes.

This introduces a Propagate_Controlled_Flags routine to that effect, which
is modeled on the existing Propagate_Concurrent_Flags routine, and is used
in most cases to do the propagation.  This also removes the handling of the
Finalize_Storage_Only flag from Inherit_Aspects_At_Freeze_Point, since the
associated aspect does not exist (only the pragma does).

gcc/ada/

* freeze.adb (Freeze_Array_Type): Call Propagate_Controlled_Flags
to propagate the controlled flags from the component to the array.
(Freeze_Record_Type): Propagate the Finalize_Storage_Only flag
from the components to the record.
* sem_ch3.adb (Analyze_Private_Extension_Declaration): Do not call
Propagate_Concurrent_Flags here but...
(Array_Type_Declaration): Tidy and call Propagate_Controlled_Flags
to propagate the controlled flags from the component to the array.
(Build_Derived_Private_Type): Do not propagate the controlled flags
manually here but...
(Build_Derived_Record_Type): ...call Propagate_Controlled_Flags to
propagate the controlled flags from parent to derived type.
(Build_Derived_Type): Likewise.
(Copy_Array_Base_Type_Attributes): Call Propagate_Controlled_Flags
to copy the controlled flags.
(Record_Type_Definition): Streamline the propagation of the
Finalize_Storage_Only flag from the components to the record.
* sem_ch7.adb (Preserve_Full_Attributes): Use Full_Base and call
Propagate_Controlled_Flags to copy the controlled flags.
* sem_ch9.adb (Analyze_Protected_Definition): Use canonical idiom
to compute Has_Controlled_Component.
(Analyze_Protected_Type_Declaration): Minor tweak.
* sem_ch13.adb (Inherit_Aspects_At_Freeze_Point): Do not deal with
Finalize_Storage_Only here.
* sem_util.ads (Propagate_Controlled_Flags): New declaration.
* sem_util.adb (Propagate_Controlled_Flags): New procedure.

ada: Remove redundant conditions from freezing code

Code cleanup; behavior is unaffected.

gcc/ada/

* freeze.adb (Check_Current_Instance): This routine is only called
with parameter E being a type entity, so there is no need to check
for types just before the equality with E.
* sem_ch13.adb (Analyze_Aspect_Specifications): Regroup condition
to avoid unnecessary evaluation.
(Check_Aspect_At_End_Of_Declarations): If In_Instance is true,
then the routine exits early.

ada: Fix style in freezing code

Code cleanup; semantics is unaffected.

gcc/ada/

* freeze.adb (Find_Aspect_No_Parts): Tune whitespace.
* sem_ch13.adb (Check_Aspect_At_End_Of_Declarations): Fix style.

ada: Remove Max_Entry_Queue_Depth pragma/aspect

It was implemented apparently because a very early version of AI12-0164
that standardizes GNAT's Max_Queue_Length opted for the subtly different
moniker, but later versions of the AI use Max_Entry_Queue_Length instead.

gcc/ada/

* aspects.ads (Aspect_Id): Remove Aspect_Max_Entry_Queue_Depth.
(global arrays): Remove entry for it.
* exp_ch9.adb (Expand_N_Protected_Type_Declaration): Remove
reference to pragma Max_Entry_Queue_Depth in comment.
* par-prag.adb (Prag): Remove handling of
Pragma_Max_Entry_Queue_Depth.
* sem_ch13.adb (Analyze_Aspect_Specifications): Remove reference
to aspect Max_Entry_Queue_Depth in comment.
(Analyze_Aspect_Specifications): Remove processing of aspect
Max_Entry_Queue_Depth.
(Check_Aspect_At_Freeze_Point): Likewise.
* sem_prag.ads (Find_Related_Declaration_Or_Body): Remove
reference to pragma Max_Entry_Queue_Depth in comment.
* sem_prag.adb (Analyze_Pragma): Remove processing of pragma
Max_Entry_Queue_Depth.
(Sig_Flags): Remove entry for Pragma_Max_Entry_Queue_Depth.
* sem_util.adb (Get_Max_Queue_Length): Remove handling of pragma
Max_Entry_Queue_Depth.
(Has_Max_Queue_Length): Likewise.
* snames.ads-tmpl (Name_Max_Entry_Queue_Depth): Move back from
pragmas section to others section.
(Pragma_Id): Remove Pragma_Max_Entry_Queue_Depth.

ada: Couple of minor fixes in GNAT Reference Manual

The Storage_Model pragma no longer exists.

gcc/ada/

* doc/gnat_rm/gnat_language_extensions.rst (Pragma Storage_Model):
Rename to Storage Model.
* doc/gnat_rm/implementation_defined_aspects.rst: Alphabetize.
* gnat_rm.texi: Regenerate.
* gnat_ugn.texi: Regenerate.

ada: Add Dump_Buffers hooks for code coverage

The purpose of this patch is to make it possible to set up code
coverage for the GNAT front end in gnat1 using GNATcoverage. It is
not obvious how to have GNATcoverage instrument gnat1's main function,
and since the front end has a clear entry point (Gnat1drv), we add
manual instrumentation annotations there.

gcc/ada/

* gnat1drv.adb (Gnat1drv): Add coverage instrumentation
annotations.

ada: Do not compute Has_Controlled_Component twice during freezing

The Has_Controlled_Component flag is computed twice during freezing when
expansion is enabled: in Freeze_Array_Type and Expand_Freeze_Array_Type
for array types, and in Freeze_Record_Type and Expand_Freeze_Record_Type
for record types.

This removes the latter computation in both cases, as well as moves the
computation of concurrent flags from the latter to the former places, which
happens to plug a loophole in the detection of errors when the No_Task_Parts
aspect is specified on peculiar types.

gcc/ada/

* exp_ch3.adb (Expand_Freeze_Array_Type): Do not propagate the
concurrent flags and the Has_Controlled_Component flag here.
(Expand_Freeze_Record_Type): Likewise.
* freeze.adb (Freeze_Array_Type): Propagate the concurrent flags.
(Freeze_Record_Type): Likewise.
* sem_util.adb (Has_Some_Controlled_Component): Adjust comment.

ada: Fix minor issues in comments

gcc/ada/

* mutably_tagged.ads: Fix minor issues in comments throughout.

ada: Document -gnatd_w for CCG

gcc/ada/

* debug.adb: Add documentation for -gnatd_w.

ada: Change messages for -gnatw.v to warnings

Previously this switch was emitting only info messages
which was both confusing in terms of the name of the
switch that was used internally and externally.

gcc/ada/

* doc/gnat_ugn/building_executable_programs_with_gnat.rst: Update
documentation for -gnatw.v.
* sem_ch13.adb: Convert all -gnatw.v related messages to warnings.
* gnat_ugn.texi: Regenerate.

ada: Convert -gnatw.n messages to warnings

Previously the messages produced by this warning switch
were info messages that were suppressed with the same
methods as regular warnings. Since info messages are now
separated as a completely different class of messages then
these messages should be converted back to warnings in order
for the previous pragma based suppression methods to work.

gcc/ada/

* doc/gnat_ugn/building_executable_programs_with_gnat.rst: Update
documentation for -gnatw.n switch.
* exp_util.adb: Convert info messages into warnings.
* gnat_ugn.texi: Regenerate.

ada: Add switch for suppressing info messages

Add a separate switch -gnatis to suppress info messages
separately from warning messages that are controlled by
-gnatws.

gcc/ada/

* doc/gnat_ugn/building_executable_programs_with_gnat.rst: Add
entry for -gnatis.
* errout.adb (Error_Msg_Internal): Stop printing info messages if
-gnatis was used.
* opt.ads: Add Info_Suppressed flag to track whether info messages
should be suppressed.
* switch-c.adb: Add parsing for -gnatis.
* gnat_ugn.texi: Regenerate.

ada: Treat Info-Warnings as Info messages

There was a general concept of info messages being a subset of
warnings. However that is no longer the case. Messages with an
info insertion character should be treated just as info messages.

gcc/ada/

* atree.ads: Remove Warning_Info_Messages.
* errout.adb: Remove various places where Warning_Info_Messages
was used.
* erroutc.adb: Remove various places where Warning_Info_Messages
was used. Create Error_Msg_Object objects with only an info
attribute if the message contained both info and warning insertion
characters. New method Has_Switch_Tag for detecting if a message
should have an error tag.
* errutil.adb: Create Error_Msg_Object objects with only an info
attribute if the message contained both info and warning insertion
characters.

ada: Update documentation for 'Super

This patch moves the documentation for 'Super from gnat language extensions to
experimental language extensions.

gcc/ada/

* doc/gnat_rm/gnat_language_extensions.rst: Add entry for 'Super.
* doc/gnat_rm/implementation_defined_attributes.rst: Remove entry
for 'Super.
* gnat_rm.texi: Regenerate.
* gnat_ugn.texi: Regenerate.

ada: Improve preprocessor error handling.

In some cases, gnatprep would correctly emit an error message and then
incorrectly exit with a return code of zero, indicating success.
In some cases, a correct message about an error detected by the integrated
preprocessor would be accompanied by an incorrect message indicating that
a source file could not be found.

gcc/ada/

* gprep.adb (Process_Files.Process_One_File): When calling OS_Exit in an error
path, pass in a Status parameter of 1 instead of 0 (because 0
indicates success).
* lib-load.adb (Load_Main_Source): Do not emit a message about a missing source file
if other error messages were generated by calling Load_Source_File;
the file isn't missing - it failed preprocessing.

ada: Fix list of attributes defined by Ada 2022

Recognize references to attributes Put_Image and Object_Size as
language-defined in Ada 2022 and implementation-defined in earlier
versions of Ada. Other attributes listed in Ada 2022 RM, K.2 and
currently implemented in GNAT are correctly categorized.

This change only affects code with restriction
No_Implementation_Attributes.

gcc/ada/

* sem_attr.adb (Attribute_22): Add Put_Image and Object_Size.
* sem_attr.ads (Attribute_Impl_Def): Remove Object_Size.

i386: Fix some ISA bit test in option_override

Adjust several new feature check in ix86_option_override_interal that
directly use TARGET_* instead of TARGET_*_P (opts->ix86_isa_flags)
to avoid cmdline option overrides target_attribute isa flag.

gcc/ChangeLog:

* config/i386/i386-options.cc (ix86_option_override_internal):
Use TARGET_*_P (opts->x_ix86_isa_flags*) instead of TARGET_*
for UINTR, LAM and APX_F.

gcc/testsuite/ChangeLog:

* gcc.target/i386/apx-ccmp-2.c: Remove -mno-apxf in option.
* gcc.target/i386/funcspec-56.inc: Drop uintr tests.
* gcc.target/i386/funcspec-6.c: Add uintr tests.

Fortran: Auto array allocation with function dependencies [PR59104]

2024-06-20  Paul Thomas  <pault@gcc.gnu.org>

gcc/fortran
PR fortran/59104
* dependency.cc (dependency_fcn, gfc_function_dependency): New
functions to detect dependency in array bounds and character
lengths on old style function results.
* dependency.h : Add prototype for gfc_function_dependency.
* error.cc (error_print): Remove trailing space.
* gfortran.h : Remove dummy_order and add fn_result_spec.
* symbol.cc : Remove declaration of next_dummy_order..
(gfc_set_sym_referenced): remove setting of symbol dummy order.
* trans-array.cc (gfc_trans_auto_array_allocation): Detect
non-dummy symbols with function dependencies and put the
allocation at the end of the initialization code.
* trans-decl.cc : Include dependency.h.
(decl_order): New function that determines uses the location
field of the symbol 'declared_at' to determine the order of two
declarations.
(gfc_defer_symbol_init): Call gfc_function_dependency to put
dependent symbols in the right part of the tlink chain. Use
the location field of the symbol declared_at to determine the
order of declarations.
(gfc_trans_auto_character_variable): Put character length
initialization of dependent symbols at the end of the chain.
* trans.cc (gfc_add_init_cleanup): Add boolean argument with
default false that determines whther an expression is placed at
the back or the front of the initialization chain.
* trans.h : Update the prototype for gfc_add_init_cleanup.

gcc/testsuite/
PR fortran/59104
* gfortran.dg/dependent_decls_2.f90: New test.

tree-optimization/114413 - SLP CSE after permute optimization

We currently fail to re-CSE SLP nodes after optimizing permutes
which results in off cost estimates.  For gcc.dg/vect/bb-slp-32.c
this shows in not re-using the SLP node with the load and arithmetic
for both the store and the reduction.  The following implements
CSE by re-bst-mapping nodes as finalization part of vect_optimize_slp.

I've tried to make the CSE part of permute materialization but it
isn't a very good fit there.  I've not bothered to implement something
more complete, also handling external defs or defs without
SLP_TREE_SCALAR_STMTS.

I realize this might result in more BB SLP which in turn might slow
down code given costing for BB SLP is difficult (even that we now
vectorize gcc.dg/vect/bb-slp-32.c on x86_64 might be not a good idea).
This is nevertheless feeding more accurate info to costing which is
good.

PR tree-optimization/114413
* tree-vect-slp.cc (release_scalar_stmts_to_slp_tree_map):
New function, split out from ...
(vect_analyze_slp): ... here.  Call it.
(vect_cse_slp_nodes): New function.
(vect_optimize_slp): Call it.

* gcc.dg/vect/bb-slp-32.c: Expect CSE and vectorization on x86.

build: Fix missing variable quotes and typo

When dlopen and pthread_create are in libc the variable is
set to "none required", therefore running configure will show
the following errors:

./configure: line 8997: test: too many arguments
./configure: line 8999: test: too many arguments
./configure: line 9003: test: too many arguments
./configure: line 9005: test: =: unary operator expected

ChangeLog:

PR bootstrap/115453
* configure.ac: Quote variable result of AC_SEARCH_LIBS.  Fix
typo ac_cv_search_pthread_crate.
* configure: Regenerate.

Signed-off-by: Collin Funk <collin.funk1@gmail.com>

vect: Tighten an assertion for lane-reducing in transform

According to logic of code nearby the assertion, all lane-reducing operations
should not appear, not just DOT_PROD_EXPR. Since "use_mask_by_cond_expr_p"
treats SAD_EXPR same as DOT_PROD_EXPR, and WIDEN_SUM_EXPR should not be allowed
by the following assertion "gcc_assert (commutative_binary_op_p (...))", so
tighten the assertion.

2024-06-16 Feng Xue <fxue@os.amperecomputing.com>

gcc/
* tree-vect-loop.cc (vect_transform_reduction): Change assertion to
cover all lane-reducing ops.

vect: Use an array to replace 3 relevant variables

It's better to place 3 relevant independent variables into array, since we
have requirement to access them via an index in the following patch. At the
same time, this change may get some duplicated code be more compact.

2024-06-16 Feng Xue <fxue@os.amperecomputing.com>

gcc/
* tree-vect-loop.cc (vect_transform_reduction): Replace vec_oprnds0/1/2
with one new array variable vec_oprnds[3].

vect: Use one reduction_type local variable

Two local variables were defined to refer same STMT_VINFO_REDUC_TYPE, better
to keep only one.

2024-06-16 Feng Xue <fxue@os.amperecomputing.com>

gcc/
* tree-vect-loop.cc (vectorizable_reduction): Remove v_reduc_type, and
replace it to another local variable reduction_type.

vect: Remove duplicated check on reduction operand

In vectorizable_reduction, one check on a reduction operand via index could be
contained by another one check via pointer, so remove the former.

2024-06-16 Feng Xue <fxue@os.amperecomputing.com>

gcc/
* tree-vect-loop.cc (vectorizable_reduction): Remove the duplicated
check.

vect: Add a function to check lane-reducing stmt

Add a utility function to check if a statement is lane-reducing operation,
which could simplify some existing code.

2024-06-16 Feng Xue <fxue@os.amperecomputing.com>

gcc/
* tree-vectorizer.h (lane_reducing_stmt_p): New function.
* tree-vect-slp.cc (vect_analyze_slp): Use new function
lane_reducing_stmt_p to check statement.

Daily bump.

Revert "build: Fix missing variable quotes"

This reverts commit c6a9ab8c920f297c4efd289182aef9fbc73f5906.

Revert "Build: Fix typo ac_cv_search_pthread_crate"

This reverts commit 8088374a868aacab4dff208ec3e3fde790a1d9a3.

[PATCH v2] RISC-V: Remove float vector eqne pattern

We can unify eqne and other comparison operations.

Tested on RV32 and RV64

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond
* config/riscv/vector.md (@pred_eqne<mode>_scalar): Remove patterns
(*pred_eqne<mode>_scalar_merge_tie_mask): Ditto
(*pred_eqne<mode>_scalar): Ditto
(*pred_eqne<mode>_scalar_narrow): Ditto

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/float-point-cmp-eqne.c: New test.

RISC-V: Promote Zaamo/Zalrsc to a when using an old binutils

Binutils 2.42 and before don't support Zaamo/Zalrsc. When users specify
both Zaamo and Zalrsc, promote them to 'a' in the -march string.

This does not affect testsuite results for users with old versions of binutils.
Testcases that failed due to 'call'/isa string continue to fail after this PATCH
when using an old version of binutils.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add 'a' extension to
riscv_combine_info.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>

bitint: Fix up lowering of COMPLEX_EXPR [PR115544]

We don't really support _Complex _BitInt(N), the only place we use
bitint complex types is for the .{ADD,SUB,MUL}_OVERFLOW internal function
results and COMPLEX_EXPR in the usual case should be either not present
yet because the ifns weren't folded and will be lowered, or optimized
into something simpler, because normally the complex bitint should be
used just for extracting the 2 subparts from it.
Still, with disabled optimizations it can occassionally happen that it
appears in the IL and that is why there is support for lowering those,
but it doesn't handle optimizing those too much, so if it uses SSA_NAME,
it relies on them having a backing VAR_DECL during the lowering.
This is normally achieves through the
                      && ((is_gimple_assign (use_stmt)
                           && (gimple_assign_rhs_code (use_stmt)
                               != COMPLEX_EXPR))
                          || gimple_code (use_stmt) == GIMPLE_COND)
hunk in gimple_lower_bitint, but as the following testcase shows, there
is one thing I've missed, the load optimization isn't guarded by the
above stuff.  So, either we'd need to add support for loads to
lower_complexexpr_stmt, or because they should be really rare, this
patch just disables the load optimization if at least one load use is
a COMPLEX_EXPR (like we do already for PHIs, calls, asm).

2024-06-19  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/115544
* gimple-lower-bitint.cc (gimple_lower_bitint): Disable optimizing
loads used by COMPLEX_EXPR operands.

* gcc.dg/bitint-107.c: New test.

i386: Zhaoxin shijidadao enablement

This patch enables -march/-mtune=shijidadao, costs and tunings are set
according to the characteristics of the processor.

gcc/ChangeLog:

* common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Recognize shijidadao.
* common/config/i386/i386-common.cc: Add shijidadao.
* common/config/i386/i386-cpuinfo.h (enum processor_subtypes):
Add ZHAOXIN_FAM7H_SHIJIDADAO.
* config.gcc: Add shijidadao.
* config/i386/driver-i386.cc (host_detect_local_cpu):
Let -march=native recognize shijidadao processors.
* config/i386/i386-c.cc (ix86_target_macros_internal): Add shijidadao.
* config/i386/i386-options.cc (m_ZHAOXIN): Add m_SHIJIDADAO.
(m_SHIJIDADAO): New definition.
* config/i386/i386.h (enum processor_type): Add PROCESSOR_SHIJIDADAO.
* config/i386/x86-tune-costs.h (struct processor_costs):
Add shijidadao_cost.
* config/i386/x86-tune-sched.cc (ix86_issue_rate): Add shijidadao.
(ix86_adjust_cost): Ditto.
* config/i386/x86-tune.def (X86_TUNE_USE_GATHER_2PARTS): Add m_SHIJIDADAO.
(X86_TUNE_USE_GATHER_4PARTS): Ditto.
(X86_TUNE_USE_GATHER_8PARTS): Ditto.
(X86_TUNE_AVOID_128FMA_CHAINS): Ditto.
* doc/extend.texi: Add details about shijidadao.
* doc/invoke.texi: Ditto.

gcc/testsuite/ChangeLog:

* g++.target/i386/mv32.C: Handle new -march
* gcc.target/i386/funcspec-56.inc: Ditto.

xtensa: Eliminate double MEMW insertions for volatile memory

This patch makes avoid inserting a MEMW instruction before a load/store
nstruction with volatile memory reference if there is already a MEMW
immediately before it.

gcc/ChangeLog:

* config/xtensa/xtensa.cc (print_operand):
When outputting MEMW before the instruction, check if the previous
instruction is already that.

libstdc++: Consistently indent <future> with tabs

libstdc++-v3/ChangeLog:

* include/std/future: Adjust whitespace to use tabs for
indentation.

libstdc++: Add noexcept to some std::promise shared state internals

Making the state ready for a std::promise<void> only needs to move a
unique_ptr, which cannot throw. Make its call operator noexcept.
Similarly, making the state ready by storing an exception_ptr also can't
throw, so make that call operator noexcept too.

libstdc++-v3/ChangeLog:

* include/std/future (_State_baseV2::_Setter<R, void>): Add
noexcept to call operator.
(_State_baseV2::_Setter<R, __exception_ptr_tag>): Likewise.

libstdc++: Add conditional noexcept to std::pair default ctor

Most of std::pair constructors implemented using C++20 concepts have a
conditional noexcept-specifier, but the default constructor doesn't.
This fixes that.

libstdc++-v3/ChangeLog:

* include/bits/stl_pair.h [__cpp_lib_concepts] (pair()): Add
conditional noexcept.

Fortran: fix for CHARACTER(len=*) dummies with bind(C) [PR115390]

gcc/fortran/ChangeLog:

PR fortran/115390
* trans-decl.cc (gfc_conv_cfi_to_gfc): Move derivation of type sizes
for character via gfc_trans_vla_type_sizes to after character length
has been set.

gcc/testsuite/ChangeLog:

PR fortran/115390
* gfortran.dg/bind_c_char_11.f90: New test.

arm: Add support for MVE Tail-Predicated Low Overhead Loops

This patch adds support for MVE Tail-Predicated Low Overhead Loops by using the
doloop funcitonality added to support predicated vectorized hardware loops.

gcc/ChangeLog:

* config/arm/arm-protos.h (arm_target_bb_ok_for_lob): Change
declaration to pass basic_block.
(arm_attempt_dlstp_transform): New declaration.
* config/arm/arm.cc (TARGET_LOOP_UNROLL_ADJUST): Define targethook.
(TARGET_PREDICT_DOLOOP_P): Likewise.
(arm_target_bb_ok_for_lob): Adapt condition.
(arm_mve_get_vctp_lanes): New function.
(arm_dl_usage_type): New internal enum.
(arm_get_required_vpr_reg): New function.
(arm_get_required_vpr_reg_param): New function.
(arm_get_required_vpr_reg_ret_val): New function.
(arm_mve_get_loop_vctp): New function.
(arm_mve_insn_predicated_by): New function.
(arm_mve_across_lane_insn_p): New function.
(arm_mve_load_store_insn_p): New function.
(arm_mve_impl_pred_on_outputs_p): New function.
(arm_mve_impl_pred_on_inputs_p): New function.
(arm_last_vect_def_insn): New function.
(arm_mve_impl_predicated_p): New function.
(arm_mve_check_reg_origin_is_num_elems): New function.
(arm_mve_dlstp_check_inc_counter): New function.
(arm_mve_dlstp_check_dec_counter): New function.
(arm_mve_loop_valid_for_dlstp): New function.
(arm_predict_doloop_p): New function.
(arm_loop_unroll_adjust): New function.
(arm_emit_mve_unpredicated_insn_to_seq): New function.
(arm_attempt_dlstp_transform): New function.
* config/arm/arm.opt (mdlstp): New option.
* config/arm/iterators.md (dlstp_elemsize, letp_num_lanes,
letp_num_lanes_neg, letp_num_lanes_minus_1): New attributes.
(DLSTP, LETP): New iterators.
* config/arm/mve.md (predicated_doloop_end_internal<letp_num_lanes>,
dlstp<dlstp_elemsize>_insn): New insn patterns.
* config/arm/thumb2.md (doloop_end): Adapt to support tail-predicated
loops.
(doloop_begin): Likewise.
* config/arm/types.md (mve_misc): New mve type to represent
predicated_loop_end insn sequences.
* config/arm/unspecs.md:
(DLSTP8, DLSTP16, DLSTP32, DSLTP64,
LETP8, LETP16, LETP32, LETP64): New unspecs for DLSTP and LETP.

gcc/testsuite/ChangeLog:

* gcc.target/arm/lob.h: Add new helpers.
* gcc.target/arm/lob1.c: Use new helpers.
* gcc.target/arm/lob6.c: Likewise.
* gcc.target/arm/mve/dlstp-compile-asm-1.c: New test.
* gcc.target/arm/mve/dlstp-compile-asm-2.c: New test.
* gcc.target/arm/mve/dlstp-compile-asm-3.c: New test.
* gcc.target/arm/mve/dlstp-int8x16.c: New test.
* gcc.target/arm/mve/dlstp-int8x16-run.c: New test.
* gcc.target/arm/mve/dlstp-int16x8.c: New test.
* gcc.target/arm/mve/dlstp-int16x8-run.c: New test.
* gcc.target/arm/mve/dlstp-int32x4.c: New test.
* gcc.target/arm/mve/dlstp-int32x4-run.c: New test.
* gcc.target/arm/mve/dlstp-int64x2.c: New test.
* gcc.target/arm/mve/dlstp-int64x2-run.c: New test.
* gcc.target/arm/mve/dlstp-invalid-asm.c: New test.

Co-authored-by: Stam Markianos-Wright <stam.markianos-wright@arm.com>

doloop: Add support for predicated vectorized loops

This patch adds support in the target agnostic doloop pass for the detection of
predicated vectorized hardware loops.  Arm is currently the only target that
will make use of this feature.

gcc/ChangeLog:

* df-core.cc (df_bb_regno_only_def_find): New helper function.
* df.h (df_bb_regno_only_def_find): Declare new function.
* loop-doloop.cc (doloop_condition_get): Add support for detecting
predicated vectorized hardware loops.
(doloop_modify): Add support for GTU condition checks.
(doloop_optimize): Update costing computation to support alterations to
desc->niter_expr by the backend.

Co-authored-by: Stam Markianos-Wright <stam.markianos-wright@arm.com>

Build: Fix typo ac_cv_search_pthread_crate

The correct variable name is
  ac_cv_search_pthread_create

ChangeLog:
PR bootstrap/115453
* configure.ac: Fix typo ac_cv_search_pthread_crate.
* configure: Regnerate.

RISC-V: Add testcases for unsigned .SAT_SUB vector form 10

After the middle-end support the form 10 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode,  thus
add more test case to cover that.

Form 10:
  #define DEF_VEC_SAT_U_SUB_FMT_10(T)                                   \
  void __attribute__((noinline))                                        \
  vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                     \
    unsigned i;                                                         \
    for (i = 0; i < limit; i++)                                         \
      {                                                                 \
        T x = op_1[i];                                                  \
        T y = op_2[i];                                                  \
        T ret;                                                          \
        bool overflow = __builtin_sub_overflow (x, y, &ret);            \
        out[i] = !overflow ? ret : 0;                                   \
      }                                                                 \
  }

Passed the rv64gcv regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_SUB vector form 9

After the middle-end support the form 9 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode,  thus
add more test case to cover that.

Form 9:
  #define DEF_VEC_SAT_U_SUB_FMT_9(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_sub_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        T ret;                                                         \
        bool overflow = __builtin_sub_overflow (x, y, &ret);           \
        out[i] = overflow ? 0 : ret;                                   \
      }                                                                \
  }

Passed the rv64gcv regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_SUB vector form 8

After the middle-end support the form 8 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode,  thus
add more test case to cover that.

Form 8:
  #define DEF_VEC_SAT_U_SUB_FMT_8(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_sub_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        T ret;                                                         \
        T overflow = __builtin_sub_overflow (x, y, &ret);              \
        out[i] = ret & (T)-(!overflow);                                \
      }                                                                \
  }

Passed the rv64gcv regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_SUB vector form 7

After the middle-end support the form 7 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode,  thus
add more test case to cover that.

Form 7:
  #define DEF_VEC_SAT_U_SUB_FMT_7(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_sub_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        T ret;                                                         \
        T overflow = __builtin_sub_overflow (x, y, &ret);              \
        out[i] = ret & (T)(overflow - 1);                              \
      }                                                                \
  }

Passed the rv64gcv regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_SUB vector form 6

After the middle-end support the form 6 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode,  thus
add more test case to cover that.

Form 6:
  #define DEF_VEC_SAT_U_SUB_FMT_6(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        out[i] = x <= y ? 0 : x - y;                                   \
      }                                                                \
  }

Passed the rv64gcv regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_SUB vector form 5

After the middle-end support the form 5 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode,  thus
add more test case to cover that.

Form 5:
  #define DEF_VEC_SAT_U_SUB_FMT_5(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        out[i] = x < y ? 0 : x - y;                                    \
      }                                                                \
  }

Passed the rv64gcv regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_SUB vector form 4

After the middle-end support the form 4 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode,  thus
add more test case to cover that.

Form 4:
  #define DEF_VEC_SAT_U_SUB_FMT_4(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        out[i] = x >= y ? x - y : 0;                                   \
      }                                                                \
  }

Passed the rv64gcv regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_SUB vector form 3

After the middle-end support the form 3 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode,  thus
add more test case to cover that.

Form 3:
  #define DEF_VEC_SAT_U_SUB_FMT_3(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        out[i] = x > y ? x - y : 0;                                    \
      }                                                                \
  }

Passed the rv64gcv regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

libstdc++: Fix warning regressions in <bits/stl_tempbuf.h>

I caused some new warnings with -Wsystem-headers with my recent changes
to std::get_temporary_buffer and std::_Temporary_buffer. There's a
-Wsign-compare warning which can be avoided by casting the ptrdiff_t
argument to size_t (which also conveniently rejects negative values).

There's also a -Wdeprecated-declarations warning because I moved where
std::get_temporary_buffer is called, but didn't move the diagnostic
pragmas that suppress the warning for calling it.

libstdc++-v3/ChangeLog:

* include/bits/stl_tempbuf.h (__get_temporary_buffer): Cast
argument to size_t to handle negative values and suppress
-Wsign-compare warning.
(_Temporary_buffer): Move diagnostic pragmas to new location of
call to std::get_temporary_buffer.

build: Fix missing variable quotes

When dlopen and pthread_create are in libc the variable is
set to "none required", therefore running configure will show
the following errors:

./configure: line 8997: test: too many arguments
./configure: line 8999: test: too many arguments
./configure: line 9003: test: too many arguments
./configure: line 9005: test: =: unary operator expected

gcc/configure also has a similar problem on
gcc_cv_as_mips_explicit_relocs:

./gcc/configure: line 30242: test: =: unary operator expected

ChangeLog:

* configure.ac: Quote variable result of AC_SEARCH_LIBS.
* configure: Regenerate.

gcc/ChangeLog:

* configure.ac: Add missing quotation of variable
gcc_cv_as_mips_explicit_relocs.
* configure: Regenerate.

Signed-off-by: Collin Funk <collin.funk1@gmail.com>

Improve gcc.dg/vect/bb-slp-32.c testcase

The following adds a correctness check to the combined store/reduce
vectorization.

* gcc.dg/vect/bb-slp-32.c: Add check for correctness.

Fortran: Set the vptr of a class typed result.

PR fortran/90076

gcc/fortran/ChangeLog:

* trans-decl.cc (gfc_generate_function_code): Set vptr for
results to declared class type.
* trans-expr.cc (gfc_reset_vptr): Allow to provide the typespec
instead of the expression.
* trans.h (gfc_reset_vptr): Same.

gcc/testsuite/ChangeLog:

* gfortran.dg/class_76.f90: Add declared vtab occurrence.
* gfortran.dg/class_78.f90: New test.

xtensa: constantsynth: Reforge to fix some non-fatal issues

The previous constant synthesis logic had some issues that were non-fatal
but worth considering:

- It didn't work with DFmode literals, because those were cast to SImode
   rather SFmode when splitting into two natural-width words by
   split_double().

- It didn't work with large literals when TARGET_AUTO_LITPOOLS was enabled,
   because those were relaxed MOVI immediates rather references to literal
   pool entries,

- It didn't take into account that when literals with the same RTL
   representation are pooled multiple times within a function, those entries
   are shared (especially important when optimizing for size).

This patch addresses the above issues by making appropriate tweaks to the
constant synthesis logic.

gcc/ChangeLog:

* config/xtensa/xtensa-protos.h (xtensa_constantsynth):
Change the second argument from HOST_WIDE_INT to rtx.
* config/xtensa/xtensa.cc (#include):
Add "context.h" and "pass_manager.h".
(machine_function): Add a new hash_map field "litpool_usage".
(xtensa_constantsynth): Make "src" (the second operand) accept
RTX literal instead of its value, and treat both bare and pooled
SI/SFmode literals equally by bit-exact canonicalization into
CONST_INT RTX internally.  And then, make avoid synthesis if
such multiple identical canonicalized literals are found in same
function when optimizing for size.  Finally, for literals where
synthesis is not possible or has been avoided, re-emit "move"
RTXes with canonicalized ones to increase the chances of sharing
literal pool entries.
* config/xtensa/xtensa.md (split patterns for constant synthesis):
Change to simply invoke xtensa_constantsynth() as mentioned above,
and add new patterns for when TARGET_AUTO_LITPOOLS is enabled.

RISC-V: Add testcases for unsigned .SAT_ADD vector form 8

After the middle-end support the form 8 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 8.

Form 8:
  #define DEF_VEC_SAT_U_ADD_FMT_8(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        out[i] = x > (T)(x + y) ? -1 : (x + y);                        \
      }                                                                \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-32.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_ADD vector form 7

After the middle-end support the form 7 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 7.

Form 7:
  #define DEF_VEC_SAT_U_ADD_FMT_7(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_add_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        out[i] = (T)(x + y) < x ? -1 : (x + y);                        \
      }                                                                \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-25.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-26.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-27.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-28.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_ADD vector form 6

After the middle-end support the form 6 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 6.

Form 6:
  #define DEF_VEC_SAT_U_ADD_FMT_6(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        out[i] = x <= (T)(x + y) ? (x + y) : -1;                       \
      }                                                                \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_ADD vector form 5

After the middle-end support the form 5 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 5.

Form 5:
  #define DEF_VEC_SAT_U_ADD_FMT_5(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        T ret;                                                         \
        out[i] = __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1;  \
      }                                                                \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-17.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-18.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-19.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-20.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_ADD vector form 4

After the middle-end support the form 4 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 4.

Form 4:
  #define DEF_VEC_SAT_U_ADD_FMT_4(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        T ret;                                                         \
        out[i] = __builtin_add_overflow (x, y, &ret) ? -1 : ret;       \
      }                                                                \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_ADD vector form 3

After the middle-end support the form 3 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 3.

Form 3:
  #define DEF_VEC_SAT_U_ADD_FMT_3(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        T ret;                                                         \
        T overflow = __builtin_add_overflow (x, y, &ret);              \
        out[i] = (T)(-overflow) | ret;                                 \
      }                                                                \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_ADD vector form 2

After the middle-end support the form 2 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 2.

Form 2:
  #define DEF_VEC_SAT_U_ADD_FMT_2(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        out[i] = (T)(x + y) >= x ? (x + y) : -1;                       \
      }                                                                \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12

After the middle-end support the form 12 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 12.

Form 12:
  #define DEF_SAT_U_SUB_FMT_12(T)                        \
  T __attribute__((noinline))                            \
  sat_u_sub_##T##_fmt_12 (T x, T y)                      \
  {                                                      \
    T ret;                                               \
    bool overflow = __builtin_sub_overflow (x, y, &ret); \
    return !overflow ? ret : 0;                          \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for
testing.
* gcc.target/riscv/sat_u_sub-45.c: New test.
* gcc.target/riscv/sat_u_sub-46.c: New test.
* gcc.target/riscv/sat_u_sub-47.c: New test.
* gcc.target/riscv/sat_u_sub-48.c: New test.
* gcc.target/riscv/sat_u_sub-run-45.c: New test.
* gcc.target/riscv/sat_u_sub-run-46.c: New test.
* gcc.target/riscv/sat_u_sub-run-47.c: New test.
* gcc.target/riscv/sat_u_sub-run-48.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11

After the middle-end support the form 11 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 11.

Form 11:
  #define DEF_SAT_U_SUB_FMT_11(T)                        \
  T __attribute__((noinline))                            \
  sat_u_sub_##T##_fmt_11 (T x, T y)                      \
  {                                                      \
    T ret;                                               \
    bool overflow = __builtin_sub_overflow (x, y, &ret); \
    return overflow ? 0 : ret;                           \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/sat_u_sub-41.c: New test.
* gcc.target/riscv/sat_u_sub-42.c: New test.
* gcc.target/riscv/sat_u_sub-43.c: New test.
* gcc.target/riscv/sat_u_sub-44.c: New test.
* gcc.target/riscv/sat_u_sub-run-41.c: New test.
* gcc.target/riscv/sat_u_sub-run-42.c: New test.
* gcc.target/riscv/sat_u_sub-run-43.c: New test.
* gcc.target/riscv/sat_u_sub-run-44.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

[MAINTAINERS] Update my email address and move to DCO.

Signed-off-by: Ramana Radhakrishnan <ramanara@nvidia.com>
* MAINTAINERS: Update my email address.

Daily bump.

RISC-V: Move mode assertion out of conditional branch in emit_insn

When emitting insns, we have an early assertion to ensure the input
operand's mode and the expanded operand's mode are the same; however, it
does not perform this check if the pattern does not have an explicit
machine mode specifying the operand. In this scenario, it will always
assume that mode = Pmode to correctly satisfy the
maybe_legitimize_operand check, however, there may be problems when
working in 32 bit environments.

Make the assert unconditional and replace it with an internal error for
more descriptive logging

gcc/ChangeLog:

* config/riscv/riscv-v.cc: Move assert out of conditional block

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
Co-authored-by: Robin Dapp <rdapp@ventanamicro.com>

RISC-V: Fix vwsll combine on rv32 targets

On rv32 targets, vwsll_zext1_scalar_<mode> would trigger an ice in
maybe_legitimize_instruction when zero extending a uint32 to uint64 due
to a mismatch between the input operand's mode (DI) and the expanded insn
operand's mode (Pmode == SI). Ensure that mode of the operands match

gcc/ChangeLog:

* config/riscv/autovec-opt.md: Fix mode mismatch

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
Co-authored-by: Robin Dapp <rdapp@ventanamicro.com>

[committed] [RISC-V] Fix wrong patch application

Applied the wrong patch which didn't have the final testsuite adjustment to
skip -Os on the new test.  Fixed thusly.

Pushed to the trunk.

gcc/testsuite
* gcc.target/riscv/zbs-ext-2.c: Do not run for -Os.

aarch64: Add comment about thunderxt81/t83 being aliases

Since these were already aliases just make it clear on that.

gcc/ChangeLog:

* config/aarch64/aarch64-cores.def: Add comment
saying thunderxt81/t83 are aliases of octeontx81/83.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

aarch64: make thunderxt88p1 an alias of thunderxt88

Since r7-6575-g71aba51d6460ff, thunderxt88 has been the same as thunderxt88p1 so let's make
them a true alias and remove the odd variant handling and moves it below thunderxt88.

Bootstrapped and tested on aarch64-linux-gnu with no regressions.

gcc/ChangeLog:

* config/aarch64/aarch64-cores.def (thunderxt88p1): Make an alias of thunderxt88 and
move below thunderxt88.
* config/aarch64/aarch64-tune.md: Regenerate.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

diagnostics: rename tree-diagnostic-path.cc to diagnostic-path.cc

Now that nothing in tree-diagnostic-path.cc uses "tree", this patch
renames it to diagnostic-path.cc and moves it from OBJS to
OBJS-libcommon.

No functional change intended.

gcc/ChangeLog:
* Makefile.in (OBJS): Move selftest-diagnostic-path.o,
selftest-logical-location.o, and tree-diagnostic-path.o to...
(OBJS-libcommon): ...here, renaming tree-diagnostic-path.o to
diagnostic-path.o.
* tree-diagnostic-path.cc: Rename to...
* diagnostic-path.cc: ...this.  Drop include of "tree.h".
(tree_diagnostic_path_cc_tests): Rename to...
(diagnostic_path_cc_tests): ...this.
* selftest-run-tests.cc (selftest::run_tests): Update for above
renaming.
* selftest.h (tree_diagnostic_path_cc_tests): Rename decl to...
(diagnostic_path_cc_tests): ...this.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

diagnostics: eliminate diagnostic_context::m_print_path callback

No functional change intended.

gcc/ChangeLog:
* diagnostic-format-json.cc (diagnostic_output_format_init_json):
Replace clearing of diagnostic_context::m_print_path callback with
setting the path format to DPF_NONE.
* diagnostic-format-sarif.cc
(diagnostic_output_format_init_sarif): Likewise.
* diagnostic.cc (diagnostic_context::show_any_path): Replace call
to diagnostic_context::m_print_path callback with a direct call to
diagnostic_context::print_path.
* diagnostic.h (diagnostic_context::print_path): New decl.
(diagnostic_context::m_print_path): Delete callback.
* tree-diagnostic-path.cc (default_tree_diagnostic_path_printer):
Convert to...
(diagnostic_context::print_path): ...this.
* tree-diagnostic.cc (tree_diagnostics_defaults): Delete
initialization of m_print_path.
* tree-diagnostic.h (default_tree_diagnostic_path_printer): Delete
decl.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

diagnostics: introduce diagnostic-macro-unwinding.h/cc

Eliminate a dependency on "tree" from the code used by
diagnostic_path handling.

No functional change intended.

gcc/ChangeLog:
* Makefile.in (OBJS): Add diagnostic-macro-unwinding.o.

gcc/c-family/ChangeLog:
* c-opts.cc: Replace include of "tree-diagnostic.h" with
"diagnostic-macro-unwinding.h".

gcc/ChangeLog:
* diagnostic-macro-unwinding.cc: New file, with material taken
from tree-diagnostic.cc.
* diagnostic-macro-unwinding.h: New file, with material taken
from tree-diagnostic.h.
* tree-diagnostic-path.cc: Repalce include of "tree-diagnostic.h"
with "diagnostic-macro-unwinding.h".
* tree-diagnostic.cc (struct loc_map_pair): Move to
diagnostic-macro-unwinding.cc.
(maybe_unwind_expanded_macro_loc): Likewise.
(virt_loc_aware_diagnostic_finalizer): Likewise.
* tree-diagnostic.h (virt_loc_aware_diagnostic_finalizer): Move
decl to diagnostic-macro-unwinding.h.
(maybe_unwind_expanded_macro_loc): Likewise.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

diagnostics: eliminate diagnostic_context::m_make_json_for_path

Now that the path-handling code for json_output_format no longer
needs "tree", and thus can be in OBJS-libcommon we can move it
from tree-diagnostic-path.cc to diagnostic-format-json.cc where it
should have been all along.

No functional change intended.

gcc/ChangeLog:
* diagnostic-format-json.cc: Include "diagnostic-path.h" and
"logical-location.h".
(make_json_for_path): Move tree-diagnostic-path.cc's
default_tree_make_json_for_path here, renaming it and making it
static.
(json_output_format::on_end_diagnostic): Replace call of
m_context's m_make_json_for_path callback with a direct call to
make_json_for_path.
* diagnostic.h (diagnostic_context::m_make_json_for_path): Drop
field.
* tree-diagnostic-path.cc: Drop include of "json.h".
(default_tree_make_json_for_path): Rename to make_json_for_path
and move to diagnostic-format-json.cc.
* tree-diagnostic.cc (tree_diagnostics_defaults): Drop
initialization of m_make_json_for_path.
* tree-diagnostic.h (default_tree_make_json_for): Delete decl.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

diagnostics: remove tree usage from tree-diagnostic-path.cc

No functional change intended.

gcc/ChangeLog:
* Makefile.in (OBJS): Add selftest-diagnostic-path.o and
selftest-logical-location.o.
* logical-location.h: Include "label-text.h".
(class logical_location): Update leading comment.
* selftest-diagnostic-path.cc: New file, adapted from
simple-diagnostic-path.cc and from material in
tree-diagnostic-path.cc.
* selftest-diagnostic-path.h: New file, adapted from
simple-diagnostic-path.h and from material in
tree-diagnostic-path.cc.
* selftest-logical-location.cc: New file.
* selftest-logical-location.h: New file.
* tree-diagnostic-path.cc: Remove includes of "tree-pretty-print.h",
"langhooks.h", and "simple-diagnostic-path.h".  Add include of
"selftest-diagnostic-path.h".
(class test_diagnostic_path): Delete, in favor of new
implementation in selftest-diagnostic-path.{h,cc}, which is
directly derived from diagnostic_path, rather than from
simple_diagnostic_path.
(selftest::test_intraprocedural_path): Eliminate tree usage,
via change to test_diagnostic_path, using strings rather than
function_decls for identifying functions in the test.
(selftest::test_interprocedural_path_1): Likewise.
(selftest::test_interprocedural_path_2): Likewise.
(selftest::test_recursion): Likewise.
(selftest::test_control_flow_1): Likewise.
(selftest::test_control_flow_2): Likewise.
(selftest::test_control_flow_3): Likewise.
(selftest::assert_cfg_edge_path_streq): Likewise.
(selftest::test_control_flow_5): Likewise.
(selftest::test_control_flow_6): Likewise.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

diagnostics: eliminate "tree" from diagnostic_{event,path}

This patch eliminates the use of "tree" from diagnostic_{event,path} in
favor of const logical_location *.

No functional change intended.

gcc/analyzer/ChangeLog:
* checker-event.h (checker_event::fndecl): Drop "final" and
"override", converting from a vfunc implementation to a plain
accessor.
* checker-path.cc (checker_path::same_function_p): New.
* checker-path.h (checker_path::same_function_p): New decl.

gcc/ChangeLog:
* diagnostic.cc: Include "logical-location.h".
(diagnostic_path::get_first_event_in_a_function): Fix typo in
leading comment.  Rewrite to use logical_location rather than
tree.  Drop test on stack depth.
(diagnostic_path::interprocedural_p): Rewrite to use
logical_location rather than tree.
(logical_location::function_p): New.
* diagnostic-path.h (diagnostic_event::get_fndecl): Eliminate
vfunc.
(diagnostic_path::same_function_p): New pure virtual func.
* logical-location.h (logical_location::get_name_for_path_output):
New pure virtual func.
* simple-diagnostic-path.cc
(simple_diagnostic_path::same_function_p): New.
(simple_diagnostic_event::simple_diagnostic_event): Initialize
m_logical_loc.
* simple-diagnostic-path.h: Include "tree-logical-location.h".
(simple_diagnostic_event::get_fndecl): Convert from a vfunc
implementation to an accessor.
(simple_diagnostic_event::get_logical_location): Use
m_logical_loc.
(simple_diagnostic_event::m_logical_loc): New field.
(simple_diagnostic_path::same_function_p): New decl.
* tree-diagnostic-path.cc: Move pragma disabling -Wformat-diag to
cover the whole file.
(can_consolidate_events): Add params "path", "ev1_idx", and
"ev2_idx".  Rewrite to use diagnostic_path::same_function_p rather
than tree.
(per_thread_summary::per_thread_summary): Add "path" param
(per_thread_summary::m_path): New field.
(event_range::event_range): Update for conversion of m_fndecl to
m_logical_loc.
(event_range::maybe_add_event): Rename param "idx" to
"new_ev_idx".  Update call to can_consolidate_events to pass in
"m_path", "m_start_idx", and "new_ev_idx".
(event_range::m_fndecl): Replace with...
(event_range::m_logical_loc): ...this.
(path_summary::get_or_create_events_for_thread_id): Pass "path" to
per_thread_summary ctor.
(per_thread_summary::interprocedural_p): Rewrite to use
diagnostic_path::same_function_p rather than tree.
(print_fndecl): Delete.
(thread_event_printer::print_swimlane_for_event_range): Update for
conversion from tree to logical_location.
(default_tree_diagnostic_path_printer): Likewise.
(default_tree_make_json_for_path): Likewise.
* tree-logical-location.cc: Include "intl.h".
(compiler_logical_location::get_name_for_tree_for_path_output):
New.
(tree_logical_location::get_name_for_path_output): New.
(current_fndecl_logical_location::get_name_for_path_output): New.
* tree-logical-location.h
(compiler_logical_location::get_name_for_tree_for_path_output):
New decl.
(tree_logical_location::get_name_for_path_output): New decl.
(current_fndecl_logical_location::get_name_for_path_output): New
decl.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

diagnostics: move simple_diagnostic_{path,thread,event} to their own .h/cc

As work towards eliminating the dependency on "tree" from
path-printing, move these classes to a new simple-diagnostic-path.h/cc.

No functional change intended.

gcc/analyzer/ChangeLog:
* checker-path.h: Include "simple-diagnostic-path.h".

gcc/ChangeLog:
* Makefile.in (OBJS): Add simple-diagnostic-path.o.
* diagnostic-path.h (class simple_diagnostic_event): Move to
simple-diagnostic-path.h.
(class simple_diagnostic_thread): Likewise.
(class simple_diagnostic_path): Likewise.
* diagnostic.cc (simple_diagnostic_path::simple_diagnostic_path):
Move to simple-diagnostic-path.cc.
(simple_diagnostic_path::num_events): Likewise.
(simple_diagnostic_path::get_event): Likewise.
(simple_diagnostic_path::num_threads): Likewise.
(simple_diagnostic_path::get_thread): Likewise.
(simple_diagnostic_path::add_thread): Likewise.
(simple_diagnostic_path::add_event): Likewise.
(simple_diagnostic_path::add_thread_event): Likewise.
(simple_diagnostic_path::connect_to_next_event): Likewise.
(simple_diagnostic_event::simple_diagnostic_event): Likewise.
(simple_diagnostic_event::~simple_diagnostic_event): Likewise.
* selftest-run-tests.cc (selftest::run_tests): Call
selftest::simple_diagnostic_path_cc_tests.
* selftest.h (selftest::simple_diagnostic_path_cc_tests): New
decl.
* simple-diagnostic-path.cc: New file, from the above material.
* simple-diagnostic-path.h: New file, from the above material
from diagnostic-path.h.
* tree-diagnostic-path.cc: Include "simple-diagnostic-path.h".

gcc/testsuite/ChangeLog
* gcc.dg/plugin/diagnostic_plugin_test_paths.c: Include
"simple-diagnostic-path.h".

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

Match: Support forms 7 and 8 for the unsigned .SAT_ADD

When investigate the vectorization of .SAT_ADD,  we notice there
are additional 2 forms,  aka form 7 and 8 for .SAT_ADD.

Form 7:
  #define DEF_SAT_U_ADD_FMT_7(T)          \
  T __attribute__((noinline))             \
  sat_u_add_##T##_fmt_7 (T x, T y)        \
  {                                       \
    return x > (T)(x + y) ? -1 : (x + y); \
  }

Form 8:
  #define DEF_SAT_U_ADD_FMT_8(T)           \
  T __attribute__((noinline))              \
  sat_u_add_##T##_fmt_8 (T x, T y)         \
  {                                        \
    return x <= (T)(x + y) ? (x + y) : -1; \
  }

Thus,  add above 2 forms to the match gimple_unsigned_integer_sat_add,
and then the vectorizer can try to recog the pattern like form 7 and
form 8.

The below test suites are passed for this patch:
1. The rv64gcv fully regression test with newlib.
2. The rv64gcv build with glibc.
3. The x86 bootstrap test.
4. The x86 fully regression test.

gcc/ChangeLog:

* match.pd: Add form 7 and 8 for the unsigned .SAT_ADD match.

Signed-off-by: Pan Li <pan2.li@intel.com>

Match: Support form 11 for the unsigned scalar .SAT_SUB

We missed one match pattern for the unsigned scalar .SAT_SUB,  aka
form 11.

Form 11:
  #define SAT_SUB_U_11(T) \
  T sat_sub_u_11_##T (T x, T y) \
  { \
    T ret; \
    bool overflow = __builtin_sub_overflow (x, y, &ret); \
    return overflow ? 0 : ret; \
  }

Thus,  add above form 11 to the match pattern gimple_unsigned_integer_sat_sub.

The below test suites are passed for this patch:
1. The rv64gcv fully regression test with newlib.
2. The rv64gcv build with glibc.
3. The x86 bootstrap test.
4. The x86 fully regression test.

gcc/ChangeLog:

* match.pd: Add form 11 match pattern for .SAT_SUB.

Signed-off-by: Pan Li <pan2.li@intel.com>

tree-optimization/115537 - ICE with SLP condition reduction vectorization

The condition rejecting "multiple-type" SLP condition reduction lacks
handling EXTRACT_LAST reductions.

PR tree-optimization/115537
* tree-vect-loop.cc (vectorizable_reduction): Also reject
SLP condition reductions of EXTRACT_LAST kind when multiple
statement copies are involved.

* gcc.dg/vect/pr115537.c: New testcase.

[to-be-committed,RISC-V] Improve bset generation when bit position is limited

  So more work in the ongoing effort to make better use of the Zbs
extension.  This time we're trying to exploit knowledge of the shift
count/bit position to allow us to use a bset instruction.

Consider this expression in SImode

  (1 << (pos & 0xf)

None of the resulting values will have bit 31 set.  So if there's an
explicit zero or sign extension to DI we can drop that explicit
extension and generate a simple bset with x0 as the input value.

Or another example (which I think came from spec at some point and IIRC
was the primary motivation for this patch):

(1 << (7-(pos) % 8))

Before this change they'd generate something like this respectively:

         li      a5,1
         andi    a0,a0,15
         sllw    a0,a5,a0

         li      a5,7
         andn    a0,a5,a0
         li      a5,1
         sllw    a0,a5,a0

After this change they generate:

         andi    a0,a0,15        # 9     [c=4 l=4]  *anddi3/1
         bset    a0,x0,a0        # 17    [c=8 l=4]  *bsetdi_2

         li      a5,7            # 27    [c=4 l=4]  *movdi_64bit/1
         andn    a0,a5,a0        # 28    [c=4 l=4]  and_notdi3
         bset    a0,x0,a0        # 19    [c=8 l=4]  *bsetdi_2

We achieve this with simple define_splits which target the bsetdi_2
pattern I recently added.  Much better than the original implementation
I did a few months back :-)  I've got a bclr/binv variant from a few
months back as well, but it needs to be updated to the simpler
implementation found here.

Just ran this through my tester.  Will wait for the precommit CI to
render its verdict before moving forward.

gcc/
* config/riscv/bitmanip.md (bset splitters): New patterns for
generating bset when bit position is limited.

libstdc++: Fix outdated comment about standard integer types

The long long and unsigned long long types have been standard since
C++11, so are not extensions. There are also the char8_t, char16_t and
char32_t types. Just refer to the standard integer types, without saying
how many there are.

libstdc++-v3/ChangeLog:

* include/bits/cpp_type_traits.h: Fix outdated comment about the
number of standard integer types.

analyzer: Fix g++ 4.8 bootstrap without using std::move to return std::unique_ptr

Revert the changes in r15-1111-ge22b7f741ab54f and fix bootstrap with
GCC 4.8 a different way. The original problem is not related to C++17
guaranteed copy elision, it's related to Core DR 1579 [1], which was
part of C++14 but only implemented in G++ as a C++11 DR with
r5-1576-gfb682f9458c6cf (so GCC 4.8 doesn't implement it).

The original fix causes -Wredundant-move warnings with GCC trunk.

[1] https://cplusplus.github.io/CWG/issues/1579.html

gcc/analyzer/ChangeLog
* constraint-manager.cc (equiv_class::make_dump_widget): Change
return type to match return value and do not use std::move on
return value.
(bounded_ranges_constraint::make_dump_widget): Likewise.
(constraint_manager::make_dump_widget): Likewise.
* constraint-manager.h (equiv_class::make_dump_widget): Change
return type.
(bounded_ranges_constraint::make_dump_widget): Likewise.
(constraint_manager::make_dump_widget): Likewise.
* program-state.cc (sm_state_map::make_dump_widget): Likewise.
(program_state::make_dump_widget): Likewise.
* program-state.h (sm_state_map::make_dump_widget): Likewise.
(program_state::make_dump_widget): Likewise.
* region-model.cc (region_to_value_map::make_dump_widget): Likewise.
(region_model::make_dump_widget): Likewise.
* region-model.h (region_to_value_map::make_dump_widget): Likewise.
(region_model::make_dump_widget): Likewise.
* region.cc (region::make_dump_widget): Likewise.
* region.h (region::make_dump_widget): Likewise.
* store.cc (binding_cluster::make_dump_widget): Likewise.
(store::make_dump_widget): Likewise.
* store.h (binding_cluster::make_dump_widget): Likewise.
(store::make_dump_widget): Likewise.
* svalue.cc (svalue::make_dump_widget): Likewise.
* svalue.h (svalue::make_dump_widget): Likewise.

[MAINTAINERS] Update my email address

Pushing to trunk.

* MAINTAINERS (aarch64 port): Update my email address.
(DCO section): Likewise.

Signed-off-by: Kyrylo Tkachov <ktkachov@nvidia.com>

aarch64: Add some uses of force_highpart_subreg

This patch adds uses of force_highpart_subreg to places that
already use force_lowpart_subreg.

gcc/
* config/aarch64/aarch64.cc (aarch64_addti_scratch_regs): Use
force_highpart_subreg instead of gen_highpart and simplify_gen_subreg.
(aarch64_subvti_scratch_regs): Likewise.

Add force_highpart_subreg

This patch adds a force_highpart_subreg to go along with the
recently added force_lowpart_subreg.

gcc/
* explow.h (force_highpart_subreg): Declare.
* explow.cc (force_highpart_subreg): New function.
* builtins.cc (expand_builtin_issignaling): Use it.
* expmed.cc (emit_store_flag_1): Likewise.

Make more use of force_lowpart_subreg

This patch makes target-independent code use force_lowpart_subreg
instead of simplify_gen_subreg and lowpart_subreg in some places.
The criteria were:

(1) The code is obviously specific to expand (where new pseudos
    can be created), or at least would be invalid to call when
    !can_create_pseudo_p () and temporaries are needed.

(2) The value is obviously an rvalue rather than an lvalue.

Doing this should reduce the likelihood of bugs like PR115464
occuring in other situations.

gcc/
* builtins.cc (expand_builtin_issignaling): Use force_lowpart_subreg
instead of simplify_gen_subreg and lowpart_subreg.
* expr.cc (convert_mode_scalar, expand_expr_real_2): Likewise.
* optabs.cc (expand_doubleword_mod): Likewise.

aarch64: Add some uses of force_lowpart_subreg

This patch makes more use of force_lowpart_subreg, similarly
to the recent patch for force_subreg.  The criteria were:

(1) The code is obviously specific to expand (where new pseudos
    can be created).

(2) The value is obviously an rvalue rather than an lvalue.

gcc/
PR target/115464
* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
simplify_gen_subreg and lowpart_subreg.
* config/aarch64/aarch64-sve-builtins-base.cc
(svset_neonq_impl::expand): Likewise.
* config/aarch64/aarch64-sve-builtins-sme.cc
(add_load_store_slice_operand): Likewise.
* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.

gcc/testsuite/
PR target/115464
* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.

Add force_lowpart_subreg

optabs had a local function called lowpart_subreg_maybe_copy
that is very similar to the lowpart version of force_subreg.
This patch adds a force_lowpart_subreg wrapper around
force_subreg and uses it in optabs.cc.

The only difference between the old and new functions is that
the old one asserted success while the new one doesn't.
It's common not to assert elsewhere when taking subregs;
normally a null result is enough.

Later patches will make more use of the new function.

gcc/
* explow.h (force_lowpart_subreg): Declare.
* explow.cc (force_lowpart_subreg): New function.
* optabs.cc (lowpart_subreg_maybe_copy): Delete.
(expand_absneg_bit): Use force_lowpart_subreg instead of
lowpart_subreg_maybe_copy.
(expand_copysign_bit): Likewise.

Make more use of force_subreg

This patch makes target-independent code use force_subreg instead
of simplify_gen_subreg in some places.  The criteria were:

(1) The code is obviously specific to expand (where new pseudos
    can be created), or at least would be invalid to call when
    !can_create_pseudo_p () and temporaries are needed.

(2) The value is obviously an rvalue rather than an lvalue.

(3) The offset wasn't a simple lowpart or highpart calculation;
    a later patch will deal with those.

Doing this should reduce the likelihood of bugs like PR115464
occuring in other situations.

gcc/
* expmed.cc (store_bit_field_using_insv): Use force_subreg
instead of simplify_gen_subreg.
(store_bit_field_1): Likewise.
(extract_bit_field_as_subreg): Likewise.
(extract_integral_bit_field): Likewise.
(emit_store_flag_1): Likewise.
* expr.cc (convert_move): Likewise.
(convert_modes): Likewise.
(emit_group_load_1): Likewise.
(emit_group_store): Likewise.
(expand_assignment): Likewise.

aarch64: Use force_subreg in more places

This patch makes the aarch64 code use force_subreg instead of
simplify_gen_subreg in more places.  The criteria were:

(1) The code is obviously specific to expand (where new pseudos
    can be created).

(2) The value is obviously an rvalue rather than an lvalue.

(3) The offset wasn't a simple lowpart or highpart calculation;
    a later patch will deal with those.

gcc/
* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
Use force_subreg instead of simplify_gen_subreg.
* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
* config/aarch64/aarch64-sve-builtins-base.cc
(svget_impl::expand): Likewise.
(svget_neonq_impl::expand): Likewise.
* config/aarch64/aarch64-sve-builtins-functions.h
(multireg_permute::expand): Likewise.

Make force_subreg emit nothing on failure

While adding more uses of force_subreg, I realised that it should
be more careful to emit no instructions on failure.  This kind of
failure should be very rare, so I don't think it's a case worth
optimising for.

gcc/
* explow.cc (force_subreg): Emit no instructions on failure.

c23: Fix for redeclared enumerator initialized with different type [PR115109]

c23 specifies that the type of a redeclared enumerator is the one of the
previous declaration.  Convert initializers with different type accordingly
and emit an error when the value does not fit.

2024-06-01 Martin Uecker  <uecker@tugraz.at>

PR c/115109

gcc/c/
* c-decl.cc (build_enumerator): When redeclaring an
enumerator convert value to previous type.  For redeclared
enumerators use underlying type for computing the next value.

gcc/testsuite/
* gcc.dg/pr115109.c: New test.
* gcc.dg/c23-tag-enum-6.c: New test.
* gcc.dg/c23-tag-enum-7.c: New test.

rs6000: Shrink rs6000_init_generated_builtins size [PR115324]

While my r15-1001-g4cf2de9b5268224 PCH PIE power fix change decreased the
.data section sizes (219792 -> 189336), it increased the size of already
huge rs6000_init_generated_builtins generated function, from 218328
to 228668 bytes.  That is because there are thousands of array references
to global arrays and we keep constructing the addresses of the arrays
again and again.

Ideally some optimization would figure out we have a single function which
has
    461   rs6000_overload_info
   1257   rs6000_builtin_info_fntype
   1768   rs6000_builtin_decls
   2548   rs6000_instance_info_fntype
array references and that maybe it might be a good idea to just preload
the addresses of those arrays into some register if it decreases code size
and doesn't slow things down.
The function actually is called just once and is huge, so code size is even
more important than speed, which is dominated by all the GC allocations
anyway.

Until that is done, here is a slightly cleaner version of the hack, which
makes the function noipa (so that LTO doesn't undo it) for GCC 8.1+ and
passes the 4 arrays as arguments to the function from the caller.
This decreases the function size from 228668 bytes to 207572 bytes.

2024-06-18  Jakub Jelinek  <jakub@redhat.com>

PR target/115324
* config/rs6000/rs6000-gen-builtins.cc (write_decls): Change
declaration of rs6000_init_generated_builtins from no arguments
to 4 pointer arguments.
(write_init_bif_table): Change rs6000_builtin_info_fntype to
builtin_info_fntype and rs6000_builtin_decls to builtin_decls.
(write_init_ovld_table): Change rs6000_instance_info_fntype to
instance_info_fntype, rs6000_builtin_decls to builtin_decls and
rs6000_overload_info to overload_info.
(write_init_file): Add __noipa__ attribute to
rs6000_init_generated_builtins for GCC 8.1+ and change the function
from no arguments to 4 pointer arguments.  Change rs6000_builtin_decls
to builtin_decls.
* config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Adjust
rs6000_init_generated_builtins caller.

tree-optimization/115493 - fix wrong code with SLP induction cond reduction

The following fixes a bad final value being used when doing single-lane
SLP integer induction cond reduction vectorization.

PR tree-optimization/115493
* tree-vect-loop.cc (vect_create_epilog_for_reduction): Use
the first scalar result.

Enhance if-conversion for automatic arrays

Automatic arrays that are not address-taken should not be subject to
store data races.  This applies to OMP SIMD in-branch lowered
functions result array which for the testcase otherwise prevents
vectorization with SSE and for AVX and AVX512 ends up with spurious
.MASK_STORE to the stack surviving.

This inefficiency was noted in PR111793.

I've introduced ref_can_have_store_data_races, commonizing uses
of flag_store_data_races in if-conversion, cselim and store motion.

PR tree-optimization/111793
* tree-ssa-alias.h (ref_can_have_store_data_races): Declare.
* tree-ssa-alias.cc (ref_can_have_store_data_races): New
function.
* tree-if-conv.cc (ifcvt_memrefs_wont_trap): Use
ref_can_have_store_data_races to allow more unconditional
stores.
* tree-ssa-loop-im.cc (execute_sm): Likewise.
* tree-ssa-phiopt.cc (cond_store_replacement): Likewise.

* gcc.dg/vect/vect-simd-clone-21.c: New testcase.

testsuite, rs6000: Replace powerpc_altivec_ok with powerpc_altivec [PR114842]

As noted in PR114842, most of the test cases which require
effective target check powerpc_altivec_ok actually care about
if ALTIVEC feature is enabled, and they should adopt effective
target powerpc_altivec instead.  Otherwise, when users are
specifying extra option -mno-altivec in RUNTESTFLAGS, the check
powerpc_altivec_ok returns true then the test case would be
tested without ALTIVEC so it would fail.  With commit r15-716,
dg-options and dg-additional-options can be taken into account
when evaluating powerpc_altivec, so this patch also moves
dg-{additional,}-options lines before dg-require-effective-target
to make it effective.

PR testsuite/114842

gcc/testsuite/ChangeLog:

* c-c++-common/pr72747-1.c: Replace powerpc_altivec_ok with
powerpc_altivec, move dg-options and dg-additional-options lines
before dg-require-effective-target lines when it doesn't cause
any side effect like note message.
* c-c++-common/pr72747-2.c: Likewise.
* g++.dg/torture/pr79905.C: Likewise.
* g++.target/powerpc/altivec-1.C: Likewise.
* g++.target/powerpc/altivec-10.C: Likewise.
* g++.target/powerpc/altivec-11.C: Likewise.
* g++.target/powerpc/altivec-12.C: Likewise.
* g++.target/powerpc/altivec-13.C: Likewise.
* g++.target/powerpc/altivec-14.C: Likewise.
* g++.target/powerpc/altivec-15.C: Likewise.
* g++.target/powerpc/altivec-16.C: Likewise.
* g++.target/powerpc/altivec-17.C: Likewise.
* g++.target/powerpc/altivec-18.C: Likewise.
* g++.target/powerpc/altivec-2.C: Likewise.
* g++.target/powerpc/altivec-4.C: Likewise.
* g++.target/powerpc/altivec-5.C: Likewise.
* g++.target/powerpc/altivec-6.C: Likewise.
* g++.target/powerpc/altivec-7.C: Likewise.
* g++.target/powerpc/altivec-8.C: Likewise.
* g++.target/powerpc/altivec-9.C: Likewise.
* g++.target/powerpc/altivec-cell-1.C: Likewise.
* g++.target/powerpc/altivec-cell-5.C: Likewise.
* g++.target/powerpc/altivec-types-1.C: Likewise.
* g++.target/powerpc/altivec-types-2.C: Likewise.
* g++.target/powerpc/altivec-types-3.C: Likewise.
* g++.target/powerpc/altivec-types-4.C: Likewise.
* gcc.target/powerpc/altivec-1-runnable.c: Likewise.
* gcc.target/powerpc/altivec-11.c: Likewise.
* gcc.target/powerpc/altivec-13.c: Likewise.
* gcc.target/powerpc/altivec-14.c: Likewise.
* gcc.target/powerpc/altivec-15.c: Likewise.
* gcc.target/powerpc/altivec-16.c: Likewise.
* gcc.target/powerpc/altivec-17.c: Likewise.
* gcc.target/powerpc/altivec-18.c: Likewise.
* gcc.target/powerpc/altivec-19.c: Likewise.
* gcc.target/powerpc/altivec-2.c: Likewise.
* gcc.target/powerpc/altivec-21.c: Likewise.
* gcc.target/powerpc/altivec-22.c: Likewise.
* gcc.target/powerpc/altivec-23.c: Likewise.
* gcc.target/powerpc/altivec-25.c: Likewise.
* gcc.target/powerpc/altivec-26.c: Likewise.
* gcc.target/powerpc/altivec-27.c: Likewise.
* gcc.target/powerpc/altivec-28.c: Likewise.
* gcc.target/powerpc/altivec-29.c: Likewise.
* gcc.target/powerpc/altivec-30.c: Likewise.
* gcc.target/powerpc/altivec-31.c: Likewise.
* gcc.target/powerpc/altivec-32.c: Likewise.
* gcc.target/powerpc/altivec-33.c: Likewise.
* gcc.target/powerpc/altivec-34.c: Likewise.
* gcc.target/powerpc/altivec-35.c: Likewise.
* gcc.target/powerpc/altivec-36.c: Likewise.
* gcc.target/powerpc/altivec-4.c: Likewise.
* gcc.target/powerpc/altivec-5.c: Likewise.
* gcc.target/powerpc/altivec-6.c: Likewise.
* gcc.target/powerpc/altivec-7.c: Likewise.
* gcc.target/powerpc/altivec-8.c: Likewise.
* gcc.target/powerpc/altivec-9.c: Likewise.
* gcc.target/powerpc/altivec-cell-1.c: Likewise.
* gcc.target/powerpc/altivec-cell-5.c: Likewise.
* gcc.target/powerpc/altivec-cell-6.c: Likewise.
* gcc.target/powerpc/altivec-cell-7.c: Likewise.
* gcc.target/powerpc/altivec-perm-1.c: Likewise.
* gcc.target/powerpc/altivec-perm-2.c: Likewise.
* gcc.target/powerpc/altivec-perm-3.c: Likewise.
* gcc.target/powerpc/altivec-perm-4.c: Likewise.
* gcc.target/powerpc/altivec-pr22085.c: Likewise.
* gcc.target/powerpc/altivec-splat.c: Likewise.
* gcc.target/powerpc/altivec-types-1.c: Likewise.
* gcc.target/powerpc/altivec-types-2.c: Likewise.
* gcc.target/powerpc/altivec-types-3.c: Likewise.
* gcc.target/powerpc/altivec-types-4.c: Likewise.
* gcc.target/powerpc/altivec-volatile.c: Likewise.
* gcc.target/powerpc/altivec_vld_vst_addr-1.c: Likewise.
* gcc.target/powerpc/bool2-av.c: Likewise.
* gcc.target/powerpc/bool2-p5.c: Likewise.
* gcc.target/powerpc/bool3-av.c: Likewise.
* gcc.target/powerpc/builtin-vec-sums-be-int.c: Likewise.
* gcc.target/powerpc/builtins-3.c: Likewise.
* gcc.target/powerpc/cell_builtin-3.c: Likewise.
* gcc.target/powerpc/cell_builtin-5.c: Likewise.
* gcc.target/powerpc/cell_builtin-6.c: Likewise.
* gcc.target/powerpc/cell_builtin-7.c: Likewise.
* gcc.target/powerpc/cell_builtin-8.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-char-fwrapv.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-char.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int-fwrapv.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-short-fwrapv.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-short.c: Likewise.
* gcc.target/powerpc/fold-vec-add-1.c: Likewise.
* gcc.target/powerpc/fold-vec-add-2.c: Likewise.
* gcc.target/powerpc/fold-vec-add-3.c: Likewise.
* gcc.target/powerpc/fold-vec-add-5.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-ld-char.c: Likewise.
* gcc.target/powerpc/fold-vec-ld-float.c: Likewise.
* gcc.target/powerpc/fold-vec-ld-int.c: Likewise.
* gcc.target/powerpc/fold-vec-ld-short.c: Likewise.
* gcc.target/powerpc/fold-vec-madd-short.c: Likewise.
* gcc.target/powerpc/fold-vec-mergehl-char.c: Likewise.
* gcc.target/powerpc/fold-vec-mergehl-float.c: Likewise.
* gcc.target/powerpc/fold-vec-mergehl-int.c: Likewise.
* gcc.target/powerpc/fold-vec-mergehl-short.c: Likewise.
* gcc.target/powerpc/fold-vec-minmax-char.c: Likewise.
* gcc.target/powerpc/fold-vec-minmax-int.c: Likewise.
* gcc.target/powerpc/fold-vec-minmax-short.c: Likewise.
* gcc.target/powerpc/fold-vec-missing-lhs.c: Likewise.
* gcc.target/powerpc/fold-vec-msum-char.c: Likewise.
* gcc.target/powerpc/fold-vec-msum-short.c: Likewise.
* gcc.target/powerpc/fold-vec-mule-char.c: Likewise.
* gcc.target/powerpc/fold-vec-mule-short.c: Likewise.
* gcc.target/powerpc/fold-vec-mult-char.c: Likewise.
* gcc.target/powerpc/fold-vec-mult-short.c: Likewise.
* gcc.target/powerpc/fold-vec-pack-int.c: Likewise.
* gcc.target/powerpc/fold-vec-pack-short.c: Likewise.
* gcc.target/powerpc/fold-vec-perm-char.c: Likewise.
* gcc.target/powerpc/fold-vec-perm-float.c: Likewise.
* gcc.target/powerpc/fold-vec-perm-int.c: Likewise.
* gcc.target/powerpc/fold-vec-perm-pixel.c: Likewise.
* gcc.target/powerpc/fold-vec-perm-short.c: Likewise.
* gcc.target/powerpc/fold-vec-shift-char.c: Likewise.
* gcc.target/powerpc/fold-vec-shift-int.c: Likewise.
* gcc.target/powerpc/fold-vec-shift-left-fwrapv.c: Likewise.
* gcc.target/powerpc/fold-vec-shift-left.c: Likewise.
* gcc.target/powerpc/fold-vec-shift-short.c: Likewise.
* gcc.target/powerpc/fold-vec-splat-32.c: Likewise.
* gcc.target/powerpc/fold-vec-splat-8.c: Likewise.
* gcc.target/powerpc/fold-vec-splat-char.c: Likewise.
* gcc.target/powerpc/fold-vec-splat-int.c: Likewise.
* gcc.target/powerpc/fold-vec-splat-short.c: Likewise.
* gcc.target/powerpc/fold-vec-splats-char.c: Likewise.
* gcc.target/powerpc/fold-vec-splats-int.c: Likewise.
* gcc.target/powerpc/fold-vec-splats-short.c: Likewise.
* gcc.target/powerpc/fold-vec-st-char.c: Likewise.
* gcc.target/powerpc/fold-vec-st-float.c: Likewise.
* gcc.target/powerpc/fold-vec-st-int.c: Likewise.
* gcc.target/powerpc/fold-vec-st-short.c: Likewise.
* gcc.target/powerpc/fold-vec-sub-char.c: Likewise.
* gcc.target/powerpc/fold-vec-sub-float.c: Likewise.
* gcc.target/powerpc/fold-vec-sub-int.c: Likewise.
* gcc.target/powerpc/fold-vec-sub-short.c: Likewise.
* gcc.target/powerpc/fold-vec-sums-int.c: Likewise.
* gcc.target/powerpc/fold-vec-unpack-char.c: Likewise.
* gcc.target/powerpc/fold-vec-unpack-pixel.c: Likewise.
* gcc.target/powerpc/fold-vec-unpack-short.c: Likewise.
* gcc.target/powerpc/ppc-fma-3.c: Likewise.
* gcc.target/powerpc/ppc-fma-4.c: Likewise.
* gcc.target/powerpc/ppc-fma-7.c: Likewise.
* gcc.target/powerpc/ppc-vector-memcpy.c: Likewise.
* gcc.target/powerpc/ppc-vector-memset.c: Likewise.
* gcc.target/powerpc/pr100645.c: Likewise.
* gcc.target/powerpc/pr101384-1.c: Likewise.
* gcc.target/powerpc/pr101384-2.c: Likewise.
* gcc.target/powerpc/pr103353.c: Likewise.
* gcc.target/powerpc/pr103702.c: Likewise.
* gcc.target/powerpc/pr108348-1.c: Likewise.
* gcc.target/powerpc/pr108348-2.c: Likewise.
* gcc.target/powerpc/pr109932-1.c: Likewise.
* gcc.target/powerpc/pr109932-2.c: Likewise.
* gcc.target/powerpc/pr110776.c: Likewise.
* gcc.target/powerpc/pr16155.c: Likewise.
* gcc.target/powerpc/pr16286.c: Likewise.
* gcc.target/powerpc/pr27158.c: Likewise.
* gcc.target/powerpc/pr37168.c: Likewise.
* gcc.target/powerpc/pr47197.c: Likewise.
* gcc.target/powerpc/pr67071-1.c: Likewise.
* gcc.target/powerpc/pr67071-2.c: Likewise.
* gcc.target/powerpc/pr67071-3.c: Likewise.
* gcc.target/powerpc/pr70010-2.c: Likewise.
* gcc.target/powerpc/pr70010-3.c: Likewise.
* gcc.target/powerpc/pr71297.c: Likewise.
* gcc.target/powerpc/pr82112.c: Likewise.
* gcc.target/powerpc/pr84220-sld.c: Likewise.
* gcc.target/powerpc/pr84878.c: Likewise.
* gcc.target/powerpc/pr86731-fwrapv.c: Likewise.
* gcc.target/powerpc/pr86731.c: Likewise.
* gcc.target/powerpc/pr88100.c: Likewise.
* gcc.target/powerpc/pragma_power6.c: Likewise.
* gcc.target/powerpc/pragma_power7.c: Likewise.
* gcc.target/powerpc/pragma_power9.c: Likewise.
* gcc.target/powerpc/swaps-p8-21.c: Likewise.
* gcc.target/powerpc/unpack-vectorize-1.c: Likewise.
* gcc.target/powerpc/vec-cg.c: Likewise.
* gcc.target/powerpc/vec-cmpne.c: Likewise.
* gcc.target/powerpc/vec-constvolatile.c: Likewise.
* gcc.target/powerpc/vec-mult-char-2.c: Likewise.
* gcc.target/powerpc/vec-rotate-1.c: Likewise.
* gcc.target/powerpc/vec-rotate-3.c: Likewise.
* gcc.target/powerpc/vec-shift.c: Likewise.
* g++.target/powerpc/altivec-3.C: Likewise.
* g++.target/powerpc/altivec-cell-2.C: Likewise.
* g++.target/powerpc/altivec-cell-3.C: Likewise.
* g++.target/powerpc/altivec-cell-4.C: Likewise.
* g++.target/powerpc/const2.C: Likewise.
* gcc.dg/debug/dwarf2/const-2.c: Likewise.
* gcc.dg/dfp/altivec-types.c: Likewise.
* gcc.dg/ubsan/pr88234.c: Likewise.
* gcc.dg/vect/vect-82_64.c: Likewise.
* gcc.dg/vect/vect-83_64.c: Likewise.
* gcc.target/powerpc/altivec-1.c: Likewise.
* gcc.target/powerpc/altivec-10.c: Likewise.
* gcc.target/powerpc/altivec-12.c: Likewise.
* gcc.target/powerpc/altivec-20.c: Likewise.
* gcc.target/powerpc/altivec-24.c: Likewise.
* gcc.target/powerpc/altivec-3.c: Likewise.
* gcc.target/powerpc/altivec-cell-2.c: Likewise.
* gcc.target/powerpc/altivec-cell-3.c: Likewise.
* gcc.target/powerpc/altivec-cell-4.c: Likewise.
* gcc.target/powerpc/altivec-consts.c: Likewise.
* gcc.target/powerpc/altivec-macros.c: Likewise.
* gcc.target/powerpc/altivec-varargs-1.c: Likewise.
* gcc.target/powerpc/altivec-vec-merge.c: Likewise.
* gcc.target/powerpc/darwin-save-world-1.c: Likewise.
* gcc.target/powerpc/le-altivec-consts.c: Likewise.
* gcc.target/powerpc/pr35907.c: Likewise.
* gcc.target/powerpc/vec-mult-char-1.c: Likewise.

i386: Handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx

gcc/ChangeLog:

* config/i386/avxintrin.h: Move cmp[p|s][s|d] to [e|x]mmintrin.h,
and move macros to xmmintrin.h
* config/i386/emmintrin.h: Add cmp[p|s]s intrins.
* config/i386/i386-builtin.def: Modify __builtin_ia32_cmp[p|s][s|d].
* config/i386/i386-expand.cc
(ix86_expand_args_builtin): Raise error when imm is in range of
[8, 32] without avx.
* config/i386/predicates.md (cmpps_imm_operand): New predicate.
* config/i386/sse.md (avx_cmp<mode>3): Modefy define_insn.
(avx_vmcmp<mode>3): Ditto.
* config/i386/xmmintrin.h (_CMP_EQ_OQ): New macro for sse/sse2.
(_CMP_LT_OS): Ditto
(_CMP_LE_OS): Ditto
(_CMP_UNORD_Q): Ditto
(_CMP_NEQ_UQ): Ditto
(_CMP_NLT_US): Ditto
(_CMP_NLE_US): Ditto
(_CMP_ORD_Q): Ditto
(_mm_cmp_ps): Move intrin from avxintrin.h to xmmintrin.h
(_mm_cmp_ss): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/sse-cmp-1.c: New test.
* gcc.target/i386/sse-cmp-2.c: Ditto.
* gcc.target/i386/sse-cmp-error.c: Ditto.

Daily bump.

aarch64: Add testcase for PR97405

This aarch64 sve specific code was fixed by r15-917-gc9842f99042454
which added a riscv specific testcase so adding an aarch64 one to test
the fix does not regress is a good idea.

Committed as obvious after testing the testcase for aarch64-linux-gnu.

PR tree-optimization/97405

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/sve/pr97405-1.c: New test.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

[to-be-committed,RISC-V] Handle zero_extract destination for single bit insertions

Combine will use zero_extract destinations for certain bitfield
insertions.  If the bitfield is a single bit constant, then we can use
bset/bclr.

In this case we are only dealing with word_mode objects, so we don't
have to worry about the SI->DI extension issues for TARGET_64BIT.

The testcase was derived from 502.gcc in spec from the RAU team.

An earlier version of this (TARGET_64BIT only) went through Ventana's CI
system.  This version has gone though mine after generalizing it to
handle rv32 as well.  I'll wait for pre-commit CI to render its verdict
before moving forward.

gcc/
* config/riscv/bitmanip.md (bsetclr_zero_extract): New pattern.

gcc/testsuite/

* gcc.target/riscv/zbs-zext-3.c: New test.