Raw NAND controller driver changes:
* Omap, Omap2, Samsung, Atmel, fsl_upm, lpc32xx_slc, lpc32xx_mlc, STM32_FMC2,
sh_ftlctl, MXC, Sunxi:
- Use devm_platform_get_and_ioremap_resource()
* Orion, vf610_nfc, Sunxi, STM32_FMC2, MTK, mpc5121, lpc32xx_slc, Intel,
FSMC, Arasan:
- Use helper function devm_clk_get_optional_enabled()
* Brcmnand:
- Use devm_platform_ioremap_resource_byname()
- Propagate init error -EPROBE_DEFER up
- Propagate error and simplify ternary operators
- Fix mtd oobsize
- Fix potential out-of-bounds access in oob write
- Fix crash during the panic_write
- Fix potential false time out warning
- Fix ECC level field setting for v7.2 controller
* fsmc: Handle clk prepare error in fsmc_nand_resume()
* Marvell: Add support for AC5 SoC
* Meson:
- Support for 512B ECC step size
- Fix build error
- Use NAND core API to check status
- dt-bindings:
* Make ECC properties dependent
* Support for 512B ECC step size
* Drop unneeded quotes
* Oxnas: Remove driver and bindings
* Qcom:
- Conversion to ->exec_op()
- Removal of the legacy interface
- Two full series of improvements/misc fixes
* Use the BIT() macro
* Use u8 instead of uint8_t
* Fix alignment with open parenthesis
* Fix the spacing
* Fix wrong indentation
* Fix a typo
* Early structure initialization
* Fix address parsing within ->exec_op()
* Remove superfluous initialization of "ret"
* Rename variables in qcom_op_cmd_mapping()
* Handle unsupported opcode in qcom_op_cmd_mapping()
* Fix the opcode check in qcom_check_op()
* Use EOPNOTSUPP instead of ENOTSUPP
* Wrap qcom_nand_exec_op() to 80 columns
* Unmap sg_list and free desc within submic_descs()
* Simplify the call to nand_prog_page_end_op()
* Do not override the error no of submit_descs()
* Sort includes alphabetically
* Clear buf_count and buf_start in raw read
* Add read/read_start ops in exec_op path
* vf610_nfc: Do not check 0 for platform_get_irq()
SPI-NAND changes:
* gigadevice: Add support for GD5F1GQ{4,5}RExxH
* esmt: Add support for F50D2G41KA
* toshiba: Add support for T{C,H}58NYG{0,2}S3HBAI4 and TH58NYG3S0HBAI6
Li Zetao [Mon, 21 Aug 2023 03:17:26 +0000 (11:17 +0800)]
mtd: spear_smi: Use helper function devm_clk_get_enabled()
Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared
and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be
replaced by devm_clk_get_enabled() when driver enables (and possibly
prepares) the clocks for the whole lifetime of the device. Moreover, it is
no longer necessary to unprepare and disable the clocks explicitly, so drop
the label "err_irq".
Li Zetao [Mon, 21 Aug 2023 03:17:37 +0000 (11:17 +0800)]
mtd: rawnand: orion: Use helper function devm_clk_get_optional_enabled()
Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared
and enabled clocks"), devm_clk_get_optional() and clk_prepare_enable() can
now be replaced by devm_clk_get_optional_enabled() when driver enables
(and possibly prepares) the clocks for the whole lifetime of the device.
Moreover, it is no longer necessary to unprepare and disable the clocks
explicitly, so drop the label "no_dev".
Li Zetao [Mon, 21 Aug 2023 03:17:35 +0000 (11:17 +0800)]
mtd: rawnand: vf610_nfc: Use helper function devm_clk_get_enabled()
Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared
and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be
replaced by devm_clk_get_enabled() when driver enables (and possibly
prepares) the clocks for the whole lifetime of the device. Moreover, it is
no longer necessary to unprepare and disable the clocks explicitly, so drop
the label "err_disable_clk".
Li Zetao [Mon, 21 Aug 2023 03:17:34 +0000 (11:17 +0800)]
mtd: rawnand: sunxi: Use helper function devm_clk_get_enabled()
Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared
and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be
replaced by devm_clk_get_enabled() when driver enables (and possibly
prepares) the clocks for the whole lifetime of the device. Moreover, it is
no longer necessary to unprepare and disable the clocks explicitly, so drop
the label "out_mod_clk_unprepare" and "out_ahb_clk_unprepare".
Li Zetao [Mon, 21 Aug 2023 03:17:33 +0000 (11:17 +0800)]
mtd: rawnand: stm32_fmc2: Use helper function devm_clk_get_enabled()
Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared
and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be
replaced by devm_clk_get_enabled() when driver enables (and possibly
prepares) the clocks for the whole lifetime of the device. Moreover, it is
no longer necessary to unprepare and disable the clocks explicitly, so drop
the label "err_clk_disable".
Li Zetao [Mon, 21 Aug 2023 03:17:32 +0000 (11:17 +0800)]
mtd: rawnand: mtk: Use helper function devm_clk_get_enabled()
Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared
and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be
replaced by devm_clk_get_enabled() when driver enables (and possibly
prepares) the clocks for the whole lifetime of the device. Moreover, it is
no longer necessary to unprepare and disable the clocks explicitly, so drop
the label "clk_disable". And both mtk_nfc_enable_clk() and
mtk_nfc_disable_clk() now have a single user, which is the resume or
suspend callback, so drop this two helper function and just move related
operations in the resume or suspend function.
Li Zetao [Mon, 21 Aug 2023 03:17:31 +0000 (11:17 +0800)]
mtd: rawnand: mpc5121: Use helper function devm_clk_get_enabled()
Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared
and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be
replaced by devm_clk_get_enabled() when driver enables (and possibly
prepares) the clocks for the whole lifetime of the device. Moreover, it is
no longer necessary to unprepare and disable the clocks explicitly.
Li Zetao [Mon, 21 Aug 2023 03:17:30 +0000 (11:17 +0800)]
mtd: rawnand: lpc32xx_slc: Use helper function devm_clk_get_enabled()
Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared
and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be
replaced by devm_clk_get_enabled() when driver enables (and possibly
prepares) the clocks for the whole lifetime of the device. Moreover, it is
no longer necessary to unprepare and disable the clocks explicitly, so drop
the label "unprepare_clk".
Li Zetao [Mon, 21 Aug 2023 03:17:29 +0000 (11:17 +0800)]
mtd: rawnand: intel: Use helper function devm_clk_get_enabled()
Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared
and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be
replaced by devm_clk_get_enabled() when driver enables (and possibly
prepares) the clocks for the whole lifetime of the device. Moreover, it is
no longer necessary to unprepare and disable the clocks explicitly, so drop
the label "err_disable_unprepare_clk".
Li Zetao [Mon, 21 Aug 2023 03:17:28 +0000 (11:17 +0800)]
mtd: rawnand: fsmc: Use helper function devm_clk_get_enabled()
Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared
and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be
replaced by devm_clk_get_enabled() when driver enables (and possibly
prepares) the clocks for the whole lifetime of the device. Moreover, it is
no longer necessary to unprepare and disable the clocks explicitly. The
label "disable_clk" no longer makes sense, rename it to "disable_fsmc".
Li Zetao [Mon, 21 Aug 2023 03:17:27 +0000 (11:17 +0800)]
mtd: rawnand: arasan: Use helper function devm_clk_get_enabled()
Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared
and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be
replaced by devm_clk_get_enabled() when driver enables (and possibly
prepares) the clocks for the whole lifetime of the device. Moreover, it is
no longer necessary to unprepare and disable the clocks explicitly, so drop
the label "disable_bus_clk" and "disable_controller_clk".
Md Sadre Alam [Fri, 18 Aug 2023 14:51:00 +0000 (20:21 +0530)]
mtd: rawnand: qcom: Clear buf_count and buf_start in raw read
Initialize buf_count and buf_start to 0 before starting the
raw read. If we will not initialize then read staus will get
updated with wrong value and we will see failure for even
successful raw read transaction.
Miquel Raynal [Fri, 18 Aug 2023 14:39:53 +0000 (16:39 +0200)]
Merge tag 'spi-nor/for-6.6' into mtd/next
SPI NOR core changes:
* fix assumption on enabling quad mode in
spi_nor_write_16bit_sr_and_check()
* avoid setting SRWD bit in SR if WP# signal not connected as it will
configure the SR permanently as read only. Add "no-wp" dt property.
* clarify the need for spi-nor compatibles in dt-bindings
SPI NOR manufacturer drivers changes:
* spansion:
- add support for S28HS02GT
- switch methods to use vreg_offset from SFDP instead of hardcoding
the register value
* microchip/sst:
- add support for sst26vf032b flash
* winbond:
- correct flags for Winbond w25q128
When building with clang 18 I see the following warning:
| drivers/mtd/maps/physmap-versatile.c:209:25: warning: cast to smaller
| integer type 'enum versatile_flashprot' from 'const void *' [-Wvoid-pointer-to-enum-cast]
| 209 | versatile_flashprot = (enum versatile_flashprot)devid->data;
This is due to the fact that `devid->data` is a void* while `enum versatile_flashprot`
has the size of an int.
Cast `devid->data` to a uintptr_t to silence the above warning for clang
builds using W=1.
When building with clang 18 I see the following warning:
| drivers/mtd/nand/raw/vf610_nfc.c:853:17: warning: cast to smaller integer
| type 'enum vf610_nfc_variant' from 'const void *' [-Wvoid-pointer-to-enum-cast]
| 853 | nfc->variant = (enum vf610_nfc_variant)of_id->data;
This is due to the fact that `of_id->data` is a void* while `enum vf610_nfc_variant`
has the size of an int.
Cast `of_id->data` to a uintptr_t to silence the above warning for clang
builds using W=1.
Ruan Jinjie [Tue, 8 Aug 2023 03:29:43 +0000 (11:29 +0800)]
mtd: rawnand: Propagate error and simplify ternary operators for brcmstb_nand_wait_for_completion()
As bcmnand_ctrl_poll_status() return negative errno, so return true if
sts < 0. The < 0 case does not exist for wait_for_completion_timeout(),
so return true if sts = 0 and zero otherwise. Both of the true return
of them can be considered as a -ETIMEDOUT err, so return -ETIMEDOUT
if err is true to propagate err from its caller.
mtd: rawnand: qcom: Simplify the call to nand_prog_page_end_op()
Now that the dma desc cleanup is moved inside submit_descs(), let's
simplify the call to nand_prog_page_end_op() inside qcom_nandc_write_page()
and qcom_nandc_write_page_raw() to match other functions.
mtd: rawnand: qcom: Unmap sg_list and free desc within submic_descs()
There are two types of dma descriptors being used in this driver allocated
by, prepare_bam_async_desc() and prep_adm_dma_desc() helper functions.
These functions map and prepare the descriptors to be used for dma
transfers.
And all the descriptors are submitted inside the submit_descs() function.
Once the transfer completion happens, those descriptors should be unmapped
and freed as a part of cleanup.
Currently, free_descs() function is doing the said cleanup of descriptors.
But the callers of submit_descs() are required to call free_descs() in both
the success and error cases.
Since there are no other transactions need to be done after submit_descs(),
let's just move the contents of free_descs() inside submit_descs() itself.
This makes sure that the cleanup is handled within the submit_descs()
thereby offloading the cleanup part from callers.
While at it, let's also rename the return variable from "r" to "ret".
mtd: rawnand: qcom: Fix the opcode check in qcom_check_op()
qcom_check_op() function checks for the invalid opcode for the instruction
types. Currently, it just returns -ENOTSUPP for all opcodes of
NAND_OP_CMD_INSTR type due to the use of "||" operator instead of "&&".
Fix it!
This also fixes the following smatch warning:
drivers/mtd/nand/raw/qcom_nandc.c:3036 qcom_check_op() warn: was && intended here instead of ||?
mtd: rawnand: qcom: Handle unsupported opcode in qcom_op_cmd_mapping()
Handle the scenario where the caller has passed an unsupported opcode to
qcom_op_cmd_mapping(). In that case, log the error and return the
-EOPNOTSUPP errono. Also, let's propagate this error code all the way up.
This also fixes the following smatch warning:
drivers/mtd/nand/raw/qcom_nandc.c:2941 qcom_op_cmd_mapping() error: uninitialized symbol 'ret'.
mtd: rawnand: qcom: Rename variables in qcom_op_cmd_mapping()
qcom_op_cmd_mapping() function accepts opcode and returns the corresponding
command register. So let's rename the local variables and parameters to
reflect the same.
Li Zetao [Fri, 18 Aug 2023 07:46:41 +0000 (15:46 +0800)]
mtd: spi-nor: nxp-spifi: Use helper function devm_clk_get_enabled()
Since commit 7ef9651e9792 ("clk: Provide new devm_clk helpers for prepared
and enabled clocks"), devm_clk_get() and clk_prepare_enable() can now be
replaced by devm_clk_get_enabled() when driver enable (and possibly
prepare) the clocks for the whole lifetime of the device. Moreover, it is
no longer necessary to unprepare and disable the clock explicitly, so drop
the label "dis_clks" and "dis_clk_reg".
Hsin-Yi Wang [Fri, 18 Aug 2023 06:42:23 +0000 (14:42 +0800)]
mtd: spi-nor: Check bus width while setting QE bit
spi_nor_write_16bit_sr_and_check() should also check if bus width is
4 before setting QE bit.
Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()") Suggested-by: Michael Walle <michael@walle.cc> Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20230818064524.1229100-2-hsinyi@chromium.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Zhu Wang [Thu, 3 Aug 2023 08:50:56 +0000 (16:50 +0800)]
mtd: rawnand: vf610_nfc: Do not check 0 for platform_get_irq()
Since platform_get_irq() never returned zero, so it need not to check
whether it returned zero, and we use the return error code of
platform_get_irq() to replace the current return error code, for that
platform_get_irq() may return -EINVAL or -ENXIO.
Li Zetao [Wed, 2 Aug 2023 01:35:00 +0000 (09:35 +0800)]
mtd: rawnand: brcmnand: Use devm_platform_ioremap_resource_byname()
Convert platform_get_resource_byname() + devm_ioremap_resource() to a
single call to devm_platform_ioremap_resource_byname(), as this is
exactly what this function does.
mtd: Clean refcounting with MTD_PARTITIONED_MASTER
The logic is way too convoluted, let's clean the kref_get/put section to
clarify what this block does when using CONFIG_MTD_PARTITIONED_MASTER:
- Iterate through all the parent mtd devices
- Grab a reference over them all but the master
- Only grab the master whith CONFIG_MTD_PARTITIONED_MASTER
Same logic must apply in the put path, otherwise it would be broken.
Cc: Tomas Winkler <tomas.winkler@intel.com> Cc: Alexander Usyskin <alexander.usyskin@intel.com> Cc: Zhang Xiaoxu <zhangxiaoxu5@huawei.com> Fixes: 19bfa9ebebb5 ("mtd: use refcount to prevent corruption") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Alexander Usyskin <alexander.usyskin@intel.com> Link: https://lore.kernel.org/linux-mtd/20230731090903.770277-1-miquel.raynal@bootlin.com
I case of partition device_unregister() in mtd_device_release()
calls mtd_release() which frees mtd_info structure for partition.
All code after device_unregister in mtd_device_release thus
uses already freed memory.
Move part of code to mtd_release() and restict mtd->dev cleanup
to non-partion object.
For partition object such cleanup have no sense as partition
mtd_info is removed.
Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Zhang Xiaoxu <zhangxiaoxu5@huawei.com> Fixes: 19bfa9ebebb5 ("mtd: use refcount to prevent corruption") Reviewed-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230731115836.542747-1-alexander.usyskin@intel.com
drivers/mtd/nand/raw/meson_nand.c:244:59: error: initializer element is not a compile-time constant
static const struct nand_ecc_step_info axg_stepinfo[] = { axg_stepinfo_1024, axg_stepinfo_512 };
^~~~~~~~~~~~~~~~~
Fixes: 0e1db39336d8 ("mtd: rawnand: meson: support for 512B ECC step size") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202307281007.MMuVjmJ9-lkp@intel.com/ Signed-off-by: Arseniy Krasnov <AVKrasnov@sberdevices.ru> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230728093810.2985324-1-AVKrasnov@sberdevices.ru
mtd: rawnand: qcom: Fix address parsing within ->exec_op()
The naddrs variable is initialized but not used. Fixing this could have
been a matter of dropping the variable, but the right way to do it looks
a bit more complex: we can avoid useless writes to the q_op structure by
using it. In practice we could even have possible out-of-bound bugs with
the existing implementation. Let's fix all that by just performing the
right number of assignments in the addr{1,2}_reg fields.
mtd: rawnand: qcom: Early structure initialization
Instead of allocating a structure on the stack with random data and then
expect the callee to perform the initialization (which is, in general,
error prone), prefer zeroing the structure explicitly at allocation and
provide the already zeroed area, so no explicit memset operation is
needed. It is probably safer to do so, so we limit the timeframe when
dirty data could actually be accessed by mistake.
Fix following checkpatch warning:
"CHECK: Please don't use multiple blank lines"
"CHECK: Please use a blank line after
function/struct/union/enum declarations"
Colin Ian King [Wed, 19 Jul 2023 10:33:54 +0000 (11:33 +0100)]
mtdblock: make warning messages ratelimited
When exercising various dev interfaces with stress-ng the mtdblock drivers
can be (ab)used to generate a lot of warning messages. Make these rate
limited to reduce the kernel log from being spammed with the same messages.
Rob Herring [Fri, 14 Jul 2023 17:47:49 +0000 (11:47 -0600)]
mtd: Explicitly include correct DT includes
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it was merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.
dt-bindings: nand: meson: make ECC properties dependent
ECC properties 'nand-ecc-strength' and 'nand-ecc-step-size' depends on
each other, so they must be both either set or not set. In first case
ECC core will try to use these values if possible (by checking ECC caps
provided by driver), in second case ECC core will select most optimal
values for both properties.
mtd: spi-nor: spansion: switch cypress_nor_get_page_size() to use vreg_offset
All users of cypress_nor_get_page_size() but S25FS256T retrieve n_dice
and vreg_offset from SFDP. S25FS256T does not define the SCCR map to
retrive the vreg_offset, but it does support it: SPINOR_REG_CYPRESS_VREG.
Switch cypress_nor_get_page_size() to always use vreg_offset so that we
use the same code base for both single and multi chip package flashes.
cypress_nor_get_page_size() is now called in the post_sfdp() hook instead
of post_bfpt(), as vreg_offset and n_dice are parsed after BFPT.
Consequently the null checks on n_dice and vreg_offset are moved to
the post_sfdp() hook.
mtd: spi-nor: spansion: switch s25hx_t to use vreg_offset for quad_enable()
All s25hx_t flashes have single or multi chip flavors and already use
n_dice and vreg_offset in cypress_nor_sr_ready_and_clear. Switch s25hx_t
to always use vreg_offset for the quad_enable() method, so that we use
the same code base for both single and multi chip package flashes.
mtd: spi-nor: spansion: let SFDP determine the flash and sector size
sector_size is used to determine the flash size and the erase size in
case of uniform erase. n_sectors is used to determine the flash_size.
But the flash size and the erase sizes are determined when parsing SFDP,
let SFDP determine them.
mtd: spi-nor: spansion: add octal DTR support in RD_ANY_REG_OP
S28HS02GT uses RD_ANY_REG_OP to read status of each die. In Octal DTR
mode, RD_ANY_REG_OP needs dummy cycles (same as params->rdsr_dummy) and
data length should be 2.
mtd: spi-nor: spansion: add MCP support in set_octal_dtr()
Infineon multi-chip package (MCP) devices require the Octal DTR
configuraion to be set on each die. We can access to configuration
registers in each die by using params->n_dice and params->vreg_offset[]
populated from SFDP. Add MCP support in set_octal_dtr().
mtd: spi-nor: spansion: switch h28hx's ready() to use vreg_offset
s28hx is the sole user of cypress_nor_set_octal_dtr, which already
uses vreg_offset to set octal DTR. Switch the ready method to use
vreg_offset as well. This is a preparation patch. The goal is to use
the same s28hx methods for the multi die version of the flash.
mtd: spi-nor: spansion: switch set_octal_dtr method to use vreg_offset
All the Infineon flashes that currently support octal DTR mode
define the optional SCCR SFDP table, thus all retrieve vreg_offset.
Switch all the available octal DTR Infineon flashes to use the
volatile register offset to set the configuration registers. The goal
is to have a single pair of methods for both single/multi-chip package
devices.
mtd: spi-nor: spansion: prepare octal dtr methods for multi chip support
Infineon's multi-chip package (MCP) devices require the octal DTR
configuration to be set for each die. Split common code in
dedicated methods to ease the octal DDR MCP support addition.
mtd: spi-nor: spansion: preserve CFR2V[7] when writing MEMLAT
CFR2V[7] is assigned to Flash's address mode (3- or 4-ybte) and must not
be changed when writing MEMLAT (CFR2V[3:0]). CFR2V shall be used in a read,
update, write back fashion.
Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Semper flash") Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230726075257.12985-3-tudor.ambarus@linaro.org Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
mtd: spi-nor: spansion: use CLPEF as an alternative to CLSR
Infineon S28Hx (SEMPER Octal) and S25FS256T (SEMPER Nano) support Clear
Program and Erase Failure Flags (CLPEF, 82h) instead of CLSR(30h).
Introduce a new mfr_flag together with the infrastructure to allow
manufacturer private data in the core. With this we remove the need
to have if checks in the code at runtime and instead set the correct
opcodes at probe time. S25Hx (SEMPER QSPI) supports CLSR but it may
be disabled by CFR3x[2] while CLPEF is always available. Therefore,
the mfr_flag is also applied to S25Hx for safety.
mtd: spi-nor: rename method for enabling or disabling octal DTR
Having an *_enable(..., bool enable) definition was misleading
as the method is used both to enable and to disable the octal DTR
mode. Splitting the method in the core in two, one to enable and
another to disable the octal DTR mode does not make sense as the
method is straight forward and we'd introduce code duplication.
Update the core to use:
int (*set_octal_dtr)(struct spi_nor *nor, bool enable);
Manufacturer drivers use different sequences of commands to enable
and disable the octal DTR mode, thus for clarity they shall
implement it as:
static int manufacturer_snor_set_octal_dtr(struct spi_nor *nor, bool enable)
{
return enable ? manufacturer_snor_octal_dtr_enable() :
manufacturer_snor_octal_dtr_disable();
}
The Winbond "w25q128" (actual vendor name W25Q128JV) has
exactly the same flags as the sibling device "w25q128jv".
The devices both require unlocking to enable write access.
The actual product naming between devices vs the Linux
strings in winbond.c:
The latter device, "w25q128jv" supports features named DTQ
and QPI, otherwise it is the same.
Not having the right flags has the annoying side effect
that write access does not work.
After this patch I can write to the flash on the Inteno
XG6846 router.
The flash memory also supports dual and quad SPI modes.
This does not currently manifest, but by turning on SFDP
parsing, the right SPI modes are emitted in
/sys/kernel/debug/spi-nor/spi1.0/capabilities
for this chip, so we also turn on this.
Since we now have determined that SFDP parsing works on
the device, we also detect the geometry using SFDP.
After this dmesg and sysfs says:
[ 1.062401] spi-nor spi1.0: w25q128 (16384 Kbytes)
cat erasesize
65536
(16384*1024)/65536 = 256 sectors
Binding files should be dual licensed. This file was initially written
as a .txt file with no specific license, so was implicitely
GPLv2. Significant part of this file and its conversion into yaml were
written by Bootlin employees which agree to comply with the rules
regarding the dual licensing so let's fix the SPDX tag to reflect the
correct license by changing it from GPL to GPL + BSD-2-Clause.
Chris Packham [Mon, 3 Jul 2023 03:50:44 +0000 (15:50 +1200)]
mtd: rawnand: marvell: add support for AC5 SoC
Add support for the AC5/AC5X SoC from Marvell. The NFC on this SoC only
supports SDR modes up to 3.
Marvell's SDK includes some predefined values for the ndtr registers.
These haven't been incorporated as the existing code seems to get good
values based on measurements taken with an oscilloscope.
Yangtao Li [Thu, 13 Jul 2023 10:44:22 +0000 (18:44 +0800)]
mtd: nand: omap: Use devm_platform_get_and_ioremap_resource()
Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Miquel Raynal [Fri, 16 Jun 2023 14:00:54 +0000 (16:00 +0200)]
dt-bindings: mtd: spi-nor: clarify the need for spi-nor compatibles
Most SPI NOR devices do not require a specific compatible, their ID can
in general be discovered with the JEDEC READ ID opcode. In this case,
only the "jedec,spi-nor" generic compatible is expected. Clarify this
information in the compatible description to (i) help device-tree
writers and (ii) prevent further attempts to extend this list with
useless information.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230616140054.2788684-1-miquel.raynal@bootlin.com
[ta: s/JEDEC/JEDEC SFDP for clarity and s/JEDEC READ ID/READ ID as
the opcode is not part of the JEDEC SFDP standard.] Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
mtd: spi-nor: Avoid setting SRWD bit in SR if WP# signal not connected
Setting the status register write disable (SRWD) bit in the status
register (SR) with WP# signal of the flash left floating or wrongly tied to
GND (that includes internal pull-downs), will configure the SR permanently
as read-only. If WP# signal is left floating or wrongly tied to GND, avoid
setting SRWD bit while writing the SR during flash protection.
dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register
If the WP# signal of the flash device is either not connected or is wrongly
tied to GND (that includes internal pull-downs), and the software sets the
status register write disable (SRWD) bit in the status register then the
status register permanently becomes read-only. To avoid this added a new
boolean DT property "no-wp". If this property is set in the DT then the
software avoids setting the SRWD during status register write operation.
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20230630142233.63585-2-amit.kumar-mahapatra@amd.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Yangtao Li [Fri, 7 Jul 2023 04:06:22 +0000 (12:06 +0800)]
mtd: physmap-core: Use devm_platform_get_and_ioremap_resource()
Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Yangtao Li [Fri, 7 Jul 2023 04:06:18 +0000 (12:06 +0800)]
mtd: lantiq-flash: Use devm_platform_get_and_ioremap_resource()
Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Yangtao Li [Fri, 7 Jul 2023 04:06:17 +0000 (12:06 +0800)]
mtd: plat-ram: Use devm_platform_get_and_ioremap_resource()
Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Yangtao Li [Fri, 7 Jul 2023 04:06:14 +0000 (12:06 +0800)]
mtd: rawnand: atmel: Use devm_platform_get_and_ioremap_resource()
Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Yangtao Li [Fri, 7 Jul 2023 04:06:12 +0000 (12:06 +0800)]
mtd: rawnand: fsl_upm: Use devm_platform_get_and_ioremap_resource()
Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Yangtao Li [Fri, 7 Jul 2023 04:06:11 +0000 (12:06 +0800)]
mtd: rawnand: lpc32xx_mlc: Use devm_platform_get_and_ioremap_resource()
Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Yangtao Li [Fri, 7 Jul 2023 04:06:10 +0000 (12:06 +0800)]
mtd: rawnand: stm32_fmc2: Use devm_platform_get_and_ioremap_resource()
Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Yangtao Li [Fri, 7 Jul 2023 04:06:09 +0000 (12:06 +0800)]
mtd: rawnand: omap2: Use devm_platform_get_and_ioremap_resource()
Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Yangtao Li [Fri, 7 Jul 2023 04:06:08 +0000 (12:06 +0800)]
mtd: rawnand: sh_flctl: Use devm_platform_get_and_ioremap_resource()
Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Yangtao Li [Fri, 7 Jul 2023 04:06:06 +0000 (12:06 +0800)]
mtd: rawnand: lpc32xx_slc: Use devm_platform_get_and_ioremap_resource()
Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Yangtao Li [Fri, 7 Jul 2023 04:06:05 +0000 (12:06 +0800)]
mtd: rawnand: sunxi: Use devm_platform_get_and_ioremap_resource()
Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
William Zhang [Thu, 6 Jul 2023 18:29:09 +0000 (11:29 -0700)]
mtd: rawnand: brcmnand: Fix mtd oobsize
brcmnand controller can only access the flash spare area up to certain
bytes based on the ECC level. It can be less than the actual flash spare
area size. For example, for many NAND chip supporting ECC BCH-8, it has
226 bytes spare area. But controller can only uses 218 bytes. So brcmand
driver overrides the mtd oobsize with the controller's accessible spare
area size. When the nand base driver utilizes the nand_device object, it
resets the oobsize back to the actual flash spare aprea size from
nand_memory_organization structure and controller may not able to access
all the oob area as mtd advises.
This change fixes the issue by overriding the oobsize in the
nand_memory_organization structure to the controller's accessible spare
area size.
William Zhang [Thu, 6 Jul 2023 18:29:08 +0000 (11:29 -0700)]
mtd: rawnand: brcmnand: Fix potential out-of-bounds access in oob write
When the oob buffer length is not in multiple of words, the oob write
function does out-of-bounds read on the oob source buffer at the last
iteration. Fix that by always checking length limit on the oob buffer
read and fill with 0xff when reaching the end of the buffer to the oob
registers.
William Zhang [Thu, 6 Jul 2023 18:29:07 +0000 (11:29 -0700)]
mtd: rawnand: brcmnand: Fix crash during the panic_write
When executing a NAND command within the panic write path, wait for any
pending command instead of calling BUG_ON to avoid crashing while
already crashing.
William Zhang [Thu, 6 Jul 2023 18:29:06 +0000 (11:29 -0700)]
mtd: rawnand: brcmnand: Fix potential false time out warning
If system is busy during the command status polling function, the driver
may not get the chance to poll the status register till the end of time
out and return the premature status. Do a final check after time out
happens to ensure reading the correct status.
Fixes: 9d2ee0a60b8b ("mtd: nand: brcmnand: Check flash #WP pin status before nand erase/program") Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-3-william.zhang@broadcom.com
William Zhang [Thu, 6 Jul 2023 18:29:05 +0000 (11:29 -0700)]
mtd: rawnand: brcmnand: Fix ECC level field setting for v7.2 controller
v7.2 controller has different ECC level field size and shift in the acc
control register than its predecessor and successor controller. It needs
to be set specifically.
mtd: rawnand: meson: use NAND core API to check status
NAND core API already has functions to send NAND_CMD_STATUS and leave
status checking mode by sending NAND_CMD_READ0, so use both of them
instead of direct access to the controller registers.
projects / thirdparty / kernel / linux.git / log
