* pci/controller/xgene:
cpu/hotplug: Remove unused cpuhp_state CPUHP_PCI_XGENE_DEAD
PCI: xgene-msi: Restructure handler setup/teardown
PCI: xgene-msi: Probe as a standard platform driver
PCI: xgene-msi: Resend an MSI racing with itself on a different CPU
PCI: xgene-msi: Sanitise MSI allocation and affinity setting
PCI: xgene-msi: Get rid of intermediate tracking structure
PCI: xgene-msi: Use device-managed memory allocations
PCI: xgene-msi: Drop superfluous fields from xgene_msi structure
PCI: xgene-msi: Make per-CPU interrupt setup robust
PCI: xgene: Drop XGENE_PCIE_IP_VER_UNKN
PCI: xgene: Drop useless conditional compilation
PCI: xgene: Defer probing if the MSI widget driver hasn't probed yet
genirq: Teach handle_simple_irq() to resend an in-progress interrupt
- Drop unused PCIe Message routing and code definitions (Hans Zhang)
- Use standard PCIe config register definitions instead of
rockchip-specific redefinitions (Geraldo Nascimento)
- Set Target Link Speed to 5.0 GT/s before retraining so we have a chance
to train at a higher speed (Geraldo Nascimento)
* pci/controller/rockchip:
PCI: rockchip: Set Target Link Speed to 5.0 GT/s before retraining
PCI: rockchip: Use standard PCIe definitions
PCI: rockchip: Remove redundant PCIe message routing definitions
- Export DWC MSI controller related APIs for use by upcoming DWC-based ECAM
implementation (Mayank Rana)
- Rename gen_pci_init() to pci_host_common_ecam_create() and export for use
by controller drivers (Mayank Rana)
- Add DT binding and driver support for SA8255p, which supports ECAM for
Configuration Space access (Mayank Rana)
- Update DT binding and driver to describe PHYs and per-Root Port resets in
a Root Port stanza and deprecate describing them in the host bridge; this
makes it possible to support multiple Root Ports in the future (Krishna
Chaitanya Chundru)
* pci/controller/qcom:
PCI: qcom: Add support for parsing the new Root Port binding
dt-bindings: PCI: qcom: Move PHY & reset GPIO to Root Port node
PCI: qcom: Add support for Qualcomm SA8255p based PCIe Root Complex
dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex
PCI: host-generic: Rename and export gen_pci_init() for PCIe controller drivers
PCI: dwc: Export DWC MSI controller related APIs
- Add IMX8MQ_EP third 64-bit BAR in epc_features (Richard Zhu)
- Add IMX8MM_EP and IMX8MP_EP fixed 256-byte BAR 4 in epc_features (Richard
Zhu)
- Factor imx_pcie_add_lut_by_rid() out of imx_pcie_enable_device() for use
by LUT configuration (Frank Li)
- Configure LUT for MSI/IOMMU in Endpoint mode so Root Complex can trigger
doorbel on Endpoint (Frank Li)
- Remove apps_reset (LTSSM_EN) from imx_pcie_{assert,deassert}_core_reset(),
which fixes a hotplug regression on i.MX8MM (Richard Zhu)
- Delay Endpoint link start until configfs 'start' written (Richard Zhu)
* pci/controller/imx6:
PCI: imx6: Delay link start until configfs 'start' written
PCI: imx6: Remove apps_reset toggling from imx_pcie_{assert/deassert}_core_reset
PCI: imx6: Add LUT configuration for MSI/IOMMU in Endpoint mode
PCI: imx6: Add helper function imx_pcie_add_lut_by_rid()
PCI: imx6: Add IMX8MM_EP and IMX8MP_EP fixed 256-byte BAR 4 in epc_features
PCI: imx6: Add IMX8MQ_EP third 64-bit BAR in epc_features
- Add optional DT 'num-lanes' property and if present, use it to override
the Maximum Link Width advertised in Link Capabilities (Jim Quinlan)
* pci/controller/brcmstb:
PCI: brcmstb: Replace open coded value with PCIE_T_RRS_READY_MS
MAINTAINERS: Drop Nicolas from maintaining pcie-brcmstb
PCI: brcmstb: Set MLW based on "num-lanes" DT property if present
dt-bindings: PCI: brcm,stb-pcie: Add num-lanes property
- Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS (the
required delay before sending config requests after a reset) (Niklas
Cassel)
- PCIE_T_RRS_READY_MS and PCIE_RESET_CONFIG_WAIT_MS were two names for the
same delay; replace PCIE_T_RRS_READY_MS with PCIE_RESET_CONFIG_WAIT_MS
and remove PCIE_T_RRS_READY_MS (Niklas Cassel)
- Add required PCIE_RESET_CONFIG_WAIT_MS delay after Link up IRQ to
dw-rockchip, qcom (Niklas Cassel)
- Add required PCIE_RESET_CONFIG_WAIT_MS after waiting for Link up on
Ports that support > 5.0 GT/s in dwc core (Niklas Cassel)
- Move LINK_WAIT_SLEEP_MS and LINK_WAIT_MAX_RETRIES to pci.h and prefix
with 'PCIE_' for potential sharing across drivers (Niklas Cassel)
* pci/controller/linkup-fix:
PCI: Move link up wait time and max retries macros to pci.h
PCI: dwc: Ensure that dw_pcie_wait_for_link() waits 100 ms after link up
PCI: qcom: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ
PCI: dw-rockchip: Wait PCIE_RESET_CONFIG_WAIT_MS after link-up IRQ
PCI: rockchip-host: Use macro PCIE_RESET_CONFIG_WAIT_MS
PCI: Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS
- Use dev_fwnode() instead of of_fwnode_handle() to remove OF dependency
in altera (fixes an unused variable), designware-host, mediatek,
mediatek-gen3, mobiveil, plda, xilinx, xilinx-dma, xilinx-nwl (Jiri
Slaby, Arnd Bergmann)
- Convert aardvark, altera, brcmstb, designware-host, iproc, mediatek,
mediatek-gen3, mobiveil, plda, rcar-host, vmd, xilinx, xilinx-dma,
xilinx-nwl from using pci_msi_create_irq_domain() to using
msi_create_parent_irq_domain() instead; this makes the interrupt
controller per-PCI device, allows dynamic allocation of vectors after
initialization, and allows support of IMS (Nam Cao)
- Convert vmd to using lock guards to tidy the code (Nam Cao)
* pci/controller/msi-parent:
PCI: vmd: Switch to msi_create_parent_irq_domain()
PCI: vmd: Convert to lock guards
PCI: plda: Switch to msi_create_parent_irq_domain()
PCI: xilinx: Switch to msi_create_parent_irq_domain()
PCI: xilinx-nwl: Switch to msi_create_parent_irq_domain()
PCI: xilinx-xdma: Switch to msi_create_parent_irq_domain()
PCI: rcar-host: Switch to msi_create_parent_irq_domain()
PCI: mediatek: Switch to msi_create_parent_irq_domain()
PCI: mediatek-gen3: Switch to msi_create_parent_irq_domain()
PCI: iproc: Switch to msi_create_parent_irq_domain()
PCI: brcmstb: Switch to msi_create_parent_irq_domain()
PCI: altera-msi: Switch to msi_create_parent_irq_domain()
PCI: aardvark: Switch to msi_create_parent_irq_domain()
PCI: mobiveil: Switch to msi_create_parent_irq_domain()
PCI: dwc: Switch to msi_create_parent_irq_domain()
PCI: controller: Use dev_fwnode() instead of of_fwnode_handle()
* pci/endpoint/doorbell:
selftests: pci_endpoint: Add doorbell test case
misc: pci_endpoint_test: Add doorbell test case
PCI: endpoint: pci-epf-test: Add doorbell test support
PCI: endpoint: Add pci_epf_align_inbound_addr() helper for inbound address alignment
PCI: endpoint: pci-ep-msi: Add checks for MSI parent and mutability
PCI: endpoint: Add RC-to-EP doorbell support using platform MSI controller
- Restore VF resizable BAR state after reset (Michał Winiarski)
- Add pci_resource_num_to_vf_bar() and pci_resource_num_from_vf_bar() to
convert between VF BAR number and the dev->resource[] index (Michał
Winiarski)
- Allow IOV resources (VF BARs) to be resized (Michał Winiarski)
- Add pci_iov_vf_bar_set_size() so drivers can control VF BAR size (Michał
Winiarski)
* pci/resources:
PCI/IOV: Allow drivers to control VF BAR size
PCI/IOV: Check that VF BAR fits within the reservation
PCI/IOV: Allow IOV resources to be resized in pci_resize_resource()
PCI/IOV: Add pci_resource_num_to_vf_bar() to convert VF BAR number to/from IOV resource
PCI/IOV: Restore VF resizable BAR state after reset
- Fix runtime PM ref imbalance on Hot-Plug Capable ports caused by
misinterpreting a config read failure after a device has been removed
(Lukas Wunner)
- Avoid creating a useless PCIe port service device for pciehp if the slot
is handled by the ACPI hotplug driver (Lukas Wunner)
- Ignore ACPI hotplug slots when calculating depth of pciehp hotplug ports
(Lukas Wunner)
- Simplify pci_bridge_d3_possible() and clarify comments (Lukas Wunner)
* pci/hotplug:
PCI: Move is_pciehp check out of pciehp_is_native()
PCI: pciehp: Use is_pciehp instead of is_hotplug_bridge
PCI/portdrv: Use is_pciehp instead of is_hotplug_bridge
PCI/ACPI: Fix runtime PM ref imbalance on Hot-Plug Capable ports
- Allow 'isolated PCI functions' (multi-function devices without a function
0) for LoongArch, similar to s390 and jailhouse (Huacai Chen)
- Mask out unrelated bits in PCIE_LNKCAP_SLS2SPEED() and
PCIE_LNKCTL2_TLS2SPEED(), which makes them more robust and fixes a
WARN_ON_ONCE() in pcie_set_target_speed() (Jiwei Sun)
- Read Link Control 2 again when retraining a link after a training failure
so we try to increase the link speed (Jiwei Sun)
- Allow built-in drivers, not just modular drivers, to use async initial
probing (Lukas Wunner)
- Support Immediate Readiness even on devices with no PM Capability (Sean
Christopherson)
* pci/enumeration:
PCI: Support Immediate Readiness on devices without PM capabilities
PCI: Allow built-in drivers to use async initial probing
PCI: Adjust the position of reading the Link Control 2 register
PCI: Fix link speed calculation on retrain failure
PCI: Extend isolated function probing to LoongArch
- Add pci_is_display() to check for "Display" base class and use it in
ALSA hda, vfio, vga_switcheroo, vt-d (Mario Limonciello)
* pci/boot-display:
ALSA: hda: Use pci_is_display()
iommu/vt-d: Use pci_is_display()
vga_switcheroo: Use pci_is_display()
vfio/pci: Use pci_is_display()
PCI: Add pci_is_display() to check if device is a display controller
Each PCIe controller on SA8775P includes a 'link_down' reset line in
hardware. This patch documents the reset in the device tree binding.
The 'link_down' reset is used to forcefully bring down the PCIe link
layer, which is useful in scenarios such as link recovery after errors,
power management transitions, and hotplug events. Including this reset
line improves robustness and provides finer control over PCIe controller
behavior.
As the 'link_down' reset was omitted in the initial submission, it is now
being documented. While this reset is not required for most of the block's
basic functionality, and device trees lacking it will continue to function
correctly in most cases, it is necessary to ensure maximum robustness when
shutting down or recovering the PCIe core. Therefore, its inclusion is
justified despite the minor ABI change.
This binding is already covered by fsl,mpc8xxx-pci.yaml schema. While
the MPC512x is mentioned here, its compatible strings aren't actually
documented and remain that way.
PCI: Move is_pciehp check out of pciehp_is_native()
pci_bridge_d3_possible() seeks to forbid runtime power management on:
* Non Hot-Plug Capable PCIe ports which are nevertheless ACPI slots
(recognizable as: bridge->is_hotplug_bridge && !bridge->is_pciehp)
* Hot-Plug Capable PCIe ports for which platform firmware has not granted
PCIe Native Hot-Plug control to the operating system
(recognizable as: bridge->is_pciehp && !pciehp_is_native(bridge))
Somewhat confusingly, the check for is_hotplug_bridge is in
pci_bridge_d3_possible(), whereas the one for is_pciehp is in
pciehp_is_native().
For clarity, check is_pciehp directly in pci_bridge_d3_possible()
(and in the other caller of pciehp_is_native(), hotplug_is_native()).
Rephrase the code comment preceding these checks to no longer mention
"System Management Mode", which is an x86 term inappropriate in generic
PCI code. Likewise no longer mention "Thunderbolt on non-Macs", because
there is nothing Thunderbolt-specific about these checks. It used to be
the case that non-Macs relied on the platform for Thunderbolt tunnel
management and hotplug, but they've since moved to OS-native tunnel
management (as Macs always have), hence the code comment is no longer
accurate.
There is a subsequent check for is_hotplug_bridge further down in
pci_bridge_d3_possible(). Change the check to is_pciehp because any
ports matching "bridge->is_hotplug_bridge && !bridge->is_pciehp" are
already filtered out at the top of the function.
Do the same for another check in acpi_pci_bridge_d3(), which is called
from pci_bridge_d3_possible() via platform_pci_bridge_d3().
PCI: pciehp: Use is_pciehp instead of is_hotplug_bridge
The PCIe hotplug driver calculates the depth of a nested hotplug port by
looking at the is_hotplug_bridge flag. The depth is used as lockdep class
to tell hotplug ports apart.
The is_hotplug_bridge flag encompasses ACPI slots handled by the ACPI
hotplug driver, hence the calculated depth may be too high. Avoid by
checking the is_pciehp flag instead.
This glitch likely has no user-visible impact: ACPI slots typically only
exist at the Root Port level, not in nested hotplug hierarchies. Also,
CONFIG_LOCKDEP is usually only used by developers. So this is just for
the sake of correctness.
PCI/portdrv: Use is_pciehp instead of is_hotplug_bridge
The PCIe port driver erroneously creates a subdevice for hotplug on ACPI
slots which are handled by the ACPI hotplug driver.
Avoid by checking the is_pciehp flag instead of is_hotplug_bridge when
deciding whether to create a subdevice. The latter encompasses ACPI slots
whereas the former doesn't.
The superfluous subdevice has no real negative impact, it occupies memory
and interrupt resources but otherwise just sits there waiting for
interrupts from the slot that are never signaled.
PCI/ACPI: Fix runtime PM ref imbalance on Hot-Plug Capable ports
pci_bridge_d3_possible() is called from both pcie_portdrv_probe() and
pcie_portdrv_remove() to determine whether runtime power management shall
be enabled (on probe) or disabled (on remove) on a PCIe port.
The underlying assumption is that pci_bridge_d3_possible() always returns
the same value, else a runtime PM reference imbalance would occur. That
assumption is not given if the PCIe port is inaccessible on remove due to
hot-unplug: pci_bridge_d3_possible() calls pciehp_is_native(), which
accesses Config Space to determine whether the port is Hot-Plug Capable.
An inaccessible port returns "all ones", which is converted to "all
zeroes" by pcie_capability_read_dword(). Hence the port no longer seems
Hot-Plug Capable on remove even though it was on probe.
The resulting runtime PM ref imbalance causes warning messages such as:
Avoid the Config Space access (and thus the runtime PM ref imbalance) by
caching the Hot-Plug Capable bit in struct pci_dev.
The struct already contains an "is_hotplug_bridge" flag, which however is
not only set on Hot-Plug Capable PCIe ports, but also Conventional PCI
Hot-Plug bridges and ACPI slots. The flag identifies bridges which are
allocated additional MMIO and bus number resources to allow for hierarchy
expansion.
The kernel is somewhat sloppily using "is_hotplug_bridge" in a number of
places to identify Hot-Plug Capable PCIe ports, even though the flag
encompasses other devices. Subsequent commits replace these occurrences
with the new flag to clearly delineate Hot-Plug Capable PCIe ports from
other kinds of hotplug bridges.
Document the existing "is_hotplug_bridge" and the new "is_pciehp" flag
and document the (non-obvious) requirement that pci_bridge_d3_possible()
always returns the same value across the entire lifetime of a bridge,
including its hot-removal.
Frank Li [Thu, 10 Jul 2025 19:13:53 +0000 (15:13 -0400)]
misc: pci_endpoint_test: Add doorbell test case
Add doorbell support with the help of three new registers:
PCIE_ENDPOINT_TEST_DB_BAR, PCIE_ENDPOINT_TEST_DB_ADDR, and
PCIE_ENDPOINT_TEST_DB_DATA.
The testcase works by triggering the doorbell in Endpoint by writing the
value from PCI_ENDPOINT_TEST_DB_DATA register to the address provided by
PCI_ENDPOINT_TEST_DB_OFFSET register of the BAR indicated by the
PCIE_ENDPOINT_TEST_DB_BAR register and waiting for the completion status
from the Endpoint.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[mani: removed one spurious change and reworded the commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Niklas Cassel <cassel@kernel.org> Link: https://patch.msgid.link/20250710-ep-msi-v21-7-57683fc7fb25@nxp.com
Frank Li [Thu, 10 Jul 2025 19:13:52 +0000 (15:13 -0400)]
PCI: endpoint: pci-epf-test: Add doorbell test support
Add doorbell support by allocating a dedicated BAR using the
pci_epf_alloc_doorbell() API and mapping the Endpoint MSI controller
message data address to it. The data to be written in the message address
is stored in the 'pci_epf_test_reg::doorbell_data' register. Finally, the
RC can trigger doorbell in the Endpoint by writing the content of
'doorbell_data' register to the offset specified in 'doorbell_offset' of
the 'doorbell_bar' BAR.
Triggering of the doorbell is detected by pci_epf_test_doorbell_handler(),
which is bound to the doorbell IRQ. On successful completion,
STATUS_DOORBELL_SUCCESS status is set in the above mentioned handler.
To avoid breaking compatibility between host and endpoint, add two new
commands: COMMAND_ENABLE_DOORBELL and COMMAND_DISABLE_DOORBELL.
The doorbell is allocated when COMMAND_ENABLE_DOORBELL command is called
and destroyed when COMMAND_DISABLE_DOORBELL is called.
This doorbell feature only works when both RC and EP drivers support it.
If one of them doesn't support the feature, the testcase will fail.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[mani: code cleanups and reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Niklas Cassel <cassel@kernel.org> Link: https://patch.msgid.link/20250710-ep-msi-v21-6-57683fc7fb25@nxp.com
Frank Li [Thu, 10 Jul 2025 19:13:51 +0000 (15:13 -0400)]
PCI: endpoint: Add pci_epf_align_inbound_addr() helper for inbound address alignment
Add pci_epf_align_inbound_addr() to align the inbound addresses according
to PCI BAR alignment requirements. The aligned base address and offset are
returned via 'base' and 'off' parameters.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[mani: reworded kernel-doc and commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Niklas Cassel <cassel@kernel.org> Link: https://patch.msgid.link/20250710-ep-msi-v21-5-57683fc7fb25@nxp.com
Frank Li [Thu, 10 Jul 2025 19:13:50 +0000 (15:13 -0400)]
PCI: endpoint: pci-ep-msi: Add checks for MSI parent and mutability
Some MSI controllers can change address/data pair during the execution of
irq_chip::irq_set_affinity() callback. Since the current PCI Endpoint
framework cannot support mutable MSI controllers, call
irq_domain_is_msi_immutable() API to check if the controller is immutable
or not.
Also ensure that the MSI domain is a parent MSI domain so that it can
allocate address/data pairs.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[mani: reworded error message and commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Niklas Cassel <cassel@kernel.org> Link: https://patch.msgid.link/20250710-ep-msi-v21-4-57683fc7fb25@nxp.com
Nam Cao [Thu, 26 Jun 2025 14:48:06 +0000 (16:48 +0200)]
PCI: vmd: Switch to msi_create_parent_irq_domain()
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain()
which was using legacy MSI domain setup.
Signed-off-by: Nam Cao <namcao@linutronix.de>
[mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: rebase on dev_fwnode() conversion, wrap long lines, squash fix
from https://lore.kernel.org/r/20250716201216.TsY3Kn45@linutronix.de] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/de3f1d737831b251e9cd2cbf9e4c732a5bbba13a.1750858083.git.namcao@linutronix.de
Nam Cao [Thu, 26 Jun 2025 14:48:03 +0000 (16:48 +0200)]
PCI: plda: Switch to msi_create_parent_irq_domain()
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain()
which was using legacy MSI domain setup.
Signed-off-by: Nam Cao <namcao@linutronix.de>
[mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: rebase on dev_fwnode() conversion, drop fwnode local var] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/1279fe6500a1d8135d8f5feb2f055df008746c88.1750858083.git.namcao@linutronix.de
Nam Cao [Thu, 26 Jun 2025 14:48:02 +0000 (16:48 +0200)]
PCI: xilinx: Switch to msi_create_parent_irq_domain()
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain()
which was using legacy MSI domain setup.
Signed-off-by: Nam Cao <namcao@linutronix.de>
[mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: rebase on dev_fwnode() conversion, drop fwnode local var] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/b1353c797ce53714c22823de3bd2ae3d09fcd84f.1750858083.git.namcao@linutronix.de
Nam Cao [Thu, 26 Jun 2025 14:48:01 +0000 (16:48 +0200)]
PCI: xilinx-nwl: Switch to msi_create_parent_irq_domain()
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain()
which was using legacy MSI domain setup.
Signed-off-by: Nam Cao <namcao@linutronix.de>
[mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: rebase on dev_fwnode() conversion, drop fwnode local var] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/5ac6e216bf2eaa438c8854baf2ff3e5cf0b2284f.1750858083.git.namcao@linutronix.de
Nam Cao [Thu, 26 Jun 2025 14:47:59 +0000 (16:47 +0200)]
PCI: rcar-host: Switch to msi_create_parent_irq_domain()
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain()
which was using legacy MSI domain setup.
Signed-off-by: Nam Cao <namcao@linutronix.de>
[mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: rebase on dev_fwnode() conversion, drop fwnode local var] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/ab4005db0a829549be1f348f6c27be50a2118b5e.1750858083.git.namcao@linutronix.de
Nam Cao [Thu, 26 Jun 2025 14:47:58 +0000 (16:47 +0200)]
PCI: mediatek: Switch to msi_create_parent_irq_domain()
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain()
which was using legacy MSI domain setup.
Signed-off-by: Nam Cao <namcao@linutronix.de>
[mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: rebase on dev_fwnode() conversion, drop fwnode local var] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/76f6e6ce6021607cd0fdfd79fef7d2eb69d9f361.1750858083.git.namcao@linutronix.de
Nam Cao [Thu, 26 Jun 2025 14:47:55 +0000 (16:47 +0200)]
PCI: brcmstb: Switch to msi_create_parent_irq_domain()
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain()
which was using legacy MSI domain setup.
Signed-off-by: Nam Cao <namcao@linutronix.de>
[mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: rebase on dev_fwnode() conversion, drop fwnode local var] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://patch.msgid.link/fa72703e06c2ee2c7554082c7152913eb0dd294f.1750858083.git.namcao@linutronix.de
Nam Cao [Thu, 26 Jun 2025 14:47:52 +0000 (16:47 +0200)]
PCI: mobiveil: Switch to msi_create_parent_irq_domain()
Switch to msi_create_parent_irq_domain() from pci_msi_create_irq_domain()
which was using legacy MSI domain setup.
Signed-off-by: Nam Cao <namcao@linutronix.de>
[mani: reworded commit message] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: rebase on dev_fwnode() conversion, drop fwnode local var] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/af46c15c47a7716f7e0c50d0f7391509c95b49c2.1750858083.git.namcao@linutronix.de
PCI: controller: Use dev_fwnode() instead of of_fwnode_handle()
All irq_domain functions now accept fwnode instead of of_node. But many
PCI controllers still extract dev to of_node and then of_node to fwnode.
Instead, clean this up and simply use the dev_fwnode() helper to extract
fwnode directly from dev. Internally, it still does dev => of_node =>
fwnode steps, but it's now hidden from the users.
In the case of altera, this also removes an unused 'node' variable that is
only used when CONFIG_OF is enabled:
drivers/pci/controller/pcie-altera.c: In function 'altera_pcie_init_irq_domain':
drivers/pci/controller/pcie-altera.c:855:29: error: unused variable 'node' [-Werror=unused-variable]
855 | struct device_node *node = dev->of_node;
Richard Zhu [Wed, 9 Jul 2025 03:37:22 +0000 (11:37 +0800)]
PCI: imx6: Delay link start until configfs 'start' written
According to Documentation/PCI/endpoint/pci-endpoint-cfs.rst, the Endpoint
controller (EPC) should only start the link when userspace writes '1' to
the '/sys/kernel/config/pci_ep/controllers/<EPC>/start' attribute, which
ultimately results in calling imx_pcie_start_link() via
pci_epc_start_store().
To align with the documented behavior, do not start the link automatically
when adding the EP controller.
Fixes: 75c2f26da03f ("PCI: imx6: Add i.MX PCIe EP mode support") Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
[mani: reworded commit subject and description] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20250709033722.2924372-3-hongxing.zhu@nxp.com
Richard Zhu [Wed, 9 Jul 2025 03:37:21 +0000 (11:37 +0800)]
PCI: imx6: Remove apps_reset toggling from imx_pcie_{assert/deassert}_core_reset
apps_reset corresponds to LTSSM_EN in i.MX7, i.MX8MQ, i.MX8MM and i.MX8MP
platforms. Since assertion/de-assertion of apps_reset is done in
imx_pcie_ltssm_enable() and imx_pcie_ltssm_disable(), remove it from
imx_pcie_assert_core_reset() and imx_pcie_deassert_core_reset().
This also fixes a failure in enumerating the PI7C9X2G608GP (hotplug) chip
reliably on i.MX8MM, as reported by Tim.
It should be noted that only i.MX7D, i.MX8MQ, i.MX8MM, and i.MX8MP
platforms have the apps_reset logic, so this change doesn't have any effect
on other platforms.
Fixes: ef61c7d8d032 ("PCI: imx6: Deassert apps_reset in imx_pcie_deassert_core_reset()") Reported-by: Tim Harvey <tharvey@gateworks.com> Closes: https://lore.kernel.org/all/CAJ+vNU3ohR2YKTwC4xoYrc1z-neDoH2TTZcMHDy+poj9=jSy+w@mail.gmail.com/ Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
[mani: reworded commit subject and description] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mp-venice-gw74xx (i.MX8MP + hotplug capable switch) Reviewed-by: Frank Li <Frank.Li@nxp.com> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20250709033722.2924372-2-hongxing.zhu@nxp.com
PCI: Support Immediate Readiness on devices without PM capabilities
Query support for Immediate Readiness irrespective of whether or not the
device supports PM capabilities, as nothing in the PCIe spec suggests that
Immediate Readiness is in any way dependent on PM functionality.
Fixes: d6112f8def51 ("PCI: Add support for Immediate Readiness") Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: David Matlack <dmatlack@google.com> Cc: Vipin Sharma <vipinsh@google.com> Cc: Aaron Lewis <aaronlewis@google.com> Link: https://patch.msgid.link/20250722155926.352248-1-seanjc@google.com
Another utterly pointless aspect of the xgene-msi driver is that
it is built around CPU hotplug. Which is quite amusing since this
is one of the few arm64 platforms that, by construction, cannot
do CPU hotplug in a supported way (no EL3, no PSCI, no luck).
Drop the CPU hotplug nonsense and just setup the IRQs and handlers
in a less overdesigned way, grouping things more logically in the
process.
Marc Zyngier [Tue, 8 Jul 2025 17:34:02 +0000 (18:34 +0100)]
PCI: xgene-msi: Probe as a standard platform driver
Now that we have made the dependency between the PCI driver and
the MSI driver explicit, there is no need to use subsys_initcall()
as a probing hook, and we can rely on builtin_platform_driver()
instead.
Marc Zyngier [Tue, 8 Jul 2025 17:34:01 +0000 (18:34 +0100)]
PCI: xgene-msi: Resend an MSI racing with itself on a different CPU
Since changing the affinity of an MSI really is about changing
the target address and that it isn't possible to mask an individual
MSI, it is completely possible for an interrupt to race with itself,
usually resulting in a lost interrupt.
Paper over the design blunder by informing the core code of this
sad state of affairs.
Marc Zyngier [Tue, 8 Jul 2025 17:34:00 +0000 (18:34 +0100)]
PCI: xgene-msi: Sanitise MSI allocation and affinity setting
Plugging a device that doesn't use managed affinity on an XGene-1
machine results in messages such as:
genirq: irq_chip PCI-MSIX-0000:01:00.0 did not update eff. affinity mask of irq 39
As it turns out, the driver was never updated to populate the effective
affinity on irq_set_affinity() call, and the core code is prickly about
that.
But upon further investigation, it appears that the driver keeps repainting
the hwirq field of the irq_data structure as a way to track the affinity
of the MSI, something that is very much frowned upon as it breaks the
fundamentals of an IRQ domain (an array indexed by hwirq).
Fixing this results more or less in a rewrite of the driver:
- Define how a hwirq and a CPU affinity map onto the MSI termination
registers
- Allocate a single entry in the bitmap per MSI instead of *8*
- Correctly track CPU affinity
- Fix the documentation so that it actually means something (to me)
- Use standard bitmap iterators
- and plenty of other cleanups
With this, the driver behaves correctly on my vintage Mustang board.
Signed-off-by: Marc Zyngier <maz@kernel.org>
[lpieralisi: replaced open coded GENMASK(6, 4) with MSInRx_HWIRQ_MASK] Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20250708173404.1278635-10-maz@kernel.org
Marc Zyngier [Tue, 8 Jul 2025 17:33:59 +0000 (18:33 +0100)]
PCI: xgene-msi: Get rid of intermediate tracking structure
The xgene-msi driver uses an odd construct in the form of an
intermediate tracking structure, evidently designed to deal with
multiple instances of the MSI widget. However, the existing HW
only has one set, and it is obvious that there won't be new HW
coming down that particular line.
Simplify the driver by using a bit of pointer arithmetic instead,
directly tracking the interrupt and avoiding extra memory allocation.
Marc Zyngier [Tue, 8 Jul 2025 17:33:58 +0000 (18:33 +0100)]
PCI: xgene-msi: Use device-managed memory allocations
Since the MSI driver is probed as a platform device, there is no
reason to not use device-managed allocations. That's including
the top-level bookkeeping structure, which is better dynamically
allocated than being static.
Marc Zyngier [Tue, 8 Jul 2025 17:33:55 +0000 (18:33 +0100)]
PCI: xgene: Drop XGENE_PCIE_IP_VER_UNKN
XGENE_PCIE_IP_VER_UNKN is only refered to when probing for the
original XGene PCIe implementation, and get immediately overridden
if the device has the "apm,xgene-pcie" compatible string.
Given that the only way to get there is by finding this very string in
the DT, it is obvious that we will always overwrite the version with
XGENE_PCIE_IP_VER_1.
Marc Zyngier [Tue, 8 Jul 2025 17:33:53 +0000 (18:33 +0100)]
PCI: xgene: Defer probing if the MSI widget driver hasn't probed yet
As a preparatory work to make the XGene MSI driver probe less of
a sorry hack, make the PCI driver check for the availability of
the MSI parent domain, and defer the probing otherwise.
Marc Zyngier [Tue, 8 Jul 2025 17:33:52 +0000 (18:33 +0100)]
genirq: Teach handle_simple_irq() to resend an in-progress interrupt
It appears that the defect outlined in 9c15eeb5362c4 ("genirq: Allow
fasteoi handler to resend interrupts on concurrent handling") also
affects some other less stellar MSI controllers, this time using
the handle_simple_irq() flow.
Teach this flow about irqd_needs_resend_when_in_progress(). Given
the invasive nature of this workaround, only this flow is updated.
Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20250708173404.1278635-2-maz@kernel.org
Frank Li [Thu, 10 Jul 2025 19:13:48 +0000 (15:13 -0400)]
PCI: imx6: Add LUT configuration for MSI/IOMMU in Endpoint mode
Add LUT entry for MSI/IOMMU in Endpoint mode by calling
imx_pcie_add_lut_by_rid() helper function. Since only one physical function
is supported in the Endpoint mode for now, '0' is passed as the Device ID.
This sets up a single LUT entry required for MSI/IOMMU.
The Endpoint function can operate without LUT configuration if neither
IOMMU nor MSI is used by the platform. This LUT configuration is used for
the EP doorbell feature by allowing the Root Complex to trigger the
doorbell on the Endpoint with the help of the Endpoint MSI controller.
Frank Li [Thu, 10 Jul 2025 19:13:47 +0000 (15:13 -0400)]
PCI: imx6: Add helper function imx_pcie_add_lut_by_rid()
Add helper function imx_pcie_add_lut_by_rid(), which will be used by the
upcoming LUT configuration for MSI/IOMMU in the Endpoint mode. No
functional change.
PCI: endpoint: pci-epf-vntb: Fix the incorrect usage of __iomem attribute
__iomem attribute is supposed to be used only with variables holding the
MMIO pointer. But here, 'mw_addr' variable is just holding a 'void *'
returned by pci_epf_alloc_space(). So annotating it with __iomem is clearly
wrong. Hence, drop the attribute.
This also fixes the below sparse warning:
drivers/pci/endpoint/functions/pci-epf-vntb.c:524:17: warning: incorrect type in assignment (different address spaces)
drivers/pci/endpoint/functions/pci-epf-vntb.c:524:17: expected void [noderef] __iomem *mw_addr
drivers/pci/endpoint/functions/pci-epf-vntb.c:524:17: got void *
drivers/pci/endpoint/functions/pci-epf-vntb.c:530:21: warning: incorrect type in assignment (different address spaces)
drivers/pci/endpoint/functions/pci-epf-vntb.c:530:21: expected unsigned int [usertype] *epf_db
drivers/pci/endpoint/functions/pci-epf-vntb.c:530:21: got void [noderef] __iomem *mw_addr
drivers/pci/endpoint/functions/pci-epf-vntb.c:542:38: warning: incorrect type in argument 2 (different address spaces)
drivers/pci/endpoint/functions/pci-epf-vntb.c:542:38: expected void *addr
drivers/pci/endpoint/functions/pci-epf-vntb.c:542:38: got void [noderef] __iomem *mw_addr
Robin Murphy [Fri, 25 Apr 2025 13:39:29 +0000 (14:39 +0100)]
PCI: Fix driver_managed_dma check
Since it's not currently safe to take device_lock() in the IOMMU probe
path, that can race against really_probe() setting dev->driver before
attempting to bind. The race itself isn't so bad, since we're only
concerned with dereferencing dev->driver itself anyway, but sadly my
attempt to implement the check with minimal churn leads to a kind of
Time-of-Check to Time-of-Use (TOCTOU) issue, where dev->driver becomes
valid after to_pci_driver(NULL) is already computed, and thus the check
fails to work as intended.
Will and I both hit this with the platform bus, but the pattern here is
the same, so fix it for correctness too.
Fixes: bcb81ac6ae3c ("iommu: Get DT/ACPI parsing into the proper probe path") Reported-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Will McVicker <willmcvicker@google.com> Link: https://patch.msgid.link/20250425133929.646493-4-robin.murphy@arm.com
PCI: qcom: Add support for parsing the new Root Port binding
The DT binding has moved the PHY, PERST# properties to Root Port node from
the Host Bridge node. So add support for parsing the new binding. The new
binding uses 'reset-gpios' property for PERST#, hence parse the same
property in the driver instead of the legacy 'perst-gpios'.
To maintain DT backwards compatibility, fallback to the legacy method of
parsing the host bridge node if the properties are not present in the Root
Port node.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
[mani: refactored the root port parsing code, fixed a bug & commit message rewording] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20250702-perst-v5-2-920b3d1f6ee1@qti.qualcomm.com
dt-bindings: PCI: qcom: Move PHY & reset GPIO to Root Port node
Move the phys, phy-names, reset-gpios properties to the PCIe Root Port node
from Host Bridge node, as agreed upon here [1].
Update the qcom,pcie-common.yaml to include the 'phys' property in the Root
Port node. 'phy-names' property is not needed in Root Port since each Root
Port supports only one PHY. Also, there is already 'reset-gpios' property
defined for PERST# in pci-bus-common.yaml, so use that property instead of
'perst-gpios'.
For backward compatibility, do not remove any existing properties in the
bridge node, but mark them as 'deprecated' instead.
Mayank Rana [Mon, 16 Jun 2025 22:42:59 +0000 (15:42 -0700)]
PCI: qcom: Add support for Qualcomm SA8255p based PCIe Root Complex
Add functionality to enable resource management (like clocks, regulators,
PHY) through firmware and enumerate ECAM compliant Root Complex on SA8255p
SoC, where the PCIe Root Complex is firmware managed and configured into
ECAM compliant mode.
Signed-off-by: Mayank Rana <mayank.rana@oss.qualcomm.com>
[mani: minor code cleanups and commit message rewording] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
[bhelgaas: add "ECAM" in comment] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20250616224259.3549811-5-mayank.rana@oss.qualcomm.com
Document the required configuration to enable the PCIe Root Complex on
SA8255p, which is managed by firmware using power-domain based handling
and configured as ECAM compliant.
Richard Zhu [Tue, 8 Jul 2025 09:10:02 +0000 (17:10 +0800)]
PCI: imx6: Add IMX8MQ_EP third 64-bit BAR in epc_features
IMX8MQ_EP has three 64-bit BAR0/2/4 capable and programmable BARs. For
IMX8MQ_EP, use imx8q_pcie_epc_features (64-bit BARs 0, 2, 4) instead
of imx8m_pcie_epc_features (64-bit BARs 0, 2).
Fixes: 75c2f26da03f ("PCI: imx6: Add i.MX PCIe EP mode support") Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
[bhelgaas: add details in subject] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20250708091003.2582846-2-hongxing.zhu@nxp.com
PCI: Allow built-in drivers to use async initial probing
The PCI core has historically not allowed built-in drivers to opt in to
async initial probing: Drivers may set "PROBE_PREFER_ASYNCHRONOUS", but
initial probing always happens synchronously. That's because the PCI core
uses device_attach() instead of device_initial_probe().
Should a driver return -EPROBE_DEFER on initial probe, reprobing later on
does honor the PROBE_PREFER_ASYNCHRONOUS setting. Modular drivers are
also allowed to probe asynchronously, which is inconsistent.
The choice of device_attach() is likely not deliberate: It was introduced
in 2013 with commit 58d9a38f6fac ("PCI: Skip attaching driver in
device_add()"), but asynchronous probing was added two years later with
commit 765230b5f084 ("driver-core: add asynchronous probing support for
drivers").
According to the kernel-doc of "enum probe_type", "the end goal is to
switch the kernel to use asynchronous probing by default". To this end,
use device_initial_probe() to allow asynchronous initial probing. The
function returns void, making the return value check unnecessary.
Initial PCI probing often takes on the order of seconds even on laptops,
so this may speed up booting significantly.
A small number of PCI drivers already opt in to asynchronous probing.
Their maintainers (who are all cc'ed) should watch out for issues, now
that asynchronous probing is not just allowed for deferred and modular
probing, but also initial probing:
All other driver maintainers may test asynchronous probing by specifying
the command line parameter "driver_async_probe=drv_name1,drv_name2,...",
and on success setting "probe_type = PROBE_PREFER_ASYNCHRONOUS" in the
pci_driver struct.
Drivers could leverage the fact that the VF BAR MMIO reservation is created
for total number of VFs supported by the device by resizing the BAR to
larger size when smaller number of VFs is enabled.
Add pci_iov_vf_bar_set_size() to control the size and a
pci_iov_vf_bar_get_sizes() helper to get the VF BAR sizes that will allow
up to num_vfs to be successfully enabled with the current underlying
reservation size.
PCI/IOV: Check that VF BAR fits within the reservation
When the resource representing a VF MMIO BAR reservation is created, its
size is always large enough to accommodate the BAR of all SR-IOV Virtual
Functions that can potentially be created (total VFs). If for whatever
reason it's not possible to accommodate all VFs, the resource is not
assigned and no VFs can be created.
An upcoming change will allow VF BAR size to be modified by drivers at a
later point in time, which means that the check for resource assignment is
no longer sufficient.
Add an additional check that verifies that the VF BAR for all enabled VFs
fits within the underlying reservation resource.
PCI/IOV: Allow IOV resources to be resized in pci_resize_resource()
Similar to regular resizable BARs, VF BARs can also be resized.
The capability layout is the same as PCI_EXT_CAP_ID_REBAR, which means we
can reuse most of the implementation, the only difference being resource
size calculation (which is multiplied by total VFs) and memory decoding
(which is controlled by a separate VF MSE field in SR-IOV cap).
Extend the pci_resize_resource() function to accept IOV resources.
projects / thirdparty / kernel / linux.git / log
