dwarf: Save bit stride information for array type entry [PR121964]
Lack of DW_AT_bit_stride in a DW_TAG_array_type entry causes GDB to infer
incorrect element size for vector types. The causes incorrect display of
SVE predicate variables as well as out of bounds memory access when reading
contents of SVE predicates from memory in GDB.
We also locate DIE referenced by DW_AT_type and set DW_AT_bit_size 1 in it.
PR debug/121964
gcc/
* dwarf2out.cc (gen_array_type_die): Add DW_AT_bit_stride attribute
for array types based on element type bit precision for integer and
boolean element types.
gcc/testsuite/
* g++.target/aarch64/dwarf-bit-stride-func.C: New test.
* g++.target/aarch64/dwarf-bit-stride-pragma.C: New test.
* g++.target/aarch64/dwarf-bit-stride-pragma-sme.C: New test.
* g++.target/aarch64/sve/dwarf-bit-stride.C: New test.
* gcc.target/aarch64/dwarf-bit-stride-func.c: New test.
* gcc.target/aarch64/dwarf-bit-stride-pragma.c: New test.
* gcc.target/aarch64/dwarf-bit-stride-pragma-sme.c: New test.
* gcc.target/aarch64/sve/dwarf-bit-stride.c: New test.
Paul Thomas [Mon, 24 Nov 2025 11:30:19 +0000 (11:30 +0000)]
Fortran: Failure with 1st PDT example in F2018 standard [PR122766]
2025-11-24 Paul Thomas <pault@gcc.gnu.org>
gcc/fortran
PR fortran/122766
* decl.cc (gfc_match_decl_type_spec): A pdt_type found while
parsing a contains section can only arise from the typespec of
a function declaration. This can be retained in the typespec.
Once we are parsing the function, the first reference to this
derived type will find that it has no symtree. Provide it with
one so that gfc_use_derived does not complain and, again,retain
it in the typespec.
gcc/testsuite
PR fortran/122766
* gfortran.dg/pdt_69.f03: New test.
Richard Biener [Mon, 24 Nov 2025 10:18:42 +0000 (11:18 +0100)]
Adjust gcc.dg/vect/bb-slp-41.c
We now perform SLP vectorization for the scalar epilog of a vector
loop where we now unroll said scalar epilog. The following adjusts
the testcase to look for SLP trying to vectorize a CTOR instead,
which I guessed from the topic of r10-4336-g818b3293f4545d which
added this testcase.
Eric Botcazou [Mon, 24 Nov 2025 09:36:35 +0000 (10:36 +0100)]
Fix wrong code for indexed component with very large index type
This fixes an old issue whereby we generate wrong code in Ada for an indexed
component in an array with a ludicrously large index type instead of raising
Storage_Error. We would need the counterpart of int_const_binop for unop in
the general case, but that's not worth the hassle and int_const_convert is
good enough.
gcc/
PR ada/33994
* fold-const.h (int_const_convert): New prototype.
* fold-const.cc (fold_convert_const_int_from_int): Rename to...
(int_const_convert): ...this, remove static keyword and add third
parameter OVERFLOWABLE.
(fold_convert_const): Call int_const_convert if ARG1 is an integer
constant.
gcc/ada/
PR ada/33994
* gcc-interface/utils.cc (convert) <INTEGER_TYPE>: Call
int_const_convert if the expression is an integer constant.
gcc/testsuite/
* gnat.dg/object_overflow6.adb: New test.
gcc: Set native_system_header_dir on aarch64-mingw
Provide a sensible default value for native_system_header_dir, namely
/mingw/include, on aarch64-mingw. This is in line with the expectations
for mingw file locations, and is already set on both x86- and
x86_64-mingw.
gcc/ChangeLog:
* config.gcc (aarch64-*-mingw*): Set native_system_header_dir.
hppa: Fix scaled and unscaled index support on targets with non-equivalent space registers
HP-UX targets have non-equivalent space registers. The base register
in most loads and stores selects the space register used to calculate
the global virtual address for the instruction.
Previously, the PA-RISC backend attempted to canonicalize the
register order in INDEX + BASE register addresses. This has always
been problematic as reload would sometimes lose the REG_POINTER
flag used to mark a base register. As a result, we allowed any
register order after reload and prayed the registers would be
in canonical order.
This broke with the new late_combine2 pass. It sometimes creates
new indexed instructions after reload. pa_legitimate_address_p
needs updating to ensure the base register is marked with the
REG_POINTER flag and the index register is not marked.
If scaled index instructions are created before reload, the LRA
pass will sometimes convert it an unscaled index instruction
plus reloads and drop the REG_POINTER flag that was in the base
register. Thus, we can't allow scaled and unscaled index loads
and stores until reload is completed.
2025-11-23 John David Anglin <danglin@gcc.gnu.org>
gcc/ChangeLog:
* config/pa/pa.cc (pa_print_operand): Use REG_POINTER
flag to select base and index registers on targets with
non-equivalent space registers.
(pa_legitimate_address_p): Don't allow scaled and unscaled
indexed addresses until reload is complete. Allow any
register order in unscaled addresses as long as the
REG_POINTER flag is correctly set/unset in the base/index
registers.
* config/pa/predicates.md (mem_operand): Remove code to
delay creating move insns with unscaled indexed addresses
until CSE is not expected.
(move_src_operand): Likewise.
Pan Li [Sat, 15 Nov 2025 03:22:23 +0000 (11:22 +0800)]
Match: Remove unnecessary convert for unsigned SAT_MUL
After we convert from bit_op outer into its captures, some
outer convert of unsigned SAT_MUL form 6 is unnecessary any
more. Thus, remove it. Meanwhile, add c after outer bit_ior
to make the test happy.
gcc/ChangeLog:
* match.pd: Remove unnecessary outer convert and add
c for the outer bit_ior.
Pan Li [Sat, 15 Nov 2025 03:21:37 +0000 (11:21 +0800)]
Test: Add test case for bit_op convert folding
Add test cases of all possible types of bit_op convert folding.
To check there is no tree dump like below:
_5 = (uint8_t) _2;
return _5;
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/bit_op_cvt.1.c: New test.
* gcc.dg/tree-ssa/bit_op_cvt.2.c: New test.
* gcc.dg/tree-ssa/bit_op_cvt.3.c: New test.
* gcc.dg/tree-ssa/bit_op_cvt.4.c: New test.
* gcc.dg/tree-ssa/bit_op_cvt.5.c: New test.
* gcc.dg/tree-ssa/bit_op_cvt.6.c: New test.
* gcc.dg/tree-ssa/bit_op_cvt.h: New test.
Pan Li [Sat, 15 Nov 2025 03:20:37 +0000 (11:20 +0800)]
Match: Simplify (T1)(a bit_op (T2)b) to (T1)a bit_op (T1)b
During the match pattern of SAT_U_MUL form 7, we found there is
a pattern like below:
(nop_convert)(a bit_op (convert b))
which result in the pattern match of SAT_U_MUL complicated and
unintuitive. According to the suggestion of Richard, we would
like to simply it to blew:
(convert a) bit_op (convert b)
which is more friendly for reading and bit_op. There are three
bit_op here, aka bit_ior, bit_and and bit_xor.
gcc/ChangeLog:
* match.pd: Add simplfy to fold outer convert of bit_op
to inner captures.
[tree-optimization] Allow LICM to hoist loads in "self write" patterns
This patch enables Loop Invariant Code Motion (LICM) to hoist loads that
alias with stores when SSA def-use analysis proves the stored value comes
from the loaded value.
The pattern a[i] = a[0] is common in TSVC benchmarks (s293):
for (int i = 0; i < N; i++)
a[i] = a[0];
Previously, GCC conservatively rejected hoisting a[0] due to potential
aliasing when i==0. However, this is a "self write" - even when aliasing
occurs, we're writing back the same value, making hoisting safe.
The optimization checks that:
1. One reference is a load, the other is a store
2. The stored SSA value equals the loaded SSA value
3. Only simple cases with single accesses per reference
This enables vectorization of these patterns by allowing the vectorizer
to see the hoisted loop-invariant value.
With the patch, the loop now vectorizes and generates:
Sandra Loosemore [Sun, 23 Nov 2025 03:29:34 +0000 (03:29 +0000)]
OpenMP: Fix "begin declare variant" test failure with -m32
As reported by Haochen Jiang, this recently-added test case was
failing on x86_64 with -m32; the target hook for matching the "arch"
selector won't match "x86_64" in that case, even if gcc was configured
for that target. It does match plain "x86" for both 64 and 32 bit targets,
so I've switched the testcase to use that instead.
Committed as obvious (at least in retrospect).
gcc/testsuite/ChangeLog
* c-c++-common/gomp/delim-declare-variant-6.c (f3): Use "x86"
instead of "x86_64" in the arch selector, to match both 64- and
32-bit targets.
I had mistakenly been checking the importedness of the originating
module decl, but this is wrong: really we want to check if the specific
decl we're currently instantating came from another module, so just
check DECL_MODULE_IMPORT_P on this directly.
Also updated slightly since there are cases where we do emit TU-local
function or variable templates, albeit unlikely to come up frequently.
PR c++/122636
gcc/cp/ChangeLog:
* module.cc (instantiating_tu_local_entity): Don't check
importingness of originating module decl; also check templates.
gcc/testsuite/ChangeLog:
* g++.dg/modules/internal-19_a.C: New test.
* g++.dg/modules/internal-19_b.C: New test.
Signed-off-by: Nathaniel Shead <nathanieloshead@gmail.com> Reviewed-by: Jason Merrill <jason@redhat.com>
Nathaniel Shead [Sat, 22 Nov 2025 11:11:35 +0000 (22:11 +1100)]
c++: Correct behaviour of layout_compatible_type for aligned types
The standard does not require two types to have the same alignment (and
hence size) to be considered layout-compatible. The same applies to
members of unions.
gcc/cp/ChangeLog:
* typeck.cc (layout_compatible_type_p): Do not check TYPE_SIZE.
Jeff Law [Sat, 22 Nov 2025 18:33:57 +0000 (11:33 -0700)]
[PR 122701] Emit fresh reg->reg copy rather than modifying existing insnO
I took an ill-advised short-cut with the recent ext-dce improvement to detect
certain shift pairs as sign/zero extensions. Specifically I was adjusting the
SET_SRC of an object.
Often we can get away with that, but as this case shows it's simply not safe
for RTL. The core issue is the right shift we're modifying into a simple
reg->reg move may have things like CLOBBERs outside the set resulting in
Even that is often OK as targets which have these kinds of clobbers often need them on their basic moves because those moves often set condition codes. But that's not true for GCN.
On GCN that transformation leads to an unrecognizable insn as seen in the pr.
The fix is pretty simple. Just emit a new move and delete the shift. Of
course we have to be prepared to handle multiple insns once we use
emit_move_insn, but that's not too bad.
PR rtl-optimization/122701
gcc/
* ext-dce.cc (ext_dce_try_optimize_rshift): Emit a fresh reg->reg
copy rather than modifying the existing right shift.
gcc/testsuite/
* gcc.dg/torture/pr122701.c: New test.
Sandra Loosemore [Thu, 20 Nov 2025 21:45:09 +0000 (21:45 +0000)]
OpenMP: C++ front end support for "begin declare variant"
This patch implements C++ support for the "begin declare variant"
construct. The OpenMP specification is hazy on interaction of this
feature with C++ language features. Variant functions in classes are
supported but must be defined as members in the class definition,
using an unqualified name for the base function which also must be
present in that class. Similarly variant functions in a namespace can
only be defined in that namespace using an unqualified name for a base
function already declared in that namespace. Variants for template
functions or inside template classes seem to (mostly) work.
Sandra Loosemore [Thu, 20 Nov 2025 21:45:08 +0000 (21:45 +0000)]
OpenMP: Add flag for code elision to omp_context_selector_matches.
The "begin declare variant" has different rules for determining
whether a context selector cannot match for purposes of code elision
than we normally use; it excludes the case of a constant false
"condition" selector for the "user" set.
gcc/ChangeLog
* omp-general.cc (omp_context_selector_matches): Add an optional
bool argument for the code elision case.
* omp-general.h (omp_context_selector_matches): Likewise.
Sandra Loosemore [Thu, 20 Nov 2025 21:45:08 +0000 (21:45 +0000)]
OpenMP: Support functions for nested "begin declare variant"
This patch adds functions for variant name mangling and context selector
merging that are shared by the C and C++ front ends.
The OpenMP specification says that name mangling is supposed to encode
the context selector for the variant, but also provides for no way to
reference these functions directly by name or from a different
compilation unit. It also gives no guidance on how dynamic selectors
might be encoded across compilation units.
The GCC implementation of this feature instead treats variant
functions as if they have no linkage and uses a simple counter to
generate names. The exception is variants declared in a module interface,
which are given module linkage.
Jakub Jelinek [Sat, 22 Nov 2025 11:39:09 +0000 (12:39 +0100)]
c++: Fix up [[maybe_unused]] handling on expansion stmts [PR122788]
This PR complains that [[maybe_unused]] attribute is ignored on
the range-for-declaration of expansion-statement.
We copy DECL_ATTRIBUTES and apply late attributes, but early attributes
don't have their handlers called again, so some extra flags need to be
copied as well.
This copies TREE_USED and DECL_READ_P flags.
2025-11-22 Jakub Jelinek <jakub@redhat.com>
PR c++/122788
* pt.cc (finish_expansion_stmt): Or in TREE_USED and DECL_READ_P
flags from range_decl to decl or from corresponding structured binding
to this_decl.
Jakub Jelinek [Sat, 22 Nov 2025 11:24:35 +0000 (12:24 +0100)]
c++: Readd type checks for cp_fold -ffold-simple-inlines foldings [PR122185]
In GCC15, cp_fold -ffold-simple-inlines code contained
if (INDIRECT_TYPE_P (TREE_TYPE (x))
&& INDIRECT_TYPE_P (TREE_TYPE (r)))
check around the optimization, but as std::to_underlying has been
added to the set, it got removed.
Now, the check isn't needed when using correct libstdc++-v3 headers,
because the function template types ensure the converted types are sane
(so for most of them both are some kind of REFERENCE_TYPEs, for addressof
one REFERENCE_TYPE and one POINTER_TYPE, for to_underlying one ENUMERAL_TYPE
and one INTEGRAL_TYPE_P).
But when some fuzzer or user attempts to implement one or more of those
std:: functions and does it wrong (sure, such code is invalid), we can ICE
because build_nop certainly doesn't handle all possible type conversions.
So, the following patch readds the INDIRECT_REF_P && INDIRECT_REF_P check
for everything but to_underlying, for which it checks ENUMERAL_TYPE to
INTEGRAL_TYPE_P. That way we don't ICE on bogus code.
Though, I wonder about 2 things, whether the CALL_EXPR_ARG in there
shouldn't be also guarded just in case somebody tries to compile
namespace std { int to_underlying (); }; int a = std::to_underlying ();
and also whether this to_underlying folding doesn't behave differently
from the libstdc++-v3 implementation if the enum is
enum A : bool { B, C };
I think -fno-fold-simple-inlines will compile it as != 0, while
the -ffold-simple-inlines code just as a cast. Sure, enum with underlying
bool can't contain enumerators with values other than 0 and 1, but it is
still 8-bit at least and so what happens with other values?
2025-11-22 Jakub Jelinek <jakub@redhat.com>
PR c++/122185
* cp-gimplify.cc (cp_fold) <case CALL_EXPR>: For -ffold-simple-inlines
restore check that both types are INDIRECT_TYPE_P, except for
"to_underlying" check that r has ENUMERAL_TYPE and x has
INTEGRAL_TYPE_P.
Deng Jianbo [Fri, 14 Nov 2025 02:22:10 +0000 (10:22 +0800)]
LoongArch: Optimize statement to use bstrins.{w|d}
For statement (a << imm1) | (b & imm2), in case the imm2 equals to
(1 << imm1) - 1, it can be optimized to use bstrins.{w|d} instruction.
gcc/ChangeLog:
* config/loongarch/loongarch.md
(*bstrins_w_for_ior_ashift_and_extend): New template.
(*bstrins_d_for_ior_ashift_and): New template.
* config/loongarch/predicates.md (const_uimm63_operand): New
predicate.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/bstrins-5.c: New test.
* gcc.target/loongarch/bstrins-6.c: New test.
zhaozhou [Fri, 14 Nov 2025 03:18:46 +0000 (11:18 +0800)]
LoongArch: Optimize V4SImode vec_construct for load index length of two.
Under the V4SImode, the vec_construct with the load index {0, 1, 0, 1}
use vldrepl.d, the vec_construct with the load index {0, 1, 0, 0} use
vldrepl.d and vshuf4i, reduced the usage of scalar load and vinsgr2vr.
Kees Cook [Fri, 21 Nov 2025 18:24:34 +0000 (10:24 -0800)]
aarch64: Extract aarch64_indirect_branch_asm for sibcall codegen
Extract indirect branch assembly generation into a new function
aarch64_indirect_branch_asm, paralleling the existing
aarch64_indirect_call_asm function. Replace the open-coded versions in
the sibcall patterns (*sibcall_insn and *sibcall_value_insn) so there
is a common helper for indirect branches where things like SLS mitigation
need to be handled.
gcc/ChangeLog:
* config/aarch64/aarch64-protos.h (aarch64_indirect_branch_asm):
Declare.
* config/aarch64/aarch64.cc (aarch64_indirect_branch_asm): New
function to generate indirect branch with SLS barrier.
* config/aarch64/aarch64.md (*sibcall_insn): Use
aarch64_indirect_branch_asm.
(*sibcall_value_insn): Likewise.
Daniele Sahebi [Wed, 19 Nov 2025 16:03:05 +0000 (17:03 +0100)]
c++: fix ICE with consteval functions in template decls [PR122658]
Currently, build_over_call calls build_cplus_new in template decls, generating
a TARGET_EXPR that it then passes to fold_non_dependent_expr, which ends up
calling tsubst_expr, and since tsubst_expr doesn't handle TARGET_EXPRs, it ICEs.
Since there is no way for this code path to be executed without causing an
ICE, I believe it can be removed.
PR c++/122658
gcc/cp/ChangeLog:
* call.cc (build_over_call): Don't call build_cplus_new in
template declarations.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/consteval42.C: New test.
Co-authored-by: Jakub Jelinek <jakub@redhat.com> Signed-off-by: Daniele Sahebi <daniele@mkryss.me> Reviewed-by: Marek Polacek <polacek@redhat.com> Reviewed-by: Patrick Palka <ppalka@redhat.com>
[PR118358, LRA]: Decrease pressure after issuing input reload insns
LRA can generate sequence of reload insns for one input operand using
intermediate pseudos. Register pressure when reload insn for another
input operand is placed before the sequence is more than when the
reload insn is placed after the sequence. The problem report reveals
a case when several such sequences increase the pressure for input
reload insns beyond available registers and as a consequence this
results in LRA cycling.
gcc/ChangeLog:
PR target/118358
* lra-constraints.cc (curr_insn_transform): Move insn reloading
constant into a register right before insn using it.
Jonathan Wakely [Wed, 19 Nov 2025 19:04:05 +0000 (19:04 +0000)]
libstdc++: Implement LWG 4406 and LWG 3424 for std::optional and std::expected
This adjusts the return statements of optional::value_or and
expected::value_or to not perform explicit conversions, so that the
actual conversion performed matches the requirements expressed in the
Mandates: elements (LWG 4406).
Also adjust the return types to remove cv-qualifiers (LWG 3424).
libstdc++-v3/ChangeLog:
* include/std/expected (expected::value_or): Use remove_cv_t for
the return type. Do not use static_cast for return statement.
Adjust static_assert conditions to match return statements.
* include/std/optional (optional::value_or): Likewise.
(optional<T&>::value_or): Likewise.
Reviewed-by: Tomasz Kamiński <tkaminsk@redhat.com>
Yuao Ma [Sun, 2 Nov 2025 07:39:38 +0000 (15:39 +0800)]
libstdc++: Implement P3223R2 Making std::istream::ignore less surprising
libstdc++-v3/ChangeLog:
* include/std/istream (ignore): Add an overload for char.
* testsuite/27_io/basic_istream/ignore/char/93672.cc: Adjust
expected behaviour for C++26 mode.
* testsuite/27_io/basic_istream/ignore/char/4.cc: New test.
Co-authored-by: Jonathan Wakely <jwakely@redhat.com>
Jonathan Wakely [Fri, 21 Nov 2025 14:33:29 +0000 (14:33 +0000)]
libstdc++: Update some old docs about predefined feature macros
libstdc++-v3/ChangeLog:
* doc/xml/faq.xml: Refresh information on _GNU_SOURCE and
_XOPEN_SOURCE being predefined.
* doc/xml/manual/internals.xml: Remove outdated paragraph about
_POSIX_SOURCE in libstdc++ source files.
* doc/html/*: Regenerate.
Jakub Jelinek [Fri, 21 Nov 2025 15:25:58 +0000 (16:25 +0100)]
libcody: Make it buildable by C++11 to C++26
The following builds with -std=c++11 and c++14 and c++17 and c++20 and c++23
and c++26.
I see the u8 string literals are mixed e.g. with strerror, so in
-fexec-charset=IBM1047 there will still be garbage, so am not 100% sure if
the u8 literals everywhere are worth it either.
2025-11-21 Jakub Jelinek <jakub@redhat.com>
* cody.hh (S2C): For __cpp_char8_t >= 201811 use char8_t instead of
char in argument type.
(MessageBuffer::Space): Revert 2025-11-15 change.
(MessageBuffer::Append): For __cpp_char8_t >= 201811 add overload
with char8_t const * type of first argument.
(Packet::Packet): Similarly for first argument.
* client.cc (CommunicationError, Client::ProcessResponse,
Client::Connect, ConnectResponse, PathnameResponse, OKResponse,
IncludeTranslateResponse): Cast u8 string literals to (const char *)
where needed.
* server.cc (Server::ProcessRequests, ConnectRequest): Likewise.
Richard Biener [Fri, 21 Nov 2025 11:14:46 +0000 (12:14 +0100)]
Fix OMP SIMD clone mask register and query
The following removes the confusion around num_mask_args that was
added to properly "guess" the number of mask elements in a AVX512
mask that's just represented as int. The actual mistake lies in
the mixup of 'ncopies' which is used to track the number of
OMP SIMD calls to be emitted rather than the number of input
vectors. So this reverts the earlier r16-5374-g5c2fdfc24e343c,
uses the proper 'ncopies' for loop mask record/query and adjusts
the guessing of the SIMD arg mask elements.
PR tree-optimization/122762
PR tree-optimization/122736
PR tree-optimization/122790
* cgraph.h (cgraph_simd_clone_arg::linear_step): Document
use for SIMD_CLONE_ARG_TYPE_MASK.
* omp-simd-clone.cc (simd_clone_adjust_argument_types):
Record the number of mask arguments in linear_step if
mask_mode is not VOIDmode.
* tree-vect-stmts.cc (vectorizable_simd_clone_call):
Remove num_mask_args computation, use a proper ncopies
to query/register loop masks, use linear_step for the
number of mask arguments when determining the number of
mask elements in a mask argument.
Richard Biener [Fri, 21 Nov 2025 09:32:12 +0000 (10:32 +0100)]
tree-optimization/122778 - missed loop masking in OMP SIMD call handling
For AVX512 style masking we fail to apply loop masking to a conditional
OMP SIMD call.
PR tree-optimization/122778
* tree-vect-stmts.cc (vectorizable_simd_clone_call): Honor
a loop mask when passing the conditional mask with AVX512
style masking.
* gcc.dg/vect/vect-simd-clone-22.c: New testcase.
* gcc.dg/vect/vect-simd-clone-22a.c: Likewise.
Marek Polacek [Thu, 20 Nov 2025 18:57:43 +0000 (13:57 -0500)]
c++: make __reference_*_from_temporary honor access [PR120529]
This PR reports that our __reference_*_from_temporary ignore access
control. The reason is that we only check if implicit_conversion
works, but not if the conversion can actually be performed, via
convert_like.
Jakub Jelinek [Fri, 21 Nov 2025 13:17:01 +0000 (14:17 +0100)]
c++: Fix up build_data_member_initialization [PR121445]
The following testcase ICEs, because the constexpr ctor in C++14
or later doesn't contain any member initializers and so the
massage_constexpr_body -> build_constexpr_constructor_member_initializers
-> build_data_member_initialization member initialization discovery
looks at the ctor body instead. And while it has various
cases where it punts, including COMPONENT_REF with a VAR_DECL as first
operand on lhs of INIT_EXPR, here there is COMPONENT_REF with
several COMPONENT_REFs and VAR_DECL only inside the innermost.
The following patch makes sure we punt on those as well, instead of
blindly assuming it is anonymous union member initializer or asserting
it is a vtable store.
An alternative to this would be some flag on the INIT_EXPRs created
by perform_member_init and let build_data_member_initialization inspect
only INIT_EXPRs with that flag set.
2025-11-21 Jakub Jelinek <jakub@redhat.com>
PR c++/121445
* constexpr.cc (build_data_member_initialization): Just return
false if member is COMPONENT_REF of COMPONENT_REF with
VAR_P get_base_address.
PR target/122275
* config/i386/32/dfp-machine.h (DFP_GET_ROUNDMODE): Change `_frnd_orig` to
`unsigned short` for x87 control word.
(DFP_SET_ROUNDMODE): Manipulate the x87 control word as `unsigned short`,
and manipulate the MXCSR as `unsigned int`.
As mentioned in the PR, the COND_SH{L,R} internal fns are expanded without
fallback, their expansion must succeed, and furthermore they don't
differentiate between scalar and vector shift counts, so again both have
to be supported. That is the case of the {ashl,lshr,ashr}v*[hsd]i
patterns which use nonimmediate_or_const_vec_dup_operand predicate for
the shift count, so if the argument isn't const vec dup, it can be always
legitimized by loading into a vector register.
This is not the case of the QImode element conditional vector shifts,
there is no fallback for those and we emit individual element shifts
in that case when not conditional and shift count is not a constant.
So, I'm afraid we can't announce such an expander because then the
vectorizer etc. count with it being fully available.
As I've tried to show in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122598#c9
even without this pattern we can sometimes emit
vgf2p8affineqb $0, .LC0(%rip), %ymm0, %ymm0{%k1}
etc. instructions.
In the testcases, the kernels scheduled on queues 11, 12, 13, 14 have
data dependencies on, respectively, 'b', 'c', 'd', and 'e', as they
write to them.
However, they also have a data dependency on 'a' and 'N', as they read
those.
Previously, the testcases exited 'a' on queue 10 and 'N' on queue 15,
meaning that it was possible for the aforementioned kernels to execute
and to have 'a' and 'N' pulled under their feet.
This patch adds waits for each of the kernels onto queue 10 before
freeing 'a', guaranteeing that 'a' outlives the kernels, and the same on
'N'.
libgomp/ChangeLog:
* testsuite/libgomp.oacc-c-c++-common/data-2-lib.c (explanatory
header): Fix typo.
(main): Insert waits on kernels reading 'a' into queue 10 before
exiting 'a', and waits on kernels reading 'N' into queue 15
before exiting 'N'.
* testsuite/libgomp.oacc-c-c++-common/data-2.c: Ditto.
Jakub Jelinek [Fri, 21 Nov 2025 10:25:27 +0000 (11:25 +0100)]
gimplify: Fix ICE in collect_fallthrough_labels [PR122773]
In r16-4212 I had to tweak two spots in the gimplifier to ignore
gotos jumping to labels with the new VACUOUS_INIT_LABEL_P flag
(set by C++ FE when implementing goto/case interceptors with
extra .DEFERRED_INIT calls, so that jumps over vacuous initialization
are handled properly with the C++26 erroneous behavior requirements).
Except as the following testcase shows, the checks blindly assumed
that gimple_goto_dest operand is a LABEL_DECL, which is not the case
for computed jumps.
The following patch checks that gimple_goto_dest argument is a LABEL_DECL
before testing VACUOUS_INIT_LABEL_P flag on it.
2025-11-21 Jakub Jelinek <jakub@redhat.com>
PR middle-end/122773
* gimplify.cc (collect_fallthrough_labels): Check whether
gimple_goto_dest is a LABEL_DECL before testing VACUOUS_INIT_LABEL_P.
(expand_FALLTHROUGH_r): Likewise.
Loeka Rogge [Fri, 21 Nov 2025 09:45:01 +0000 (11:45 +0200)]
arc: emit clobber of CC for -mcpu=em x >> 31
Address PR target/120375
Devices without a barrel shifter end up using a sequence of
instructions. These can use the condition codes and/or loop count
register, so those need to be marked as 'clobbered'. These clobbers were
previously added only after split1, which is too late. This patch adds
these clobbers from the beginning, in the define_expand.
Previously, define_insn_and_split *<insn>si3_nobs would match any shift or
rotate instruction and would generate the necessary patterns to emulate a
barrel shifter, but it did not have any output assembly for itself.
In many cases this would create a loop with parallel clobbers. This pattern
is then matched by the <insn>si3_loop pattern.
Leading to an issue: the add.f instructions overwrites CC but beq expects
CC to contain an earlier value indicating mag == 0x7f800000.
Now, these are combined in define_insn_and_split <insn>si3_loop that is
explicitly emitted in the define_expand and already contains the clobbers.
This can then be split into another pattern or remain the loop pattern.
* config/arc/arc.md (*<insn>si3_nobs): merged with <insn>si3_loop.
(<insn>si3_loop): splits to relevant pattern or emits loop assembly.
(<insn>si3_cnt1_clobber): Removes clobber for shift or rotate by
const1.
gcc/testsuite/ChangeLog:
* gcc.target/arc/no-barrel-shifter.c: New test.
Co-authored-by: Keith Packard <keithp@keithp.com> Signed-off-by: Loeka Rogge <loeka@synopsys.com>
Bob Duff [Wed, 12 Nov 2025 19:53:17 +0000 (14:53 -0500)]
ada: Follow-on for duplicate formal iterator names
A previous fix titled "Avoid incorrect errors for duplicate formal
iterator names" caused regressions. This patch cleans it up.
In particular, the previous patch involved calling Preanalyze on
a block statement in order to get the scope created, and then
later calling Analyze on the same block statement. This caused
certain temps created inside the block statement to be
incorrectly duplicated. The fix here is to avoid setting
the Statements of the block until after it has been
preanalyzed.
gcc/ada/ChangeLog:
* exp_ch5.adb (Expand_Formal_Container_Loop):
Preanalyze block with empty statements; then set
the statements later before doing Analyze of the
block.
Eric Botcazou [Wed, 12 Nov 2025 15:13:03 +0000 (16:13 +0100)]
ada: Remove obsolete call to Establish_Transient_Scope
There is a preceding call to Establish_Transient_Scope in the procedure for
the cases where it is required, and we no longer build the aggregate on the
stack before copying it to the heap for an allocator.
gcc/ada/ChangeLog:
* exp_aggr.adb (Expand_Array_Aggregate): Remove obsolete call to
Establish_Transient_Scope for an allocator in a loop.
* exp_ch7.adb (Establish_Transient_Scope): Adjust description.
Piotr Trojanek [Wed, 5 Nov 2025 19:14:33 +0000 (20:14 +0100)]
ada: Sort cross-reference table using heap and not stack
Cross-references are used by GNATprove for code that is not in SPARK. They are
sorted using an auxiliary array. This array should be allocated on the heap and
not on stack, because it can be arbitrarily large, especially for
auto-generated code.
gcc/ada/ChangeLog:
* lib-xref.adb (Output_References): Put local array object on the heap.
Is_Redundant_Error_Message is used to filter diagnostic messages
that would appear on the same line to avoid the noise comming from
cascading error messages. However we still want to trigger an error
even if the line already had a warning or a non-serious error at the
same location so that we now that a fatal error has occured and the
compiler knows how to exit correctly in that scenario.
Eric Botcazou [Tue, 11 Nov 2025 20:12:54 +0000 (21:12 +0100)]
ada: Fix warnings given by static analyzer on Exp_Ch4
gcc/ada/ChangeLog:
* exp_ch4.adb (Expand_N_Op_Eq): Use No instead of not Present.
(Optimize_Length_Comparison): Initialize Is_Zero and Comp variables.
(Safe_In_Place_Array_Op): Do not use local variable to pass data to
nested function Is_Safe_Operand.
Javier Miranda [Tue, 11 Nov 2025 19:00:22 +0000 (19:00 +0000)]
ada: No extra formals on anonymous access types of C subprograms
Extra formals must not be added to anonymous access to subprogram
types defined in the profile of imported C subprograms.
gcc/ada/ChangeLog:
* sem_ch6.adb (Create_Extra_Formals): Do not add extra formals to
anonymous access to subprogram types defined in the profile of
subprograms that have foreign convention.
Eric Botcazou [Tue, 11 Nov 2025 09:35:54 +0000 (10:35 +0100)]
ada: Fix memory leak for unconstrained limited arrays in anonymous contexts
A change made a long time ago has introduced a leak of the secondary stack
at run time for unconstrained limited non-controlled arrays in anonymous
contexts, because of the lack of a transient scope in these contexts.
The large comment preceding the call to Establish_Transient_Scope in the
Resolve_Call procedure explains the strategy for build-in-place functions,
so the best course of action is probably to revert the commit and to fix
the original problem along the lines of the comment.
gcc/ada/ChangeLog:
* exp_ch3.adb (Expand_N_Object_Declaration): Delete ancient comment.
* exp_ch6.adb (Expand_Call_Helper): Do not establish a transient
scope for build-in-place functions in anonymous contexts here...
(Make_Build_In_Place_Call_In_Anonymous_Context): ...but here instead.
* sem_attr.adb (Resolve_Attribute) <Attribute_Range>: Remove obsolete
code dealing with transient scopes.
* sem_res.adb (Resolve_Actuals): Likewise.
(Resolve_Call): Adjust comment on the strategy for transient scopes.
Bob Duff [Mon, 10 Nov 2025 18:21:02 +0000 (13:21 -0500)]
ada: Avoid incorrect errors for duplicate formal iterator names
This patch fixes the following bug: If a type has an Iterable aspect
(as in the formal containers), and two or more cursor loops of the
form "for C in ..." occur in the same scope, and the cursor type has
discriminants without defaults, the compiler complains incorrectly
about duplicate names "Tc".
This is because the generated declaration of the C object was being
analyzed in the wrong scope. In the discriminated case, an internal
subtype name TcS is generated for each C. Errout "helpfully" removes "S"
in the error message, resulting in a complaint about "Tc". The fix is
to push the correct scope (that of the generated surrounding block
statement) when analyzing the declaration of C.
gcc/ada/ChangeLog:
* exp_ch5.adb (Expand_Formal_Container_Loop):
Analyze Init_Decl in the correct scope. Remove patch-up
code that was needed because we were using the wrong scope.
* exp_ch7.adb (Process_Object_Declaration):
Remove code to unique-ify the name of Master_Node_Id;
no longer needed because of change to exp_ch5.adb.
* sem_warn.adb (Check_References):
Suppress warnings during preanalysis, because we don't
have complete information yet; otherwise, the new Preanalyze
call in exp_ch5.adb generates bogus warnings.
Steve Baird [Mon, 10 Nov 2025 22:36:33 +0000 (14:36 -0800)]
ada: Improve Append performance for Ada.Containers.Bounded_Vectors
In (any instance of) Ada.Containers.Bounded_Vectors, for the procedure
overload of Append that takes parameters of types Vector and Element_Type,
improve performance in the case where either of the GNAT-defined checks
Container_Checks or Tampering_Check are suppressed.
gcc/ada/ChangeLog:
* libgnat/a-cobove.adb
(Append): Add an equivalent fast path for the case where tampering
checks are suppressed.
Eric Botcazou [Mon, 10 Nov 2025 11:44:47 +0000 (12:44 +0100)]
ada: Remove suspicious entries generated by -gnatR for generic formal types
Generic formal type parameters may have an unspecified layout when they are
processed for the -gnatR output, so it's better to skip them entirely.
The change also reverts an earlier change that would output "??" for an
unknown alignment on a type, which is inconsistent and undocumented.
gcc/ada/ChangeLog:
* repinfo.adb (List_Location): Do not output the final comma.
(List_Common_Type_Info): Adjust to above change. Do not output
"??" for an unknown alignment.
(List_Entities): Do not output generic types.
(List_Object_Info): Adjust to above change.
(List_Subprogram_Info): Likewise.
Viljar Indus [Thu, 16 Jan 2025 19:40:54 +0000 (21:40 +0200)]
ada: Ensure a limited type is marking the packing as used
gcc/ada/ChangeLog:
* sem_ch4.adb (Analyze_Call): ensure we generate a reference to the
non limited view of the return type to avoid scenarios where
the with-ed unit is not considered referenced.
Josef Melcr [Thu, 20 Nov 2025 22:57:57 +0000 (23:57 +0100)]
ipa: Remove LTO requirement for builtin callback carriers.
Due to the if statement in ipa_compute_jump_functions_for_bb, callback
edges were never constructed for builtin functions unless LTO was
enabled. This patch corrects this behavior, allowing GCC to optimize
callbacks more broadly. It also extends our testing capabilities.
gcc/ChangeLog:
* attr-callback.cc (callback_edge_callee_has_attr): New
function.
* attr-callback.h (callback_edge_callee_has_attr): New function
decl.
* ipa-prop.cc (ipa_compute_jump_functions_for_bb): Don't skip
callback carriers when calculating jump functions.
Josef Melcr [Thu, 20 Nov 2025 22:46:38 +0000 (23:46 +0100)]
ipa: Rewrite callback_edge_useful_p heuristic.
This function is used to determine whether a callback edge should be
kept or not. It was supposed to capture the idea that a callback edge
has been redirected at some point, however, it only considered
redirecting to some clone. However, an edge may not always be
redirected to a clone. For example, common function bodies produced by
icf are not clones. This version of this function should cover all
cases, at least for the time being.
gcc/ChangeLog:
PR ipa/122768
* attr-callback.cc (callback_edge_useful_p): Rewrite the
heuristic, now consider clones as well as icf bodies.
Deng Jianbo [Mon, 17 Nov 2025 07:28:19 +0000 (15:28 +0800)]
LoongArch: Add more numbers supported for {x}vldi
When the most significant bit of the 13 bit immediate value in LoongArch
{x}vldi isntruction is set 1, it can generate different numbers based on
the algorithm. This patch adds to support these numbers to be
generated by {x}vldi instruction.
gcc/ChangeLog:
* config/loongarch/constraints.md: Update constraint YI to support
more numbers.
* config/loongarch/loongarch-protos.h
(loongarch_const_vector_vrepli): Rename.
(loongarch_const_vector_vldi): Ditto.
* config/loongarch/loongarch.cc (VLDI_NEG_MASK): New macro.
(loongarch_parse_vldi_const): New function to check if numbers can
be generated by {x}vldi instruction.
(loongarch_const_vector_vrepli): Rename.
(loongarch_const_vector_vldi): Use above function.
(loongarch_const_insns): Call renamed function.
(loongarch_split_vector_move_p): Ditto.
(loongarch_output_move): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/lasx/lasx-builtin.c: Replace xvrepli
with xvldi.
* gcc.target/loongarch/vector/lasx/lasx-vec-init-2.c: Fix test.
* gcc.target/loongarch/vector/lsx/lsx-builtin.c: Repalce vrepli with
vldi.
* gcc.target/loongarch/vrepli.c: Ditto.
* gcc.target/loongarch/vector/lasx/lasx-xvldi-2.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vldi-2.c: New test.
zhaozhou [Fri, 14 Nov 2025 03:09:13 +0000 (11:09 +0800)]
LoongArch: Fix operands[2] predicate of lsx_vreplvei_mirror.
UNSPEC_LSX_VREPLVEI_MIRROR describes the mirroring operation that copies
the lower 64 bits of a 128-bit register to the upper 64 bits. So in any
mode, the value range of op2 can only be 0 or 1 for the vreplvei.d insn.
Andrew MacLeod [Thu, 20 Nov 2025 17:10:25 +0000 (12:10 -0500)]
Improve PHI analyzer performance
Only do iterative analysis if it might be worthwhile.
PR tree-optimization/121345
gcc/
* gimple-range-phi.cc (phi_group::calculate_using_modifier): Restore
performance loss by being more selective when iterating.
François Dumont [Thu, 20 Nov 2025 06:01:53 +0000 (07:01 +0100)]
libstdc++: [_GLIBCXX_DEBUG] Fix std::erase_if behavior for __gnu_debug::vector
When using directly __gnu_debug::vector the std::erase_if is called with a
reference to the std::vector base class and so is missing the invalidation
of the iterators implied by this operation.
To fix this provide a std::erase_if overload dedicated to __gnu_debug::vector.
Doing so we can cleanup the implementation dedicated to std::vector from any
_GLIBCXX_DEBUG consideration.
libstdc++-v3/ChangeLog:
* include/debug/vector (std::erase_if, std::erase): New overloads for
std::__debug::vector instances.
* include/std/vector (std::erase_if, std::erase): Make overloads specific
to normal std::vector implementation.
* testsuite/23_containers/vector/debug/erase.cc: New test case.
* testsuite/23_containers/vector/debug/invalidation/erase.cc: New test case.
Luc Grosheintz [Tue, 18 Nov 2025 14:24:52 +0000 (15:24 +0100)]
libstdc++: Prepare mdspan-related code for submdspan.
The changes needed for submdspan are:
* In submdspan related code the user-defined integer-like
types need to be copy- and move-constructable.
* The traits for writing tests that work with both left- and right,
possibly padded, layouts will also be useful for submdspan.
Therefore, this code is moved up and generalized.
* Move __offset further up in <mdspan> and fix some formatting
mistakes.
Kito Cheng [Wed, 5 Nov 2025 09:55:39 +0000 (17:55 +0800)]
RISC-V: Add RTL pass to combine cm.popret with zero return value
This patch implements a new RTL pass that combines "li a0, 0" and
"cm.popret" into a single "cm.popretz" instruction for the Zcmp
extension.
This optimization cannot be done during prologue/epilogue expansion
because it would cause shrink-wrapping to generate incorrect code as
documented in PR113715. The dedicated RTL pass runs after shrink-wrap
but before branch shortening, safely performing this combination.
Changes since v2:
- Apply Jeff's comment
- Use CONST0_RTX rather than const0_rtx, this make this pass able to
handle (const_double:SF 0.0) as well.
- Adding test case for float/double zero return value.
Changes since v1:
- Tweak the testcase.
gcc/ChangeLog:
* config/riscv/riscv-opt-popretz.cc: New file.
* config/riscv/riscv-passes.def: Insert pass_combine_popretz before
pass_shorten_branches.
* config/riscv/riscv-protos.h (make_pass_combine_popretz): New
declaration.
* config/riscv/t-riscv: Add riscv-opt-popretz.o build rule.
* config.gcc (riscv*): Add riscv-opt-popretz.o to extra_objs.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr113715.c: New test.
* gcc.target/riscv/rv32e_zcmp.c: Update expected output for
test_popretz.
* gcc.target/riscv/rv32i_zcmp.c: Likewise.
Pan Li [Thu, 20 Nov 2025 15:16:10 +0000 (08:16 -0700)]
[PATCH v1] RISC-V: Fix missed zero extend for unsigned scalar SAT_TRUNC [PR122692]
When the input of the scalar unsigned SAT_TRUNC is not Xmode,
the rtx need to zero extend to Xmode before the underlying
code gen. Most of other SAT_* code gen has leveraged
the API riscv_extend_to_xmode_reg but still have the ustrunc
missed. Then results in the failures mentioned in PR.
The below test suites are passed for this patch series.
* The rv64gcv fully regression test.
PR target/122692
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_ustrunc): Leverage
riscv_extend_to_xmode_reg to take care of src rtx.
gcc/testsuite/ChangeLog:
* g++.target/riscv/pr122692-run-1.C: New test.
* g++.target/riscv/pr122692-run-2.C: New test.
Tamar Christina [Thu, 20 Nov 2025 14:14:59 +0000 (14:14 +0000)]
middle-end: add target hook for isel
This adds a new target hook to gimple-sel to allow targets to
do target specific massaging of the gimple IL to prepare for
expand.
Tejas will be sending up part 2 of this soon to help convert
SVE packed boolean VEC_COND_EXPR into something that we can
handle more efficiently if expanded in a different order.
We also want to use this to e.g. for Adv. SIMD prefer avoiding
!= vector compare expressions because the ISA doesn't have
this instruction and so we expand to == + ~ but changing the
expression from a MIN to MAX only for VECTOR_BOOLEAN_TYPE_P
and flipping the operands we can expand more efficient.
These are the kind of things we want to use the hook for,
not generic changes that apply to all target.
gcc/ChangeLog:
* target.def (instruction_selection): New.
* doc/tm.texi.in: Document it.
* doc/tm.texi: Regenerate
* gimple-isel.cc (pass_gimple_isel::execute): Use it.
* targhooks.cc (default_instruction_selection): New.
* targhooks.h (default_instruction_selection): New.
Josef Melcr [Thu, 20 Nov 2025 12:32:45 +0000 (13:32 +0100)]
ipa: Add early return when the hashed edge is a callback-carrying edge.
The inclusion of this early return statement has been discussed before,
it was ultimately left out of the original patch, but it turns out to be
necessary.
When a callback edge is being created, it is first created by
symbol_table::create_edge, which is where it is added to the call site
hash. However, its callback flag is not set at that point, so the early
return for callback edges doesn't affect it. This causes the wrong edge
to be hashed, ultimately leading to segfaults and ICEs. This happens
many times in the testsuite, the one I noticed first was
libgomp.fortran/simd7.f90.
gcc/ChangeLog:
PR ipa/122358
* cgraph.cc (cgraph_add_edge_to_call_site_hash): Add an early
return when the hashed edge is a callback-carrying edge.
Arsen Arsenović [Thu, 20 Nov 2025 11:17:38 +0000 (12:17 +0100)]
gcc/doc: Fix usages of @itemize with named items in Regs and Memory
The old usage lead to makeinfo emitting text like "pseudo registers This
is the most common case. Most subregs have pseudo regs as their first
operand." when, clearly, "pseudo registers" was intended to be the name
of an item, and the rest of the paragraph a description. This is
because @itemize was used, which does not support "naming" items.
Now, the paragraph used as an example above looks like this:
pseudo registers
This is the most common case. Most ‘subreg’s have pseudo
‘reg’s as their first operand.
gcc/ChangeLog:
* doc/rtl.texi (Regs and Memory): Use @table instead of @itemize
for lists with named items.
Xinhui Yang [Tue, 11 Nov 2025 02:19:35 +0000 (10:19 +0800)]
gcc: check if target install name equals the full driver name
When a major version program suffix is specified, along with
--with-gcc-major-version-only, GCC tries to install $TRIPLE-gcc-tmp into
the destination BINDIR and link it to TRIPLE-gcc-SUFFIX. However this
executable is installed in the previous step, thus leaving the gcc-tmp
unmodified.
This is because when --program-suffix=15 (any major version) and
--with-gcc-major-version-only, $(version) will be the major version
number, thus making FULL_DRIVER_NAME and GCC_TARGET_INSTALL_NAME
identical to each other. We check if these two is identical and skip the
latter step if they are.
gcc/
PR bootstrap/105664
* Makefile.in (install-driver): detect name collision when
installing the driver program.
Rainer Orth [Thu, 20 Nov 2025 09:34:13 +0000 (10:34 +0100)]
Switch from USE_GAS/GLD to HAVE_GNU_AS/LD
We currently have two ways to distinguish GNU and non-GNU assemblers and
linkers:
* USE_GAS and USE_GLD, defined via gcc/config/usegas.h and usegld.h
which are included via config.gcc
* HAVE_GNU_AS and HAVE_GNU_LD, determined from gcc/configure.ac
This is confusing and leads to weird mistakes like combining both into
an undefined USE_GNU_LD. Since both are based on the same info ($gas
resp. $gnu_ld in gcc/configure.ac), it seems best to standardise on one
of them. Since the USE_* form is almost exclusively used in
Solaris-specific contexts, it's clearer to use the HAVE_GNU_* forms
instead.
This is what this patch does.
Most of the changes are either Solaris-specific or border on obvious.
Outside of Solaris code, there are only two cases:
* gcc/config/ia64/hpux.h has one macro guarded by !USE_GAS. This wasn't
defined before since the configuration for this target doesn't include
usegas.h. However, the code is still needed, so the HAVE_GNU_AS form is
now used.
* Uses of usegas.h in various powerpc*-*-* configurations in
gcc/config.gcc. Those make no difference since USE_GAS isn't used in any
of the affected files.
Bootstrapped without regressions on i386-pc-solaris2.11 and
sparc-sun-solaris2.11 (as/ld, gas/ld, and gas/gld configurations).
Rainer Orth [Thu, 20 Nov 2025 09:31:56 +0000 (10:31 +0100)]
driver: Simplify LINK_ARCH*_SPEC on Solaris
The various LINK_ARCH*_SPECs proved to be way more complex than
necessary:
* All uses of -YP,* can just go: they match the Solaris and GNU ld
defaults. In addition, the /usr/lib/libp entries are now superfluous:
they only contain compatiblity symlinks to their counterparts in
/usr/lib. The %R parts are superceded by the -z sysroot/--sysroot
options.
* With those options gone, LINK_ARCH{32,64}_SPEC_BASE are now identical
and can be merged.
* It's no longer necessary to use arch-specific versions of the Solaris
ld map.below4G linker map: with the new v2 mapfile syntax a single
file can be used for all of SPARC, and x86, 32 and 64-bit.
* Similarly, with LINK_ARCH{32,64,DEFAULT}_SPEC being identical, a
common LINK_ARCH_SPEC can be used with the single difference (erroring
out on the non-default multilib in non-multilib configurations,
e.g. -m64 for -m32-only configs) moved to a separate
LINK_ARCH_ERROR_SPEC.
Bootstrapped without regressions on {i386,amd64}-pc-solaris2.11,
sparc{,v9}-sun-solaris2.11 with as/ld, gas/ld, and gas/gld plus
--disable-multilib builds of those.
Xi Ruoyao [Sun, 16 Nov 2025 11:57:35 +0000 (19:57 +0800)]
LoongArch: NFC: Simplify logic of vec_perm{v32qi,v16hi}
De-duplicate the login by introducing gen_lasx_xvpermi_d (mode, ...)
with "@". Also remove the merge_two label: we should really not (ab)use
goto when avoiding it is trivial.
* config/loongarch/lasx.md (lasx_xvpermi_d): Add "@".
* config/loongarch/loongarch.cc (loongarch_expand_vec_perm_1):
Use gen_lasx_xvpermi_d instead of
gen_lasx_xvpermi_d_{v32qi,v16hi} to deduplicate the logic. Do
structrual programming instead of goto and label.
projects / thirdparty / gcc.git / log
