John Garry [Tue, 26 Jul 2022 10:02:44 +0000 (18:02 +0800)]
pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSM
All the many other configs depend on config PINCTRL_MSM, yet for config
PINCTRL_SM8450 we select config PINCTRL_MSM. Make config PINCTRL_SM8450
depend on PINCTRL_MSM to be consistent with the rest.
dt-bindings: pinctrl: mt8186: Add and use drive-strength-microamp
Commit e5fabbe43f3f ("pinctrl: mediatek: paris: Support generic
PIN_CONFIG_DRIVE_STRENGTH_UA") added support for using
drive-strength-microamp instead of mediatek,drive-strength-adv.
Similarly to the mt8192 and mt8195, there's no user of property
'mediatek,drive-strength-adv', hence removing it is safe.
Fixes: 338e953f1bd1 ("dt-bindings: pinctrl: mt8186: add pinctrl file and binding document") Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220725110702.11362-3-allen-kh.cheng@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The output is currently split across two lines making it more
difficult to parse unless the newlines are removed between pins
or it's read in by a parser like Libreoffice Calc or Google docs.
To make it easier to follow to the naked eye in a terminal window:
* drop the newline in the middle of pin definitions
* shorten all output using unicode characters
* align all pipe delimitters
* output the same phrase even for disabled functions
(but with a ∅ character)
pinctrl: amd: Fix newline declaration in debugfs output
Currently the debugfs output for pinctrl-amd puts the first line
combined with "GPIO bank". This makes it a little harder to process
as the file needs to be manually corrected for the mistake.
Rob Herring [Tue, 19 Jul 2022 21:49:54 +0000 (15:49 -0600)]
dt-bindings: pinctrl: st,stm32: Correct 'resets' property name
The correct property name for the reset binding is 'resets', not 'reset'.
Assuming actual users are correct, this error didn't show up due to
missing 'additionalProperties: false'. Fix the name and add missing
'additionalProperties'.
dt-bindings: pinctrl: mt8195: Use drive-strength-microamp in examples
The property mediatek,drive-strength-adv was deprecated: change the
example for i2c0-pins to use drive-strength-microamp.
Fixes: b6d9af2c6b69 ("dt-bindings: pinctrl: mt8195: Add and use drive-strength-microamp") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220715103029.204500-1-angelogioacchino.delregno@collabora.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Samuel Holland [Wed, 13 Jul 2022 02:52:33 +0000 (21:52 -0500)]
pinctrl: sunxi: Add driver for Allwinner D1
This SoC contains a pinctrl with a new register layout. Use the variant
parameter to set the right register offsets. This pinctrl also increases
the number of functions per pin from 8 to 16, taking advantage of all 4
bits in the mux config field (so far, only functions 0-8 and 14-15 are
used). This increases the maximum possible number of functions.
Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20220713025233.27248-7-samuel@sholland.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Samuel Holland [Wed, 13 Jul 2022 02:52:32 +0000 (21:52 -0500)]
pinctrl: sunxi: Make some layout parameters dynamic
Starting with the D1/D1s/T113 SoC, Allwinner changed the layout of the
pinctrl registers. This new layout widens the drive level field, which
affects the pull register offset and the overall bank size.
In order to support multiple register layouts, some of the layout
parameters need to be set based on the pinctrl variant. This requires
passing the pinctrl struct pointer to the register/offset calculation
functions.
Starting with the D1/D1s/T113 SoC, Allwinner changed the layout of the
pinctrl registers. This new layout widens the drive level field, which
affects the pull register offset and the overall bank size.
As a first step to support this, combine the register and offset
calculation functions, and refactor the math to depend on one constant
for field widths instead of three. This minimizes the code size impact
of making some of the factors dynamic.
While rewriting these functions, move them to the implementation file,
since that is the only file where they are used. And make the comment
more generic, without mentioning specific offsets/sizes.
The callers are updated to expect a shifted mask, and to use consistent
terminology (reg/shift/mask/val).
Samuel Holland [Wed, 13 Jul 2022 02:52:30 +0000 (21:52 -0500)]
pinctrl: sunxi: Support the 2.5V I/O bias mode
H616 and newer SoCs feature a 2.5V I/O bias mode in addition to the
1.8V and 3.3V modes. This mode is entered by selecting the 3.3V level
and disabling the "withstand function".
H616 supports this capability on its main PIO only. A100 supports this
capability on both its PIO and R-PIO.
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220713025233.27248-4-samuel@sholland.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
dt-bindings: pinctrl: mt8195: Add and use drive-strength-microamp
As was already done for MT8192 in commit b52e695324bb ("dt-bindings:
pinctrl: mt8192: Add drive-strength-microamp"), replace the custom
mediatek,drive-strength-adv property with the standardized pinconf
'drive-strength-microamp' one.
Similarly to the mt8192 counterpart, there's no user of property
'mediatek,drive-strength-adv', hence removing it is safe.
Fixes: 69c3d58dc187 ("dt-bindings: pinctrl: mt8195: Add mediatek,drive-strength-adv property") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220630131543.225554-1-angelogioacchino.delregno@collabora.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andre Przywara [Fri, 8 Jul 2022 10:52:32 +0000 (11:52 +0100)]
dt-bindings: pinctrl: sunxi: allow vcc-pi-supply
The Allwinner H616 SoC contains a VCC_PI pin, which supplies the voltage
for GPIO port I.
Extend the range of supply port names to include vcc-pi-supply to cover
that.
Andre Przywara [Fri, 8 Jul 2022 10:52:30 +0000 (11:52 +0100)]
dt-bindings: pinctrl: sunxi: Make interrupts optional
The R_PIO pinctrl device on the Allwinner H616 SoC does not have an
interrupt (it features only two pins).
However the binding requires at least naming one upstream interrupt,
plus the #interrupt-cells and interrupt-controller properties.
Drop the unconditional requirement for the interrupt properties, and
make them dependent on being not this particular pinctrl device.
Jianlong Huang [Mon, 27 Jun 2022 08:53:33 +0000 (10:53 +0200)]
pinctrl: starfive: Serialize adding groups and functions
The pinctrl dt_node_to_map method may be called in parallel which leads
us to call pinconf_generic_add_group and pinconf_generic_add_function
in parallel. This is not supported though and leads to errors, so add a
mutex to serialize these calls.
Merge tag 'intel-pinctrl-v5.20-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v5.20-1
* Update MAINTAINERS to set the Intel pin control status to Supported
* Switch Intel pin control drivers to use struct pingroup
The following is an automated git shortlog grouped by driver:
baytrail:
- Switch to to embedded struct pingroup
cherryview:
- Switch to to embedded struct pingroup
intel:
- Add Intel Meteor Lake pin controller support
- Drop no more used members of struct intel_pingroup
- Switch to to embedded struct pingroup
- Embed struct pingroup into struct intel_pingroup
lynxpoint:
- Switch to to embedded struct pingroup
MAINTAINERS:
- Update Intel pin control to Supported
Robert Marko [Fri, 24 Jun 2022 19:51:12 +0000 (21:51 +0200)]
pinctrl: qcom: spmi-gpio: make the irqchip immutable
Commit 6c846d026d49 ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning to indicate if the gpiolib is altering the
internals of irqchips.
Following this change the following warning is now observed for the SPMI
PMIC pinctrl driver:
gpio gpiochip1: (200f000.spmi:pmic@0:gpio@c000): not an immutable chip, please consider fixing it!
Fix this by making the irqchip in the SPMI PMIC pinctrl driver immutable.
Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220624195112.894916-1-robimarko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
According to Rev.0.51 datasheet 004_R-CarV4H_pin_function.xlsx,
GP1_23 - GP1_28 are 1.8/3.3V. But they are not on Table 7.28.
According to the HW team, there are no bits assigned.
This patch follows HW team's comment.
MODSEL8 controls I2C vs. GPIO modes, and the Datasheet (Rev.0.51) is
indicating that I2C needs 1. But we should use 0 for all cases in
reality. New Datasheet should be updated.
Phil Edworthy [Fri, 24 Jun 2022 08:48:33 +0000 (09:48 +0100)]
pinctrl: renesas: Add RZ/V2M pin and gpio controller driver
Add support for pin and gpio controller driver for RZ/V2M SoC.
Based on the RZ/G2L driver.
Note that the DETDO and DETMS dedicated pins are currently not
documented in the HW manual as to which pin group they are in.
HW team has since said that the output level of 1.8V I/O group 4
(for MD0-7, and debugger) is the same as the 1.8V I/O group 3.
Andy Shevchenko [Thu, 30 Jun 2022 12:38:58 +0000 (15:38 +0300)]
pinctrl: intel: Add Intel Meteor Lake pin controller support
This driver adds pinctrl/GPIO support for Intel Meteor Lake. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Samuel Holland [Tue, 21 Jun 2022 03:42:23 +0000 (22:42 -0500)]
pinctrl: axp209: Support the AXP221/AXP223/AXP809 variant
These PMICs each have 2 GPIOs with the same register layout as AXP813,
but without an ADC function. They all fall back to the AXP221 compatible
string, so only that one needs to be listed in the driver.
dt-bindings: pinctrl: mt8192: Add RSEL values to bias-pull-{up,down}
Commit fe44e4984018 ("pinctrl: mediatek: add rsel setting on mt8192")
added RSEL bias type definition for some pins on mt8192. In order to be
able to configure the bias on those pins, add the RSEL values in the
bias-pull-up and bias-pull-down properties in the binding.
pinctrl: samsung: do not use bindings header with constants
The Samsung SoC pin controller driver uses only three defines from the
bindings header with pin configuration register values, which proves
the point that this header is not a proper bindings-type abstraction
layer with IDs.
Define the needed register values directly in the driver and stop using
the bindings header.
Fix the below kernel-doc warning by adding the description for return
value.
"warning: No description found for return value of
'zynqmp_pmux_get_function_groups'".
pinctrl: pinctrl-zynqmp: Add support for output-enable and bias-high-impedance
Add support to handle 'output-enable' and 'bias-high-impedance'
configurations. As part of the output-enable configuration, ZynqMP pinctrl
driver takes care of removing the pins from tri-state.
Clément Léger [Fri, 17 Jun 2022 10:35:48 +0000 (12:35 +0200)]
pinctrl: ocelot: allow building as a module
Set PINCTRL_OCELOT config option as a tristate and add
MODULE_DEVICE_TABLE()/MODULE_LICENSE() to export appropriate
information. Moreover, switch from builtin_platform_driver()
to module_platform_driver().
Linus Walleij [Sun, 26 Jun 2022 23:55:16 +0000 (01:55 +0200)]
pinctrl: mediatek: mt8192: Fix compile warnings
After applying patches I get these warnings:
drivers/pinctrl/mediatek/pinctrl-mt8192.c:1302:56:
warning: "/*" within comment [-Wcomment]
drivers/pinctrl/mediatek/pinctrl-mt8192.c:1362:56:
warning: "/*" within comment [-Wcomment]
Something is wrong with the missing end-slashes. Add them.
Cc: Guodong Liu <guodong.liu@mediatek.com> Cc: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Guodong Liu [Fri, 24 Jun 2022 13:37:00 +0000 (21:37 +0800)]
pinctrl: mediatek: fix the pinconf definition of some GPIO pins
Remove pin definitions that do not support the R0 & R1 pinconfig property.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220624133700.15487-6-guodong.liu@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Guodong Liu [Fri, 24 Jun 2022 13:36:59 +0000 (21:36 +0800)]
pinctrl: mediatek: dropping original advanced drive configuration function
Function bias_combo getter/setters already handle all cases advanced drive
configuration, include drive for I2C related pins.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220624133700.15487-5-guodong.liu@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Guodong Liu [Fri, 24 Jun 2022 13:36:58 +0000 (21:36 +0800)]
pinctrl: mediatek: add rsel setting on mt8192
1. I2C pins's resistance value can be controlled by rsel register.
This patch provides rsel (resistance selection) setting on mt8192.
2. Also add the missing pull type array for mt8192 to document the
pull type of each pin and prevent invalid pull type settings.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220624133700.15487-4-guodong.liu@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Guodong Liu [Fri, 24 Jun 2022 13:36:57 +0000 (21:36 +0800)]
pinctrl: mediatek: add drive for I2C related pins on mt8192
This patch provides the advanced drive raw data setting version
for I2C used pins on mt8192.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220624133700.15487-3-guodong.liu@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Guodong Liu [Fri, 24 Jun 2022 13:36:56 +0000 (21:36 +0800)]
pinctrl: mediatek: add generic driving setup property on mt8192
1. The dt-binding expects that drive-strength arguments be passed
in mA, but the driver was expecting raw values. And that this
commit changes the driver so that it is aligned with the binding.
2. This commit provides generic driving setup, which support
2/4/6/8/10/12/14/16mA driving, original driver just set raw data
setup setting when use drive-strength property.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220624133700.15487-2-guodong.liu@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Stefan Wahren [Tue, 14 Jun 2022 20:28:31 +0000 (22:28 +0200)]
pinctrl: bcm2835: Make the irqchip immutable
Commit 6c846d026d49 ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning to indicate if the gpiolib is altering the
internals of irqchips. The bcm2835 pinctrl is also affected by this
warning.
Fix this by making the irqchip in the bcm2835 pinctrl driver immutable.
Stefan Wahren [Tue, 14 Jun 2022 20:28:30 +0000 (22:28 +0200)]
pinctrl: bcm2835: drop irq_enable/disable callbacks
The commit b8a19382ac62 ("pinctrl: bcm2835: Fix support for threaded level
triggered IRQs") assigned the irq_mask/unmask callbacks with the
already existing functions for irq_enable/disable. The wasn't completely
the right way (tm) to fix the issue, because these callbacks shouldn't
be identical. So fix this by rename the functions to represent their
intension and drop the unnecessary irq_enable/disable assigment.
Lukas Bulwahn [Mon, 13 Jun 2022 12:29:55 +0000 (14:29 +0200)]
MAINTAINERS: add include/dt-bindings/pinctrl to PIN CONTROL SUBSYSTEM
Maintainers of the directory Documentation/devicetree/bindings/pinctrl
are also the maintainers of the corresponding directory
include/dt-bindings/pinctrl.
Add the file entry for include/dt-bindings/pinctrl to the appropriate
section in MAINTAINERS.
Nikita Travkin [Sun, 12 Jun 2022 14:59:54 +0000 (19:59 +0500)]
pinctrl: qcom: msm8916: Allow CAMSS GP clocks to be muxed
GPIO 31, 32 can be muxed to GCC_CAMSS_GP(1,2)_CLK respectively but the
function was never assigned to the pingroup (even though the function
exists already).
Update lpass lpi pin control driver, with clock optional check for ADSP
disabled platforms. This check required for distingushing ADSP based
platforms and ADSP bypass platforms.
In case of ADSP enabled platforms, where audio is routed through ADSP
macro and decodec GDSC Switches are triggered as clocks by pinctrl
driver and ADSP firmware controls them. So It's mandatory to enable
them in ADSP based solutions.
In case of ADSP bypass platforms clock voting is optional as these macro
and dcodec GDSC switches are maintained as power domains and operated from
lpass clock drivers.
Add boolean param qcom,adsp-bypass-mode to support adsp bypassed sc7280
platforms. Which is required to make clock voting as optional for ADSP
bypass platforms.
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