Julian Seward [Mon, 17 Dec 2012 21:54:10 +0000 (21:54 +0000)]
IR: add the ability to specify the call-didn't-happen ("default")
return value for conditional dirty helper calls returning values. The
default value can be either all-zeroes or all-ones.
Julian Seward [Sun, 25 Nov 2012 15:26:48 +0000 (15:26 +0000)]
Initial front changes for ARM, to generate direct IR for at least some
conditional loads and stores. Very incomplete -- most load-store
cases still use the old scheme.
Petar Jovanovic [Fri, 23 Nov 2012 00:44:37 +0000 (00:44 +0000)]
Correctly model LL/SC on MIPS.
As the issue with RMW on MIPS does not block execution anymore (see Valgrind
patch r13136), we can switch back to model it through LoadL and StoreC instead
of using incorrect Load and Store.
This will give back correct output to memcheck/tests/atomic_incs on MIPS.
Carl Love [Tue, 20 Nov 2012 17:32:48 +0000 (17:32 +0000)]
VEX, ppc fix use of modified value in the Iop_32HLto64 implementation
The issue with the Iop_32HLto64, as explained by Julian:
One of the "rules of the game" of instruction selection is that the register
returned by any of the isel* functions may not be modified -- if it needs to
be modified, first copy the value off to a different register. The rule exists
because, in this case, e->Iex.Binop.arg2 might be an IRExpr_RdTmp, in which
case iselWordExpr_R simply returns the register which holds the value of the
relevant IR temporary. And so if r_Lo is modified then any subsequent uses of
that IR temporary will get the wrong value. In this case, r_Lo is
modified without first copying it.
This patch fixes the issue by assigning the result of the AND operation to
a temporary and then using the temporary result in the OR operation thus
avoiding using a modified value.
Julian Seward [Tue, 20 Nov 2012 15:24:24 +0000 (15:24 +0000)]
Add a special-case implementation of PCMPISTRI $0x3A, which generates
in-line IR instead of calling helpers. This is so that Memcheck can
do exact definedness propagation through it. This is important for
dealing with inlined PCMPISTRI-based strlen calls.
#309921, comment 6. (Patrick J. LoPresti , lopresti@gmail.com)
Julian Seward [Thu, 8 Nov 2012 10:57:08 +0000 (10:57 +0000)]
Improve accuracy of definedness tracking through the x86 PMOVMSKB and
BSF instructions, as the lack of it causes false positives (VEX side).
Fixes #308627. Combined efforts of Patrick J. LoPresti
<lopresti@gmail.com> and me.
Carl Love [Mon, 29 Oct 2012 20:23:41 +0000 (20:23 +0000)]
Valgrind, ppc: Fix missing checks for 64-bit instructions operating in 32-bit mode, Bugzilla 308573
A number of the POWER instructions are only intended to run on 64-bit
hardware. These instructions will give a SIGILL instruction on 32-bit
hardware. The check for 32-bit mode on some of these instructions is
missing. Although, the 64-bit hardware will execute these instructions
on 64-bit hardware without generating a SIGILL the use of these
instructions in 32-bit mode on 64-bit hardware is typically indicative of
a programming error. There are cases where these instructions are used
to determine if the code is running on 32-bit hardware or not. In these
cases, the instruction needs to generate a SIGILL for the error handler
to properly determine the hardware is running in 32-bit mode.
This patch adds the 32-bit mode check for those 64-bit instructions that
do not have the check. If the check fails, the instruction is flagged
as an unsupported instruction and a SIGILL message is generated.
This patch fixes the bug reported in:
Bug 308573 - Internal Valgrind error on 64-bit instruction executed in
32-bit mode
Note, there is an accompaning fix to memcheck/tests/ppc32/power_ISA2_05.c
to only execute the 64-bit instruction prtyd test in 64-bit mode.
Florian Krohm [Sun, 7 Oct 2012 19:44:40 +0000 (19:44 +0000)]
Add data structures for cache representation to libvex.h:
VexCacheInfo, VexCache, and VexCacheKind.
VexArchInfo gets a VexCacheInfo member which LibVEX_default_VexArchInfo
initialises.
Florian Krohm [Sun, 7 Oct 2012 15:42:37 +0000 (15:42 +0000)]
s390: This is a pre-patch for DFP support. It renames certain
identifiers to explicitly refer to BFP, as there will be counterparts
in the future for DFP.
Patch by Maran <maranp@linux.vnet.ibm.com>.
Part of fixing #307113.
Make header files compilable by itself to get two benefits:
- never have to worry about order of inclusion
- never have to figure out hidden dependencies in order to be
able to include a file
Change the return value of LibVEX_{Chain,UnChain,PatchProfInc}.
These functions now always return the address range that was
patched. Therefore, these functions no longer need knowledge
about I-cache coherency of the host system.
Petar Jovanovic [Fri, 21 Sep 2012 00:06:14 +0000 (00:06 +0000)]
Shorten the list of allocable registers for MIPS to fit Loongson MIPS32 mode.
In order to fit MIPS32 mode on Loongson and work around its issues, we avoid
use of odd single precision FP registers. This results in expected execution/
results of some FPU instructions on Loongson. Running FPU intensive tests has
not shown any performance decrease after the change is introduced.
STM<c>.W <Rn>{!},<registers> (Encoding T2): allow the base register to
appear in the list in any position, provided that writeback is not
selected. Fixes #306297.
Tweak the IR injector so it can handle an immediate operand for
shift operations. This is needed for Iop_ShlD64 and the like on
powerpc where the shift amount is an immediate field in the insn.
Part of fixing bugzilla #305948.
s390: Change the handling of S390_ROUND_PER_FPC (which indicates that the
actual rounding mode is to be taken from the FPC register). Previously, this
was just mapped to S390_ROUND_NEAREST_EVEN, which obviously has correctness
issues.
First, we add a function get_bfp_rounding_mode_from_fpc to extract the
rounding mode from the guest FPC when building IR.
Second, have encode_bfp_rounding_mode invoke get_bfp_rounding_mode_from_fpc
whenever a S390_ROUND_PER_FPC is requested.
Third, in insn selection track whether (and if so to what value) the
rounding mode was set for the IRSB at hand. That way redundant assignments
can be avoided. This works well because the IR optimiser do a fine job
recognising end eliminating the expressions returned earlier from
get_bfp_rounding_more_from_fpc. So they get all mapped to the same IRTemp.
Note, VEX r2524 is essential to get this behaviour.
Fourth, remove the rounding more from the bfp_unop/binop/triop s390_insns.
Fifth, if the rounding mode can be set on the insn directly, prefer that
over setting it in the FPC and picking it up from there.
s390: More prep work bfp reorg. In the future unary/binary/ternary
operations on bfp data will no longer require a rounding mode in the
s390_insn. Only type conversion operations need a rounding mode.
So in this patch S390_BFP_CONVERT is introduced and
S390_BFP128_CONVERT_TO/FROM are consolidated to S390_BFP128_CONVERT.
This also makes the representation of bfp and bfp128 symmetric.
s390_insn gets a new variant: s390_convert.
The type conversion ops get their own data type now: s390_conv_t
s390: Prepare for bfp reorg. Change the emit functions for the
convert-to-fixed and load-rounded instructions to emit the extended
form. E.g. change s390_emit_CEFBR to s390_emit_CEFBRA. In the future
we will take advantage of those insns if the host's hardware facilities
allow it.
Petar Jovanovic [Sun, 9 Sep 2012 01:10:59 +0000 (01:10 +0000)]
Correcting how load/store doubles are modelled on MIPS for big-endian.
One of the previous changes, r2511, was correct for little-endian and introduced
a regression for big-endian MIPS. This corrects the endianness issues.
s390: Fix condition code computation for convert-to-fixed/logical
insns. Previously the condition code was computed based on the
to-be-converted value only. But that is not sufficient as testcase
none/tests/s390x/rounding-1 shows. The rounding mode needs to be
considered, too. Therefore, the rounding mode is now stored in the
flags thunk as well (in IRRoundingMode encoding). Note, that this is
done for *all* convert-to-fixed/logical insns. It's possible that some
of them do not need the rounding mode but I did not bother exploring
the fine print. Setting the rounding mode as it was on the incoming
insn certainly will not be detrimental so we can as well do it.
This patch fixes bugzilla #306054.
s390: Non-functional change.
Rename enable_rounding_mode to enable_bfp_rounding_mode in
anticipation of dfp coming. Change its return value to be an
IRTemp which will be handy soon. Fix all call-sites.
Binary floating point cleanup. This was an area that was hushed up
a bit when the s390 port was first committed. Time to get it in shape.
This patch
- completes s390_round_t to list all rounding modes that can appear
in a convert-to instruction
- adapts function encode_rounding_mode accordingly
- ensures that all s390_round_t -> IRRoundingMode conversions go through
encode_rounding_mode
Carl Love [Tue, 4 Sep 2012 22:09:48 +0000 (22:09 +0000)]
Add vassert for DFP shift value to make sure shift value is an immediate value.
V-bit tester was putting shift value in a register for the DFP shift
instructions causing the test to crash, see bugzilla #305948.
Petar Jovanovic [Tue, 4 Sep 2012 13:45:42 +0000 (13:45 +0000)]
Load/store doubles on MIPS are modeled through Ity_F64 rather than two Ity_F32.
This patch changes how the load/store doublewords are modeled on MIPS.
Previously, this was modeled through two Ity_F32s which caused test reports to
be different to expected.
This fixes memcheck/tests/fprw.
s390: Undo part of r2501. The "convert to fixed" opcodes always have an m3
field -- independent of the floating point extension facility.
So do not issue an emulation warning for those opcodes.
Support the variety of "convert to/from fixed" and "load rounded" opcodes
that have an additional m3 and/or m4 field.
Add emulation warning EmWarn_S390X_fpext_rounding and issue it in case
the current opcode cannot be emulated correctly (i.e. with the specified
rounding mode).
New function: emulation_warning.
Part of fixing bugzilla #306098.
Remove alignment checks for VMPSADBW, VPHMINPOSUW, VPALIGNR since they
do not apply to the AVX versions of these instructions. Fixes #305926.
(Jakub Jelinek, jakub@redhat.com)
s390: Generate an emulation failure if an insn is encountered that
requires the floating point extension facility but the host does not
have it. Factored out function emulation_failure.
s390: Add support for the "convert from/to logical" instruction family.
A few (7) new IROps are introduced.
Patch by Christian Borntraeger (borntraeger@de.ibm.com).
Fixes bugzilla #274695.
Florian Krohm [Wed, 29 Aug 2012 17:40:52 +0000 (17:40 +0000)]
Fix address computation in IR injection. When loading / storing a
128-bit value as 2 64-bit values, the two memory locations are 8 bytes
apart. Always. Everywhere. Due to a thinko this was busted on 32-bit
eachines.
Also add an assert that values requiring more than 128 bit are currently
not supported.
Florian Krohm [Tue, 28 Aug 2012 16:49:30 +0000 (16:49 +0000)]
VEX-side support for the V-bit tester.
- recognise the new "special instruction" for all architectures
(ARM needs implementation work; x86 and ARM are untested)
- inject IR into the superblock
- type definition for the IR injection control block
Florian Krohm [Sun, 26 Aug 2012 18:58:13 +0000 (18:58 +0000)]
s390: Add support for the ecag insn. Patch from Divya Vyas
(divyvyas@linux.vnet.ibm.com) with mods to terminate the super block
with EmFail in case the insn is not available on the host.
Part of fixing bugzilla #275800.
Florian Krohm [Sat, 25 Aug 2012 21:48:04 +0000 (21:48 +0000)]
Rename libvex_emwarn.h to libvex_emnote.h and fix all
#include's. The renaming of guest_EMWARN, VexemWarn etc will
be done in a followup patch.
The rationale for all this is that we want to reuse the existing
machinery for emulation warnings also for emulation failures.
And that calls for some kind of neutral naming scheme.
projects / thirdparty / valgrind.git / log
