Stephen Boyd [Mon, 21 Dec 2020 01:17:37 +0000 (17:17 -0800)]
Merge branches 'clk-tegra', 'clk-imx', 'clk-sifive', 'clk-mediatek' and 'clk-summary' into clk-next
- Support for SiFive FU740 PRCI
- Add hardware enable information to clk_summary debugfs
* clk-tegra:
clk: tegra: Fix duplicated SE clock entry
clk: tegra: bpmp: Clamp clock rates on requests
clk: tegra: Do not return 0 on failure
* clk-imx: (24 commits)
clk: imx: scu: remove the calling of device_is_bound
clk: imx: scu: Make pd_np with static keyword
clk: imx8mq: drop of_match_ptr from of_device_id table
clk: imx8mp: drop of_match_ptr from of_device_id table
clk: imx8mn: drop of_match_ptr from of_device_id table
clk: imx8mm: drop of_match_ptr from of_device_id table
clk: imx: gate2: Remove unused variable ret
clk: imx: gate2: Add locking in is_enabled op
clk: imx: gate2: Add cgr_mask for more flexible number of control bits
clk: imx: gate2: Check if clock is enabled against cgr_val
clk: imx: gate2: Keep the register writing in on place
clk: imx: gate2: Remove the IMX_CLK_GATE2_SINGLE_BIT special case
clk: imx: scu: fix build break when compiled as modules
clk: imx: remove redundant assignment to pointer np
clk: imx: remove unneeded semicolon
clk: imx: lpcg: add suspend/resume support
clk: imx: clk-imx8qxp-lpcg: add runtime pm support
clk: imx: lpcg: allow lpcg clk to take device pointer
clk: imx: imx8qxp-lpcg: add parsing clocks from device tree
clk: imx: scu: add suspend/resume support
...
* clk-sifive:
clk: sifive: Add clock enable and disable ops
clk: sifive: Fix the wrong bit field shift
clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
clk: sifive: Use common name for prci configuration
clk: sifive: Extract prci core to common base
dt-bindings: fu740: prci: add YAML documentation for the FU740 PRCI
* clk-mediatek:
clk: mediatek: Make mtk_clk_register_mux() a static function
* clk-summary:
clk: Add hardware-enable column to clk summary
Stephen Boyd [Mon, 21 Dec 2020 01:17:01 +0000 (17:17 -0800)]
Merge branches 'clk-doc', 'clk-qcom', 'clk-simplify', 'clk-hw', 'clk-renesas' and 'clk-samsung' into clk-next
- Camera clks on Qualcomm SC7180 SoCs
- GCC and RPMh clks on Qualcomm SDX55 SoCs
- RPMh clks on Qualcomm SM8350 SoCs
- LPASS clks on Qualcomm SM8250 SoCs
- Add devm variant of clk_notifier_register()
- Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw
* clk-doc:
clk: fix a kernel-doc markup
* clk-qcom: (27 commits)
clk: qcom: rpmh: add support for SM8350 rpmh clocks
dt-bindings: clock: Add RPMHCC bindings for SM8350
clk: qcom: lpasscc: Introduce pm autosuspend for SC7180
clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2
clk: qcom: gcc-sc7180: Use floor ops for sdcc clks
clk: qcom: Add GDSC support for SDX55 GCC
dt-bindings: clock: Add GDSC in SDX55 GCC
clk: qcom: Add support for SDX55 RPMh clocks
dt-bindings: clock: Introduce RPMHCC bindings for SDX55
clk: qcom: Add SDX55 GCC support
dt-bindings: clock: Add SDX55 GCC clock bindings
clk: qcom: Kconfig: Fix spelling mistake "dyanmic" -> "dynamic"
clk: qcom: rpmh: Add CE clock on sdm845.
dt-bindings: clock: Add entry for crypto engine RPMH clock resource
clk: qcom: dispcc-sm8250: handle MMCX power domain
clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones
clk: qcom: lpass-sc7180: Clean up on error in lpass_sc7180_init()
clk: qcom: Add support to LPASS AON_CC Glitch Free Mux clocks
clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocks
dt-bindings: clock: Add support for LPASS Always ON Controller
...
* clk-hw:
clk: meson: g12: use devm variant to register notifiers
clk: add devm variant of clk_notifier_register
clk: meson: g12: drop use of __clk_lookup()
clk: add api to get clk consumer from clk_hw
clk: avoid devm_clk_release name clash
Dmitry Osipenko [Sun, 15 Nov 2020 20:34:32 +0000 (23:34 +0300)]
clk: Add hardware-enable column to clk summary
Add "hardware enable" column to the clk summary in order to show actual
hardware enable-state of all clocks. The possible states are "Y/N/?",
where question mark means that state is unknown, i.e. clock isn't a
mux and clk-driver doesn't support is_enabled() callback for this clock.
In conjunction with clk_ignore_unused, this tells us what unused clocks
are left enabled after bootloader. This is also a useful aid for
debugging interactions with firmware which changes clock states without
notifying kernel.
Zong Li [Wed, 9 Dec 2020 09:49:14 +0000 (17:49 +0800)]
clk: sifive: Add a driver for the SiFive FU740 PRCI IP block
Add driver code for the SiFive FU740 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU740 device and
implements SoC-level clock tree controls and dividers.
The link of unmatched as follow, and the U740-C000 manual would
be present in the same page as soon.
https://www.sifive.com/boards/hifive-unmatched
This driver contains bug fixes and contributions from
Henry Styles <hes@sifive.com>
Erik Danie <erik.danie@sifive.com>
Pragnesh Patel <pragnesh.patel@sifive.com>
Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Cc: Henry Styles <hes@sifive.com> Cc: Erik Danie <erik.danie@sifive.com> Cc: Pragnesh Patel <pragnesh.patel@sifive.com> Link: https://lore.kernel.org/r/20201209094916.17383-4-zong.li@sifive.com
[sboyd@kernel.org: Include header to silence sparse] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Zong Li [Wed, 9 Dec 2020 09:49:12 +0000 (17:49 +0800)]
clk: sifive: Extract prci core to common base
Extract common core of prci driver to an independent file, it could
allow other chips to reuse it. Separate SoCs-dependent code 'fu540'
from prci core, then we can easily add 'fu740' later.
Almost these changes are code movement. The different is adding the
private data for each SoC use, so it needs to get match data in probe
callback function, then use the data for initialization.
Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Link: https://lore.kernel.org/r/20201209094916.17383-2-zong.li@sifive.com
[sboyd@kernel.org: Include header to silence sparse] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Zong Li [Thu, 26 Nov 2020 03:00:43 +0000 (11:00 +0800)]
dt-bindings: fu740: prci: add YAML documentation for the FU740 PRCI
Add YAML DT binding documentation for the SiFive FU740 PRCI. The
link of unmatched board as follow, the U740-C000 manual would be present
in the same page later.
Stephen Boyd [Thu, 10 Dec 2020 20:59:43 +0000 (12:59 -0800)]
Merge tag 'renesas-clk-for-v5.11-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Update git repo branch for Renesas clock drivers
- Add camera (CSI) and video-in (VIN) clocks on R-Car V3U
- Add RPC (QSPI/HyperFLASH) clocks on RZ/G2M, RZ/G2N, and RZ/G2E
- Stop using __raw_*() I/O accessors
- One more conversion of DT bindings to json-schema
- Minor fixes and improvements
* tag 'renesas-clk-for-v5.11-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Convert bindings to json-schema
clk: renesas: sh73a0: Stop using __raw_*() I/O accessors
clk: renesas: r8a774c0: Add RPC clocks
clk: renesas: r8a779a0: Fix R and OSC clocks
clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv
clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get()
clk: renesas: r8a774b1: Add RPC clocks
clk: renesas: r8a774a1: Add RPC clocks
clk: renesas: r8a779a0: Add VIN clocks
clk: renesas: r8a779a0: Add CSI4[0-3] clocks
MAINTAINERS: Update git repo for Renesas clock drivers
clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() static
clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI
Stephen Boyd [Thu, 10 Dec 2020 20:53:31 +0000 (12:53 -0800)]
Merge tag 'clk-imx-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx
Pull i.MX clk driver updates from Shawn Guo:
- A series from Abel Vesa to improve clk-gate2 driver and make it more
flexible.
- A patch set from Dong Aisheng to add a new two cells binding for SCU
clocks, so that IMX SCU based platforms like MX8QM and MX8QXP can be
supported with SS (Subsystems).
- Drop of_match_ptr from of_device_id table for i.MX8 clock drivers, as
they can only be probed from device tree.
- Other small cosmetic changes.
* tag 'clk-imx-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (24 commits)
clk: imx: scu: remove the calling of device_is_bound
clk: imx: scu: Make pd_np with static keyword
clk: imx8mq: drop of_match_ptr from of_device_id table
clk: imx8mp: drop of_match_ptr from of_device_id table
clk: imx8mn: drop of_match_ptr from of_device_id table
clk: imx8mm: drop of_match_ptr from of_device_id table
clk: imx: gate2: Remove unused variable ret
clk: imx: gate2: Add locking in is_enabled op
clk: imx: gate2: Add cgr_mask for more flexible number of control bits
clk: imx: gate2: Check if clock is enabled against cgr_val
clk: imx: gate2: Keep the register writing in on place
clk: imx: gate2: Remove the IMX_CLK_GATE2_SINGLE_BIT special case
clk: imx: scu: fix build break when compiled as modules
clk: imx: remove redundant assignment to pointer np
clk: imx: remove unneeded semicolon
clk: imx: lpcg: add suspend/resume support
clk: imx: clk-imx8qxp-lpcg: add runtime pm support
clk: imx: lpcg: allow lpcg clk to take device pointer
clk: imx: imx8qxp-lpcg: add parsing clocks from device tree
clk: imx: scu: add suspend/resume support
...
Dmitry Osipenko [Sun, 25 Oct 2020 22:42:12 +0000 (01:42 +0300)]
clk: tegra: Fix duplicated SE clock entry
The periph_clks[] array contains duplicated entry for Security Engine
clock which was meant to be defined for T210, but it wasn't added
properly. This patch corrects the T210 SE entry and fixes the following
error message on T114/T124: "Tegra clk 127: register failed with -17".
Fixes: dc37fec48314 ("clk: tegra: periph: Add new periph clks and muxes for Tegra210")
Tested-by Nicolas Chauvet <kwizart@gmail.com>
Reported-by Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20201025224212.7790-1-digetx@gmail.com Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Douglas Anderson [Thu, 10 Dec 2020 18:22:39 +0000 (10:22 -0800)]
clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2
50 MHz is an incredibly common clock rate for SD cards to run at.
It's "high speed" mode in SD (not very fast these days, but it used to
be) or:
#define HIGH_SPEED_MAX_DTR 50000000
If we don't support this then older "high speed" cards can only run at
25 MHz or at half their normal speed. There doesn't seem to be any
reason to skip this clock rate, so add it.
Douglas Anderson [Thu, 10 Dec 2020 18:22:38 +0000 (10:22 -0800)]
clk: qcom: gcc-sc7180: Use floor ops for sdcc clks
I would repeat the same commit message that was in commit 5e4b7e82d497
("clk: qcom: gcc-sdm845: Use floor ops for sdcc clks") but it seems
silly to do so when you could just go read that commit.
NOTE: this is actually extra terrible because we're missing the 50 MHz
rate in the table (see the next patch AKA ("clk: qcom: gcc-sc7180: Add
50 MHz clock rate for SDC2")). That means then when you run an older
SD card it'll try to clock it at 100 MHz when it's only specced to run
at 50 MHz max. As you can probably guess that doesn't work super
well.
clk: pwm: drop of_match_ptr from of_device_id table
The driver can match only via the DT table so the table should be always
used and the of_match_ptr does not have any sense (this also allows ACPI
matching via PRP0001, even though it might be not relevant here). This
fixes compile warning (!CONFIG_OF && !CONFIG_MODULES):
drivers/clk/clk-pwm.c:139:34: warning:
‘clk_pwm_dt_ids’ defined but not used [-Wunused-const-variable=]
clk: renesas: sh73a0: Stop using __raw_*() I/O accessors
There is no reason to keep on using the __raw_{read,write}l() I/O
accessors in Renesas ARM driver code. Switch to using the plain
{read,write}l() I/O accessors, to have a chance that this works on
big-endian.
Lad Prabhakar [Mon, 16 Nov 2020 10:10:02 +0000 (10:10 +0000)]
clk: renesas: r8a774c0: Add RPC clocks
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR
driver.
Add new clk type CLK_TYPE_GEN3_E3_RPCSRC to register rpcsrc as a fixed
clock on R-Car Gen3 E3 (and also RZ/G2E which is identical to E3 SoC),
parent and the divider is set based on the register value CPG_RPCCKCR[4:3]
which has been set prior to booting the kernel.
The R-Car V3U clock driver defines the R and OSC clocks using R-Car Gen3
clock types. However, The R-Car V3U clock driver does not use the R-Car
Gen3 clock driver core, hence registering the R and OSC clocks fails:
renesas-cpg-mssr e6150000.clock-controller: Failed to register core clock osc: -22
renesas-cpg-mssr e6150000.clock-controller: Failed to register core clock r: -22
Fix this by introducing clock definition macros specific to R-Car V3U.
Note that rcar_r8a779a0_cpg_clk_register() already handled the related
clock types. Drop the now unneeded include of rcar-gen3-cpg.h.
Biju Das [Fri, 16 Oct 2020 12:17:08 +0000 (13:17 +0100)]
clk: renesas: r8a774b1: Add RPC clocks
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2N (R8A774B1) CPG/MSSR
driver.
Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").
Biju Das [Fri, 16 Oct 2020 12:17:07 +0000 (13:17 +0100)]
clk: renesas: r8a774a1: Add RPC clocks
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it,
as well as the RPC-IF module clock, in the RZ/G2M (R8A774A1) CPG/MSSR
driver.
Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks").
clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() static
When compiling with clang:
drivers/clk/renesas/r8a779a0-cpg-mssr.c:156:21: warning: no previous prototype for function 'rcar_r8a779a0_cpg_clk_register' [-Wmissing-prototypes]
struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
^
drivers/clk/renesas/r8a779a0-cpg-mssr.c:156:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
^
static
Similarly, with sparse:
drivers/clk/renesas/r8a779a0-cpg-mssr.c:156:12: warning: symbol 'rcar_r8a779a0_cpg_clk_register' was not declared. Should it be static?
There are no users of rcar_r8a779a0_cpg_clk_register() outside this
file, so it should be static.
Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200924111808.15358-1-geert+renesas@glider.be
Michael Walle [Sun, 8 Nov 2020 18:51:11 +0000 (19:51 +0100)]
clk: fsl-flexspi: new driver
Add support for the FlexSPI clock on Freescale Layerscape SoCs. The
clock is a simple divider based one and is located inside the device
configuration space (DCFG).
This will allow switching the SCK frequencies for the FlexSPI interface
on the LS1028A and the LX2160A.
The Freescale QorIQ clock controller is only present on Freescale E500MC
and Layerscape SoCs. Add platform dependencies to the CLK_QORIQ config
symbol, to avoid asking the user about it when configuring a kernel
without E500MC or Layerscape support.
Stephen Boyd [Sat, 5 Dec 2020 06:27:22 +0000 (22:27 -0800)]
Merge tag 'clk-v5.11-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung
Pull Samsung clk driver updates from Sylwester Nawrocki:
- Correction of Kconfig dependencies for better compile test coverage
- Refactoring of the PLL clocks driver
* tag 'clk-v5.11-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: Prevent potential endless loop in the PLL ops
clk: samsung: Allow compile testing of Exynos, S3C64xx and S5Pv210
Dong Aisheng [Thu, 19 Nov 2020 11:43:02 +0000 (19:43 +0800)]
clk: imx: scu: remove the calling of device_is_bound
The device_is_bound() is invisible to drivers when built as modules.
It's also not aimed to be used by drivers according to Greg K.H.
Let's remove it from clk-scu driver and find another way to do proper
driver loading sequence.
Johan Jonker [Wed, 18 Nov 2020 13:58:17 +0000 (14:58 +0100)]
clk: rockchip: fix i2s gate bits on rk3066 and rk3188
The Rockchip PX2/RK3066 uses these bits in CRU_CLKGATE7_CON:
hclk_i2s_8ch_gate_en bit 4 (dtsi: i2s0)
hclk_i2s0_2ch_gate_en bit 2 (dtsi: i2s1)
hclk_i2s1_2ch_gate_en bit 3 (dtsi: i2s2)
The Rockchip PX3/RK3188 uses this bit in CRU_CLKGATE7_CON:
hclk_i2s_2ch_gate_en bit 2 (dtsi: i2s0)
The bits got somehow mixed up in the clk-rk3188.c file.
The labels in the dtsi files are not suppose to change.
The sclk and hclk names should match for
"trace_event=clk_disable,clk_enable",
so remove GATE HCLK_I2S0 from the common clock tree and
fix the bits in the rk3066 and rk3188 clock tree.
Stephen Boyd [Fri, 27 Nov 2020 20:19:48 +0000 (12:19 -0800)]
Merge tag 'for-5.11-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-tegra
Pull a couple Tegra clk driver updates from Thierry Reding:
This set consists of two fixes for minor issues that rarely, if ever,
happen, so not urgent enough for these to go into v5.10.
* tag 'for-5.11-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: bpmp: Clamp clock rates on requests
clk: tegra: Do not return 0 on failure
Sivaram Nair [Wed, 21 Oct 2020 10:10:54 +0000 (13:10 +0300)]
clk: tegra: bpmp: Clamp clock rates on requests
BPMP firmware ABI expects the rate inputs in int64_t. However,
tegra_bpmp_clk_round_rate() and tegra_bpmp_clk_set_rate() functions
directly assign 'unsigned long' inputs to a int64_t value causing
unexpected rounding errors.
Neil Armstrong [Thu, 26 Nov 2020 14:16:00 +0000 (15:16 +0100)]
clk: meson: g12a: add MIPI DSI Host Pixel Clock
This adds the MIPI DSI Host Pixel Clock, unlike AXG, the pixel clock can be different
from the VPU ENCL output clock to feed the DSI Host controller with a different clock rate.
clk: samsung: Prevent potential endless loop in the PLL ops
The PLL status polling loops in the set_rate callbacks of some PLLs
have no timeout detection and may become endless loops when something
goes wrong with the PLL.
For some PLLs there is already the ktime API based timeout detection,
but it will not work in all conditions when .set_rate gets called.
In particular, before the clocksource is initialized or when the
timekeeping is suspended.
This patch adds a common helper with the PLL status bit polling and
timeout detection. For conditions where the timekeeping API should not
be used a simple readl_relaxed/cpu_relax() busy loop is added with the
iterations limit derived from measurements of readl_relaxed() execution
time for various PLL types and Exynos SoCs variants.
Actual PLL lock time depends on the P divider value, the VCO frequency
and a constant PLL type specific LOCK_FACTOR and can be calculated as
lock_time = Pdiv * LOCK_FACTOR / VCO_freq
For the ktime API use cases a common timeout value of 20 ms is applied
for all the PLLs with an assumption that maximum possible value of Pdiv
is 64, maximum possible LOCK_FACTOR value is 3000 and minimum VCO
frequency is 24 MHz.
clk: samsung: Allow compile testing of Exynos, S3C64xx and S5Pv210
So far all Exynos, S3C64xx and S5Pv210 clock units were selected by
respective SOC/ARCH Kconfig option. On a kernel built for selected
SoCs, this allowed to build only limited set of matching clock drivers.
However compile testing was not possible in such case as Makefile object
depends on SOC/ARCH option.
Add separate Kconfig options for each of them to be able to compile
test.
Neil Armstrong [Tue, 15 Sep 2020 12:45:52 +0000 (14:45 +0200)]
clk: meson: axg: add Video Clocks
Add the clocks entries used in the video clock path, the clock path is
doubled to permit having different synchronized clocks for different parts
of the video pipeline.
The AXG only has a single ENCL CTS clock and even if VCLK exist along
VCLK2, only VCLK2 is used since it clocks the MIPI DSI IP directly.
All dividers are flagged with CLK_GET_RATE_NOCACHE, and all gates are
flagged with CLK_IGNORE_UNUSED since they are currently directly handled by
the Meson DRM Driver. Once the DRM Driver is fully migrated to using the
Common Clock Framework to handle the video clock tree, the
CLK_GET_RATE_NOCACHE and CLK_IGNORE_UNUSED will be dropped.
Dmitry Baryshkov [Fri, 23 Oct 2020 13:19:25 +0000 (16:19 +0300)]
clk: qcom: dispcc-sm8250: handle MMCX power domain
On SM8250 MMCX power domain is required to access MMDS_GDSC registers.
This power domain is expressed as mmcx-supply regulator property. Use
this regulator as MDSS_GDSC supply.
Jerome Brunet [Wed, 21 Oct 2020 16:38:47 +0000 (18:38 +0200)]
clk: meson: g12: use devm variant to register notifiers
Until now, nothing was done to unregister the dvfs clock notifiers of the
Amlogic g12 SoC family. This is not great but this driver was not really
expected to be unloaded. With the ongoing effort to build everything as
module for this platform, this needs to be cleanly handled.
Jerome Brunet [Wed, 21 Oct 2020 16:21:47 +0000 (18:21 +0200)]
clk: meson: g12: drop use of __clk_lookup()
g12 clock controller used __clk_lookup() to get struct clk from a
struct clk_hw. This type of hack is no longer required as CCF now provides
the necessary functions to get this.
Jerome Brunet [Wed, 21 Oct 2020 16:21:46 +0000 (18:21 +0200)]
clk: add api to get clk consumer from clk_hw
clk_register() is deprecated. Using 'clk' member of struct clk_hw is
discouraged. With this constraint, it is difficult for driver to
register clocks using the clk_hw API and then use the clock with
the consumer API
This adds a simple helper, clk_hw_get_clk(), to get a struct clk from
a struct clk_hw. Like other clk_get() variant, each call to this helper
must be balanced with a call to clk_put(). To make life easier on the
consumers, a memory managed version is provided as well.
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201021162147.563655-3-jbrunet@baylibre.com Tested-by: Kevin Hilman <khilman@baylibre.com>
[sboyd@kernel.org: Fix kernel-doc] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jerome Brunet [Wed, 21 Oct 2020 16:21:45 +0000 (18:21 +0200)]
clk: avoid devm_clk_release name clash
In clk-devres.c, devm_clk_release() is used to call clk_put() memory
managed clock. In clk.c the same name, in a different scope is used to call
clk_unregister().
As it stands, it is not really a problem but it does not readability,
especially if we need to call clk_put() on managed clock in clk.c
Lukas Bulwahn [Fri, 6 Nov 2020 09:48:20 +0000 (10:48 +0100)]
clk: remove unneeded dead-store initialization
make clang-analyzer on x86_64 defconfig caught my attention with:
drivers/clk/clk.c:423:19:
warning: Value stored to 'parent' during its initialization is never read
[clang-analyzer-deadcode.DeadStores]
struct clk_core *parent = ERR_PTR(-ENOENT);
^
Commit fc0c209c147f ("clk: Allow parents to be specified without string
names") introduced clk_core_fill_parent_index() with this unneeded
dead-store initialization.
So, simply remove this unneeded dead-store initialization to make
clang-analyzer happy.
As compilers will detect this unneeded assignment and optimize this anyway,
the resulting object code is identical before and after this change.
Stephen Boyd [Sat, 14 Nov 2020 17:44:08 +0000 (09:44 -0800)]
clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones
Let's call pm_runtime_get() here instead of calling the PM clk APIs
directly. This avoids a compilation problem on CONFIG_PM=n where the
pm_clk_runtime_{resume,suspend}() functions don't exist and covers the
intent, i.e. enable the clks for this device so we can program PLL
settings.
Reported-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Nathan Chancellor <natechancellor@gmail.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Taniya Das <tdas@codeaurora.org> Cc: "Rafael J. Wysocki" <rafael@kernel.org> Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Fixes: 15d09e830bbc ("clk: qcom: camcc: Add camera clock controller driver for SC7180") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20201114174408.579047-1-sboyd@kernel.org
Dan Carpenter [Fri, 13 Nov 2020 10:14:19 +0000 (13:14 +0300)]
clk: qcom: lpass-sc7180: Clean up on error in lpass_sc7180_init()
Clean up the first driver if the second driver can't be registered.
Fixes: 4ee9fe3e292b ("clk: qcom: lpass-sc7180: Disentangle the two clock devices") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20201113101419.GC168908@mwanda Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: imx8mq: drop of_match_ptr from of_device_id table
The driver can match only via the DT table so the table should be always
used and the of_match_ptr does not have any sense (this also allows ACPI
matching via PRP0001, even though it might be not relevant here). This
fixes compile warning (!CONFIG_OF && !CONFIG_MODULES):
drivers/clk/imx/clk-imx8mq.c:626:34: warning:
‘imx8mq_clk_of_match’ defined but not used [-Wunused-const-variable=]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
clk: imx8mp: drop of_match_ptr from of_device_id table
The driver can match only via the DT table so the table should be always
used and the of_match_ptr does not have any sense (this also allows ACPI
matching via PRP0001, even though it might be not relevant here). This
fixes compile warning (!CONFIG_OF && !CONFIG_MODULES):
drivers/clk/imx/clk-imx8mp.c:751:34: warning:
‘imx8mp_clk_of_match’ defined but not used [-Wunused-const-variable=]
Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
clk: imx8mn: drop of_match_ptr from of_device_id table
The driver can match only via the DT table so the table should be always
used and the of_match_ptr does not have any sense (this also allows ACPI
matching via PRP0001, even though it might be not relevant here). This
fixes compile warning (!CONFIG_OF && !CONFIG_MODULES):
drivers/clk/imx/clk-imx8mn.c:592:34: warning:
‘imx8mn_clk_of_match’ defined but not used [-Wunused-const-variable=]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
clk: imx8mm: drop of_match_ptr from of_device_id table
The driver can match only via the DT table so the table should be always
used and the of_match_ptr does not have any sense (this also allows ACPI
matching via PRP0001, even though it might be not relevant here). This
fixes compile warning (!CONFIG_OF && !CONFIG_MODULES):
drivers/clk/imx/clk-imx8mm.c:641:34: warning:
‘imx8mm_clk_of_match’ defined but not used [-Wunused-const-variable=]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Douglas Anderson [Mon, 19 Oct 2020 22:49:35 +0000 (15:49 -0700)]
clk: qcom: lpass-sc7180: Disentangle the two clock devices
The sc7180 lpass clock driver manages two different devices. These
two devices were tangled together, using one probe and a lookup to
figure out the real probe. I think it's cleaner to really separate
the probe for these two devices since they're really different things,
just both managed by the same driver.
Douglas Anderson [Mon, 19 Oct 2020 22:49:34 +0000 (15:49 -0700)]
clk: qcom: lpasscc-sc7810: Use devm in probe
Let's convert the lpass clock control driver to use devm. This is a
few more lines of code, but it will be useful in a later patch which
disentangles the two devices handled by this driver.
projects / thirdparty / kernel / linux.git / log
