Merge tag 'apple-soc-dt-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/dt
Apple SoC DT update for 6.20
- Add all required nodes and connections for USB3 support. This is
responsible for the majority of the diffstat. The dt-bindings for the
Type-C PHY are scheduled to be sent via the PHY tree and are already
in next.
- Add RTC subnodes to the System Management Controller
- Add chassis-type property for all M1 and M2 machines
- Fix some minor power management issues
- Add backlight nodes for the A9X-based iPad Pro
* tag 'apple-soc-dt-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux:
arm64: dts: apple: t60xx: Add nodes for integrated USB Type-C ports
arm64: dts: apple: t8112: Add nodes for integrated USB Type-C ports
arm64: dts: apple: t8103: Add nodes for integrated USB Type-C ports
arm64: dts: apple: t8103: Add ps_pmp dependency to ps_gfx
arm64: dts: apple: t8103: Mark ATC USB AON domains as always-on
arm64: dts: apple: t8112-j473: Keep the HDMI port powered on
arm64: dts: apple: Add chassis-type property for Apple iMacs
arm64: dts: apple: Add chassis-type property for Mac Pro
arm64: dts: apple: Add chassis-type property for Apple desktop devices
arm64: dts: apple: Add chassis-type property for all Macbooks
arm64: dts: apple: s8001: Add DWI backlight for J98a, J99a
arm64: dts: apple: t8103,t60xx,t8112: Add SMC RTC node
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Merge tag 'lpc32xx-dt-for-6.20' of https://github.com/vzapolskiy/linux-lpc32xx into soc/dt
ARM: nxp: lpc: device tree updates for v6.20
This pull request contains device tree changes for ARM NXP LPC32xx intended
for v6.20, please pull the following:
- Frank fixes device tree checker warnings reported for NXP LPC32xx boards,
- Piotr addes a DMA mux block under SCB, DMA properties to controllers and
I2S support for NXP LPC32xx,
- Kuldeep corrects values of PrimeCell PL022 'clocks' and 'clock-names'
properties, this is the change from a waiting queue, recently it was
repeatedly done by Frank, the hesitation was about a probable ABI break,
but here in particular the risk is practically negligible due to the kept
backwards compatibale 'clocks' property,
- Vladimir adds a few missing properties to a number of LPC32xx controllers.
* tag 'lpc32xx-dt-for-6.20' of https://github.com/vzapolskiy/linux-lpc32xx:
arm: dts: lpc32xx: add interrupts property to Motor Control PWM
arm: dts: lpc32xx: add clocks property to Motor Control PWM device tree node
ARM: dts: lpc32xx: Add missing properties to I2S device tree nodes
ARM: dts: lpc32xx: Declare the second AHB master support on PL080 DMA controller
ARM: dts: lpc32xx: Add missing DMA properties
ARM: dts: lpc32xx: Use syscon for system control block
ARM: dts: lpc32xx: describe FLASH_INT of SLC NAND controller
ARM: dts: lpc32xx: change NAND controllers node names
ARM: dts: lpc32xx: Update spi clock properties
ARM: dts: lpc3250-phy3250: replace deprecated at25 properties with new ones
ARM: dts: lpc3250-phy3250: rename nodename at@0 to eeprom@0
ARM: dts: lpc3250-ea3250: add key- prefix for gpio-keys
ARM: dts: lpc32xx: remove usb bus and elevate all children nodes
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Merge tag 'aspeed-6.20-devicetree-1' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
aspeed: second batch of arm devicetree changes for 6.20
New platforms:
- Facebook Anacapa
The Meta Anacapa BMC is the DC-SCM (Data Center Secure Control
Module) controller for the Meta OCP Open Rack Wide (ORW) compute tray.
This platform is a key component of the AMD Helios AI rack reference
design system, designed for next-generation AI workloads.
The BMC utilizes the Aspeed AST2600 SoC to manage the compute tray, which
contains up to 4 AMD Instinct MI450 Series GPUs (connected via a Broadcom
OCP NIC) and host CPUs. Its primary role is to provide essential system
control, power sequencing, and telemetry reporting for the compute complex
via the OpenBMC software stack.
For more detail on the AMD Helios reference design:
Merge tag 'nuvoton-arm64-6.20-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
Nuvoton arm64 devicetree changes for 6.20
Just the one patch from Rob adding the device_type property to the memory node
of the NPCM845 EVB DTS.
* tag 'nuvoton-arm64-6.20-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux:
arm64: dts: nuvoton: Add missing "device_type" property on memory node
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Merge tag 'juno-updates-7.0' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
Armv8 Juno/Vexpress updates for v7.0
This contains a small set of DT updates:
1. Align DTS node naming with established coding style by replacing underscores
with hyphens in node names. This is a safe change and does not affect ABI.
2. Add support for the CMN PMU on the Arm Morello platform, exposing the
CMN-Skeena (CMN-600 r3p1–compatible) PMU via the standard CMN-600 binding.
This enables PMU access on real Morello SDP hardware, where the registers
are functional.
* tag 'juno-updates-7.0' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
arm64: dts: arm: Use hyphen in node names
arm64: dts: morello: Add CMN PMU
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those
interruption lines are multiplexed by the GPIO Interrupt Multiplexer in
order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.
The GPIO interrupt multiplexer IP does nothing but select 8 GPIO
IRQ lines out of the 96 available to wire them to the GIC input lines.
Sven Peter [Tue, 13 Jan 2026 07:03:14 +0000 (08:03 +0100)]
Merge patch series "arm64: dts: apple: Add integrated USB Type-C ports"
Janne Grunau <j@jannau.net> says:
Now that all dependencies for USB 2.0 and 3.x support are either merged
(tipd changes in v6.18, dwc3-apple in v6.19-rc1) or in linux-next (Apple
Type-C PHY) prepare device tree changes to expose the ports.
Each port on Apple silicon devices is driven by a separate collection of
hardware blocks. For USB 2.0 and 3.x the collection consists of:
- Apple Type-C PHY, combo PHY for USB 2.0, USB 3.x, USB4/Thunderbolt and
DisplayPort
- Synopsys Designware dwc3 USB controller
- two DART iommu instances for dwc3
- CD321x USB PD controller (similar to Ti's TPS6598x series)
The CD321x nodes are already present so this series add the remaining
devices nodes, typec connector nodes and connections between all
components.
The devices expose except for a few exceptions noted below all ports. M1
and M2 have two ports, M1 and M2 Pro and Max have four ports and
M1 and M2 Ultra have eight ports.
The Pro and Max based Macbook Pros use only three ports. The fourth port
is used as DisplayPort PHY to drive a HDMI output via an integrated
DP to HDMI converter.
The Ultra based Mac studio devices only use six ports. The third and
fourth port on the second die is completely fused off.
The changes for t600x and t602x are in a single commit since the devices
share .dtsi files across SoC generations due to their similarity.
Depends on commit c1538b87caef ("dt-bindings: phy: Add Apple Type-C
PHY") in linux-phy's [1] next branch for `make dtbs_check` to pass.
checkpatch warns about the undocumented DT compatible strings
"apple,t8112-atcphy", "apple,t6000-atcphy" and "apple,t6020-atcphy" but
not about "apple,t8103-atcphy". I don't under why it doesn't warn about
the last. "apple,t8103-atcphy" is only found in the added devicetree
files and nowhere else in v6.19-rc1.
Tested on top of next-20260106 on M1, M2, M1 Max and M2 Pro Mac mini /
Mac studio and a few fixes for dwc3-apple and atc [2, 3, 4, 5].
Janne Grunau [Fri, 9 Jan 2026 14:07:06 +0000 (15:07 +0100)]
arm64: dts: apple: t60xx: Add nodes for integrated USB Type-C ports
Add device nodes and connections to support USB 3.x on the SoC's
integrated Type-C ports of M1 and M2 Pro, Max and Ultra based devices.
Each Type-C port has an Apple Type-C PHY for USB 2.0, USB 3.x,
USB4/Thunderbolt, and DisplayPort, a Synopsys Designware USB 3.x
controller, two DART iommu instances and a CD321x USB PD controller.
M1 and M2 Max based Mac Studio device have two additional USB Type-C
ports on the front which are driven by an AsMedia PCIe USB controller
and integrated USB hub. These ports are not covered by this change.
The port labels use Apple's established naming scheme for the ports.
Co-developed-by: R <rqou@berkeley.edu> Signed-off-by: R <rqou@berkeley.edu> Co-developed-by: Hector Martin <marcan@marcan.st> Signed-off-by: Hector Martin <marcan@marcan.st> Signed-off-by: Janne Grunau <j@jannau.net> Tested-by: Sven Peter <sven@kernel.org> # M1 mac mini and macbook air Reviewed-by: Sven Peter <sven@kernel.org> Reviewed-by: Neal Gompa <neal@gompa.dev> Link: https://patch.msgid.link/20260109-apple-dt-usb-c-atc-dwc3-v1-3-ce0e92c1a016@jannau.net Signed-off-by: Sven Peter <sven@kernel.org>
Hector Martin [Fri, 9 Jan 2026 14:07:05 +0000 (15:07 +0100)]
arm64: dts: apple: t8112: Add nodes for integrated USB Type-C ports
Add device nodes and connections to support USB 3.x on the SoC's
integrated USBi Type-C ports of M2-based devices.
Each Type-C port has an Apple Type-C PHY for USB 2.0, USB 3.x,
USB4/Thunderbolt, and DisplayPort, a Synopsys Designware USB 3.x
controller, two DART iommu instances and a CD321x USB PD controller.
The port labels use Apple's established naming scheme for the ports.
Signed-off-by: Hector Martin <marcan@marcan.st> Co-developed-by: Janne Grunau <j@jannau.net> Signed-off-by: Janne Grunau <j@jannau.net> Tested-by: Sven Peter <sven@kernel.org> # M1 mac mini and macbook air Reviewed-by: Sven Peter <sven@kernel.org> Reviewed-by: Neal Gompa <neal@gompa.dev> Link: https://patch.msgid.link/20260109-apple-dt-usb-c-atc-dwc3-v1-2-ce0e92c1a016@jannau.net Signed-off-by: Sven Peter <sven@kernel.org>
Hector Martin [Fri, 9 Jan 2026 14:07:04 +0000 (15:07 +0100)]
arm64: dts: apple: t8103: Add nodes for integrated USB Type-C ports
Add device nodes and connections to support USB 3.x on the SoC's
integrated USB-C ports of M1-based devices.
Each Type-C port has an Apple Type-C PHY for USB 2.0, USB 3.x,
USB4/Thunderbolt, and DisplayPort, a Synopsys Designware USB 3.x
controller, two DART iommu instances and a CD321x USB PD controller.
The iMac variant with four USB-C ports has two SoC integrated USB-C
ports and two additional USB-C ports driven by an AsMedia PCIe USB
controller. The latter ports are not covered by this change.
The port labels use Apple's established naming scheme for the ports.
Signed-off-by: Hector Martin <marcan@marcan.st> Co-developed-by: Sven Peter <sven@kernel.org> Signed-off-by: Janne Grunau <j@jannau.net> Tested-by: Sven Peter <sven@kernel.org> # M1 mac mini and macbook air Reviewed-by: Sven Peter <sven@kernel.org> Reviewed-by: Neal Gompa <neal@gompa.dev> Link: https://patch.msgid.link/20260109-apple-dt-usb-c-atc-dwc3-v1-1-ce0e92c1a016@jannau.net Signed-off-by: Sven Peter <sven@kernel.org>
Janne Grunau [Thu, 8 Jan 2026 21:04:03 +0000 (22:04 +0100)]
arm64: dts: apple: t8103: Add ps_pmp dependency to ps_gfx
AGX appears to have a hidden communication channel to pmp, a power
management related co-processor already brought up by Apple's
bootloader. As there is not driver for this co-processor its
power-domain gets shut down after the initial boot.
This crashes the firmware running on AGX immediately.
Until there is a pmp driver and the dependency between AGX and pmp is
understood keep "ps_pmp" as dependency of "ps_gfx".
Hector Martin [Thu, 8 Jan 2026 21:04:02 +0000 (22:04 +0100)]
arm64: dts: apple: t8103: Mark ATC USB AON domains as always-on
Shutting these down breaks dwc3 init done by the firmware. We probably
never want to do this anyway. "always-on" is a plausible interpretation
of the "aon" suffix.
The t8112, t600x and t602x "ps_atc?_usb_aon" power-controller nodes are
have already "apple,always-on" properties.
Janne Grunau [Thu, 8 Jan 2026 21:04:01 +0000 (22:04 +0100)]
arm64: dts: apple: t8112-j473: Keep the HDMI port powered on
Add the display controller and DPTX phy power-domains to the framebuffer
node to keep the framebuffer and display out working after device probing
finished.
The OS has more control about the display pipeline used for the HDMI
output on M2 based devices. The HDMI output is driven by an integrated
DisplayPort to HDMI converter (Parade PS190). The DPTX phy is now
controlled by the OS and no longer by firmware running on the display
co-processor. This allows using the second display controller on the
second USB type-c port or tunneling 2 DisplayPort connections over
USB4/Thunderbolt.
The m1n1 bootloader uses the second display controller to drive the HDMI
output. Adjust for this difference compared to the notebooks as well.
Janne Grunau [Fri, 9 Jan 2026 15:25:45 +0000 (16:25 +0100)]
arm64: dts: apple: Add chassis-type property for Mac Pro
The tower and rack mount Mac Pro variants share the same .dts file and
are identical except for the chassis. There doesn't appear to be a
property in Apple's device tree to distinguish these two devices so use
"server" as chassis type which describes both if one doesn't look too
carefully.
Janne Grunau [Fri, 9 Jan 2026 15:25:44 +0000 (16:25 +0100)]
arm64: dts: apple: Add chassis-type property for Apple desktop devices
Apple's Mac mini and Studio are desktop devices. The SMBIOS has chassis
types which might be more accurate like "low profile desktop" or "mini
pc" but without clear definition what those are use plain "desktop" as
chassis-type in the root node.
arm: dts: lpc32xx: add interrupts property to Motor Control PWM
Motor Control PWM shares an interrupt line with TIMER4 on MIC interrupt
controller, the interrupt serves as period (timer limit), pulse-width (match)
and capture event interrupt.
Laurent Pinchart [Mon, 27 Oct 2025 21:56:36 +0000 (23:56 +0200)]
arm64: dts: rockchip: Add rk3588s-orangepi-cm5-base device tree
The Orange Pi CM5 Base board is a carrier board for the Orange Pi CM5
compute module. It has 3 ethernet ports, 2 USB ports, one HDMI output
and 4 CSI-2 inputs.
The device tree is split in two files, a .dtsi for the compute module
and a .dts for the carrier board. All the devices present on the carrier
board are enabled and tested, with the exception of the IR receiver due
to missing support for input capture in the PWM device's DT binding (and
driver).
This work is based on a combination of the Orange Pi 5 device tree from
the upstream kernel and the Orange Pi CM5 device tree from the BSP
kernel. All nodes and properties have been carefully checked to the best
of my abilities against the schematics of the carrier board. The
schematics of the compute module is not available publicly, so the
configuration of the PMIC hasn't been double-checked.
Laurent Pinchart [Mon, 27 Oct 2025 21:56:35 +0000 (23:56 +0200)]
dt-bindings: arm: rockchip: Add Orange Pi CM5 Base
The Orange Pi CM5 Base board is a carrier board for the Orange Pi CM5
compute module. It has 3 ethernet ports, 2 USB ports, one HDMI output
and 4 CSI-2 inputs.
Chris Morgan [Wed, 19 Nov 2025 22:55:26 +0000 (16:55 -0600)]
arm64: dts: rockchip: Add HDMI to Gameforce Ace
Add support for the HDMI port for the Gameforce Ace. The HDMI port
has no HPD pin present (the manufacturer's devicetree states the pin
is reused for an additional face button) so add the attribute of
no-hpd to poll for connected devices.
ARM: dts: lpc32xx: Add missing properties to I2S device tree nodes
Add NXP LPC32xx I2S controller device tree properties in accordance to
nxp,lpc3220-i2s.yaml.
Link to the original change:
* https://lore.kernel.org/linux-arm-kernel/20240627150046.258795-7-piotr.wojtaszczyk@timesys.com/
Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
[vzapolskiy: changes to the commit message] Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Add properties declared in the new DT binding nxp,lpc3220-dmamux.yaml
and corresponding phandles.
[vzapolskiy]:
1. rebased the change,
2. dmamux unit address shall be 0x78 instead of 0x7c,
3. removed unsupported 'dmas' properties from sd, ssp0, ssp1 and HS UARTs,
4. more non-functional updates by reordering properies,
5. minor updates to the commit message.
Link to the original change:
* https://lore.kernel.org/linux-arm-kernel/20240627150046.258795-6-piotr.wojtaszczyk@timesys.com/
Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
ARM: dts: lpc32xx: Use syscon for system control block
The clock controller is a part of NXP LPC32xx system control block (SCB),
and SCB provides a number of controllers apart of the clock controller.
[vzapolskiy]:
1. kept a simple comment,
2. renamed SoC specific compatible to 'nxp,lpc3220-scb' due to the SoC UM,
3. changed size in 'ranges', since it should cover more SCB functions,
4. updated the commit message.
Link to the original change:
* https://lore.kernel.org/linux-arm-kernel/20240627150046.258795-5-piotr.wojtaszczyk@timesys.com/
Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Kuldeep Singh [Wed, 24 Dec 2025 04:52:05 +0000 (06:52 +0200)]
ARM: dts: lpc32xx: Update spi clock properties
PL022 binding require two clocks to be defined but NXP LPC32xx platform
doesn't comply with the bindings and define only one clock i.e apb_pclk.
Update SPI clocks and clocks-names property by adding appropriate clock
reference to make it compliant with the bindings.
Noteworthy, strictly speaking the change tackles DT ABI by changing
the order in the list of clock-names property values, however this level
of impact is considered as acceptable.
Cc: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Kuldeep Singh <singh.kuldeep87k@gmail.com>
[vzapolskiy: rebased and minor update to the commit message] Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
ARM: dts: aspeed: ibm: Use non-deprecated AT25 properties
The at25,* properties have been deprecated since 2012. These platforms
weren't upstream until 2020 and 2023, so it should be safe to switch
over to the "new" properties and just drop the deprecated ones.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Document ASRock Rack ALTRAD8 (ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q)
compatibles.
Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Tan Siewert <tan.siewert@hetzner.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251218161816.38155-2-rebecca@bsdio.com
[arj: Drop erroneous Tested-by tag from Tan] Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Cosmo Chou [Fri, 19 Dec 2025 06:29:48 +0000 (14:29 +0800)]
ARM: dts: aspeed: bletchley: Remove try-power-role from connectors
Remove the "try-power-role = sink" property from all USB-C connectors.
The try mechanism is unnecessary and wastes time during connection.
Since power-role = "dual" is already configured, standard USB PD
negotiation is sufficient and more efficient.
Signed-off-by: Cosmo Chou <chou.cosmo@gmail.com> Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Peter Shen [Fri, 19 Dec 2025 09:16:32 +0000 (17:16 +0800)]
ARM: dts: aspeed: Add Facebook Anacapa platform
The Meta Anacapa BMC is the DC-SCM (Data Center Secure Control
Module) controller for the Meta OCP Open Rack Wide (ORW) compute tray.
This platform is a key component of the AMD Helios AI rack reference
design system, designed for next-generation AI workloads.
The BMC utilizes the Aspeed AST2600 SoC to manage the compute tray, which
contains up to 4 AMD Instinct MI450 Series GPUs (connected via a Broadcom
OCP NIC) and host CPUs. Its primary role is to provide essential system
control, power sequencing, and telemetry reporting for the compute complex
via the OpenBMC software stack.
For more detail on the AMD Helios reference design:
Peter Shen [Fri, 19 Dec 2025 09:16:31 +0000 (17:16 +0800)]
dt-bindings: arm: aspeed: Add compatible for Facebook Anacapa BMC
This patch adds the compatible string for the Facebook Anacapa BMC
which uses an Aspeed AST2600 SoC. This is required before adding
the board's device tree source file.
Arnd Bergmann [Wed, 7 Jan 2026 17:12:47 +0000 (18:12 +0100)]
Merge tag 'renesas-dts-for-v6.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.20
- Add USB3.2 host and more RSCI serial support for the RZ/G3E SoC and
the RZ/G3E SMARC EVK board,
- Add display and USB3.0 host support for the RZ/V2H and RZ/V2N SoCs
and their EVK boards,
- Add SPI NOR Flash support for the Yuridenki-Shokai Kakip board,
- Add PCIe support for the RZ/G3S SoC and the RZ/G3S SMARC EVK board,
- Add SPI, interrupt controller, and DMAC support for the RZ/T2H,
RZ/N2H, and RZ/V2N SoCs,
- Add NMI wakeup button support for the RZ/V2N EVK board,
- Add thermal support for the RZ/V2N SoC,
- Add system watchdog timer support for R-Car V3H, which is reserved
for secure firmware,
- Add window watchdog timer support for R-Car V3M, V3H, and Gen4 SoCs,
- Miscellaneous fixes and improvements.
Arnd Bergmann [Wed, 7 Jan 2026 17:05:51 +0000 (18:05 +0100)]
Merge tag 'aspeed-6.20-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
First batch of ASPEED Arm devicetree changes for 6.20
New platforms:
- NVIDIA MSX4 BMC
The NVIDIA MSX4 HPM (host platform module) is a reference board for
managing up to 8 PCIe connected NVIDIA GPUs via ConnectX-8 (CX8)
SuperNICs. The BMC manages all GPUs and CX8s for both telemetry and
firmware update via MCTP over USB. The host CPUs are dual socket Intel
Granite Rapids processors.
Heiko Stuebner [Tue, 12 Aug 2025 08:52:13 +0000 (10:52 +0200)]
arm64: dts: rockchip: enable NPU on rk3588-jaguar
Enable the NPU cores and their mmus and wire up the supply-regulator.
The regulator itself was already defined, but it does not need to be
always on - the npu can control it.
Heiko Stuebner [Tue, 12 Aug 2025 08:52:12 +0000 (10:52 +0200)]
arm64: dts: rockchip: enable NPU on rk3588-tiger
Enable the NPU cores and their mmus and wire up the supply-regulator.
The regulator itself was already defined, but it does not need to be
always on - the npu can control it.
Ricardo Pardini [Thu, 1 Jan 2026 06:43:11 +0000 (07:43 +0100)]
arm64: dts: rockchip: Enable the NPU on Turing RK1
Enable the NPU on Turing RK1.
The regulator vdd_npu_s0 was already in place; since
the NPU power domain supply is now described, remove the
regulator's always-on.
Ricardo Pardini [Thu, 1 Jan 2026 06:43:10 +0000 (07:43 +0100)]
arm64: dts: rockchip: Enable the NPU on FriendlyElec CM3588
Enable the NPU on FriendlyElec CM3588.
The regulator vdd_npu_s0 was already in place; since
the NPU power domain supply is now described, remove the
regulator's always-on.
Ricardo Pardini [Thu, 1 Jan 2026 06:43:09 +0000 (07:43 +0100)]
arm64: dts: rockchip: Enable the NPU on NanoPC T6/T6-LTS
Enable the NPU on FriendlyElec NanoPC T6/T6-LTS boards.
The regulator vdd_npu_s0 was already in place; since
the NPU power domain supply is now described, remove the
regulator's always-on.
Ondrej Jirman [Fri, 26 Dec 2025 03:43:20 +0000 (19:43 -0800)]
arm64: dts: rockchip: Add light/proximity sensor to Pinephone Pro
Pinephone Pro uses STK3311 according to the schematics.
Tests:
~ $ monitor-sensor --light
// When the sensor is exposed, it get's fluctating values such as
Light changed: 1.800000 (lux)
Light changed: 1.700000 (lux)
Light changed: 1.800000 (lux)
Light changed: 1.700000 (lux)
Light changed: 1.600000 (lux)
Light changed: 1.100000 (lux)
// When covering the sensor, it prints a low value and stops printing
Light changed: 0.200000 (lux)
~ $ monitor-sensor --proximity
// When it goes away from an object
Proximity value changed: 0
// When it comes near an object
Proximity value changed: 1
Wolfram Sang [Mon, 15 Dec 2025 03:13:19 +0000 (12:13 +0900)]
arm64: dts: renesas: condor/v3hsk: Mark SWDT as reserved
This watchdog can't be used with Linux because the firmware needs it on
R-Car V3H boards. Sadly, it doesn't mark the node as reserved, so this
is added manually here.
Ovidiu Panait [Tue, 9 Dec 2025 09:11:15 +0000 (09:11 +0000)]
arm64: dts: renesas: r9a09g056: Add TSU nodes
The Renesas RZ/V2N SoC includes a Thermal Sensor Unit (TSU) block designed
to measure the junction temperature. The device provides real-time
temperature measurements for thermal management, utilizing two dedicated
channels for temperature sensing:
- TSU0, which is located near the DRP-AI block
- TSU1, which is located near the CPU and DRP-AI block
Since TSU1 is physically closer the CPU and the highest temperature
spot, it is used for CPU throttling through a passive trip and cooling
map. TSU0 is configured only with a critical trip.
Add TSU nodes along with thermal zones and keep them enabled in the SoC
DTSI.
Cosmin Tanislav [Mon, 1 Dec 2025 11:29:33 +0000 (13:29 +0200)]
arm64: dts: renesas: r9a09g087: Add ICU support
The Renesas RZ/N2H (R9A09G087) SoC has an Interrupt Controller (ICU)
block that routes external interrupts to the GIC's SPIs, with the
ability of level-translation, and can also produce software and
aggregate error interrupts.
Cosmin Tanislav [Mon, 1 Dec 2025 11:29:32 +0000 (13:29 +0200)]
arm64: dts: renesas: r9a09g077: Add ICU support
The Renesas RZ/T2H (R9A09G077) SoC has an Interrupt Controller (ICU)
block that routes external interrupts to the GIC's SPIs, with the
ability of level-translation, and can also produce software and
aggregate error interrupts.
Biju Das [Sat, 29 Nov 2025 18:51:57 +0000 (18:51 +0000)]
arm64: dts: renesas: renesas-smarc2: Move aliases to board DTS
SMARC2 board dtsi is common for multiple SoCs. So Move aliases
to board DTS as SoC may have different IPs for a given alias.
eg: RZ/G3S does not have RSCI interface.
Lad Prabhakar [Tue, 25 Nov 2025 22:45:33 +0000 (22:45 +0000)]
arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add NMI wakeup button support
Add support for the NMI connected user pushbutton on the RZ/V2N EVK.
The button is wired to the SoC NMI input and can be used to wake the
system from low-power states.
Versa3 clock generator available on RZ/G3S SMARC Module provides the
reference clock for SoC PCIe interface. Update the device tree to reflect
this connection.
Lad Prabhakar [Wed, 19 Nov 2025 11:05:03 +0000 (11:05 +0000)]
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB3.0 PHYs and xHCI controllers
Enable the USB3.0 (CH0) and USB3.1 (CH1) host controllers on the RZ/V2H
Evaluation Kit. The CN4 stacked connector on the EVK provides access to
both channels, with CH0 corresponding to USB3.0 and CH1 to USB3.1.
projects / thirdparty / kernel / linux.git / log
