c++: modules and debug marker stmts

21_strings/basic_string/operations/contains/nonnull.cc was failing because
the module was built with debug markers and the testcase was built not
expecting debug markers, so we crashed in lower_stmt.  Let's accommodate
this by discarding debug marker statements we don't want.

gcc/cp/ChangeLog:

* module.cc (trees_in::core_vals) [STATEMENT_LIST]: Skip
DEBUG_BEGIN_STMT if !MAY_HAVE_DEBUG_MARKER_STMTS.

c++: modules and tsubst_friend_class

In 20_util/function_objects/mem_fn/constexpr.cc we start to instantiate
_Mem_fn_base's friend declaration of _Bind_check_arity before we've loaded
the namespace-scope declaration, so lookup_imported_hidden_friend doesn't
find it.  But then we load the namespace-scope declaration in
lookup_template_class during substitution, and so when we get around to
pushing the result of substitution, they conflict.  Fixed by calling
lazy_load_pendings in lookup_imported_hidden_friend.

gcc/cp/ChangeLog:

* name-lookup.cc (lookup_imported_hidden_friend): Call
lazy_load_pendings.

AVR: target/117726 - Better optimizations of ASHIFT:SI insns.

This patch improves the 4-byte ASHIFT insns.
1) It adds a "r,r,C15" alternative for improved long << 15.
2) It adds 3-operand alternatives (depending on options) and
   splits them after peephole2 / before avr-fuse-move into
   a 3-operand byte shift and a 2-operand residual bit shift.
For better control, it introduces new option -msplit-bit-shift
that's activated at -O2 and higher per default.  2) is even
performed with -Os, but not with -Oz.

PR target/117726
gcc/
* config/avr/avr.opt (-msplit-bit-shift): Add new optimization option.
* common/config/avr/avr-common.cc (avr_option_optimization_table)
[OPT_LEVELS_2_PLUS]: Turn on -msplit-bit-shift.
* config/avr/avr.h (machine_function.n_avr_fuse_add_executed):
New bool component.
* config/avr/avr.md (attr "isa") <2op, 3op>: Add new values.
(attr "enabled"): Handle them.
(ashlsi3, *ashlsi3, *ashlsi3_const): Add "r,r,C15" alternative.
Add "r,0,C4l" and "r,r,C4l" alternatives (depending on 2op / 3op).
(define_split) [avr_split_bit_shift]: Add 2 new ashift:ALL4 splitters.
(define_peephole2) [ashift:ALL4]: Add (match_dup 3) so that the scratch
won't overlap with the output operand of the matched insn.
(*ashl<mode>3_const_split): Remove unused ashift:ALL4 splitter.
* config/avr/avr-passes.cc (emit_valid_insn)
(emit_valid_move_clobbercc): Move out of anonymous namespace.
(make_avr_pass_fuse_add) <gate>: Don't override.
<execute>: Set n_avr_fuse_add_executed according to
func->machine->n_avr_fuse_add_executed.
(pass_data avr_pass_data_split_after_peephole2): New object.
(avr_pass_split_after_peephole2): New rtl_opt_pass.
(avr_emit_shift): New static function.
(avr_shift_is_3op, avr_split_shift_p, avr_split_shift)
(make_avr_pass_split_after_peephole2): New functions.
* config/avr/avr-passes.def (avr_pass_split_after_peephole2):
Insert new pass after pass_peephole2.
* config/avr/avr-protos.h
(n_avr_fuse_add_executed, avr_shift_is_3op, avr_split_shift_p)
(avr_split_shift, avr_optimize_size_level)
(make_avr_pass_split_after_peephole2): New prototypes.
* config/avr/avr.cc (n_avr_fuse_add_executed): New global variable.
(avr_optimize_size_level): New function.
(avr_set_current_function): Set n_avr_fuse_add_executed
according to cfun->machine->n_avr_fuse_add_executed.
(ashlsi3_out) [case 15]: Output optimized code for this offset.
(avr_rtx_costs_1) [ASHIFT, SImode]: Adjust costs of oggsets 15, 16.
* config/avr/constraints.md (C4a, C4r, C4r): New constraints.
* pass_manager.h (pass_manager): Adjust comments.

AVR: Fix a nit in avr-passes.cc::absint_t.dump().

gcc/
* config/avr/avr-passes.cc (absint_t::dump): Fix missing
newline in dump.

[RISC-V][PR target/116590] Avoid emitting multiple instructions from fmacc patterns

So much like my patch from last week, this removes alternatives that
create multiple instructions that we really should have never needed.

In this case it fixes one of two bugs in pr116590.  In particular we
don't want vmvNr instructions for thead-vector.  Those instructions were
emitted as part of those two instruction sequences.

I've tested this in my tester and assuming the pre-commit tester is
happy, I'll push it to the trunk.

PR target/116590
gcc
* config/riscv/vector.md (pred_mul_<optab>mode_undef): Drop
unnecessary alternatives.
(pred_<madd_msub><mode>): Likewise.
(pred_<macc_msac><mode>): Likewise.
(pred_<madd_msub><mode>_scalar): Likewise.
(pred_<macc_msac><mode>_scalar): Likewise.
(pred_mul_neg_<optab><mode>_undef): Likewise.
(pred_<nmsub_nmadd><mode>): Likewise.
(pred_<nmsac_nmacc><mode>): Likewise.
(pred_<nmsub_nmadd><mode>_scalar): Likewise.
(pred_<nmsac_nmacc><mode>_scalar): Likewise.

gcc/testsuite
* gcc.target/riscv/pr116590.c: New test.

Match: Refactor the unsigned SAT_ADD match pattern [NFC]

This patch would like to refactor the unsigned SAT_ADD pattern by:
* Extract type check outside.
* Extract common sub pattern.
* Re-arrange the related match pattern forms together.
* Remove unnecessary helper pattern matches.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.
* The x86 bootstrap test.
* The x86 fully regression test.

gcc/ChangeLog:

* match.pd: Refactor sorts of unsigned SAT_ADD match pattern.

Signed-off-by: Pan Li <pan2.li@intel.com>
Signed-off-by: Pan Li <pan2.li@intel.com>

middle-end: Pass along SLP node when costing vector loads/stores

With the support to SLP only we now pass the VMAT through the SLP node, however
the majority of the costing calls inside vectorizable_load and
vectorizable_store do no pass the SLP node along.  Due to this the backend costing
never sees the VMAT for these cases anymore.

Additionally the helper around record_stmt_cost when both SLP and stmt_vinfo are
passed would only pass the SLP node along.  However the SLP node doesn't contain
all the info available in the stmt_vinfo and we'd have to go through the
SLP_TREE_REPRESENTATIVE anyway.  As such I changed the function to just Always
pass both along.  Unlike the VMAT changes, I don't believe there to be a
correctness issue here but would minimize the number of churn in the backend
costing until vectorizer costing as a whole is revisited in GCC 16.

These changes re-enable the cost model on AArch64 and also correctly find the
VMATs on loads and stores fixing testcases such as sve_iters_low_2.c.

gcc/ChangeLog:

* tree-vect-data-refs.cc (vect_get_data_access_cost): Pass NULL for SLP
node.
* tree-vect-stmts.cc (record_stmt_cost): Expose.
(vect_get_store_cost, vect_get_load_cost): Extend with SLP node.
(vectorizable_store, vectorizable_load): Pass SLP node to all costing.
* tree-vectorizer.h (record_stmt_cost): Always pass both SLP node and
stmt_vinfo to costing.
(vect_get_load_cost, vect_get_store_cost): Extend with SLP node.

Use decl size in Solaris ASM_DECLARE_OBJECT_NAME [PR102296]

Solaris has modified versions of ASM_DECLARE_OBJECT_NAME on both i386
and sparc.  When

commit ce597aedd79e646c4a5517505088d380239cbfa5
Author: Ilya Enkovich <ilya.enkovich@intel.com>
Date:   Thu Aug 7 08:04:55 2014 +0000

    elfos.h (ASM_DECLARE_OBJECT_NAME): Use decl size instead of type size.

was applied, those were missed.  At the same time, the testcase was
restricted to Linux though there's nothing Linux-specific in there, so
the error remained undetected.

This patch fixes the definitions to match elfos.h and enables the test
on Solaris, too.

Bootstrapped without regressions on i386-pc-solaris2.11 and
sparc-sun-solaris2.11.

2024-11-19  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

gcc/testsuite:
PR target/102296
* gcc.target/i386/struct-size.c: Enable on *-*-solaris*.

gcc:
PR target/102296
* config/i386/sol2.h (ASM_DECLARE_OBJECT_NAME): Use decl size
instead of type size.
* config/sparc/sol2.h (ASM_DECLARE_OBJECT_NAME): Likewise.

forwprop: Try to blend two isomorphic VEC_PERM sequences

This extends forwprop by yet another VEC_PERM optimization:
It attempts to blend two isomorphic vector sequences by using the
redundancy in the lane utilization in these sequences.
This redundancy in lane utilization comes from the way how specific
scalar statements end up vectorized: two VEC_PERMs on top, binary operations
on both of them, and a final VEC_PERM to create the result.
Here is an example of this sequence:

  v_in = {e0, e1, e2, e3}
  v_1 = VEC_PERM <v_in, v_in, {0, 2, 0, 2}>
  // v_1 = {e0, e2, e0, e2}
  v_2 = VEC_PERM <v_in, v_in, {1, 3, 1, 3}>
  // v_2 = {e1, e3, e1, e3}

  v_x = v_1 + v_2
  // v_x = {e0+e1, e2+e3, e0+e1, e2+e3}
  v_y = v_1 - v_2
  // v_y = {e0-e1, e2-e3, e0-e1, e2-e3}

  v_out = VEC_PERM <v_x, v_y, {0, 1, 6, 7}>
  // v_out = {e0+e1, e2+e3, e0-e1, e2-e3}

To remove the redundancy, lanes 2 and 3 can be freed, which allows to
change the last statement into:
  v_out' = VEC_PERM <v_x, v_y, {0, 1, 4, 5}>
  // v_out' = {e0+e1, e2+e3, e0-e1, e2-e3}

The cost of eliminating the redundancy in the lane utilization is that
lowering the VEC PERM expression could get more expensive because of
tighter packing of the lanes.  Therefore this optimization is not done
alone, but in only in case we identify two such sequences that can be
blended.

Once all candidate sequences have been identified, we try to blend them,
so that we can use the freed lanes for the second sequence.
On success we convert 2x (2x BINOP + 1x VEC_PERM) to
2x VEC_PERM + 2x BINOP + 2x VEC_PERM traded for 4x VEC_PERM + 2x BINOP.

The implemented transformation reuses (rewrites) the statements
of the first sequence and the last VEC_PERM of the second sequence.
The remaining four statements of the second statment are left untouched
and will be eliminated by DCE later.

This targets x264_pixel_satd_8x4, which calculates the sum of absolute
transformed differences (SATD) using Hadamard transformation.
We have seen 8% speedup on SPEC's x264 on a 5950X (x86-64) and 7%
speedup on an AArch64 machine.

Bootstrapped and reg-tested on x86-64 and AArch64 (all languages).

gcc/ChangeLog:

* tree-ssa-forwprop.cc (struct _vec_perm_simplify_seq): New data
structure to store analysis results of a vec perm simplify sequence.
(get_vect_selector_index_map): Helper to get an index map from the
provided vector permute selector.
(recognise_vec_perm_simplify_seq): Helper to recognise a
vec perm simplify sequence.
(narrow_vec_perm_simplify_seq): Helper to pack the lanes more
tight.
(can_blend_vec_perm_simplify_seqs_p): Test if two vec perm
sequences can be blended.
(calc_perm_vec_perm_simplify_seqs): Helper to calculate the new
permutation indices.
(blend_vec_perm_simplify_seqs): Helper to blend two vec perm
simplify sequences.
(process_vec_perm_simplify_seq_list): Helper to process a list
of vec perm simplify sequences.
(append_vec_perm_simplify_seq_list): Helper to add a vec perm
simplify sequence to the list.
(pass_forwprop::execute): Integrate new functionality.

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/satd-hadamard.c: New test.
* gcc.dg/tree-ssa/vector-10.c: New test.
* gcc.dg/tree-ssa/vector-8.c: New test.
* gcc.dg/tree-ssa/vector-9.c: New test.
* gcc.target/aarch64/sve/satd-hadamard.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

apx-ndd-tls-1[ab].c: Add -std=gnu17

Since GCC 15 defaults to -std=gnu23, add -std=gnu17 to apx-ndd-tls-1[ab].c
to avoid:

gcc.target/i386/apx-ndd-tls-1a.c: In function ‘k’:
gcc.target/i386/apx-ndd-tls-1a.c:29:7: error: too many arguments to function ‘l’
gcc.target/i386/apx-ndd-tls-1a.c:25:5: note: declared here

* gcc.target/i386/apx-ndd-tls-1a.c: -std=gnu17.
* gcc.target/i386/apx-ndd-tls-1b.c: Likewise.

Signed-off-by: H.J. Lu <hjl.tools@gmail.com>

libgomp: testsuite: Fix libgomp.c/alloc-pinned-3.c etc. for C23 on non-Linux

Since the switch to a C23 default, three libgomp tests FAIL on Solaris:

FAIL: libgomp.c/alloc-pinned-3.c (test for excess errors)
UNRESOLVED: libgomp.c/alloc-pinned-3.c compilation failed to produce executable
FAIL: libgomp.c/alloc-pinned-4.c (test for excess errors)
UNRESOLVED: libgomp.c/alloc-pinned-4.c compilation failed to produce executable
FAIL: libgomp.c/alloc-pinned-6.c (test for excess errors)
UNRESOLVED: libgomp.c/alloc-pinned-6.c compilation failed to produce executable

Excess errors:
/vol/gcc/src/hg/master/local/libgomp/testsuite/libgomp.c/alloc-pinned-3.c:104:3: error: too many arguments to function 'set_pin_limit'

Fixed by adding the missing size argument to the stub functions.

Tested on i386-pc-solaris2.11 and sparc-sun-solaris2.11.

2024-11-20  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

libgomp:
* testsuite/libgomp.c/alloc-pinned-3.c [!__linux__]
(set_pin_limit): Add size arg.
* testsuite/libgomp.c/alloc-pinned-4.c [!__linux__]
(set_pin_limit): Likewise.
* testsuite/libgomp.c/alloc-pinned-6.c [!__linux__]
(set_pin_limit): Likewise.

include: Add new post-DWARF 5 DW_LANG_* enumerators

DWARF changed the language code assignment to be on a web page and
after DWARF 5 has been published already 27 codes have been assigned.
We have some of those already in the header, but most of them were missing,
including one added just yesterday (DW_LANG_C23).
Note, this is really post-DWARF 5 stuff rather than DWARF 6, because
DWARF 6 plans to switch from DW_AT_language to DW_AT_language_{name,version}
pair where we'll say DW_LNAME_C with 202311 version instead of this.

2024-11-21  Jakub Jelinek  <jakub@redhat.com>

* dwarf2.h (enum dwarf_source_language): Add comment where
the post DWARF 5 additions start.  Refresh list from
https://dwarfstd.org/languages.html.

tree-optimization/117720 - check alignment for VMAT_STRIDED_SLP

While vectorizable_store was already checking alignment requirement
of the stores and fall back to elementwise accesses if not honored
the vectorizable_load path wasn't doing this.  After the previous
change to disregard alignment checking for VMAT_STRIDED_SLP in
get_group_load_store_type this now tripped on power.

PR tree-optimization/117720
* tree-vect-stmts.cc (vectorizable_load): For VMAT_STRIDED_SLP
verify the choosen load type is OK with regard to alignment.

c-family, docs: Adjust descriptions/documentation for C23 publication

As C23 has been published already https://www.iso.org/standard/82075.html
we don't need to say that it is expected to be published etc.

Furthermore, standards.texi was still documenting that -std=gnu17
is the default.

2024-11-21  Jakub Jelinek  <jakub@redhat.com>

gcc/
* doc/invoke.texi (-std=c23): Adjust documentation for
publication of the ISO/IEC 9899:2024 standard.
* doc/standards.texi: Likewise.  Document -std=gnu17 and
-std=gnu23 options.  Mention that -std=gnu23 rather than
-std=gnu17 is now the default for C.
gcc/c-family/
* c.opt (std=c23, std=gnu23, std=iso9899:2024): Adjust description
for publication of the ISO/IEC 9899:2024 standard.

phiopt: Improve spaceship_replacement for HONOR_NANS [PR117612]

The following patch optimizes spaceship followed by comparisons of the
spaceship value even for floating point spaceship when NaNs can appear.
operator<=> for this emits roughly
signed char c; if (i == j) c = 0; else if (i < j) c = -1; else if (i > j) c = 1; else c = 2;
and I believe the
/* The optimization may be unsafe due to NaNs.  */
comment just isn't true.
Sure, the i == j comparison doesn't raise exceptions on qNaNs, but if
one of the operands is qNaN, then i == j is false and i < j or i > j
is then executed and raises exceptions even on qNaNs.
And we can safely optimize say
c == -1 comparison after the above into i < j, that also raises
exceptions like before and handles NaNs the same way as the original.
The only unsafe transormation would be c == 0 or c != 0, turning it
into i == j or i != j wouldn't raise exception, so I'm not doing that
optimization (but other parts of the compiler optimize the i < j comparison
away anyway).

Anyway, to match the HONOR_NANS case, we need to verify that the
second comparison has true edge to the phi_bb (yielding there -1 or 1),
it can't be the false edge because when NaNs are honored, the false
edge is for both the case where the inverted comparison is true or when
one of the operands is NaN.  Similarly we need to ensure that the two
non-equality comparisons are the opposite, while for -ffast-math we can in
some cases get one comparison x >= 5.0 and the other x > 5.0 and it is fine,
because NaN is UB, when NaNs are honored, they must be different to leave
the unordered case with 2 value as the last one remaining.
The patch also punts if HONOR_NANS and the phi has just 3 arguments instead
of 4.
When NaNs are honored, we also in some cases need to perform some comparison
and then invert its result (so that exceptions are properly thrown and we
get the correct result).

2024-11-21  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/94589
PR tree-optimization/117612
* tree-ssa-phiopt.cc (spaceship_replacement): Handle
HONOR_NANS (TREE_TYPE (lhs1)) case when possible.

* gcc.dg/pr94589-5.c: New test.
* gcc.dg/pr94589-6.c: New test.
* g++.dg/opt/pr94589-5.C: New test.
* g++.dg/opt/pr94589-6.C: New test.

phiopt: Fix a pasto in spaceship_replacement [PR117612]

When working on the PR117612 fix, I've noticed a pasto in
tree-ssa-phiopt.cc (spaceship_replacement).
The code is
      if (absu_hwi (tree_to_shwi (arg2)) != 1)
        return false;
      if (e1->flags & EDGE_TRUE_VALUE)
        {
          if (tree_to_shwi (arg0) != 2
              || absu_hwi (tree_to_shwi (arg1)) != 1
              || wi::to_widest (arg1) == wi::to_widest (arg2))
            return false;
        }
      else if (tree_to_shwi (arg1) != 2
               || absu_hwi (tree_to_shwi (arg0)) != 1
               || wi::to_widest (arg0) == wi::to_widest (arg1))
        return false;
where arg{0,1,2,3} are PHI args and wants to ensure that if e1 is a
true edge, then arg0 is 2 and one of arg{1,2} is -1 and one is 1,
otherwise arg1 is 2 and one of arg{0,2} is -1 and one is 1.
But due to pasto in the latte case doesn't verify that arg0
is different from arg2, it could be both -1 or both 1 and we wouldn't
punt.  The wi::to_widest (arg0) == wi::to_widest (arg1) test
is always false when we've made sure in the earlier conditions that
arg1 is 2 and arg0 is -1 or 1, so never 2.

2024-11-21  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/94589
PR tree-optimization/117612
* tree-ssa-phiopt.cc (spaceship_replacement): Fix up
a pasto in check when arg1 is 2.

c: Add u{,l,ll,imax}abs builtins [PR117024]

The following patch adds u{,l,ll,imax}abs builtins, which just fold
to ABSU_EXPR, similarly to how {,l,ll,imax}abs builtins fold to
ABS_EXPR.

2024-11-21  Jakub Jelinek  <jakub@redhat.com>

PR c/117024
gcc/
* coretypes.h (enum function_class): Add function_c2y_misc
enumerator.
* builtin-types.def (BT_FN_UINTMAX_INTMAX, BT_FN_ULONG_LONG,
BT_FN_ULONGLONG_LONGLONG): New DEF_FUNCTION_TYPE_1s.
* builtins.def (DEF_C2Y_BUILTIN): Define.
(BUILT_IN_UABS, BUILT_IN_UIMAXABS, BUILT_IN_ULABS,
BUILT_IN_ULLABS): New builtins.
* builtins.cc (fold_builtin_abs): Handle also folding of u*abs
to ABSU_EXPR.
(fold_builtin_1): Handle BUILT_IN_U{,L,LL,IMAX}ABS.
gcc/lto/ChangeLog:
* lto-lang.cc (flag_isoc2y): New variable.
gcc/ada/ChangeLog:
* gcc-interface/utils.cc (flag_isoc2y): New variable.
gcc/testsuite/
* gcc.c-torture/execute/builtins/lib/abs.c (uintmax_t): New typedef.
(uabs, ulabs, ullabs, uimaxabs): New functions.
* gcc.c-torture/execute/builtins/uabs-1.c: New test.
* gcc.c-torture/execute/builtins/uabs-1.x: New file.
* gcc.c-torture/execute/builtins/uabs-1-lib.c: New file.
* gcc.c-torture/execute/builtins/uabs-2.c: New test.
* gcc.c-torture/execute/builtins/uabs-2.x: New file.
* gcc.c-torture/execute/builtins/uabs-2-lib.c: New file.
* gcc.c-torture/execute/builtins/uabs-3.c: New test.
* gcc.c-torture/execute/builtins/uabs-3.x: New test.
* gcc.c-torture/execute/builtins/uabs-3-lib.c: New test.

rs6000: Adjust FLOAT128 signbit2 expander for P8 LE [PR114567]

As the associated test case shows, signbit generated assembly
is sub-optimal for _Float128 argument from memory on P8 LE.
On P8 LE, p8swap pass puts an explicit AND -16 on the memory,
which causes mode_dependent_address_p considers it's invalid
to change its mode and combine fails to make use of the
existing pattern signbit<SIGNBIT:mode>2_dm_mem.  Considering
it's always more efficient to make use of 8 bytes load and
shift on P8 LE, this patch is to adjust the current expander
and treat it specially.

PR target/114567

gcc/ChangeLog:

* config/rs6000/rs6000.md (expander signbit<FLOAT128:mode>2): Adjust.
(*signbit<mode>2_dm_mem): Rename to ...
(signbit<mode>2_dm_mem): ... this.

gcc/testsuite/ChangeLog:

* gcc.target/powerpc/pr114567.c: New test.

rs6000: Use standard name {add,sub}v1ti3 for altivec_v{add,sub}uqm

This patch is to adjust define_insn altivec_v{add,sub}uqm
with standard names, as the associated test case shows, w/o
this patch, it ends up with scalar {add,subf}c/{add,subf}e,
the standard names help to exploit v{add,sub}uqm.

gcc/ChangeLog:

* config/rs6000/altivec.md (altivec_vadduqm): Rename to ...
(addv1ti3): ... this.
(altivec_vsubuqm): Rename to ...
(subv1ti3): ... this.
* config/rs6000/rs6000-builtins.def (__builtin_altivec_vadduqm):
Replace bif expander altivec_vadduqm with addv1ti3.
(__builtin_altivec_vsubuqm): Replace bif expander altivec_vsubuqm with
subv1ti3.

gcc/testsuite/ChangeLog:

* gcc.target/powerpc/p8vector-int128-3.c: New test.

rs6000: Remove entry for V1TImode from VI_unit

When making a patch to adjust VECTOR_P8_VECTOR rs6000_vector
enum, I noticed that V1TImode's mode attribute in VI_unit
VECTOR_UNIT_ALTIVEC_P (V1TImode) is never true, since
VECTOR_UNIT_ALTIVEC_P checks if vector_unit[V1TImode] is
equal to VECTOR_ALTIVEC, but vector_unit[V1TImode] can only
be VECTOR_NONE or VECTOR_P8_VECTOR, there is no chance to be
VECTOR_ALTIVEC:
  rs6000_vector_unit[V1TImode]
      = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;

By checking all uses of VI_unit, the used mode iterator is
one of VI2, VI, VP_small and VP, none of them has V1TImode,
so the entry for V1TImode is useless.  I guessed it was
designed to have one mode attribute to cover all integer
vector modes, but later we separated V1TI handlings to its
own patterns (those guarded with TARGET_VADDUQM).  Anyway,
this patch is to remove this useless and confusing entry.

gcc/ChangeLog:

* config/rs6000/altivec.md (mode attr for V1TI in VI_unit): Remove.

rs6000: Add veqv support to *eqv<mode>3_internal1

When making patch to replace TARGET_P8_VECTOR, I noticed
for *eqv<BOOL_128:mode>3_internal1 unlike the other logical
operations, we only exploited the vsx version.  I think it
is an oversight, this patch is to consider veqv as well.

gcc/ChangeLog:

* config/rs6000/rs6000.md (*eqv<BOOL_128:mode>3_internal1): Generate
insn veqv if TARGET_ALTIVEC and operands are altivec_register_operand.

rs6000: Remove ISA_3_0_MASKS_IEEE and check P9_VECTOR instead

When working to get rid of mask bit OPTION_MASK_P8_VECTOR,
I noticed that the check on ISA_3_0_MASKS_IEEE is actually
to check TARGET_P9_VECTOR, since we check all three mask
bits together and p9 vector guarantees p8 vector and vsx
should be enabled.  So this patch is to adjust this first
as preparatory patch for the following patch to change
all uses of OPTION_MASK_P8_VECTOR and TARGET_P8_VECTOR.

gcc/ChangeLog:

* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_IEEE): Remove.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Replace
ISA_3_0_MASKS_IEEE check with TARGET_P9_VECTOR.

rs6000: Simplify some conditions or code related to TARGET_DIRECT_MOVE

When I was making a patch to rework TARGET_P8_VECTOR, I
noticed that there are some redundant checks and dead code
related to TARGET_DIRECT_MOVE, so I made this patch as one
separated preparatory patch, it consists of:
  - Check either TARGET_DIRECT_MOVE or TARGET_P8_VECTOR only
    according to the context, rather than checking both of
    them since they are actually the same (TARGET_DIRECT_MOVE
    is defined as TARGET_P8_VECTOR).
  - Simplify TARGET_VSX && TARGET_DIRECT_MOVE as
    TARGET_DIRECT_MOVE since direct move ensures VSX enabled.
  - Replace some TARGET_POWERPC64 && TARGET_DIRECT_MOVE as
    TARGET_DIRECT_MOVE_64BIT to simplify it.
  - Remove some dead code guarded with TARGET_DIRECT_MOVE
    but the condition never holds here.

gcc/ChangeLog:

* config/rs6000/rs6000.cc (rs6000_option_override_internal): Simplify
TARGET_P8_VECTOR && TARGET_DIRECT_MOVE as TARGET_P8_VECTOR.
(rs6000_output_move_128bit): Simplify TARGET_VSX && TARGET_DIRECT_MOVE
as TARGET_DIRECT_MOVE.
* config/rs6000/rs6000.h (TARGET_XSCVDPSPN): Simplify conditions
TARGET_DIRECT_MOVE || TARGET_P8_VECTOR as TARGET_P8_VECTOR.
(TARGET_XSCVSPDPN): Likewise.
(TARGET_DIRECT_MOVE_128): Simplify TARGET_DIRECT_MOVE &&
TARGET_POWERPC64 as TARGET_DIRECT_MOVE_64BIT.
(TARGET_VEXTRACTUB): Likewise.
(TARGET_DIRECT_MOVE_64BIT): Simplify TARGET_P8_VECTOR &&
TARGET_DIRECT_MOVE as TARGET_DIRECT_MOVE.
* config/rs6000/rs6000.md (signbit<mode>2, @signbit<mode>2_dm,
*signbit<mode>2_dm_mem, floatsi<mode>2_lfiwax,
floatsi<SFDF:mode>2_lfiwax_<QHI:mode>_mem_zext,
floatunssi<mode>2_lfiwzx, float<QHI:mode><SFDF:mode>2,
*float<QHI:mode><SFDF:mode>2_internal, floatuns<QHI:mode><SFDF:mode>2,
*floatuns<QHI:mode><SFDF:mode>2_internal, p8_mtvsrd_v16qidi2,
p8_mtvsrd_df, p8_xxpermdi_<mode>, reload_vsx_from_gpr<mode>,
p8_mtvsrd_sf, reload_vsx_from_gprsf, p8_mfvsrd_3_<mode>,
reload_gpr_from_vsx<mode>, reload_gpr_from_vsxsf, unpack<mode>_dm):
Simplify TARGET_DIRECT_MOVE && TARGET_POWERPC64 as
TARGET_DIRECT_MOVE_64BIT.
(unpack<mode>_nodm): Simplify !TARGET_DIRECT_MOVE || !TARGET_POWERPC64
as !TARGET_DIRECT_MOVE_64BIT.
(fix_trunc<mode>si2, fix_trunc<mode>si2_stfiwx,
fix_trunc<mode>si2_internal): Simplify TARGET_P8_VECTOR &&
TARGET_DIRECT_MOVE as TARGET_DIRECT_MOVE.
(fix_trunc<mode>si2_stfiwx, fixuns_trunc<mode>si2_stfiwx): Remove some
dead code as the guard TARGET_DIRECT_MOVE there never holds.
(fixuns_trunc<mode>si2_stfiwx): Change TARGET_P8_VECTOR with
TARGET_DIRECT_MOVE which is a better fit.
* config/rs6000/vsx.md (define_peephole2 for SFmode in GPR): Simplify
TARGET_DIRECT_MOVE && TARGET_POWERPC64 as TARGET_DIRECT_MOVE_64BIT.

testsuite: arm: Use -march=unset for pr69175.C test

Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.

gcc/testsuite/ChangeLog:

* g++.dg/opt/pr69175.C: Added option "-mcpu=unset".

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>

testsuite: arm: Use -march=unset for cortex-m55* tests

Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.

gcc/testsuite/ChangeLog:

* gcc.target/arm/cortex-m55-nodsp-flag-hard.c: Added option
"-march=unset".
* gcc.target/arm/cortex-m55-nodsp-flag-softfp.c: Likewise.
* gcc.target/arm/cortex-m55-nodsp-nofp-flag-softfp.c: Likesie.
* gcc.target/arm/cortex-m55-nofp-flag-hard.c: Likewise.
* gcc.target/arm/cortex-m55-nofp-flag-softfp.c: Likewise.
* gcc.target/arm/cortex-m55-nofp-nomve-flag-softfp.c: Likewise.
* gcc.target/arm/cortex-m55-nomve-flag-hard.c: Likewise.
* gcc.target/arm/cortex-m55-nomve-flag-softfp.c: Likewise.
* gcc.target/arm/cortex-m55-nomve.fp-flag-hard.c: Likewise.
* gcc.target/arm/cortex-m55-nomve.fp-flag-softfp.c: Likewise.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>

testsuite: arm: Use effective target for pr57735.C test

Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.

gcc/testsuite/ChangeLog:

* g++.dg/ext/pr57735.C: Use effective-target arm_cpu_xscale_arm.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>

testsuite: arm: Use effective-target for nomve_fp_1.c test

Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.

gcc/testsuite/ChangeLog:

* g++.target/arm/mve/general-c++/nomve_fp_1.c: Added option
"-mcpu=unset".

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>

testsuite: arm: Use effective-target for vect-early-break-cbranch test

Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.

gcc/testsuite/ChangeLog:

* gcc.target/arm/vect-early-break-cbranch.c: Use
effective-target arm_arch_v8a_hard.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>

testsuite: arm: Use effective-target for {gcc,g++}.target/arm/ tests

Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.

gcc/testsuite/ChangeLog:

* g++.target/arm/pr103676.C: Use effective-target
arm_cpu_cortex_m7.
* gcc.target/arm/no-volatile-in-it.c: Likewise.
* gcc.target/arm/fma-sp.c: Use effective-target
arm_cpu_cortex_m4_hard.
* gcc.target/arm/pr53859.c: Use effective-target
arm_cpu_cortex_m4.
* gcc.target/arm/mve/intrinsics/pr97327.c: Use effective-target
arm_cpu_cortex_m55.
* gcc.target/arm/pr65067.c: Use effective-target
arm_cpu_cortex_m3.
* lib/target-supports.exp: Define effective-target
arm_cpu_cortex_m3, arm_cpu_cortex_m4, arm_cpu_cortex_m4_hard,
arm_cpu_cortex_m7 and arm_cpu_cortex_m55.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>

testsuite: arm: Use effective-target for thumb2-slow-flash-data* tests

Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.

gcc/testsuite/ChangeLog:

* gcc.target/arm/thumb2-slow-flash-data-2.c: Use
effective-target arm_arch_v7em_hard.
* gcc.target/arm/thumb2-slow-flash-data-3.c: Likewise.
* gcc.target/arm/thumb2-slow-flash-data-4.c: Likewise.
* gcc.target/arm/thumb2-slow-flash-data-5.c: Likewise.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>

testsuite: arm: Use effective-target for small-multiply-m* tests

Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.

gcc/testsuite/ChangeLog:

* gcc.target/arm/small-multiply-m0-1.c: Use effective-target
arm_arch_v6m and added option "-march=unset".
* gcc.target/arm/small-multiply-m0-2.c: Likewise.
* gcc.target/arm/small-multiply-m0-3.c: Likewise.
* gcc.target/arm/small-multiply-m0plus-1.c: Likewise.
* gcc.target/arm/small-multiply-m0plus-2.c: Likewise.
* gcc.target/arm/small-multiply-m0plus-3.c: Likewise.
* gcc.target/arm/small-multiply-m1-1.c: Likewise.
* gcc.target/arm/small-multiply-m1-2.c: Likewise.
* gcc.target/arm/small-multiply-m1-3.c: Likewise.
* lib/target-supports.exp: Define effective-target
arm_cpu_cortex_m0_small, arm_cpu_cortex_m0plus_small and
arm_cpu_cortex_m1_small.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>

testsuite: arm: Use effective-target for pure-code/* tests

Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.

gcc/testsuite/ChangeLog:

* gcc.target/arm/pure-code/no-literal-pool-m0.c: Use
effective-target arm_cpu_cortex-m0.
* gcc.target/arm/pure-code/no-literal-pool-m23.c: Use
effective-target arm_cpu_cortex-m23.
* gcc.target/arm/pure-code/pr94538-1.c: Likewise.
* gcc.target/arm/pure-code/pr109800.c: Use effective-target
arm_arch_v7em_hard.
* lib/target-supports.exp: Define effective-target
arm_cpu_cortex_m0, arm_cpu_cortex_m23 and arm_arch_v7em_hard.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>

testsuite: arm: Use effective-target for crc_hf_1.c test

Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.

gcc/testsuite/ChangeLog:

* gcc.target/arm/acle/crc_hf_1.c: Use effective-target
arm_arch_v8a_crc_hard.
* lib/target-supports.exp: Define effective-target
arm_arch_v8a_crc_hard.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>

testsuite: arm: Use effective-target for pacbti-m-predef* tests

Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.

gcc/testsuite/ChangeLog:

* gcc.target/arm/acle/pacbti-m-predef-1.c: Use effective-target
arm_arch_v8_1m_main.
* gcc.target/arm/acle/pacbti-m-predef-2.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-3.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-4.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-5.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-6.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-8.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-9.c: Likewise.
* gcc.target/arm/acle/pacbti-m-predef-10.c: Likewise.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>

testsuite: arm: Use effective-target for bti* and pac* tests

Update test cases to use -mcpu=unset/-march=unset feature introduced in
r15-3606-g7d6c6a0d15c.

gcc/testsuite/ChangeLog:

* gcc.target/arm/pac-1.c: Use effective-target
arm_arch_v8_1m_main_pacbti.
* gcc.target/arm/pac-2.c: Likewise.
* gcc.target/arm/pac-3.c: Likewise.
* gcc.target/arm/pac-4.c: Likewise.
* gcc.target/arm/pac-5.c: Likewise.
* gcc.target/arm/pac-7.c: Likewise.
* gcc.target/arm/pac-8.c: Likewise.
* gcc.target/arm/pac-9.c: Likewise.
* gcc.target/arm/pac-10.c: Likewise.
* gcc.target/arm/pac-11.c: Likewise.
* gcc.target/arm/pac-12.c: Added option "-mcpu=unset".
* gcc.target/arm/pac-13.c: Likewise.
* gcc.target/arm/pac-14.c: Likewise.
* lib/target-supports.exp
(check_effective_target_arm_pacbti_hw): Likewise.
* gcc.target/arm/pac-6.c: Use effective-target
arm_arch_v8_1m_main.
* gcc.target/arm/pac-15.c: Use effective-target
arm_arch_v8_1m_main_pacbti and added option "-mcpu=unset".

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
Co-authored-by: Yvan ROUX <yvan.roux@foss.st.com>

Daily bump.

tree-cfg: Fix call to next_discriminator_for_locus()

While testing future 64-bit location_t support, I ran into an
-fcompare-debug issue that was traced back here. Despite the name,
next_discriminator_for_locus() is meant to take an integer line number
argument, not a location_t. There is one call site which has been passing a
location_t instead. For the most part that is harmless, although in case
there are two CALL stmts on the same line with different location_t, it may
fail to generate a unique discriminator where it should. If/when location_t
changes to be 64-bit, however, it will produce an -fcompare-debug
failure. Fix it by passing the line number rather than the location_t.

I am not aware of a testcase that demonstrates any observable wrong
behavior, but the file debug/pr53466.C is an example where the discriminator
assignment is indeed different before and after this change.

gcc/ChangeLog:

* tree-cfg.cc (assign_discriminators): Fix incorrect value passed to
next_discriminator_for_locus().

PR modula2/117703: libgm2 soname bumps for GCC 15

Bump libgm2 version ready for the gcc-15 release.

libgm2/ChangeLog:

PR modula2/117703
* configure: Regenerate.
* configure.ac (libtool_VERSION): Bump to 20:0:0.

Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>

Fortran: fix checking of protected variables in submodules [PR83135]

When a symbol was use-associated in the ancestor of a submodule, a
PROTECTED attribute was ignored in the submodule or its descendants.
Find the real ancestor of symbols when used in a variable definition
context in a submodule.

PR fortran/83135

gcc/fortran/ChangeLog:

* expr.cc (sym_is_from_ancestor): New helper function.
(gfc_check_vardef_context): Refine checking of PROTECTED attribute
of symbols that are indirectly use-associated in a submodule.

gcc/testsuite/ChangeLog:

* gfortran.dg/protected_10.f90: New test.

c: Diagnose compound literal for empty array [PR114266]

As reported in bug 114266, GCC fails to pedwarn for a compound
literal, whose type is an array of unknown size, initialized with an
empty initializer.  This case is disallowed by C23 (which doesn't have
zero-size objects); the case of a named object is diagnosed as
expected, but not that for compound literals.  (Before C23, the
pedwarn for empty initializers sufficed.)  Add a check for this
specific case with a pedwarn.

Bootstrapped with no regressions for x86_64-pc-linux-gnu.

PR c/114266

gcc/c/
* c-decl.cc (build_compound_literal): Diagnose array of unknown
size with empty initializer for C23.

gcc/testsuite/
* gcc.dg/c23-empty-init-4.c: New test.

libgccjit: Add support for setting the comment ident

gcc/jit/ChangeLog:

* docs/topics/compatibility.rst (LIBGCCJIT_ABI_34): New ABI tag.
* docs/topics/contexts.rst: Document gcc_jit_context_set_output_ident.
* jit-playback.cc (set_output_ident): New method.
* jit-playback.h (set_output_ident): New method.
* jit-recording.cc (recording::context::set_output_ident,
recording::output_ident::output_ident,
recording::output_ident::~output_ident,
recording::output_ident::replay_into,
recording::output_ident::make_debug_string,
recording::output_ident::write_reproducer): New methods.
* jit-recording.h (class output_ident): New class.
* libgccjit.cc (gcc_jit_context_set_output_ident): New function.
* libgccjit.h (gcc_jit_context_set_output_ident): New function.
* libgccjit.map: New function.

gcc/testsuite/ChangeLog:

* jit.dg/all-non-failing-tests.h: New test.
* jit.dg/test-output-ident.c: New test.

libgccjit: Add support for creating temporary variables

gcc/jit/ChangeLog:

* docs/topics/compatibility.rst (LIBGCCJIT_ABI_33): New ABI tag.
* docs/topics/functions.rst: Document gcc_jit_function_new_temp.
* jit-playback.cc (new_local): Add support for temporary
variables.
* jit-recording.cc (recording::function::new_temp): New method.
(recording::local::write_reproducer): Support temporary
variables.
* jit-recording.h (new_temp): New method.
* libgccjit.cc (gcc_jit_function_new_temp): New function.
* libgccjit.h (gcc_jit_function_new_temp): New function.
* libgccjit.map: New function.

gcc/testsuite/ChangeLog:

* jit.dg/all-non-failing-tests.h: Mention test-temp.c.
* jit.dg/test-temp.c: New test.

[PR116587][LRA]: Fix last chance reload pseudo allocation

On i686 PR116587 test compilation resulted in LRA failure to find
registers for a reload insn pseudo.  The insn requires 6 regs for 4
reload insn pseudos where two of them require 2 regs each.  But we
have only 5 free regs as sp is a fixed reg, bp is fixed because of
-fno-omit-frame-pointer, bx is assigned to pic_offset_table_pseudo
because of -fPIC.  LRA spills pic_offset_table_pseudo as the last
chance approach to allocate registers to the reload pseudo.  Although
it makes 2 free registers for the unallocated reload pseudo requiring
also 2 regs, the pseudo still can not be allocated as the 2 free regs
are disjoint.  The patch spills all pseudos conflicting with the
unallocated reload pseudo including already allocated reload insn
pseudos, then standard LRA code allocates spilled pseudos requiring
more one register first and avoid situation of the disjoint regs for
reload pseudos requiring more one reg.

gcc/ChangeLog:

PR target/116587
* lra-assigns.cc (find_all_spills_for): Consider all pseudos whose
classes intersect given pseudo class.

gcc/testsuite/ChangeLog:

PR target/116587
* gcc.target/i386/pr116587.c: New test.

libgccjit: Add support for machine-dependent builtins

gcc/jit/ChangeLog:
PR jit/108762
* docs/topics/compatibility.rst (LIBGCCJIT_ABI_32): New ABI tag.
* docs/topics/functions.rst: Add documentation for the function
gcc_jit_context_get_target_builtin_function.
* dummy-frontend.cc: Include headers target.h, jit-recording.h,
print-tree.h, unordered_map and string, new variables (target_builtins,
target_function_types, and target_builtins_ctxt), new function
(tree_type_to_jit_type).
* jit-builtins.cc: Specify that the function types are not from
target builtins.
* jit-playback.cc: New argument is_target_builtin to new_function.
* jit-playback.h: New argument is_target_builtin to
new_function.
* jit-recording.cc: New argument is_target_builtin to
new_function_type, function_type constructor and function
constructor, new function
(get_target_builtin_function).
* jit-recording.h: Include headers string and unordered_map, new
variable target_function_types, new argument is_target_builtin
to new_function_type, function_type and function, new functions
(get_target_builtin_function, copy).
* libgccjit.cc: New function
(gcc_jit_context_get_target_builtin_function).
* libgccjit.h: New function
(gcc_jit_context_get_target_builtin_function).
* libgccjit.map: New functions
(gcc_jit_context_get_target_builtin_function).

gcc/testsuite:
PR jit/108762
* jit.dg/all-non-failing-tests.h: New test test-target-builtins.c.
* jit.dg/test-target-builtins.c: New test.

aarch64: Fix aarch64 after moving to C23

This fixes a few aarch64 specific testcases after the move to default to GNU C23.
For the SME testcases, the GNU C23 cases as `()` changing to mean `(void)` instead
of a non-prototype declaration; the non-prototype declaration merging was confusing
some of the time so the updated way is the expected way even for that.
For pic-*.c `-Wno-old-style-definition` was added not to warn about old style definitions.
For pr113573.c, I added `-std=gnu17` since I was not sure if `(...)` with C23 would invoke
the same issue.

tested for aarch64-linux-gnu.

PR testsuite/117680
gcc/testsuite/ChangeLog:

* gcc.target/aarch64/pic-constantpool1.c: Add -Wno-old-style-definition.
* gcc.target/aarch64/pic-symrefplus.c: Likewise.
* gcc.target/aarch64/pr113573.c: Add `-std=gnu17`
* gcc.target/aarch64/sme/streaming_mode_1.c: Correct testcase.
* gcc.target/aarch64/sme/za_state_1.c: Likewise.
* gcc.target/aarch64/sme/za_state_2.c: Likewise.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

rtl-reader: Disable reuse_rtx support for generator building

reuse_rtx is not documented nor the format to use it is ever documented.
So it should not be supported for the .md files.

This also fixes the problem if an invalid index is supplied for reuse_rtx,
instead of ICEing, put out a real error message.  Note since this code
still uses atoi, an invalid index can still be used in some cases but that is
recorded as part of PR 44574.

Note I did a grep of the sources to make sure that this was only used for
the read rtl in the GCC rather than while reading in .md files.

Bootstrapped and tested on x86_64-linux-gnu.

gcc/ChangeLog:

* read-md.h (class rtx_reader): Don't include m_reuse_rtx_by_id
when GENERATOR_FILE is defined.
* read-rtl.cc (rtx_reader::read_rtx_code): Disable reuse_rtx
support when GENERATOR_FILE is defined.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

RISC-V: testsuite: restrict big endian test to non vector

RISC-V vector currently does not support big endian so the postcommit
was getting the sorry, not implemented error on vector targets. Restrict
the testcase to non-vector targets

gcc/testsuite/ChangeLog:

* gcc.target/riscv/pr117595.c: Restrict to non vector targets.

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>

tree-optimization/117709 - bogus offset for gather load

When diverting to VMAT_GATHER_SCATTER we fail to zero *poffset
which was previously set if a load was classified as
VMAT_CONTIGUOUS_REVERSE.  The following refactors
get_group_load_store_type a bit to avoid this but this all needs
some serious TLC.

PR tree-optimization/117709
* tree-vect-stmts.cc (get_group_load_store_type): Only
set *poffset when we end up with VMAT_CONTIGUOUS_DOWN
or VMAT_CONTIGUOUS_REVERSE.

tree-optimization/117698 - SLP vectorization and alignment

When SLP vectorizing we fail to mark the general alignment check
as irrelevant when using VMAT_STRIDED_SLP (the implementation checks
for itself) and when VMAT_INVARIANT the override isn't effective.

This results in extra FAILs on sparc which the following fixes.

PR tree-optimization/117698
* tree-vect-stmts.cc (get_group_load_store_type): Properly
disregard alignment for VMAT_STRIDED_SLP and VMAT_INVARIANT.
(vectorizable_load): Adjust guard for dumping whether we
vectorize and unaligned access.
(vectorizable_store): Likewise.

libgccjit: Allow comparing aligned int types

gcc/jit/ChangeLog:

* jit-common.h: Add forward declaration of memento_of_get_aligned.
* jit-recording.h (type::is_same_type_as): Compare integer
types.
(dyn_cast_aligned_type): New method.
(type::is_aligned, memento_of_get_aligned::is_same_type_as,
memento_of_get_aligned::is_aligned): new methods.

gcc/testsuite/ChangeLog:

* jit.dg/test-types.c: Add checks comparing aligned types.

libgccjit: Add option to allow special characters in function names

gcc/jit/ChangeLog:

* docs/topics/contexts.rst: Add documentation for new option.
* jit-recording.cc (recording::context::get_str_option): New
method.
* jit-recording.h (get_str_option): New method.
* libgccjit.cc (gcc_jit_context_new_function): Allow special
characters in function names.
* libgccjit.h (enum gcc_jit_str_option): New option.

gcc/testsuite/ChangeLog:

* jit.dg/test-special-chars.c: New test.

libgccjit: Add vector permutation and vector access operations

gcc/jit/ChangeLog:
PR jit/112602
* docs/topics/compatibility.rst (LIBGCCJIT_ABI_31): New ABI tag.
* docs/topics/expressions.rst: Document
gcc_jit_context_new_rvalue_vector_perm and
gcc_jit_context_new_vector_access.
* jit-playback.cc (playback::context::new_rvalue_vector_perm,
common_mark_addressable_vec,
gnu_vector_type_p,
lvalue_p,
convert_vector_to_array_for_subscript,
new_vector_access): new functions.
* jit-playback.h (new_rvalue_vector_perm, new_vector_access):
New functions.
* jit-recording.cc (recording::context::new_rvalue_vector_perm,
recording::context::new_vector_access,
memento_of_new_rvalue_vector_perm,
recording::memento_of_new_rvalue_vector_perm::replay_into,
recording::memento_of_new_rvalue_vector_perm::visit_children,
recording::memento_of_new_rvalue_vector_perm::make_debug_string,
recording::memento_of_new_rvalue_vector_perm::write_reproducer,
recording::vector_access::replay_into,
recording::vector_access::visit_children,
recording::vector_access::make_debug_string,
recording::vector_access::write_reproducer): New methods.
* jit-recording.h (class memento_of_new_rvalue_vector_perm,
class vector_access): New classes.
* libgccjit.cc (gcc_jit_context_new_vector_access,
gcc_jit_context_new_rvalue_vector_perm): New functions.
* libgccjit.h (gcc_jit_context_new_rvalue_vector_perm,
gcc_jit_context_new_vector_access): New functions.
* libgccjit.map: New functions.

gcc/testsuite/ChangeLog:
PR jit/112602
* jit.dg/all-non-failing-tests.h: New test test-vector-perm.c.
* jit.dg/test-vector-perm.c: New test.

OpenMP: common C/C++ testcases for dispatch + adjust_args

gcc/testsuite/ChangeLog:

* c-c++-common/gomp/declare-variant-2.c: Adjust dg-error directives.
* c-c++-common/gomp/adjust-args-1.c: New test.
* c-c++-common/gomp/adjust-args-2.c: New test.
* c-c++-common/gomp/declare-variant-dup-match-clause.c: New test.
* c-c++-common/gomp/dispatch-1.c: New test.
* c-c++-common/gomp/dispatch-2.c: New test.
* c-c++-common/gomp/dispatch-3.c: New test.
* c-c++-common/gomp/dispatch-4.c: New test.
* c-c++-common/gomp/dispatch-5.c: New test.
* c-c++-common/gomp/dispatch-6.c: New test.
* c-c++-common/gomp/dispatch-7.c: New test.
* c-c++-common/gomp/dispatch-8.c: New test.
* c-c++-common/gomp/dispatch-9.c: New test.
* c-c++-common/gomp/dispatch-10.c: New test.

libgomp/ChangeLog:

* testsuite/libgomp.c-c++-common/dispatch-1.c: New test.
* testsuite/libgomp.c-c++-common/dispatch-2.c: New test.

OpenMP: C++ front-end support for dispatch + adjust_args

This patch adds C++ support for the `dispatch` construct and the `adjust_args`
clause. It relies on the c-family bits comprised in the corresponding C front
end patch for pragmas and attributes.

Additional C/C++ common testcases are provided in a subsequent patch in the
series.

gcc/cp/ChangeLog:

* decl.cc (omp_declare_variant_finalize_one): Set adjust_args
need_device_ptr attribute.
* parser.cc (cp_parser_direct_declarator): Update call to
cp_parser_late_return_type_opt.
(cp_parser_late_return_type_opt): Add 'tree parms' parameter. Update
call to cp_parser_late_parsing_omp_declare_simd.
(cp_parser_omp_clause_name): Handle nocontext and novariants clauses.
(cp_parser_omp_clause_novariants): New function.
(cp_parser_omp_clause_nocontext): Likewise.
(cp_parser_omp_all_clauses): Handle PRAGMA_OMP_CLAUSE_NOVARIANTS and
PRAGMA_OMP_CLAUSE_NOCONTEXT.
(cp_parser_omp_dispatch_body): New function, inspired from
cp_parser_assignment_expression and cp_parser_postfix_expression.
(OMP_DISPATCH_CLAUSE_MASK): Define.
(cp_parser_omp_dispatch): New function.
(cp_finish_omp_declare_variant): Add parameter. Handle adjust_args
clause.
(cp_parser_late_parsing_omp_declare_simd): Add parameter. Update calls
to cp_finish_omp_declare_variant and cp_finish_omp_declare_variant.
(cp_parser_omp_construct): Handle PRAGMA_OMP_DISPATCH.
(cp_parser_pragma): Likewise.
* semantics.cc (finish_omp_clauses): Handle OMP_CLAUSE_NOCONTEXT and
OMP_CLAUSE_NOVARIANTS.
* pt.cc (tsubst_omp_clauses): Handle OMP_CLAUSE_NOCONTEXT and
OMP_CLAUSE_NOVARIANTS.
(tsubst_stmt): Handle OMP_DISPATCH.
(tsubst_expr): Handle IFN_GOMP_DISPATCH.

gcc/testsuite/ChangeLog:

* g++.dg/gomp/adjust-args-1.C: New test.
* g++.dg/gomp/adjust-args-2.C: New test.
* g++.dg/gomp/adjust-args-3.C: New test.
* g++.dg/gomp/dispatch-1.C: New test.
* g++.dg/gomp/dispatch-2.C: New test.
* g++.dg/gomp/dispatch-3.C: New test.
* g++.dg/gomp/dispatch-4.C: New test.
* g++.dg/gomp/dispatch-5.C: New test.
* g++.dg/gomp/dispatch-6.C: New test.
* g++.dg/gomp/dispatch-7.C: New test.

OpenMP: C front-end support for dispatch + adjust_args

This patch adds support to the C front-end to parse the `dispatch` construct and
the `adjust_args` clause. It also includes some common C/C++ bits for pragmas
and attributes.

Additional common C/C++ testcases are in a later patch in the series.

gcc/c-family/ChangeLog:

* c-attribs.cc (c_common_gnu_attributes): Add attribute for adjust_args
need_device_ptr.
* c-omp.cc (c_omp_directives): Uncomment dispatch.
* c-pragma.cc (omp_pragmas): Add dispatch.
* c-pragma.h (enum pragma_kind): Add PRAGMA_OMP_DISPATCH.
(enum pragma_omp_clause): Add PRAGMA_OMP_CLAUSE_NOCONTEXT and
PRAGMA_OMP_CLAUSE_NOVARIANTS.

gcc/c/ChangeLog:

* c-parser.cc (c_parser_omp_dispatch): New function.
(c_parser_omp_clause_name): Handle nocontext and novariants clauses.
(c_parser_omp_clause_novariants): New function.
(c_parser_omp_clause_nocontext): Likewise.
(c_parser_omp_all_clauses): Handle nocontext and novariants clauses.
(c_parser_omp_dispatch_body): New function adapted from
c_parser_expr_no_commas.
(OMP_DISPATCH_CLAUSE_MASK): Define.
(c_parser_omp_dispatch): New function.
(c_finish_omp_declare_variant): Parse adjust_args.
(c_parser_omp_construct): Handle PRAGMA_OMP_DISPATCH.
* c-typeck.cc (c_finish_omp_clauses): Handle OMP_CLAUSE_NOVARIANTS and
OMP_CLAUSE_NOCONTEXT.

gcc/testsuite/ChangeLog:

* gcc.dg/gomp/adjust-args-1.c: New test.
* gcc.dg/gomp/dispatch-1.c: New test.
* gcc.dg/gomp/dispatch-2.c: New test.
* gcc.dg/gomp/dispatch-3.c: New test.
* gcc.dg/gomp/dispatch-4.c: New test.
* gcc.dg/gomp/dispatch-5.c: New test.

OpenMP: middle-end support for dispatch + adjust_args

This patch adds middle-end support for the `dispatch` construct and the
`adjust_args` clause. The heavy lifting is done in `gimplify_omp_dispatch` and
`gimplify_call_expr` respectively. For `adjust_args`, this mostly consists in
emitting a call to `omp_get_mapped_ptr` for the adequate device.

For dispatch, the following steps are performed:

* Handle the device clause, if any: set the default-device ICV at the top of the
dispatch region and restore its previous value at the end.

* Handle novariants and nocontext clauses, if any. Evaluate compile-time
constants and select a variant, if possible. Otherwise, emit code to handle all
possible cases at run time.

gcc/ChangeLog:

* builtins.cc (builtin_fnspec): Handle BUILT_IN_OMP_GET_MAPPED_PTR.
* gimple-low.cc (lower_stmt): Handle GIMPLE_OMP_DISPATCH.
* gimple-pretty-print.cc (dump_gimple_omp_dispatch): New function.
(pp_gimple_stmt_1): Handle GIMPLE_OMP_DISPATCH.
* gimple-walk.cc (walk_gimple_stmt): Likewise.
* gimple.cc (gimple_build_omp_dispatch): New function.
(gimple_copy): Handle GIMPLE_OMP_DISPATCH.
* gimple.def (GIMPLE_OMP_DISPATCH): Define.
* gimple.h (gimple_build_omp_dispatch): Declare.
(gimple_has_substatements): Handle GIMPLE_OMP_DISPATCH.
(gimple_omp_dispatch_clauses): New function.
(gimple_omp_dispatch_clauses_ptr): Likewise.
(gimple_omp_dispatch_set_clauses): Likewise.
(gimple_return_set_retval): Handle GIMPLE_OMP_DISPATCH.
* gimplify.cc (enum omp_region_type): Add ORT_DISPATCH.
(struct gimplify_omp_ctx): Add in_call_args.
(gimplify_call_expr): Handle need_device_ptr arguments.
(is_gimple_stmt): Handle OMP_DISPATCH.
(gimplify_scan_omp_clauses): Handle OMP_CLAUSE_DEVICE in a dispatch
construct. Handle OMP_CLAUSE_NOVARIANTS and OMP_CLAUSE_NOCONTEXT.
(omp_has_novariants): New function.
(omp_has_nocontext): Likewise.
(omp_construct_selector_matches): Handle OMP_DISPATCH with nocontext
clause.
(find_ifn_gomp_dispatch): New function.
(gimplify_omp_dispatch): Likewise.
(gimplify_expr): Handle OMP_DISPATCH.
* gimplify.h (omp_has_novariants): Declare.
* internal-fn.cc (expand_GOMP_DISPATCH): New function.
* internal-fn.def (GOMP_DISPATCH): Define.
* omp-builtins.def (BUILT_IN_OMP_GET_MAPPED_PTR): Define.
(BUILT_IN_OMP_GET_DEFAULT_DEVICE): Define.
(BUILT_IN_OMP_SET_DEFAULT_DEVICE): Define.
* omp-general.cc (omp_construct_traits_to_codes): Add OMP_DISPATCH.
(struct omp_ts_info): Add dispatch.
(omp_resolve_declare_variant): Handle novariants. Adjust
DECL_ASSEMBLER_NAME.
* omp-low.cc (scan_omp_1_stmt): Handle GIMPLE_OMP_DISPATCH.
(lower_omp_dispatch): New function.
(lower_omp_1): Call it.
* tree-inline.cc (remap_gimple_stmt): Handle GIMPLE_OMP_DISPATCH.
(estimate_num_insns): Handle GIMPLE_OMP_DISPATCH.

OpenMP: dispatch + adjust_args tree data structures and front-end interfaces

This patch introduces the OMP_DISPATCH tree node, as well as two new clauses
`nocontext` and `novariants`. It defines/exposes interfaces that will be
used in subsequent patches that add front-end and middle-end support, but
nothing generates these nodes yet.

gcc/ChangeLog:

* builtin-types.def (BT_FN_PTR_CONST_PTR_INT): New.
* omp-selectors.h (enum omp_ts_code): Add OMP_TRAIT_CONSTRUCT_DISPATCH.
* tree-core.h (enum omp_clause_code): Add OMP_CLAUSE_NOVARIANTS and
OMP_CLAUSE_NOCONTEXT.
* tree-pretty-print.cc (dump_omp_clause): Handle OMP_CLAUSE_NOVARIANTS
and OMP_CLAUSE_NOCONTEXT.
(dump_generic_node): Handle OMP_DISPATCH.
* tree.cc (omp_clause_num_ops): Add OMP_CLAUSE_NOVARIANTS and
OMP_CLAUSE_NOCONTEXT.
(omp_clause_code_name): Add "novariants" and "nocontext".
* tree.def (OMP_DISPATCH): New.
* tree.h (OMP_DISPATCH_BODY): New macro.
(OMP_DISPATCH_CLAUSES): New macro.
(OMP_CLAUSE_NOVARIANTS_EXPR): New macro.
(OMP_CLAUSE_NOCONTEXT_EXPR): New macro.

gcc/fortran/ChangeLog:

* types.def (BT_FN_PTR_CONST_PTR_INT): Declare.

libgccjit: Fix float playback for cross-compilation

gcc/jit/ChangeLog:
PR jit/113343
* jit-playback.cc (new_rvalue_from_const): Fix to have the
correct value when cross-compiling.

Enable symbolic backtraces on more Linux and BSD ports (continued)

gcc/ada
PR ada/117538
PR ada/117708
* Makefile.rtl (GNU Hurd): Add $(TRASYM_DWARF_UNIX_PAIRS).
(x86-64 kfreebsd): Likewise.
(aarch64 FreeBSD): Likewise.
(x86-64 DragonFly): Likewise.
(S390 Linux): Likewise and add Linux version of s-tsmona.adb.
(Mips Linux): Likewise.
(SPARC Linux): Likewise.
(HP/PA Linux): Linux.
(M68K Linux): Likewise.
(SH4 Linux): Likewise.
(Alpha Linux): Likewise.
(RISC-V Linux): Likewise.

libgccjit: Add type checks in gcc_jit_block_add_assignment_op

gcc/jit/ChangeLog:

* libgccjit.cc (RETURN_IF_FAIL_PRINTF3): New macro.
(gcc_jit_block_add_assignment_op): Add numeric checks.

gcc/testsuite/ChangeLog:

* jit.dg/test-error-bad-assignment-op.c: New test.

libgccjit: Support signed char flag

gcc/jit/ChangeLog:

* dummy-frontend.cc (jit_langhook_init): Send flag_signed_char
argument to build_common_tree_nodes.

gcc/testsuite/ChangeLog:

* jit.dg/all-non-failing-tests.h: Add test-signed-char.c.
* jit.dg/test-signed-char.c: New test.

aarch64: Add support for SME2p1

This patch adds support for FEAT_SME2p1.  There are two sets of
new instructions: MOVAZ to read from ZA and zero the source data,
and new forms of ZERO.  All of them require streaming mode.

MOVAZ can't reuse the existing UNSPEC_SME_READ* patterns because
of the write to ZA.  I did wonder about trying to use a define_subst,
but it seemed a bit too awkward.

gcc/
* config/aarch64/aarch64-option-extensions.def (sme2p1): New extension.
* doc/invoke.texi: Document it.
* config/aarch64/aarch64.h (TARGET_STREAMING_SME2p1): New macro.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Conditionally define __ARM_FEATURE_SME2p1.
* config/aarch64/iterators.md (UNSPEC_SME_READZ, UNSPEC_SME_READZ_HOR)
(UNSPEC_SME_READZ_VER): New unspecs.
(optab, hv): Handle them.
(SME_READZ_HV): New int iterator.
* config/aarch64/aarch64-sme.md
(UNSPEC_SME_ZERO_SLICES): New unspec.
(@aarch64_sme_<SME_READZ_HV:optab><v_int_container><mode>)
(*aarch64_sme_<SME_READZ_HV:optab><v_int_container><mode>_plus)
(@aarch64_sme_<SME_READZ_HV:optab><VNx1TI_ONLY:mode><SVE_FULL:mode>)
(@aarch64_sme_<SME_READZ_HV:optab><SVE_FULLx24:mode><mode>)
(*aarch64_sme_<SME_READZ_HV:optab><SVE_FULLx24:mode><mode>_plus)
(@aarch64_sme_readz<mode>, *aarch64_sme_readz<mode>_plus)
(@aarch64_sme_zero_za_slices<mode>): New patterns.
(*aarch64_sme_zero_za_slices<mode>_plus): Likewise.
* config/aarch64/aarch64-sve-builtins-shapes.h
(inherent_za_slice): Declare.
* config/aarch64/aarch64-sve-builtins-shapes.cc
(inherent_za_slice_def, inherent_za_slice): New shape.
* config/aarch64/aarch64-sve-builtins-sme.h (svreadz_za)
(svreadz_hor_za, svreadz_ver_za): Declare.
* config/aarch64/aarch64-sve-builtins-sme.cc
(svread_za_slice_base): New class, split out from...
(svread_za_impl): ...here.
(svreadz_za_impl, svreadz_za_tile_impl): New type aliases.
(zero_slices_mode): New function.
(svzero_za_impl::expand): Handle the slice forms.
(svreadz_za, svreadz_hor_za, svreadz_ver_za): New functions.
* config/aarch64/aarch64-sve-builtins-sme.def: Add the SME2p1
instructions.

gcc/testsuite/
* lib/target-supports.exp: Test the assembler for sve-b16b16 support.
* gcc.target/aarch64/pragma_cpp_predefs_4.c: Add tests for
__ARM_FEATURE_SME2p1.
* gcc.target/aarch64/sme2/acle-asm/readz_hor_za128.c: New test.
* gcc.target/aarch64/sme2/acle-asm/readz_hor_za16.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_hor_za16_vg2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_hor_za16_vg4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_hor_za32.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_hor_za32_vg2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_hor_za32_vg4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_hor_za64.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_hor_za64_vg2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_hor_za64_vg4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_hor_za8.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_hor_za8_vg2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_hor_za8_vg4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_ver_za16.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_ver_za16_vg2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_ver_za16_vg4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_ver_za32.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_ver_za32_vg2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_ver_za32_vg4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_ver_za64.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_ver_za64_vg2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_ver_za64_vg4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_ver_za8.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_ver_za8_vg2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_ver_za8_vg4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_za16_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_za16_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_za32_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_za32_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_za64_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_za64_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_za8_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/readz_za8_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/zero_za64_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/zero_za64_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/zero_za64_vg2x1.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/zero_za64_vg2x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/zero_za64_vg2x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/zero_za64_vg4x1.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/zero_za64_vg4x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/zero_za64_vg4x4.c: Likewise.

aarch64: Add support for SME_B16B16

This patch adds support for the SME_B16B16 extension.  It follows
similar lines to the SME_F16F16 extension added earlier.

gcc/
* config/aarch64/aarch64-option-extensions.def
(sme-b16b16): New extension.
* doc/invoke.texi: Document it.
* config/aarch64/aarch64.h (TARGET_STREAMING_SME_B16B16): New macro.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Conditionally define __ARM_FEATURE_SME_B16B16.
* config/aarch64/aarch64-sve-builtins-sme.def: Add SME_B16B16 forms
of existing intrinsics.
* config/aarch64/aarch64-sme.md
(@aarch64_sme_<SME_BINARY_SLICE_HSDF:optab><mode>)
(*aarch64_sme_<SME_BINARY_SLICE_HSDF:optab><mode>_plus)
(@aarch64_sme_<SME_FP_TERNARY_SLICE:optab><mode><mode>)
(*aarch64_sme_<SME_FP_TERNARY_SLICE:optab><mode><mode>_plus)
(@aarch64_sme_single_<SME_FP_TERNARY_SLICE:optab><mode><mode>)
(*aarch64_sme_single_<SME_FP_TERNARY_SLICE:optab><mode><mode>_plus)
(@aarch64_sme_lane_<SME_FP_TERNARY_SLICE:optab><mode><mode>)
(*aarch64_sme_lane_<SME_FP_TERNARY_SLICE:optab><mode><mode>)
(@aarch64_sme_<SME_FP_MOP:optab><mode><mode>): Extend to BF16 modes.
* config/aarch64/aarch64-sve-builtins.cc (TYPES_za_h_bfloat): New
type macro.
* config/aarch64/iterators.md (SME_ZA_HSDFx24): Add BF16 modes.
(SME_MOP_HSDF): Likewise.

gcc/testsuite/
* lib/target-supports.exp: Test the assembler for sve-b16b16 support.
* gcc.target/aarch64/pragma_cpp_predefs_4.c: Add tests for
__ARM_FEATURE_SME_B16B16.
* gcc.target/aarch64/sme2/acle-asm/add_za16_bf16_vg1x2.c: New test.
* gcc.target/aarch64/sme2/acle-asm/add_za16_bf16_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_bf16_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_bf16_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mla_za16_bf16_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mla_za16_bf16_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mls_lane_za16_bf16_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mls_lane_za16_bf16_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mls_za16_bf16_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mls_za16_bf16_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mopa_za16_bf16.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mops_za16_bf16.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/sub_za16_bf16_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/sub_za16_bf16_vg1x4.c: Likewise.

aarch64: Add support for SME_F16F16

This patch adds support for the SME_F16F16 extension.  The extension
adds two new instructions to convert from a single vector of f16s
to two vectors of f32s.  It also adds f16 variants of existing SME
ZA instructions.

gcc/
* config/aarch64/aarch64-option-extensions.def
(sme-f16f16): New extension.
* doc/invoke.texi: Document it.  Also document that sme-i16i64 and
sme-f64f64 enable SME.
* config/aarch64/aarch64.h (TARGET_STREAMING_SME_F16F16): New macro.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Conditionally define __ARM_FEATURE_SME_F16F16.
* config/aarch64/aarch64-sve-builtins-sve2.def (svcvt, svcvtl): Add
new SME_F16F16 intrinsics.
* config/aarch64/aarch64-sve-builtins-sme.def: Add SME_F16F16 forms
of existing intrinsics.
* config/aarch64/aarch64-sve-builtins.cc (TYPES_h_float)
(TYPES_cvt_f32_f16, TYPES_za_h_float): New type macros.
* config/aarch64/aarch64-sve-builtins-base.cc
(svcvt_impl::expand): Add sext_optab as another possibility.
* config/aarch64/aarch64-sve-builtins-sve2.h (svcvtl): Declare.
* config/aarch64/aarch64-sve-builtins-sve2.cc (svcvtl_impl): New class.
(svcvtl): New function.
* config/aarch64/iterators.md (VNx8SF_ONLY): New mode iterator.
(SME_ZA_SDFx24): Replace with...
(SME_ZA_HSDFx24): ...this.
(SME_MOP_SDF): Replace with...
(SME_MOP_HSDF): ...this.
(SME_BINARY_SLICE_SDF): Replace with...
(SME_BINARY_SLICE_HSDF): ...this.
* config/aarch64/aarch64-sve2.md (extendvnx8hfvnx8sf2)
(@aarch64_sve_cvtl<mode>): New patterns.
* config/aarch64/aarch64-sme.md
(@aarch64_sme_<SME_BINARY_SLICE_SDF:optab><mode>): Extend to...
(@aarch64_sme_<SME_BINARY_SLICE_HSDF:optab><mode>): ...this.
(*aarch64_sme_<SME_BINARY_SLICE_SDF:optab><mode>_plus): Extend to...
(*aarch64_sme_<SME_BINARY_SLICE_HSDF:optab><mode>_plus): ...this.
(@aarch64_sme_<SME_FP_TERNARY_SLICE:optab><mode><mode>): Extend to
HF modes.
(*aarch64_sme_<SME_FP_TERNARY_SLICE:optab><mode><mode>_plus)
(@aarch64_sme_single_<SME_FP_TERNARY_SLICE:optab><mode><mode>)
(*aarch64_sme_single_<SME_FP_TERNARY_SLICE:optab><mode><mode>_plus)
(@aarch64_sme_lane_<SME_FP_TERNARY_SLICE:optab><mode><mode>)
(*aarch64_sme_lane_<SME_FP_TERNARY_SLICE:optab><mode><mode>)
(@aarch64_sme_<SME_FP_MOP:optab><mode><mode>): Likewise.

gcc/testsuite/
* lib/target-supports.exp: Test the assembler for sve-f16f16 support.
* gcc.target/aarch64/pragma_cpp_predefs_4.c: Add tests for
__ARM_FEATURE_SME_F16F16.  Also extend the existing SME tests.
* gcc.target/aarch64/sve/acle/asm/test_sve_acle.h
(TEST_X2_WIDE): New macro
* gcc.target/aarch64/sme2/acle-asm/add_za16_f16_vg1x2.c: New test.
* gcc.target/aarch64/sme2/acle-asm/add_za16_f16_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/cvt_f32_f16_x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/cvtl_f32_f16_x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_f16_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_f16_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mla_za16_f16_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mla_za16_f16_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mls_lane_za16_f16_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mls_lane_za16_f16_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mls_za16_f16_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mls_za16_f16_vg1x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mopa_za16_f16.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/mops_za16_f16.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/sub_za16_f16_vg1x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/sub_za16_f16_vg1x4.c: Likewise.

aarch64: Add support for SVE_B16B16

This patch adds support for the SVE_B16B16 extension, which provides
non-widening BF16 versions of existing instructions.

Mostly it's just a simple extension of iterators.  The main
complications are:

(1) The new instructions have no immediate forms.  This is easy to
    handle for the cond_* patterns (the ones that have an explicit
    else value) since those are already divided into register and
    non-register versions.  All we need to do is tighten the predicates.

    However, the @aarch64_pred_<optab><mode> patterns handle the
    immediates directly.  Rather than complicate them further,
    it seemed best to add a single @aarch64_pred_<optab><mode> for
    all BF16 arithmetic.

(2) There is no BFSUBR, so the usual method of handling reversed
    operands breaks down.  The patch deals with this using some
    new attributes that together disable the "BFSUBR" alternative.

(3) Similarly, there are no BFMAD or BFMSB instructions, so we need
    to disable those forms in the BFMLA and BFMLS patterns.

The patch includes support for generic bf16 vectors too.

It would be possible to use these instructions for scalars, as with
the recent FLOGB patch, but that's left as future work.

gcc/
* config/aarch64/aarch64-option-extensions.def
(sve-b16b16): New extension.
* doc/invoke.texi: Document it.
* config/aarch64/aarch64.h (TARGET_SME_B16B16, TARGET_SVE2_OR_SME2)
(TARGET_SSVE_B16B16): New macros.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Conditionally define __ARM_FEATURE_SVE_B16B16
* config/aarch64/aarch64-sve-builtins-sve2.def: Add AARCH64_FL_SVE2
to the SVE2p1 requirements.  Add SVE_B16B16 forms of existing
intrinsics.
* config/aarch64/aarch64-sve-builtins.cc (type_suffixes): Treat
bfloat as a floating-point type.
(TYPES_h_bfloat): New macro.
* config/aarch64/aarch64.md (is_bf16, is_rev, supports_bf16_rev)
(mode_enabled): New attributes.
(enabled): Test mode_enabled.
* config/aarch64/iterators.md (SVE_FULL_F_BF): New mode iterator.
(SVE_CLAMP_F): Likewise.
(SVE_Fx24): Add BF16 modes when TARGET_SSVE_B16B16.
(sve_lane_con): Handle BF16 modes.
(b): Handle SF and DF modes.
(is_bf16): New mode attribute.
(supports_bf16, supports_bf16_rev): New int attributes.
* config/aarch64/predicates.md
(aarch64_sve_float_maxmin_immediate): Reject BF16 modes.
* config/aarch64/aarch64-sve.md
(*post_ra_<sve_fp_op><mode>3): Add BF16 support, and likewise
for the associated define_split.
(<optab:SVE_COND_FP_BINARY_OPTAB><mode>): Add BF16 support.
(@cond_<optab:SVE_COND_FP_BINARY><mode>): Likewise.
(*cond_<optab:SVE_COND_FP_BINARY><mode>_2_relaxed): Likewise.
(*cond_<optab:SVE_COND_FP_BINARY><mode>_2_strict): Likewise.
(*cond_<optab:SVE_COND_FP_BINARY><mode>_3_relaxed): Likewise.
(*cond_<optab:SVE_COND_FP_BINARY><mode>_3_strict): Likewise.
(*cond_<optab:SVE_COND_FP_BINARY><mode>_any_relaxed): Likewise.
(*cond_<optab:SVE_COND_FP_BINARY><mode>_any_strict): Likewise.
(@aarch64_mul_lane_<mode>): Likewise.
(<optab:SVE_COND_FP_TERNARY><mode>): Likewise.
(@aarch64_pred_<optab:SVE_COND_FP_TERNARY><mode>): Likewise.
(@cond_<optab:SVE_COND_FP_TERNARY><mode>): Likewise.
(*cond_<optab:SVE_COND_FP_TERNARY><mode>_4_relaxed): Likewise.
(*cond_<optab:SVE_COND_FP_TERNARY><mode>_4_strict): Likewise.
(*cond_<optab:SVE_COND_FP_TERNARY><mode>_any_relaxed): Likewise.
(*cond_<optab:SVE_COND_FP_TERNARY><mode>_any_strict): Likewise.
(@aarch64_<optab:SVE_FP_TERNARY_LANE>_lane_<mode>): Likewise.
* config/aarch64/aarch64-sve2.md
(@aarch64_pred_<optab:SVE_COND_FP_BINARY><mode>): Define BF16 version.
(@aarch64_sve_fclamp<mode>): Add BF16 support.
(*aarch64_sve_fclamp<mode>_x): Likewise.
(*aarch64_sve_<maxmin_uns_op><SVE_Fx24:mode>): Likewise.
(*aarch64_sve_single_<maxmin_uns_op><SVE_Fx24:mode>): Likewise.
* config/aarch64/aarch64.cc (aarch64_sve_float_arith_immediate_p)
(aarch64_sve_float_mul_immediate_p): Return false for BF16 modes.

gcc/testsuite/
* lib/target-supports.exp: Test the assembler for sve-b16b16 support.
* gcc.target/aarch64/pragma_cpp_predefs_4.c: Test the new B16B16
macros.
* gcc.target/aarch64/sve/fmad_1.c: Test bfloat16 too.
* gcc.target/aarch64/sve/fmla_1.c: Likewise.
* gcc.target/aarch64/sve/fmls_1.c: Likewise.
* gcc.target/aarch64/sve/fmsb_1.c: Likewise.
* gcc.target/aarch64/sve/cond_mla_9.c: New test.
* gcc.target/aarch64/sme2/acle-asm/clamp_bf16_x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/clamp_bf16_x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/max_bf16_x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/max_bf16_x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/maxnm_bf16_x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/maxnm_bf16_x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/min_bf16_x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/min_bf16_x4.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/minnm_bf16_x2.c: Likewise.
* gcc.target/aarch64/sme2/acle-asm/minnm_bf16_x4.c: Likewise.
* gcc.target/aarch64/sve/bf16_arith_1.c: Likewise.
* gcc.target/aarch64/sve/bf16_arith_1.h: Likewise.
* gcc.target/aarch64/sve/bf16_arith_2.c: Likewise.
* gcc.target/aarch64/sve/bf16_arith_3.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/add_bf16.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/clamp_bf16.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/max_bf16.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/maxnm_bf16.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/min_bf16.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/minnm_bf16.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/mla_bf16.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/mla_lane_bf16.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/mls_bf16.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/mls_lane_bf16.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/mul_bf16.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/mul_lane_bf16.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/sub_bf16.c: Likewise.

aarch64: Fix the choice of unspec in two SME patterns

@aarch64_sme_write<mode> and *aarch64_sme_write<mode>_plus
were using UNSPEC_SME_READ instead of UNSPEC_SME_WRITE.

gcc/
* config/aarch64/aarch64-sme.md (@aarch64_sme_write<mode>)
(*aarch64_sme_write<mode>_plus): Use UNSPEC_SME_WRITE instead
of UNSPEC_SME_READ.

aarch64: Rename some SME iterators

This patch just renames the iterators SME_READ and SME_WRITE to
SME_READ_HV and SME_WRITE_HV, to distinguish them from other forms
of ZA read and write.

gcc/
* config/aarch64/iterators.md (SME_READ): Rename to...
(SME_READ_HV): ...this.
(SME_WRITE): Rename to...
(SME_WRITE_HV): ...this.
* config/aarch64/aarch64-sme.md: Update accordingly.

aarch64: Refactor SVE predicated-to-unpredicated splits

There are separate patterns for predicated FADD, FSUB, and FMUL.
Previously they each had their own in-built split to convert the
instruction to unpredicated form where appropriate.  However, it's
more convenient for later patches if we use a single separate split
instead.

gcc/
* config/aarch64/iterators.md (SVE_COND_FP): New code attribute.
* config/aarch64/aarch64-sve.md: Use a single define_split to
handle the conversion of predicated FADD, FSUB, and FMUL into
unpredicated forms.

aarch64: Rework sme_2mode_function insns

Many of the SME ZA intrinsics have two type suffixes: one for ZA
and one for the vectors.  The ZA suffix only conveys an element
size, while the vector suffix conveys both an element type and
an element size.  Internally, the ZA suffix maps to an integer mode;
e.g. za32 maps to VNx4SI.

For SME2, it was relatively convenient to use the modes associated
with both suffixes directly.  For example, the (non-widening) FMLA
intrinsics used SME_ZA_SDF_I to iterate over the possible ZA modes,
used SME_ZA_SDFx24 to iterate over the possible vector tuple modes,
and used a C++ condition to make sure that the element sizes agree.

However, for later patches it's more convenient to rely only on
the vector mode in cases where the ZA and vector element sizes
are the same.  This means splitting the widening MOPA/S patterns
from the non-widening ones, but otherwise it's not a big change.

gcc/
* config/aarch64/iterators.md (SME_ZA_SDF_I): Delete.
(SME_MOP_HSDF): Replace with...
(SME_MOP_SDF): ...this.
* config/aarch64/aarch64-sme.md: Change the non-widening FMLA and
FMLS patterns so that both mode parameters are the same, rather than
using both SME_ZA_SDF_I and SME_ZA_SDFx24 and checking that their
element sizes are the same.  Split the FMOPA and FMOPS patterns
into separate non-widening and widening forms, then update the
non-widening forms in a similar way to FMLA and FMLS.
* config/aarch64/aarch64-sve-builtins-functions.h
(sme_2mode_function_t::expand): If the two type suffixes have the same
element size, use the vector tuple mode for both mode parameters.

fortran: Evaluate once BACK argument of MINLOC/MAXLOC with DIM [PR90608]

Evaluate the BACK argument of MINLOC/MAXLOC once before the
scalarization loops in the case where the DIM argument is present.

This is a follow-up to r15-1994-ga55d24b3cf7f4d07492bb8e6fcee557175b47ea3
which added knowledge of BACK to the scalarizer, to
r15-2701-ga10436a8404ad2f0cc5aa4d6a0cc850abe5ef49e which removed it to
handle it out of scalarization instead, and to more immediate previous
patches that added inlining support for MINLOC/MAXLOC with DIM.  The
inlining support for MINLOC/MAXLOC with DIM introduced nested loops, which
made the evaluation of BACK (removed from the scalarizer knowledge by the
forementionned commit) wrapped in a loop, so possibly executed more than
once.  This change adds BACK to the scalarization chain if MINLOC/MAXLOC
will use nested loops, so that it is evaluated by the scalarizer only once
before the outermost loop in that case.

PR fortran/90608

gcc/fortran/ChangeLog:

* trans-intrinsic.cc
(walk_inline_intrinsic_minmaxloc): Add a scalar element for BACK as
first item of the chain if BACK is present and there will be nested
loops.
(gfc_conv_intrinsic_minmaxloc): Evaluate BACK using an inherited
scalarization chain if there is a nested loop.

gcc/testsuite/ChangeLog:

* gfortran.dg/maxloc_8.f90: New test.
* gfortran.dg/minloc_9.f90: New test.

i386: Remove workaround for Solaris ld 64-bit TLS IE limitation

As detailed in PR target/43309, the Solaris linker initially took the
64-bit x86 TLS IE code sequence literally, assuming that the spec only
allowed %rax as target register.

A workaround has been in place for more than a decade, but is no longer
necessary.  The bug had already been fixed for Solaris 11.1, while trunk
requires Solaris 11.4.

Uros pointed this out and suggested the attached patch.

Bootstrapped without regressions on i386-pc-solaris2.11.

2024-10-15  Uros Bizjak  <ubizjak@gmail.com>

gcc:
* config/i386/i386.cc (legitimize_tls_address)
<TLS_MODEL_INITIAL_EXEC>: Remove 64-bit Solaris ld workaround.
* config/i386/i386.md (UNSPEC_TLS_IE_SUN): Remove.
(tls_initial_exec_64_sun): Remove.

testsuite: i386: Fix gcc.target/i386/pr117232-1.c etc. with Solaris as

Two tests FAIL on Solaris/x86 with the native assembler:

FAIL: gcc.target/i386/pr117232-1.c scan-assembler-times (?n)cmovn?c 7
FAIL: gcc.target/i386/pr117232-apx-1.c scan-assembler-times (?n)cmovn?c 7

The problem is that as expects a slightly different insn syntax, e.g.

cmovl.nc %esi, %eax

instead of

cmovnc %esi, %eax

This patch allows for both forms.

Tested on i386-pc-solaris2.11 (as and gas) and x86_64-pc-linux-gnu.

2024-11-15  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

gcc/testsuite:
* gcc.target/i386/pr117232-1.c (scan-assembler-times): Allow for
cmovl.nc etc.
* gcc.target/i386/pr117232-apx-1.c: Likewise.

RISC-V: Refine the rtl dump expand check for vector SAT_ADD

This patch would like to remove the unnecessary option for the
vector SAT_ADD testcases at first.  And the different optimization
option like O2 and O3 will be passed to the test files for rtl
expand dump check.  If there are different dump check times for
different optimization options, the target no-opts and/or any-opts
will be leveraged for the dg-final check.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c: Remove
the unnecessary option and refine the rtl IFN dump check.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Introduce riscv/rvv/autovec/sat folder to rvv.exp testsuite

After we move vector SAT_ADD testcases into a isolated folder, aka
riscv/rvv/autovec/sat.  We would like to add the folder as one of
the test items of the rvv.exp testsuite.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/rvv.exp: Add the vector sat folder to
the rvv.exp testsuite.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Rearrange the test files for vector SAT_ADD [NFC]

The test files of scalar SAT_TRUNC only has numbers as the suffix.
Rearrange the file name to -{form number}-{target-type}.  For example,
test form 3 for uint32_t SAT_TRUNC will have -3-u32.c for asm check and
-run-3-u32.c for the run test.

Meanwhile, all related test files moved to riscv/rvv/autovec/sat/.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-6.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-7.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-5.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-10.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-11.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-12.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-9.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-14.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-15.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-13.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-2.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-3.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-4.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-1.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-1-s8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-6.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-7.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-5.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-2-s8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-10.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-11.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-12.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-9.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-3-s8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-14.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-15.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-13.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-run-4-s8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-2.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-3.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-4.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-1.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-1-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-2-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-3-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-4-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-18.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-19.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-20.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-17.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-5-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-6-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-26.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-27.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-28.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-25.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-7-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-30.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-31.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-32.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-29.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-8-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-2.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-3.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-4.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-1.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-1-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-6.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-7.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-5.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-2-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-10.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-11.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-12.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-9.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-3-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-14.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-15.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-16.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-13.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-run-4-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-2.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-3.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-4.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-1.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-6.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-7.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-8.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-5.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-10.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-11.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-12.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-9.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-14.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-15.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c: ...here.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm_reconcile-13.c: Move to...
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c: ...here.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_binary_vvv_run.h: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_binary_vvx_run.h: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_binary_vx_run.h: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

tree-optimization/117574 - bougs niter lt-to-ne

When trying to change a IV from IV0 < IV1 to IV0' != IV1' we apply
fancy adjustments to the may_be_zero condition we compute rather
than using the obvious IV0->base >= IV1->base expression (to be
able to use > instead of >=?).  This doesn't seem to go well.

PR tree-optimization/117574
* tree-ssa-loop-niter.cc (number_of_iterations_lt_to_ne):
Use the obvious may_be_zero condition.

* gcc.dg/torture/pr117574-1.c: New testcase.

Extend expand_absneg_bit to vector modes

Expand can implement NEG and ABS of scalar floating-point modes
by using logic ops to manipulate the sign bit.  This patch extends
that approach to vectors, since it fits relatively easily into the
same structure.

The motivating use case was to inline bf16 NEG and ABS operations
for AArch64.  The patch includes tests for that.

get_absneg_bit_mode required a new opt_mode constructor, so that
opt_mode<T> can be constructed from opt_mode<U> if T is no less
general than U.

gcc/
* machmode.h (opt_mode::opt_mode): New overload.
* optabs-query.h (get_absneg_bit_mode): Declare.
* optabs-query.cc (get_absneg_bit_mode): New function, split
out from expand_absneg_bit.
(can_open_code_p): Use get_absneg_bit_mode.
* optabs.cc (expand_absneg_bit): Likewise.  Take an outer and inner
mode, rather than just one.  Handle vector modes.
(expand_unop, expand_abs_nojump): Update calls accordingly.
Handle vector modes.

gcc/testsuite/
* gcc.target/aarch64/abs_bf_1.c: New test.
* gcc.target/aarch64/neg_bf_1.c: Likewise.
* gcc.target/aarch64/neg_bf_2.c: Likewise.

Use can_implement_p in the vectoriser

This patch goes through the tree-vect-* code and mechanically replaces
all tests of optab_handler against CODE_FOR_nothing with calls to the
new helper functions.

gcc/
* tree-vect-data-refs.cc (vect_supportable_dr_alignment): Use
can_implement_p instead of optab_handler.
* tree-vect-generic.cc (add_rshift, expand_vector_divmod): Likewise.
(optimize_vector_constructor, type_for_widest_vector_mode): Likewise.
(lower_vec_perm, expand_vector_operations_1): Likewise.
* tree-vect-loop.cc (have_whole_vector_shift): Likewise.
* tree-vect-patterns.cc (vect_recog_rotate_pattern): Likewise.
(target_has_vecop_for_code, vect_recog_mult_pattern): Likewise.
(vect_recog_divmod_pattern): Likewise.
* tree-vect-stmts.cc (vect_supportable_shift, vectorizable_shift)
(scan_store_can_perm_p, check_scan_store, vectorizable_store)
(vectorizable_load, vectorizable_condition): Likewise.
(vectorizable_comparison_1): Likewise.

Add helpers to test whether an optab can be implemented

The vectoriser and vector lowering passes both had tests of the form:

    if (op
&& (optab_handler (op, compute_mode) != CODE_FOR_nothing
    || optab_libfunc (op, compute_mode)))
      ...success...
    if (code == MULT_HIGHPART_EXPR
&& can_mult_highpart_p (compute_mode,
TYPE_UNSIGNED (compute_type)))
      ...success...

This patch adds helper routines for this kind of test, so that it's
easier to handle other optab alternatives in a similar way.

gcc/
* optabs-query.cc (can_open_code_p, can_implement_p): Declare.
* optabs-query.h (can_open_code_p, can_implement_p): New functions.
* optabs-tree.cc (target_supports_op_p): Use can_implement_p.
* tree-vect-stmts.cc (vectorizable_operation): Likewise.
* tree-vect-generic.cc (get_compute_type): Likewise.  Remove code
parameter.
(expand_vector_scalar_condition, expand_vector_conversion)
(expand_vector_operations_1): Update calls accordingly.

arm, mve: Fix arm_mve_dlstp_check_dec_counter's use of single_pred

Call 'single_pred_p' before 'single_pred' to verify it is safe to do so.

gcc/ChangeLog:

* config/arm/arm.cc (arm_mve_dlstp_check_dec_counter): Call
single_pred_p to verify it's safe to call single_pred.

gcc/testsuite/ChangeLog:

* gcc.target/arm/mve/dlstp-loop-form.c: Add loop that triggered ICE.

fortran: Check for empty MINLOC/MAXLOC ARRAY along DIM only

In the function generating inline code to implement MINLOC and MAXLOC, only
check for ARRAY size along DIM if DIM is present.

The check for ARRAY emptyness had been checking the size of the full array,
which is correct for MINLOC and MAXLOC without DIM.  But if DIM is
present, the reduction is along DIM only so the check for emptyness
should consider that dimension only as well.

This sounds like a correctness issue, but fortunately the cases where it
makes a difference are cases where ARRAY is empty, so even if the value
calculated for MINLOC or MAXLOC is wrong, it's wrapped in a zero iteration
loop, and the wrong values are not actually used.  In the end this just
avoids unnecessary calculations.

A previous version of this patch regressed on non-constant DIM with rank 1
ARRAY.  The new testcase checks that that case is supported.

gcc/fortran/ChangeLog:

* trans-intrinsic.cc (gfc_conv_intrinsic_minmaxloc): Only get the size
along DIM instead of the full size if DIM is present.

gcc/testsuite/ChangeLog:

* gfortran.dg/minmaxloc_22.f90: New test.

PR target/117669 - RISC-V:The 'VEEWTRUNC4' iterator 'RVVMF2BF' type condition error

This patch fix the wrong condition for RVVMF2BF. It should be
TARGET_VECTOR_ELEN_BF_16.
gcc/ChangeLog:

PR target/117669
* config/riscv/vector-iterators.md:

Signed-off-by: Feng Wang <wangfeng@eswincomputing.com>

Add microarchtecture tunable for pass_align_tight_loops [PR117438]

Hi Hongtao:
   Add m_CASCADELAK, and m_SKYLAKE_AVX512.
   Place X86_TUNE_ALIGN_TIGHT_LOOPS in the appropriate section.

   Bootstrapped X86_64.
   Ok for trunk?
BR
Mayshao
gcc/ChangeLog:

PR target/117438
* config/i386/i386-features.cc (TARGET_ALIGN_TIGHT_LOOPS):
default true in all processors except for m_ZHAOXIN, m_CASCADELAKE, and
m_SKYLAKE_AVX512.
* config/i386/i386.h (TARGET_ALIGN_TIGHT_LOOPS): New Macro.
* config/i386/x86-tune.def (X86_TUNE_ALIGN_TIGHT_LOOPS):
New tune

testsuite: arm: Only check for absence of literal pools in no-literal-pool-m0.c

With the changes in r15-1579-g792f97b44ff, the constants have been
updated.
This patch drops the fragile check on the constants and instead only
checks that there is no literal pool generated.

gcc/testsuite/ChangeLog:

* gcc.target/arm/pure-code/no-literal-pool-m0.c: Only check for
absence of literal pools.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>

libstdc++: Use const_iterator in std::set::find<K> return type

François noticed that the "wrong" type is used in the return type for a
std::set member function template.

The iterator for our std::set is the same type as const_iterator,
so this doesn't actually matter. But it's clearer if the return type
matches the type used in the function body.

libstdc++-v3/ChangeLog:

* include/bits/stl_set.h (set::find): Use const_iterator in
return type, not iterator.

libstdc++: Fix std::unordered_set::emplace optimization [PR117686]

The __is_key_type specialization that matches a pair<key_type, T>
argument is intended for std::unordered_map, not for
std::unordered_set<std::pair<K,T>>.

This uses a pair<const Args&...> as the template argument for
__is_key_type, so that it won't match a set's key_type.

libstdc++-v3/ChangeLog:

PR libstdc++/117686
* include/bits/hashtable.h (_Hashtable::_M_emplace_uniq):
Adjust usage of __is_key_type to avoid false positive.
* testsuite/23_containers/unordered_set/insert/117686.cc:
New test.

RISC-V: Refine the rtl expand check for strided ld/st

This patch would like to remove the unnecessary option for the
strided load/store testcases.  After fix the option from the rvv.exp,
both the O2 and O3 will be passed to the test files for rtl expand
dump check but the O2 has 2 time for IFN while the O3 has 4 times with
-fvectorize specificed.

Thus, add xfail O2 for IFN 4 times check, as well as xfail O3 for 2
times check.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c: Remove
unnecessary optimization option and xfail O2/O3 diff IFN times
from the rtl expand dump.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Fix incorrect optimization options passing to strided ld/st test

The testcases of vector strided load/store are designed to pick up
different sorts of optimization options but actually these option
are ignored according to the Execution log of gcc.log.  This patch
would like to make it correct, and then you will see the build option
similar as below from the gcc.log.

Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1 ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1 ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m4 ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m8 ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=dynamic ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m8 ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4 ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2 ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=dynamic ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 ...

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization options.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add the mini support for SiFive extensions.

This patch add the mini support for xsfvqmaccqoq, xsfvqmaccdod and
 xsfvfnrclipxfqf extensions.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: New.
* config/riscv/riscv.opt: New.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-sf-3.c: New test.
* gcc.target/riscv/predef-sf-4.c: New test.
* gcc.target/riscv/predef-sf-5.c: New test.

[RISC-V][PR target/117649] Fix branch on masked values splitter

Andreas reported GCC mis-compiled GAS for risc-v  Thankfully he also reduced it
to a nice little testcase.

So the whole point of the pattern in question is to "reduce" the constants by
right shifting away common unnecessary bits in RTL expressions like this:

>   [(set (pc)
>         (if_then_else (any_eq
>                     (and:ANYI (match_operand:ANYI 1 "register_operand" "r")
>                           (match_operand 2 "shifted_const_arith_operand" "i"))
>                     (match_operand 3 "shifted_const_arith_operand" "i"))
>          (label_ref (match_operand 0 "" ""))
>          (pc)))

When applicable, the reduced constants in operands 2/3 fit into a simm12 and
thus do not need multi-instruction synthesis.  Note that we have to also shift
operand 1.

That shift should have been an arithmetic shift, but was incorrectly coded as a
logical shift.

Fixed with the obvious change on the right shift opcode.

Expecting to push to the trunk once the pre-commit tester renders its verdict.
I've already tested in this my tester for rv32 and rv64.

PR target/117649
gcc/
* config/riscv/riscv.md (branch on masked/shifted operands): Use
arithmetic rather than logical shift for operand 1.

gcc/testsuite

* gcc.target/riscv/branch-1.c: Update expected output.
* gcc.target/riscv/pr117649.c: New test.

c: Fix ICE for integer constexpr initializers of wrong type [PR115515]

Bug 115515 (plus its duplicate 117139) reports an ICE with constexpr
initializer for an integer type variable that is not of integer type.
Fix this by not calling int_fits_type_p unless the previous check for
an integer constant expression passes.

Bootstrapped with no regressions for x86_64-pc-linux-gnu.

PR c/115515

gcc/c/
* c-typeck.cc (check_constexpr_init): Do not call int_fits_type_p
for arguments that are not integer constant expressions.

gcc/testsuite/
* gcc.dg/c23-constexpr-10.c, gcc.dg/gnu23-constexpr-2.c: New
tests.

RISC-V: Remove unnecessary option for all other scalar SAT_* testcase

After we create a isolated folder to hold all SAT scalar test,
we have fully control of what optimization options passing to
the testcase.  Thus, it is better to remove the unnecessary
work around for flto option, as well as the -O3 option for
each cases.  The riscv.exp will pass sorts of different optimization
options for each case.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat/sat_s_sub-1-i16.c: Remove flto
dg-skip workaround and -O3 option.
* gcc.target/riscv/sat/sat_s_sub-1-i32.c: Ditto.
* gcc.target/riscv/sat/sat_s_sub-1-i64.c: Ditto.
* gcc.target/riscv/sat/sat_s_sub-1-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_sub-2-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_sub-2-i32.c: Ditto.
* gcc.target/riscv/sat/sat_s_sub-2-i64.c: Ditto.
* gcc.target/riscv/sat/sat_s_sub-2-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_sub-3-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_sub-3-i32.c: Ditto.
* gcc.target/riscv/sat/sat_s_sub-3-i64.c: Ditto.
* gcc.target/riscv/sat/sat_s_sub-3-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_sub-4-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_sub-4-i32.c: Ditto.
* gcc.target/riscv/sat/sat_s_sub-4-i64.c: Ditto.
* gcc.target/riscv/sat/sat_s_sub-4-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-1-i16-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i32.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-2-i16-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i32.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-3-i16-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i32.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-4-i16-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i32.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-5-i16-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i32.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-6-i16-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i32.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-7-i16-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i32.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-8-i16-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i8.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i16.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i32.c: Ditto.
* gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Rearrange the rest of test files for scalar SAT_* [NFC]

Move all the other files of scalar SAT to dir riscv/sat/.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_s_sub-1-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-1-i16.c: ...here.
* gcc.target/riscv/sat_s_sub-1-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-1-i32.c: ...here.
* gcc.target/riscv/sat_s_sub-1-i64.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-1-i64.c: ...here.
* gcc.target/riscv/sat_s_sub-1-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-1-i8.c: ...here.
* gcc.target/riscv/sat_s_sub-2-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-2-i16.c: ...here.
* gcc.target/riscv/sat_s_sub-2-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-2-i32.c: ...here.
* gcc.target/riscv/sat_s_sub-2-i64.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-2-i64.c: ...here.
* gcc.target/riscv/sat_s_sub-2-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-2-i8.c: ...here.
* gcc.target/riscv/sat_s_sub-3-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-3-i16.c: ...here.
* gcc.target/riscv/sat_s_sub-3-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-3-i32.c: ...here.
* gcc.target/riscv/sat_s_sub-3-i64.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-3-i64.c: ...here.
* gcc.target/riscv/sat_s_sub-3-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-3-i8.c: ...here.
* gcc.target/riscv/sat_s_sub-4-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-4-i16.c: ...here.
* gcc.target/riscv/sat_s_sub-4-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-4-i32.c: ...here.
* gcc.target/riscv/sat_s_sub-4-i64.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-4-i64.c: ...here.
* gcc.target/riscv/sat_s_sub-4-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-4-i8.c: ...here.
* gcc.target/riscv/sat_s_sub-run-1-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-run-1-i16.c: ...here.
* gcc.target/riscv/sat_s_sub-run-1-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-run-1-i32.c: ...here.
* gcc.target/riscv/sat_s_sub-run-1-i64.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-run-1-i64.c: ...here.
* gcc.target/riscv/sat_s_sub-run-1-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-run-1-i8.c: ...here.
* gcc.target/riscv/sat_s_sub-run-2-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-run-2-i16.c: ...here.
* gcc.target/riscv/sat_s_sub-run-2-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-run-2-i32.c: ...here.
* gcc.target/riscv/sat_s_sub-run-2-i64.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-run-2-i64.c: ...here.
* gcc.target/riscv/sat_s_sub-run-2-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-run-2-i8.c: ...here.
* gcc.target/riscv/sat_s_sub-run-3-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-run-3-i16.c: ...here.
* gcc.target/riscv/sat_s_sub-run-3-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-run-3-i32.c: ...here.
* gcc.target/riscv/sat_s_sub-run-3-i64.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-run-3-i64.c: ...here.
* gcc.target/riscv/sat_s_sub-run-3-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-run-3-i8.c: ...here.
* gcc.target/riscv/sat_s_sub-run-4-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-run-4-i16.c: ...here.
* gcc.target/riscv/sat_s_sub-run-4-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-run-4-i32.c: ...here.
* gcc.target/riscv/sat_s_sub-run-4-i64.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-run-4-i64.c: ...here.
* gcc.target/riscv/sat_s_sub-run-4-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_sub-run-4-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-1-i16-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-1-i16-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-1-i32-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-1-i32-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-1-i64-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-1-i64-to-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i32.c: ...here.
* gcc.target/riscv/sat_s_trunc-1-i64-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-2-i16-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-2-i16-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-2-i32-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-2-i32-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-2-i64-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-2-i64-to-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i32.c: ...here.
* gcc.target/riscv/sat_s_trunc-2-i64-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-3-i16-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-3-i16-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-3-i32-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-3-i32-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-3-i64-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-3-i64-to-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i32.c: ...here.
* gcc.target/riscv/sat_s_trunc-3-i64-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-4-i16-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-4-i16-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-4-i32-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-4-i32-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-4-i64-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-4-i64-to-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i32.c: ...here.
* gcc.target/riscv/sat_s_trunc-4-i64-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-5-i16-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-5-i16-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-5-i32-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-5-i32-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-5-i64-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-5-i64-to-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i32.c: ...here.
* gcc.target/riscv/sat_s_trunc-5-i64-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-6-i16-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-6-i16-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-6-i32-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-6-i32-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-6-i64-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-6-i64-to-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i32.c: ...here.
* gcc.target/riscv/sat_s_trunc-6-i64-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-7-i16-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-7-i16-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-7-i32-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-7-i32-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-7-i64-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-7-i64-to-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i32.c: ...here.
* gcc.target/riscv/sat_s_trunc-7-i64-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-8-i16-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-8-i16-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-8-i32-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-8-i32-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-8-i64-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-8-i64-to-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i32.c: ...here.
* gcc.target/riscv/sat_s_trunc-8-i64-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-1-i16-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-1-i16-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-1-i32-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-1-i32-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-1-i64-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-1-i64-to-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i32.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-1-i64-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-2-i16-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-2-i16-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-2-i32-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-2-i32-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-2-i64-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-2-i64-to-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i32.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-2-i64-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-3-i16-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-3-i16-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-3-i32-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-3-i32-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-3-i64-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-3-i64-to-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i32.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-3-i64-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-4-i16-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-4-i16-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-4-i32-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-4-i32-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-4-i64-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-4-i64-to-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i32.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-4-i64-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-5-i16-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-5-i16-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-5-i32-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-5-i32-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-5-i64-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-5-i64-to-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i32.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-5-i64-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-6-i16-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-6-i16-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-6-i32-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-6-i32-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-6-i64-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-6-i64-to-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i32.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-6-i64-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-7-i16-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-7-i16-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-7-i32-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-7-i32-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-7-i64-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-7-i64-to-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i32.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-7-i64-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-8-i16-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-8-i16-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-8-i32-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-8-i32-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i8.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-8-i64-to-i16.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i16.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-8-i64-to-i32.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i32.c: ...here.
* gcc.target/riscv/sat_s_trunc-run-8-i64-to-i8.c: Move to...
* gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i8.c: ...here.
* gcc.target/riscv/sat_arith.h: Removed.
* gcc.target/riscv/sat_arith_data.h: Removed.

Signed-off-by: Pan Li <pan2.li@intel.com>

Daily bump.

fortran: Inline non-character MINLOC/MAXLOC with DIM [PR90608]

Enable generation of inline MINLOC/MAXLOC code in the cases where DIM is a
constant, and either ARRAY is of REAL type or MASK is an array.  Those cases
are the remaining bits to fully support inlining of non-CHARACTER
MINLOC/MAXLOC with constant DIM.  They are treated together because they
generate similar code, the NANs for REAL types being handled a bit like a
second level of masking.  These are the cases for which we generate two
loops.

This change affects the code generating the second loop, that was
previously accessible only in cases ARRAY had rank 1.

The main changes are in gfc_conv_intrinsic_minmaxloc the replacement of the
locally initialized scalarization loop with the one provided and previously
initialized by the scalarizer.  Same goes for the locally initialized MASK
scalarizer chain.

As this is enabling the code generating a second loop in a context of
reduction and nested loops, care is taken not to advance the parent
scalarization chain twice.

The scalarization chain element(s) for an array MASK are inserted in the
chain at a different place from that of a scalar MASK.  This is done on
purpose to match the code consuming the chains which are in different places
for scalar and array MASK.

PR fortran/90608

gcc/fortran/ChangeLog:

* trans-intrinsic.cc (gfc_inline_intrinsic_function_p): Return TRUE
for MINLOC/MAXLOC with constant DIM and either REAL ARRAY or
non-scalar MASK.
(walk_inline_intrinsic_minmaxloc): Walk MASK and if it's an array
add the chain obtained before that of ARRAY.
(gfc_conv_intrinsic_minmaxloc): Use the nested loop if there is one.
To evaluate MASK (respectively ARRAY in the second loop), inherit
the scalarizer chain if in a nested loop, otherwise keep using the
chain obtained by walking MASK (respectively ARRAY).  If there is a
nested loop, avoid advancing the parent scalarization chain a second
time in the second loop.

gcc/testsuite/ChangeLog:

* gfortran.dg/minmaxloc_21.f90: New test.

c: Do not register nullptr_t built-in type [PR114869]

As reported in bug 114869, the C front end wrongly creates nullptr_t
as a built-in typedef; it should only be defined in <stddef.h>.  While
the type node needs a name for debug info generation, it doesn't need
to be a valid identifier; use typeof (nullptr) instead, similar to how
the C++ front end uses decltype(nullptr) for this purpose.

Bootstrapped with no regressions for x86_64-pc-linux-gnu.

PR c/114869

gcc/c/
* c-decl.cc (c_init_decl_processing): Register nullptr_type_node
as typeof (nullptr) not nullptr_t.

gcc/testsuite/
* gcc.dg/c23-nullptr-5.c: Use typeof (nullptr) not nullptr_t.
* gcc.dg/c11-nullptr-2.c, gcc.dg/c11-nullptr-3.c,
gcc.dg/c23-nullptr-7.c: New tests

AVR: target/54378 - Reconsider the default shift costs.

This patch calculates more accurate shift costs, but makes
the costs for larger offsets no more expensive than the costs
for an unrolled shift.

gcc/
PR target/54378
* config/avr/avr.cc (avr_default_shift_costs): New static function.
(avr_rtx_costs_1) [ASHIFT, LSHIFTRT, ASHIFTRT]: Use it
to determine the default shift costs for shifts with a
constant shift offset.

fortran: Check MASK directly instead of its scalarization chain

Update the conditions used by the inline MINLOC/MAXLOC code generation
function to check directly the properties of MASK instead of the
variable holding its scalarization chain.

The inline implementation of MINLOC/MAXLOC in gfc_conv_intrinsic_minmaxloc
uses several conditions checking the presence of a scalarization chain for
MASK, which means that the argument is present and non-scalar.  The next
patch will allow inlining MINLOC/MAXLOC with DIM and MASK, and in that
case the scalarization chain for MASK is initialized elsewhere, so the
variable usually holding it in the function is not used, and the conditions
won't work in that case.

This change updates the conditions to check directly the properties of
MASK so that they work even if the scalarization chain variable is not used.

gcc/fortran/ChangeLog:

* trans-intrinsic.cc (gfc_conv_intrinsic_minmaxloc): Use
conditionals based on the MASK expression rather than on its
scalarization chains.

c-family: Fix ICE with __sync_*_and_* on _BitInt [PR117641]

Only __atomic_* builtins are meant to work on arbitrary _BitInt types
(if not supported in hw we emit a CAS loop which uses __atomic_load_*
in that case), the compatibility __sync_* builtins work only if there
is a corresponding normal integral type (for _BitInt on 32-bit ARM
we'll need to limit even that to no padding, because the padding bits
are well defined there and the hw or libatomic __sync_* APIs don't
guarantee that), IMHO people shouldn't mix very old APIs with very
new ones and I don't see a replacement for the __atomic_load_*.

For size > 16 that is how it already correctly behaves,
in the hunk shown in the patch it is immediately followed by

  if (fetch && !orig_format && TREE_CODE (type) == BITINT_TYPE)
    return -1;

which returns -1 for the __atomic_* builtins (i.e. !orig_format),
which causes caller to use atomic_bitint_fetch_using_cas_loop,
and otherwise does diagnostic and return 0 (which causes caller
to punt).  But for size == 16 if TImode isn't suipported (i.e.
mostly 32-bit arches), we return (correctly) -1 if !orig_format,
so again force atomic_bitint_fetch_using_cas_loop on those arches
for e.g. _BitInt(115), but for orig_format the function returns
16 as if it could do 16 byte __sync_*_and_* (which it can't
because TImode isn't supported; for 16 byte it can only do
(perhaps using libatomic) normal compare and swap).  So we need
to error and return 0, rather than return 16.

The following patch ensures that.

2024-11-19  Jakub Jelinek  <jakub@redhat.com>

PR c/117641
* c-common.cc (sync_resolve_size): For size == 16 fetch of
BITINT_TYPE if TImode isn't supported scalar mode diagnose
and return 0 if orig_format instead of returning 16.

* gcc.dg/bitint-115.c: New test.

c: Fix up __builtin_stdc_rotate_{left,right} lowering [PR117456]

Apparently the middle-end/expansion can only handle {L,R}ROTATE_EXPR
on types with mode precision, or large/huge BITINT_TYPE.
So, the following patch uses the rotate exprs only in those cases
where it can be handled, and emits code with shifts/ior otherwise.
As types without mode precision including small/medium BITINT_TYPE
have unlikely power of two precision and TRUNC_MOD_EXPR is on many targets
quite expensive, I chose to expand e.g. __builtin_stdc_rotate_left (arg1,
arg2) as
((tem = arg1, count = arg2 % prec)
 ? ((tem << count) | (tem >> (prec - count))) : tem)
rather than
(((tem = arg1) << (count = arg2 % prec))
 | (tem >> (-count % prec))
(where the assignments are really save_exprs, so no UB), because
I think another TRUNC_MOD_EXPR would be more costly in most cases
when the shift count is non-constant (and when it is constant,
it folds to 2 shifts by constant and ior in either case).

2024-11-19  Jakub Jelinek  <jakub@redhat.com>

PR c/117456
gcc/c/
* c-parser.cc (c_parser_postfix_expression): Use LROTATE_EXPR
or RROTATE_EXPR only if type_has_mode_precision_p or if arg1
has BITINT_TYPE with precision larger than MAX_FIXED_MODE_SIZE.
Otherwise build BIT_IOR_EXPR of LSHIFT_EXPR and RSHIFT_EXPR
and wrap it into a COND_EXPR depending on if arg2 is 0 or not.
* c-fold.cc (c_fully_fold_internal): Check for suppression of
-Wshift-count-overflow warning.
gcc/testsuite/
* gcc.dg/builtin-stdc-rotate-4.c: New test.