dt-bindings: pinctrl: qcom: drop common properties
Drop common properties already defined in referenced common Qualcomm SoC
TLMM bindings and use "unevaluatedProperties: false". This makes the
binding smaller and easier to review.
In few places move the "required:" block to bottom, to match convention.
dt-bindings: pinctrl: qcom: create common LPASS LPI schema
Just like regular TLMM pin controllers in Qualcomm SoCs, the Low Power
Audio SubSystem (LPASS) Low Power Island (LPI) TLMM blocks share a lot
of properties, so common part can be moved to separate schema to reduce
code duplication and make reviewing easier.
Except the move of common part, this introduces effective changes:
1. To all LPASS LPI bindings: Reference pinmux-node.yaml in each pin
muxing and configuration node, to bring definition of "function" and
"pins" properties.
2. qcom,sc7280-lpass-lpi-pinctrl: Reference pinctrl.yaml in top leve.
Johan Hovold [Thu, 30 Nov 2023 17:28:34 +0000 (18:28 +0100)]
dt-bindings: pinctrl: qcom,pmic-mpp: clean up example
The Multi-Purpose Pin controller block is part of an SPMI PMIC (which in
turns sits on an SPMI bus) and uses a single value for the register
property that corresponds to its base address.
Clean up the example by adding a parent PMIC node with proper
'#address-cells' and '#size-cells' properties, dropping the incorrect
second register value, adding some newline separators and increasing the
indentation to four spaces.
Linus Walleij [Mon, 18 Dec 2023 22:42:42 +0000 (23:42 +0100)]
Merge tag 'intel-pinctrl-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v6.8-1
* New agnostic driver to support Lunar Lake and newer platforms
* New driver for Intel Meteor Point-S (PCH for Meteor Lake-S)
* Update drivers to use new PM helpers
* Use RAII for locking in a few drivers (Raag, Andy)
* Reduce locking scope in some functions (Raag)
* Miscellaneous cleanups (Raag)
The following is an automated git shortlog grouped by driver:
alderlake:
- Switch to use Intel pin control PM ops
baytrail:
- Simplify code with cleanup helpers
- Move default strength assignment to a switch-case
- Factor out byt_gpio_force_input_mode()
- Fix types of config value in byt_pin_config_set()
broxton:
- Switch to use Intel pin control PM ops
cannonlake:
- Switch to use Intel pin control PM ops
cedarfork:
- Switch to use Intel pin control PM ops
denverton:
- Switch to use Intel pin control PM ops
elkhartlake:
- Switch to use Intel pin control PM ops
emmitsburg:
- Switch to use Intel pin control PM ops
geminilake:
- Switch to use Intel pin control PM ops
icelake:
- Switch to use Intel pin control PM ops
intel:
- Add Intel Meteor Point pin controller and GPIO support
- use the correct _PM_OPS() export macro
- Add a generic Intel pin control platform driver
- Revert "Unexport intel_pinctrl_probe()"
- allow independent COMPILE_TEST
- Refactor intel_pinctrl_get_soc_data()
- Move default strength assignment to a switch-case
- Make PM ops functions static
- Provide Intel pin control wide PM ops structure
jasperlake:
- Switch to use Intel pin control PM ops
lakefield:
- Switch to use Intel pin control PM ops
lewisburg:
- Switch to use Intel pin control PM ops
lynxpoint:
- Simplify code with cleanup helpers
meteorlake:
- Switch to use Intel pin control PM ops
sunrisepoint:
- Switch to use Intel pin control PM ops
tangier:
- simplify locking using cleanup helpers
- Move default strength assignment to a switch-case
- Enable 910 Ohm bias
tigerlake:
- Switch to use Intel pin control PM ops
Linus Walleij [Mon, 18 Dec 2023 14:07:23 +0000 (15:07 +0100)]
Merge tag 'samsung-pinctrl-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
Samsung pinctrl drivers changes for v6.8
1. New hardware: Add pin controllers for Samsung ExynosAutov920 and
Google Tensor GS101.
2. Few DT bindings cleanups: add specific compatibles for each device
using generic compatible as fallback. This affects only DTS, no
driver changes are needed.
3. Allow setting affinity on non wake-up external GPIO interrupts.
Andy Shevchenko [Thu, 14 Dec 2023 15:46:53 +0000 (17:46 +0200)]
pinctrl: intel: Add Intel Meteor Point pin controller and GPIO support
This driver supports pinctrl/GPIO hardware found on Intel Meteor Point
(a Meteor Lake PCH) providing users a pinctrl and GPIO interfaces
including GPIO interrupts.
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Claudiu Beznea [Thu, 7 Dec 2023 07:06:55 +0000 (09:06 +0200)]
pinctrl: renesas: rzg2l: Add output enable support
Some of the Ethernet pins on RZ/G3S (but also valid for RZ/G2L) need to
have the direction of the IO buffer set as output for Ethernet to work
properly. On RZ/G3S, these pins are P1_0/P7_0, P1_1/P7_1, and can have
the following Ethernet functions: TXC/TX_CLK or TX_CTL/TX_EN.
As the pins supporting output enable are SoC specific, and there is a
limited number of these pins (TXC/TX_CLK and/or TX_CTL/TX_EN), specify
output enable capable port limits in the platform-based configuration
data structure, to ensure proper validation.
The OEN support has been intantiated for RZ/G3S at the moment.
Claudiu Beznea [Thu, 7 Dec 2023 07:06:54 +0000 (09:06 +0200)]
pinctrl: renesas: rzg2l: Add support to select power source for Ethernet pins
The GPIO controller available on RZ/G3S (but also on RZ/G2L) supports
setting the power source for Ethernet pins. Based on the interface b/w
the Ethernet controller and the Ethernet PHY, and on board design, a
specific power source needs to be selected. The GPIO controller
supports 1.8V, 2.5V, and 3.3V power source selection for the Ethernet
pins. This can be selected though the ETHx_POC registers (x={0, 1}).
Adjust the driver to support this, and to do proper instantiation for
the RZ/G3S and RZ/G2L SoCs. On RZ/G2L only the get operation has been
tested at the moment.
While at it, as the power registers on RZ/G2L support access sizes of 8
bits, and these registers on RZ/G3S support access sizes of 8/16/32
bits, replace writel()/readl() on these registers with writeb()/readb().
This should allow us to use the same code on both SoCs w/o any issues.
Claudiu Beznea [Thu, 7 Dec 2023 07:06:53 +0000 (09:06 +0200)]
pinctrl: renesas: rzg2l: Add pin configuration support for pinmux groups
On RZ/G3S different Ethernet pins need to be configured with different
settings (e.g. power-source needs to be set, RGMII TXC and TX_CTL pins
need output-enable). Adjust the driver to allow specifying pin
configuration for pinmux groups. With this, DT settings like the
following are taken into account by the driver:
Claudiu Beznea [Thu, 7 Dec 2023 07:06:52 +0000 (09:06 +0200)]
pinctrl: renesas: rzg2l: Move arg and index in the main function block
Move arg and index in the main block of the function as they are used by
more than one case block of switch-case (3 out of 4 for arg, 2 out of 4
for index). In this way some lines of code are removed.
Jaewon Kim [Mon, 11 Dec 2023 11:41:44 +0000 (20:41 +0900)]
pinctrl: samsung: support ExynosAuto GPIO structure
New ExynosAuto series GPIO have a different register structure.
In the existing Exynos series, EINT control register is enumerated after
a specific offset (e.g EXYNOS_GPIO_ECON_OFFSET, EXYNOS_GPIO_EMASK_OFFSET).
However, from ExynosAutov920 SoC, the register that controls EINT belongs
to each GPIO bank, and each GPIO bank has 0x1000 align.
This is a structure to protect the GPIO bank using S2MPU in VM environment,
and will only be applied in ExynosAuto series SoCs.
Herve Codina [Tue, 28 Nov 2023 13:25:33 +0000 (14:25 +0100)]
pinctrl: Add support for the Lantic PEF2256 pinmux
The Lantiq PEF2256 is a framer and line interface component designed to
fulfill all required interfacing between an analog E1/T1/J1 line and the
digital PCM system highway/H.100 bus.
This kind of component can be found in old telecommunication system.
It was used to digital transmission of many simultaneous telephone calls
by time-division multiplexing. Also using HDLC protocol, WAN networks
can be reached through the framer.
This pinmux support handles the pin muxing part (pins RP(A..D) and pins
XP(A..D)) of the PEF2256.
Herve Codina [Tue, 28 Nov 2023 13:25:32 +0000 (14:25 +0100)]
net: wan: framer: Add support for the Lantiq PEF2256 framer
The Lantiq PEF2256 is a framer and line interface component designed to
fulfill all required interfacing between an analog E1/T1/J1 line and the
digital PCM system highway/H.100 bus.
Herve Codina [Tue, 28 Nov 2023 13:25:31 +0000 (14:25 +0100)]
dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer
The Lantiq PEF2256 is a framer and line interface component designed to
fulfill all required interfacing between an analog E1/T1/J1 line and the
digital PCM system highway/H.100 bus.
Herve Codina [Tue, 28 Nov 2023 13:25:30 +0000 (14:25 +0100)]
net: wan: Add framer framework support
A framer is a component in charge of an E1/T1 line interface.
Connected usually to a TDM bus, it converts TDM frames to/from E1/T1
frames. It also provides information related to the E1/T1 line.
The framer framework provides a set of APIs for the framer drivers
(framer provider) to create/destroy a framer and APIs for the framer
users (framer consumer) to obtain a reference to the framer, and
use the framer.
This basic implementation provides a framer abstraction for:
- power on/off the framer
- get the framer status (line state)
- be notified on framer status changes
- get/set the framer configuration
Andy Shevchenko [Mon, 11 Dec 2023 18:58:05 +0000 (20:58 +0200)]
pinctrl: starfive: Convert to use grp member
Convert drivers to use grp member embedded in struct group_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin group description.
Andy Shevchenko [Mon, 11 Dec 2023 18:58:04 +0000 (20:58 +0200)]
pinctrl: renesas: Convert to use grp member
Convert drivers to use grp member embedded in struct group_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin group description.
Andy Shevchenko [Mon, 11 Dec 2023 18:58:03 +0000 (20:58 +0200)]
pinctrl: mediatek: Convert to use grp member
Convert drivers to use grp member embedded in struct group_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin group description.
Andy Shevchenko [Mon, 11 Dec 2023 18:58:02 +0000 (20:58 +0200)]
pinctrl: keembay: Convert to use grp member
Convert drivers to use grp member embedded in struct group_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin group description.
Andy Shevchenko [Mon, 11 Dec 2023 18:58:01 +0000 (20:58 +0200)]
pinctrl: ingenic: Convert to use grp member
Convert drivers to use grp member embedded in struct group_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin group description.
Andy Shevchenko [Mon, 11 Dec 2023 18:58:00 +0000 (20:58 +0200)]
pinctrl: imx: Convert to use grp member
Convert drivers to use grp member embedded in struct group_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin group description.
Andy Shevchenko [Mon, 11 Dec 2023 18:57:59 +0000 (20:57 +0200)]
pinctrl: equilibrium: Convert to use grp member
Convert drivers to use grp member embedded in struct group_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin group description.
Andy Shevchenko [Mon, 11 Dec 2023 18:57:58 +0000 (20:57 +0200)]
pinctrl: bcm: Convert to use grp member
Convert drivers to use grp member embedded in struct group_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin group description.
Andy Shevchenko [Mon, 11 Dec 2023 18:57:57 +0000 (20:57 +0200)]
pinctrl: core: Embed struct pingroup into struct group_desc
struct group_desc is a particular version of the struct pingroup
with associated opaque data. Start switching pin control core and
drivers to use it explicitly.
ExynosAutov920 SoC wake-up pin controller has different register layout
than Exynos7, thus it should not be marked as compatible. Neither DTS
nor Linux driver was merged yet, so the change does not impact ABI.
Cc: Jaewon Kim <jaewon02.kim@samsung.com> Fixes: 904140fa4553 ("dt-bindings: pinctrl: samsung: use Exynos7 fallbacks for newer wake-up controllers") Link: https://lore.kernel.org/r/20231210133915.42112-1-krzysztof.kozlowski@linaro.org Reviewed-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
gs101 is similar to newer Exynos SoCs like Exynos850 and ExynosAutov9
where more than one pin controller can do external wake-up interrupt.
So add a dedicated compatible for it.
gpiolib: use gpiochip_dup_line_label() in for_each helpers
Rework for_each_requested_gpio_in_range() to use the new helper to
retrieve a dynamically allocated copy of the descriptor label and free
it at the end of each iteration. We need to leverage the CLASS()'
destructor to make sure that the label is freed even when breaking out
of the loop.
Andy Shevchenko [Mon, 4 Dec 2023 15:56:33 +0000 (17:56 +0200)]
pinctrl: core: Make pins const unsigned int pointer in struct group_desc
It's unclear why it's not a const unsigned int pointer from day 1.
Make the pins member const unsigned int pointer in struct group_desc.
Update necessary APIs.
Document the Qualcomm X1E80100 SoC Low Power Audio SubSystem Low Power
Island (LPASS LPI) pin controller, compatible with earlier SM8550 model.
Cc: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20231129155738.167030-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
On j7200, during suspend to ram pinctrl contexts are lost. To save and
restore contexts during suspend/resume, the flag PCS_CONTEXT_LOSS_OFF
shall be set.
Richard Acayan [Tue, 28 Nov 2023 02:02:04 +0000 (21:02 -0500)]
pinctrl: qcom: fail to retrieve configuration from invalid pin groups
The pinconf-groups debugfs file dumps each valid configuration item of
all pin groups. Some platforms and devices may have pin groups which
cannot be accessed, according to commit 691bf5d5a7bf ("pinctrl: qcom:
Don't allow protected pins to be requested"). Fail for each
configuration item of an invalid pin group by checking the GPIO chip's
valid mask.
The validity of the pin group cannot be checked in the generic pinconf
dump (function "pinconf_generic_dump_one"), as it does not directly
interact with the gpiochip or the pinmux callbacks (which would give it
access to the request callback). Instead, an entry contains the ID and
name of the pingroup with no properties when all items fail.
Andy Shevchenko [Wed, 29 Nov 2023 16:06:28 +0000 (18:06 +0200)]
pinctrl: imx: Use temporary variable to hold pins
The pins are allocated from the heap, but in order to pass
them as constant object, we need to use non-constant pointer.
Achieve this by using a temporary variable.
Andy Shevchenko [Wed, 29 Nov 2023 16:06:27 +0000 (18:06 +0200)]
pinctrl: equilibrium: Use temporary variable to hold pins
The pins are allocated from the heap, but in order to pass
them as constant object, we need to use non-constant pointer.
Achieve this by using a temporary variable.
Andy Shevchenko [Wed, 29 Nov 2023 16:06:26 +0000 (18:06 +0200)]
pinctrl: equilibrium: Unshadow error code of of_property_count_u32_elems()
of_property_count_u32_elems() might return an error code in some cases.
It's naturally better to assign what it's returned to the err variable
and supply the real code to the upper layer(s). Besides that, it's a
common practice to avoid assignments for the data in cases when we know
that the error condition happened. Refactor the code accordingly.
Signed-off-by: Youngmin Nam <youngmin.nam@samsung.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Tested-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20231126094618.2545116-1-youngmin.nam@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Andy Shevchenko [Wed, 22 Nov 2023 17:50:38 +0000 (19:50 +0200)]
pinctrl: baytrail: Move default strength assignment to a switch-case
When ->pin_config_set() is called from the GPIO library (assumed
GpioIo() ACPI resource), the argument can be 1, when, for example,
PullDefault is provided. In such case we supply sane default in
the driver. Move that default assingment to a switch-case, so
it will be consolidated in one place.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andrew Davis [Thu, 16 Nov 2023 22:30:45 +0000 (16:30 -0600)]
pinctrl: as3722: Use devm_gpiochip_add_data() to simplify remove path
Use devm version of gpiochip add function to handle removal for us.
Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Andy Shevchenko <andy@kernel.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20231116223045.274211-1-afd@ti.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Rajendra Nayak [Fri, 17 Nov 2023 09:39:21 +0000 (15:09 +0530)]
pinctrl: qcom: Add X1E80100 pinctrl driver
Add initial pinctrl driver to support pin configuration with pinctrl
framework for X1E80100 SoC.
Co-developed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231117093921.31968-3-quic_sibis@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tomer Maimon [Wed, 15 Nov 2023 21:12:09 +0000 (13:12 -0800)]
pinctrl: npcm7xx: prevent glitch when setting the GPIO to output high
Enable GPIO output after setting the output value to prevent a glitch
when pinctrl driver sets gpio pin to output high and the pin is in
the default state (high->low->high).
Sergey Shtylyov [Wed, 15 Nov 2023 20:34:53 +0000 (23:34 +0300)]
pinctrl: stm32: return errors from stm32_gpio_direction_output()
In the STMicroelectronics STM32 driver, stm32_gpio_direction_output()
ignores the result of pinctrl_gpio_direction_output() for no good reason.
Let's propagate errors from pinctrl_gpio_direction_output() upstream...
Found by Linux Verification Center (linuxtesting.org) with the Svace static
analysis tool.
dt-bindings: pinctrl: samsung: use Exynos7 fallbacks for newer wake-up controllers
Older ARM8 SoCs like Exynos5433, Exynos7 and Exynos7885 have the pin
controller with wake-up interrupts muxed, thus the wake-up interrupt
controller device node has interrupts property, while its pin banks
might not (because they are muxed by the wake-up controller).
Newer SoCs like Exynos850 and ExynosAutov9 do not used muxed wake-up
interrupts:
1. Wake-up interrupt controller device node has no interrupts,
2. Its pin banks have interrupts (since there is no muxing).
Their programming interface is however still compatible with Exynos7,
thus change the bindings to express this: retain compatibility with
Exynos7 and add new compatibility fallback of Exynos850 in newer
designs.
No driver changes are needed. This is necessary only to properly
describe DTS.
Raag Jadav [Wed, 22 Nov 2023 10:54:01 +0000 (16:24 +0530)]
pinctrl: intel: use the correct _PM_OPS() export macro
Since we don't have runtime PM handles here, we should be using
EXPORT_NS_GPL_DEV_SLEEP_PM_OPS() macro, so that the compiler can
discard it in case CONFIG_PM_SLEEP=n.
Fixes: b10a74b5c0c1 ("pinctrl: intel: Provide Intel pin control wide PM ops structure") Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
dt-bindings: pinctrl: samsung: add specific compatibles for existing SoC
Samsung Exynos SoC reuses several devices from older designs, thus
historically we kept the old (block's) compatible only. This works fine
and there is no bug here, however guidelines expressed in
Documentation/devicetree/bindings/writing-bindings.rst state that:
1. Compatibles should be specific.
2. We should add new compatibles in case of bugs or features.
Add compatibles specific to each SoC in front of all old-SoC-like
compatibles.
Andy Shevchenko [Mon, 13 Nov 2023 12:28:48 +0000 (14:28 +0200)]
pinctrl: intel: Add a generic Intel pin control platform driver
New generations of Intel platforms will provide better description
of the pin control devices in the ACPI tables. Hence, we may provide
a generic pin control platform driver to cover all of them. Currently
the following Intel SoCs / platforms require this to be functional:
- Lunar Lake
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
projects / thirdparty / kernel / linux.git / log
