Alexandre Oliva [Wed, 24 May 2023 06:08:10 +0000 (03:08 -0300)]
[testsuite] [x86] cope with --enable-frame-pointer
Various x86 tests fail if the toolchain is configured with
--enable-frame-pointer, because the unexpected extra insns mess with
the expected asm counts. Add -fomit-frame-pointer so that they can
still pass.
Andrew MacLeod [Wed, 24 May 2023 13:52:26 +0000 (09:52 -0400)]
Gimple range PHI analyzer and testcases
Provide a PHI analyzer framework to provive better initial values for
PHI nodes which formk groups with initial values and single statements
which modify the PHI values in some predicatable way.
PR tree-optimization/107822
PR tree-optimization/107986
gcc/
* Makefile.in (OBJS): Add gimple-range-phi.o.
* gimple-range-cache.h (ranger_cache::m_estimate): New
phi_analyzer pointer member.
* gimple-range-fold.cc (fold_using_range::range_of_phi): Use
phi_analyzer if no loop info is available.
* gimple-range-phi.cc: New file.
* gimple-range-phi.h: New file.
* tree-vrp.cc (execute_ranger_vrp): Utililze a phi_analyzer.
Andrew MacLeod [Wed, 24 May 2023 13:17:32 +0000 (09:17 -0400)]
Provide relation queries for a stmt.
Allow fur_list and fold_stmt to be provided a range_query rather than
always defaultsing to NULL (which becomes a global query).
Also provide a fold_relations () routine which can provide a range_trio
for an arbitrary statement using any range_query
Andrew MacLeod [Wed, 24 May 2023 13:06:26 +0000 (09:06 -0400)]
Make ssa_cache a range_query.
By providing range_of_expr as a range_query, we can fold and do other
interesting things using values from the global table. Make ranger's
knonw globals available via const_query.
Harald Anlauf [Sun, 21 May 2023 20:25:29 +0000 (22:25 +0200)]
Fortran: checking and simplification of RESHAPE intrinsic [PR103794]
gcc/fortran/ChangeLog:
PR fortran/103794
* check.cc (gfc_check_reshape): Expand constant arguments SHAPE and
ORDER before checking.
* gfortran.h (gfc_is_constant_array_expr): Add prototype.
* iresolve.cc (gfc_resolve_reshape): Expand constant argument SHAPE.
* simplify.cc (is_constant_array_expr): If array is determined to be
constant, expand small array constructors if needed.
(gfc_is_constant_array_expr): Wrapper for is_constant_array_expr.
(gfc_simplify_reshape): Fix check for insufficient elements in SOURCE
when no padding specified.
gcc/testsuite/ChangeLog:
PR fortran/103794
* gfortran.dg/reshape_10.f90: New test.
* gfortran.dg/reshape_11.f90: New test.
PR libstdc++/109949
* include/experimental/bits/simd.h (__intrinsic_type): If
__ALTIVEC__ is defined, map gnu::vector_size types to their
corresponding __vector T types without losing unsignedness of
integer types. Also prefer long long over long.
* include/experimental/bits/simd_ppc.h (_S_popcount): Cast mask
object to the expected unsigned vector type.
Roger Sayle [Wed, 24 May 2023 16:32:20 +0000 (17:32 +0100)]
PR middle-end/109840: Preserve popcount/parity type in match.pd.
PR middle-end/109840 is a regression introduced by my recent patch to
fold popcount(bswap(x)) as popcount(x). When the bswap and the popcount
have the same precision, everything works fine, but this optimization also
allowed a zero-extension between the two. The oversight is that we need
to be strict with type conversions, both to avoid accidentally changing
the argument type to popcount, and also to reflect the effects of
argument/return-value promotion in the call to bswap, so this zero extension
needs to be preserved/explicit in the optimized form.
Interestingly, match.pd should (in theory) be able to narrow calls to
popcount and parity, removing a zero-extension from its argument, but
that is an independent optimization, that needs to check IFN_ support.
Many thanks to Andrew Pinski for his help/fixes with these transformations.
2023-05-24 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
PR middle-end/109840
* match.pd <popcount optimizations>: Preserve zero-extension when
optimizing popcount((T)bswap(x)) and popcount((T)rotate(x,y)) as
popcount((T)x), so the popcount's argument keeps the same type.
<parity optimizations>: Likewise preserve extensions when
simplifying parity((T)bswap(x)) and parity((T)rotate(x,y)) as
parity((T)x), so that the parity's argument type is the same.
gcc/testsuite/ChangeLog
PR middle-end/109840
* gcc.dg/fold-parity-8.c: New test.
* gcc.dg/fold-popcount-11.c: Likewise.
Aldy Hernandez [Wed, 17 May 2023 09:29:32 +0000 (11:29 +0200)]
Provide an API for ipa_vr.
This patch encapsulates the ipa_vr internals into an API. It also
makes it type agnostic, in preparation for upcoming changes to IPA.
Interestingly, there's a 0.44% improvement to IPA-cp, which I'm sure
we'll soak up with future changes in this area :).
gcc/ChangeLog:
* ipa-cp.cc (ipa_value_range_from_jfunc): Use new ipa_vr API.
(ipcp_store_vr_results): Same.
* ipa-prop.cc (ipa_vr::ipa_vr): New.
(ipa_vr::get_vrange): New.
(ipa_vr::set_unknown): New.
(ipa_vr::streamer_read): New.
(ipa_vr::streamer_write): New.
(write_ipcp_transformation_info): Use new ipa_vr API.
(read_ipcp_transformation_info): Same.
(ipa_vr::nonzero_p): Delete.
(ipcp_update_vr): Use new ipa_vr API.
* ipa-prop.h (class ipa_vr): Provide an API and hide internals.
* ipa-sra.cc (zap_useless_ipcp_results): Use new ipa_vr API.
One of the supplied argument strings is unneccesarily long (c-sky, using
basically the same code, fixed it to a shorter length) and this fixes overflow
warnings, as GCC fails to deduce that the full 256 bytes for load_op[] are
not used at all.
gcc/ChangeLog:
* config/mcore/mcore.cc (output_inline_const) Make buffer smaller to
silence overflow warnings later on.
Uros Bizjak [Wed, 24 May 2023 14:17:55 +0000 (16:17 +0200)]
i386: Add v<any_shift:insn>v4qi3 expander
Also, move v<any_shift:insn>v8qi3 expander to a better place and enable
it with TARGET_MMX_WITH_SSE. Remove handling of V8QImode from
ix86_expand_vecop_qihi2 since all partial QI->HI vector modes expand
via ix86_expand_vecop_qihi_partial.
gcc/ChangeLog:
* config/i386/i386-expand.cc (ix86_expand_vecop_qihi2):
Remove handling of V8QImode.
* config/i386/mmx.md (v<insn>v8qi3): Move from sse.md.
Call ix86_expand_vecop_qihi_partial. Enable for TARGET_MMX_WITH_SSE.
(v<insn>v4qi3): Ditto.
* config/i386/sse.md (v<insn>v8qi3): Remove.
gcc/testsuite/ChangeLog:
* gcc.target/i386/vect-shiftv4qi.c (dg-options):
Remove -ftree-vectorize.
* gcc.target/i386/vect-shiftv8qi.c (dg-options): Ditto.
* gcc.target/i386/vect-vshiftv4qi.c: New test.
* gcc.target/i386/vect-vshiftv8qi.c: New test.
Richard Biener [Wed, 24 May 2023 08:07:36 +0000 (10:07 +0200)]
target/109944 - avoid STLF fail for V16QImode CTOR expansion
The following dispatches to V2DImode CTOR expansion instead of
using sets of (subreg:DI (reg:V16QI 146) [08]) which causes
LRA to spill DImode and reload V16QImode. The same applies for
V8QImode or V4HImode construction from SImode parts which happens
during 32bit libgcc build.
PR target/109944
* config/i386/i386-expand.cc (ix86_expand_vector_init_general):
Perform final vector composition using
ix86_expand_vector_init_general instead of setting
the highpart and lowpart which causes spilling.
* gcc.target/i386/pr109944-1.c: New testcase.
* gcc.target/i386/pr109944-2.c: Likewise.
Andrew MacLeod [Tue, 23 May 2023 19:20:56 +0000 (15:20 -0400)]
Use negative values to reflect always_current in the temporal cache.
Instead of using 0, use negative timestamps to reflect always_current state.
If the value doesn't change, keep the timestamp rather than creating a new
one and invalidating any dependencies.
PR tree-optimization/109695
* gimple-range-cache.cc (temporal_cache::temporal_value): Return
a positive int.
(temporal_cache::current_p): Check always_current method.
(temporal_cache::set_always_current): Add param and set value
appropriately.
(temporal_cache::always_current_p): New.
(ranger_cache::get_global_range): Adjust.
(ranger_cache::set_global_range): set always current first.
Richard Biener [Wed, 24 May 2023 10:36:28 +0000 (12:36 +0200)]
tree-optimization/109849 - fix fallout of PRE hoisting change
The PR109849 fix made us no longer hoist some memory loads because
of the expression set intersection. We can still avoid to compute
the union by simply taking the first sets expressions and leave
the pruning of expressions with values not suitable for hoisting
to sorted_array_from_bitmap_set.
PR tree-optimization/109849
* tree-ssa-pre.cc (do_hoist_insertion): Do not intersect
expressions but take the first sets.
PR libstdc++/109261
* include/experimental/bits/simd.h (__intrinsic_type):
Specialize __intrinsic_type<double, 8> and
__intrinsic_type<double, 16> in any case, but provide the member
type only with __aarch64__.
PR libstdc++/109261
* include/experimental/bits/simd_neon.h (_S_reduce): Add
constexpr and make NEON implementation conditional on
not __builtin_is_constant_evaluated.
Gaius Mulley [Wed, 24 May 2023 10:14:07 +0000 (11:14 +0100)]
PR modula2/109952 Inconsistent HIGH values with 'ARRAY OF CHAR'
This patch fixes the case when a single character constant literal is
passed as a string actual parameter to an ARRAY OF CHAR formal parameter.
To be consistent a single character is promoted to a string and nul
terminated (and its high value is 1). Previously a single character
string would not be nul terminated and the high value was 0.
The documentation now includes a section describing the expected behavior
and included in this patch is some regression test code matching the
table inside the documentation.
gcc/ChangeLog:
PR modula2/109952
* doc/gm2.texi (High procedure function): New node.
(Using): New menu entry for High procedure function.
gcc/m2/ChangeLog:
PR modula2/109952
* Make-maintainer.in: Change header to include emacs file mode.
* gm2-compiler/M2GenGCC.mod (BuildHighFromChar): Check whether
operand is a constant string and is nul terminated then return one.
* gm2-compiler/PCSymBuild.mod (WalkFunction): Add default return
TRUE. Static analysis missing return path fix.
* gm2-libs/IO.mod (Init): Rewrite to help static analysis.
* target-independent/m2/gm2-libs.texi: Rebuild.
gcc/testsuite/ChangeLog:
PR modula2/109952
* gm2/pim/run/pass/hightests.mod: New test.
early-remat: Resync with new DF postorders [PR109940]
When I wrote early-remat, the DF_FORWARD block order was a postorder
of a reverse/backward walk (i.e. of the inverted cfg), rather than a
reverse postorder of a forward walk. A postorder of a backward walk
lacked the important property that dominators come before the blocks
they dominate; instead it ensures that postdominators come after
the blocks that they postdominate.
The DF_BACKWARD block order was similarly a postorder of a forward
walk. Since early-remat wanted a standard postorder and reverse
postorder with normal dominator properties, it used the DF_BACKWARD
order instead of the DF_FORWARD order.
g:53dddbfeb213ac4ec39f fixed the DF orders so that DF_FORWARD was
an RPO of a forward walk and so that DF_BACKWARD was an RPO of a
backward walk. This meant that iterating backwards over the
DF_BACKWARD order had the exact problem that the original DF_FORWARD
order had, triggering a flurry of ICEs for SVE.
This fixes the build with SVE enabled. It also fixes an ICE
in g++.target/aarch64/sve/pr99766.C with normal builds. I've
included the test from the PR as well, for extra coverage.
gcc/
PR rtl-optimization/109940
* early-remat.cc (postorder_index): Rename to...
(rpo_index): ...this.
(compare_candidates): Sort by decreasing rpo_index rather than
increasing postorder_index.
(early_remat::sort_candidates): Calculate the forward RPO from
DF_FORWARD.
(early_remat::local_phase): Follow forward RPO using DF_FORWARD,
rather than DF_BACKWARD in reverse.
gcc/testsuite/
* gcc.dg/torture/pr109940.c: New test.
Kyrylo Tkachov [Wed, 24 May 2023 08:33:04 +0000 (09:33 +0100)]
arm: PR target/109939 Correct signedness of return type of __ssat intrinsics
As the PR says we shouldn't be using qualifier_unsigned for the return type of the __ssat intrinsics.
UNSIGNED_SAT_BINOP_UNSIGNED_IMM_QUALIFIERS already exists for that.
This was just a thinko.
This patch fixes this and the warning with -Wconversion goes away.
Bootstrapped and tested on arm-none-linux-gnueabihf.
gcc/ChangeLog:
PR target/109939
* config/arm/arm-builtins.cc (SAT_BINOP_UNSIGNED_IMM_QUALIFIERS): Use
qualifier_none for the return operand.
gcc/testsuite/ChangeLog:
PR target/109939
* gcc.target/arm/pr109939.c: New test.
Juzhe-Zhong [Wed, 24 May 2023 07:31:46 +0000 (15:31 +0800)]
RISC-V: Add RVV mask logic auto-vectorization
This patch is adding mask logic auto-vectorization, define the pattern
as "define_insn_and_split" to allow combine PASS easily combine series
instructions.
For example:
combine vmxor.mm + vmnot.m into vmxnor.mm
Alexandre Oliva [Wed, 24 May 2023 06:07:44 +0000 (03:07 -0300)]
[testsuite] [i386] enable sse2 for signbit-2.c
The expected results for signbit-2 only arise on x86 with avx512f
disabled and sse2 enabled. The patch already disables avx512f
explicitly, but it fails to enable sse2.
Alexandre Oliva [Wed, 24 May 2023 06:07:41 +0000 (03:07 -0300)]
Check for sysconf decl on vxworks
The sysconf function is only available in rtp mode on vxworks. In
kernel mode, it is not even declared, but the feature test macro in
the testsuite doesn't notice its absence because it's a link test, and
vxworks kernel mode uses partial linking.
This patch introduces an alternate test on vxworks targets to check
for a declaration and for an often-used sysconf parameter.
for gcc/testsuite/ChangeLog
* lib/target-supports.exp (check_effective_target_sysconf):
Check for declaration and _SC_PAGESIZE on vxworks.
Kewen Lin [Wed, 24 May 2023 05:05:01 +0000 (00:05 -0500)]
vect: Enhance cost evaluation in vect_transform_slp_perm_load_1
Following Richi's suggestion in [1], I'm working on deferring
cost evaluation next to the transformation, this patch is
to enhance function vect_transform_slp_perm_load_1 which
could under-cost for vector permutation, since the costing
doesn't try to consider nvectors_per_build, it's inconsistent
with the transformation part.
Basically it changes the below
if (index == count)
{
if (!noop_p)
{
// A ...
// ++*n_perms;
if (!analyze_only)
{
// B1 ...
// B2 ...
for ...
// B3 building VEC_PERM_EXPR
}
}
else if (!analyze_only)
{
// no B2 since no any further uses here.
for ...
// B4 building nothing
}
// B5 ...
}
to:
if (index == count)
{
if (!noop_p)
{
// A ...
if (!analyze_only)
// B1 ...
// B2 ... (trivial computations during analyze_only or not)
for ...
{
// now n_perms is consistent with building VEC_PERM_EXPR
// ++*n_perms;
if (analyze_only)
continue;
// B3 building VEC_PERM_EXPR
}
}
else if (!analyze_only)
{
// no B2 since no any further uses here.
for ...
// B4 building nothing
}
// B5 ...
}
Juzhe-Zhong [Wed, 24 May 2023 03:37:01 +0000 (11:37 +0800)]
RISC-V: Add RVV comparison autovectorization
This patch enable RVV auto-vectorization including floating-point
unorder and order comparison.
The testcases are leveraged from Richard. So include Richard as co-author.
And this patch is the prerequisite patch for my current middle-end work.
Without this patch, I can't support len_mask_xxx middle-end pattern
since the mask is generated by comparison.
For example,
for (int i...; i < n.)
if (cond[i])
a[i] = b[i]
We need len_mask_load/len_mask_store for such code and I am gonna
support them in the middle-end after this patch is merged.
Both integer && floating (order and unorder) are tested.
built && regression passed.
Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai> Co-Authored-By: Richard Sandiford <richard.sandiford@arm.com>
gcc/ChangeLog:
* config/riscv/autovec.md (@vcond_mask_<mode><vm>): New pattern.
(vec_cmp<mode><vm>): New pattern.
(vec_cmpu<mode><vm>): New pattern.
(vcond<V:mode><VI:mode>): New pattern.
(vcondu<V:mode><VI:mode>): New pattern.
* config/riscv/riscv-protos.h (enum insn_type): Add new enum.
(emit_vlmax_merge_insn): New function.
(emit_vlmax_cmp_insn): Ditto.
(emit_vlmax_cmp_mu_insn): Ditto.
(expand_vec_cmp): Ditto.
(expand_vec_cmp_float): Ditto.
(expand_vcond): Ditto.
* config/riscv/riscv-v.cc (emit_vlmax_merge_insn): Ditto.
(emit_vlmax_cmp_insn): Ditto.
(emit_vlmax_cmp_mu_insn): Ditto.
(get_cmp_insn_code): Ditto.
(expand_vec_cmp): Ditto.
(expand_vec_cmp_float): Ditto.
(expand_vcond): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/rvv.exp:
* gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: New test.
* gcc.target/riscv/rvv/autovec/cmp/vcond-2.c: New test.
* gcc.target/riscv/rvv/autovec/cmp/vcond-3.c: New test.
* gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: New test.
* gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: New test.
Pan Li [Thu, 18 May 2023 06:21:30 +0000 (14:21 +0800)]
RISC-V: Support RVV VREINTERPRET from vbool*_t to vuint*m1_t
This patch support the RVV VREINTERPRET from the vbool*_t to the
vuint*m1_t. Aka:
vuint*m1_t __riscv_vreinterpret_x_x(vbool*_t);
These APIs help the users to convert vector the vbool*_t to the LMUL=1
unsigned integer vint*_t. According to the RVV intrinsic SPEC as below,
the reinterpret intrinsics only change the types of the underlying contents.
For example, given below code.
vuint8m1_t test_vreinterpret_v_b1_vuint8m1 (vbool1_t src) {
return __riscv_vreinterpret_v_b1_u8m1 (src);
}
It will generate the assembly code similar as below:
vsetvli a5,zero,e8,m8,ta,ma
vlm.v v1,0(a1)
vs1r.v v1,0(a0)
ret
Please NOTE the test files doesn't cover all the possible combinations
of the intrinsic APIs introduced by this PATCH due to too many.
This is the last PATCH for the reinterpret between the signed/unsigned
and the bool vector types.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/genrvv-type-indexer.cc (main): Add
unsigned_eew*_lmul1_interpret for indexer.
* config/riscv/riscv-vector-builtins-functions.def (vreinterpret):
Register vuint*m1_t interpret function.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS):
New macro for vuint8m1_t.
(DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
(vbool1_t): Add to unsigned_eew*_interpret_ops.
(vbool2_t): Likewise.
(vbool4_t): Likewise.
(vbool8_t): Likewise.
(vbool16_t): Likewise.
(vbool32_t): Likewise.
(vbool64_t): Likewise.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS):
New macro for vuint*m1_t.
(DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
(required_extensions_p): Add vuint*m1_t interpret case.
* config/riscv/riscv-vector-builtins.def (unsigned_eew8_lmul1_interpret):
Add vuint*m1_t interpret to base type.
(unsigned_eew16_lmul1_interpret): Likewise.
(unsigned_eew32_lmul1_interpret): Likewise.
(unsigned_eew64_lmul1_interpret): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c:
Enrich test cases.
Pan Li [Thu, 18 May 2023 02:46:38 +0000 (10:46 +0800)]
RISC-V: Support RVV VREINTERPRET from vbool*_t to vint*m1_t
This patch support the RVV VREINTERPRET from the vbool*_t to the
vint*m1_t. Aka:
vint*m1_t __riscv_vreinterpret_x_x(vbool*_t);
These APIs help the users to convert vector the vbool*_t to the LMUL=1
signed integer vint*_t. According to the RVV intrinsic SPEC as below,
the reinterpret intrinsics only change the types of the underlying contents.
For example, given below code.
vint8m1_t test_vreinterpret_v_b1_vint8m1 (vbool1_t src) {
return __riscv_vreinterpret_v_b1_i8m1 (src);
}
It will generate the assembly code similar as below:
vsetvli a5,zero,e8,m8,ta,ma
vlm.v v1,0(a1)
vs1r.v v1,0(a0)
ret
Please NOTE the test files doesn't cover all the possible combinations
of the intrinsic APIs introduced by this PATCH due to too many.
The reinterpret from vbool*_t to vuint*m1_t with lmul=1 will be coverred
in another PATCH.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/genrvv-type-indexer.cc (EEW_SIZE_LIST): New macro
for the eew size list.
(LMUL1_LOG2): New macro for the log2 value of lmul=1.
(main): Add signed_eew*_lmul1_interpret for indexer.
* config/riscv/riscv-vector-builtins-functions.def (vreinterpret):
Register vint*m1_t interpret function.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS):
New macro for vint8m1_t.
(DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
(vbool1_t): Add to signed_eew*_interpret_ops.
(vbool2_t): Likewise.
(vbool4_t): Likewise.
(vbool8_t): Likewise.
(vbool16_t): Likewise.
(vbool32_t): Likewise.
(vbool64_t): Likewise.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS):
New macro for vint*m1_t.
(DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
(required_extensions_p): Add vint8m1_t interpret case.
* config/riscv/riscv-vector-builtins.def (signed_eew8_lmul1_interpret):
Add vint*m1_t interpret to base type.
(signed_eew16_lmul1_interpret): Likewise.
(signed_eew32_lmul1_interpret): Likewise.
(signed_eew64_lmul1_interpret): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c:
Enrich the test cases.
Martin Uecker [Sun, 21 May 2023 17:32:01 +0000 (19:32 +0200)]
Fix ICEs related to VM types in C 2/2 [PR109450]
Size expressions were sometimes lost and not gimplified correctly,
leading to ICEs and incorrect evaluation order. Fix this by 1) not
recursing pointers when gimplifying parameters, which was incorrect
because it might access variables declared later for incomplete
structs, and 2) adding a decl expr for variably-modified arrays
that are pointed to by parameters declared as arrays.
gcc/c/
* c-decl.cc (add_decl_expr): New function.
(grokdeclarator): Add decl expr for size expression in
types pointed to by parameters declared as arrays.
gcc/testsuite/
* gcc.dg/pr109450-1.c: New test.
* gcc.dg/pr109450-2.c: New test.
* gcc.dg/vla-26.c: New test.
Martin Uecker [Thu, 13 Apr 2023 17:37:12 +0000 (19:37 +0200)]
Fix ICEs related to VM types in C 1/2 [PR70418, PR107557, PR108423]
Size expressions were sometimes lost and not gimplified correctly, leading to
ICEs and incorrect evaluation order. Fix this by 1) not recursing into
pointers when gimplifying parameters in the middle-end (the code is merged with
gimplify_type_sizes), which is incorrect because it might access variables
declared later for incomplete structs, and 2) tracking size expressions for
struct/union members correctly, 3) emitting code to evaluate size expressions
for missing cases (nested functions, empty declarations, and structs/unions).
PR c/70418
PR c/106465
PR c/107557
PR c/108423
gcc/c/
* c-decl.cc (start_decl): Make sure size expression are
evaluated only in correct context.
(grokdeclarator): Size expression in fields may need a bind
expression, make sure DECL_EXPR is always created.
(grokfield, declspecs_add_type): Pass along size expressions.
(finish_struct): Remove unneeded DECL_EXPR.
(start_function): Evaluate size expressions for nested functions.
* c-parser.cc (c_parser_struct_declarations,
c_parser_struct_or_union_specifier): Pass along size expressions.
(c_parser_declaration_or_fndef): Evaluate size expression.
(c_parser_objc_at_property_declaration,
c_parser_objc_class_instance_variables): Adapt.
* c-tree.h (grokfield): Adapt declaration.
gcc/testsuite/
* gcc.dg/nested-vla-1.c: New test.
* gcc.dg/nested-vla-2.c: New test.
* gcc.dg/nested-vla-3.c: New test.
* gcc.dg/pr70418.c: New test.
* gcc.dg/pr106465.c: New test.
* gcc.dg/pr107557-1.c: New test.
* gcc.dg/pr107557-2.c: New test.
* gcc.dg/pr108423-1.c: New test.
* gcc.dg/pr108423-2.c: New test.
* gcc.dg/pr108423-3.c: New test.
* gcc.dg/pr108423-4.c: New test.
* gcc.dg/pr108423-5.c: New test.
* gcc.dg/pr108423-6.c: New test.
* gcc.dg/typename-vla-2.c: New test.
* gcc.dg/typename-vla-3.c: New test.
* gcc.dg/typename-vla-4.c: New test.
* gcc.misc-tests/gcov-pr85350.c: Adapt.
This patch decreses one machine instruction from "single bit extraction
with shifting" operation, and tries to eliminate the conditional
branch if CST2_POW2 doesn't fit into signed 12 bits with the help
of ifcvt optimization.
/* example #1 */
int test0(int x) {
return (x & 1048576) != 0 ? 1024 : 0;
}
extern int foo(void);
int test1(void) {
return (foo() & 1048576) != 0 ? 16777216 : 0;
}
In addition, if the left shift amount ('exact_log2(CST2_POW2)') is
between 1 through 3 and a either addition or subtraction with another
register follows, emit a ADDX[248] or SUBX[248] machine instruction
instead of separate left shift and add/subtract ones.
/* example #2 */
int test2(int x, int y) {
return ((x & 1048576) != 0 ? 4 : 0) + y;
}
int test3(int x, int y) {
return ((x & 2) != 0 ? 8 : 0) - y;
}
;; before
test2:
movi.n a9, 4
srai a2, a2, 18
and a2, a2, a9
add.n a2, a2, a3
ret.n
test3:
movi.n a9, 8
slli a2, a2, 2
and a2, a2, a9
sub a2, a2, a3
ret.n
* config/xtensa/predicates.md (addsub_operator): New.
* config/xtensa/xtensa.md (*extzvsi-1bit_ashlsi3,
*extzvsi-1bit_addsubx): New insn_and_split patterns.
* config/xtensa/xtensa.cc (xtensa_rtx_costs):
Add a special case about ifcvt 'noce_try_cmove()' to handle
constant loads that do not fit into signed 12 bits in the
patterns added above.
Richard Biener [Tue, 23 May 2023 13:03:00 +0000 (15:03 +0200)]
tree-optimization/109747 - SLP cost of CTORs
The x86 backend looks at the SLP node passed to the add_stmt_cost
hook when costing vec_construct, looking for elements that require
a move from a GPR to a vector register and cost that. But since
vect_prologue_cost_for_slp decomposes the cost for an external
SLP node into individual pieces this cost gets applied N times
without a chance for the backend to know it's just dealing with
a part of the SLP node. Just looking at a part is also not perfect
since the GPR to XMM move cost applies only once per distinct
element so handling the whole SLP node one more correctly reflects
cost (albeit without considering other external SLP nodes).
The following addresses the issue by passing down the SLP node
only for one piece and nullptr for the rest. The x86 backend
is currently the only one looking at it.
In the future the cost of external elements is something to deal
with globally but that would require the full SLP tree be available
to costing.
It's difficult to write a testcase, at the tipping point not
vectorizing is better so I'll followup with x86 specific adjustments
and will see to add a testcase later.
PR tree-optimization/109747
* tree-vect-slp.cc (vect_prologue_cost_for_slp): Pass down
the SLP node only once to the cost hook.
Georg-Johann Lay [Tue, 23 May 2023 16:49:19 +0000 (18:49 +0200)]
Improve cost computation for single-bit bit insertions.
Some miscomputation of rtx_costs lead to sub-optimal code for
single-bit bit insertions. This patch implements TARGET_INSN_COST,
which has a chance to see the whole insn during insn combination;
in partictlar the SET_DEST of (set (zero_extract (...) ...)).
gcc/
* config/avr/avr.cc (avr_insn_cost): New static function.
(TARGET_INSN_COST): Define to that function.
Richard Biener [Tue, 23 May 2023 13:12:33 +0000 (15:12 +0200)]
Account for vector splat GPR->XMM move cost
The following also accounts for a GPR->XMM move cost for splat
operations and properly guards eliding the cost when moving from
memory only for SSE4.1 or HImode or larger operands. This
doesn't fix the PR fully yet.
PR target/109944
* config/i386/i386.cc (ix86_vector_costs::add_stmt_cost):
For vector construction or splats apply GPR->XMM move
costing. QImode memory can be handled directly only
with SSE4.1 pinsrb.
Richard Biener [Tue, 23 May 2023 13:58:52 +0000 (15:58 +0200)]
Generic vector op costing adjustment
This is a small adjustment to the work done for PR108752 and
better reflects the cost of the generated sequence.
PR tree-optimization/108752
* tree-vect-stmts.cc (vectorizable_operation): For bit
operations with generic word_mode vectors do not cost
an extra stmt. For plus, minus and negate also cost the
constant materialization.
Aldy Hernandez [Tue, 23 May 2023 10:34:45 +0000 (12:34 +0200)]
Remove buggy special case in irange::invert [PR109934].
This patch removes a buggy special case in irange::invert which seems
to have been broken for a while, and probably never triggered because
the legacy code was handled elsewhere, and the non-legacy code was
using an int_range_max of int_range<255> which made it extremely
likely for num_ranges == 255. However, with auto-resizing ranges,
int_range_max will start off at 3 and can hit this bogus code in the
unswitching code.
PR tree-optimization/109934
gcc/ChangeLog:
* value-range.cc (irange::invert): Remove buggy special case.
This is because complx_t is passed and returned in FPRs, but GCC gives
it DImode. We therefore “need” to assemble a DImode pseudo from the
two individual floats, bitcast it to a vector, do the arithmetic,
bitcast it back to a DImode pseudo, then extract the individual floats.
There are many problems here. The most basic is that we shouldn't
use SLP for such a trivial example. But SLP should in principle be
beneficial for more complicated examples, so preventing SLP for the
example above just changes the reproducer needed. A more fundamental
problem is that it doesn't make sense to use single DImode pseudos in a
testcase like this. I have a WIP patch to allow re and im to be stored
in individual SFmode pseudos instead, but it's quite an invasive change
and might end up going nowhere.
A simpler problem to tackle is that we allow DImode pseudos to be stored
in FPRs, but we don't provide any patterns for inserting values into
them, even though INS makes that easy for element-like insertions.
This patch adds some patterns for that.
Doing that showed that aarch64_modes_tieable_p was too strict:
it didn't allow SFmode and DImode values to be tied, even though
both of them occupy a single GPR and FPR, and even though we allow
both classes to change between the modes.
The *aarch64_bfidi<ALLX:mode>_subreg_<SUBDI_BITS> pattern is
especially ugly, but it's not clear what target-independent
code ought to simplify it to, if it was going to simplify it.
We should probably do the same thing for extractions, but that's left
as future work.
After the patch we generate:
ins v0.s[1], v1.s[0]
ins v2.s[1], v3.s[0]
fadd v0.2s, v0.2s, v2.2s
fmov x0, d0
ushr d1, d0, 32
lsr w0, w0, 0
fmov s0, w0
ret
which seems like a step in the right direction.
All in all, there's nothing elegant about this patchh. It just
seems like the least worst option.
gcc/
PR target/109632
* config/aarch64/aarch64.cc (aarch64_modes_tieable_p): Allow
subregs between any scalars that are 64 bits or smaller.
* config/aarch64/iterators.md (SUBDI_BITS): New int iterator.
(bits_etype): New int attribute.
* config/aarch64/aarch64.md (*insv_reg<mode>_<SUBDI_BITS>)
(*aarch64_bfi<GPI:mode><ALLX:mode>_<SUBDI_BITS>): New patterns.
(*aarch64_bfidi<ALLX:mode>_subreg_<SUBDI_BITS>): Likewise.
md: Allow <FOO> to refer to the value of int iterator FOO
In a follow-up patch, I wanted to use an int iterator to iterate
over various possible values of a const_int. But one problem
with int iterators was that there was no way of referring to the
current value of the iterator. This is unlike modes and codes,
which provide automatic "mode", "MODE", "code" and "CODE"
attribbutes. These automatic definitions are the equivalent
of an explicit:
(define_mode_attr mode [(QI "qi") (HI "hi") ...])
We obviously can't do that for every possible value of an int.
One option would have been to go for some kind of lazily-populated
attribute. But that sounds quite complicated. This patch instead
goes for the simpler approach of allowing <FOO> to refer to the
current value of FOO.
In principle it would be possible to allow the same thing
for mode and code iterators. But for modes there are at least
4 realistic possiblities:
- the E_* enumeration value (which is what this patch would give)
- the user-facing C token, like DImode, SFmode, etc.
- the equivalent of <MODE>
- the equivalent of <mode>
Because of this ambiguity, it seemed better to stick to the
current approach for modes. For codes it's less clear-cut,
but <CODE> and <code> are both realistic possibilities, so again
it seemed better to be explicit.
The patch also removes “Each @var{int} must have the same rtx format.
@xref{RTL Classes}.”, which was erroneously copied from the code
iterator section.
gcc/
* doc/md.texi: Document that <FOO> can be used to refer to the
numerical value of an int iterator FOO. Tweak other parts of
the int iterator documentation.
* read-rtl.cc (iterator_group::has_self_attr): New field.
(map_attr_string): When has_self_attr is true, make <FOO>
expand to the current value of iterator FOO.
(initialize_iterators): Set has_self_attr for int iterators.
Juzhe-Zhong [Tue, 23 May 2023 10:22:54 +0000 (18:22 +0800)]
RISC-V: Refactor the framework of RVV auto-vectorization
This patch is to refactor the framework of RVV auto-vectorization.
Since we find out are keep adding helpers && wrappers when implementing
auto-vectorization.
It will make the RVV auto-vectorizaiton very messy.
After double check my downstream RVV GCC, assemble all auto-vectorization
patterns we are going to have. Base on these informations, I refactor the
RVV framework to make it is easier and flexible for future use.
For example, we will definitely implement len_mask_load/len_mask_store
patterns which have both length && mask operand and use undefine merge operand.
len_cond_div or cond_div will have length or mask operand and use a real
merge operand instead of undefine merge operand.
Also, we will have some patterns will use tail undisturbed and mask any.
etc..... We will defintely have various features.
Base on these circumstances, we add these following private members:
int m_op_num;
/* It't true when the pattern has a dest operand. Most of the patterns have
dest operand wheras some patterns like STOREs does not have dest
operand.
*/
bool m_has_dest_p;
bool m_fully_unmasked_p;
bool m_use_real_merge_p;
bool m_has_avl_p;
bool m_vlmax_p;
bool m_has_tail_policy_p;
bool m_has_mask_policy_p;
enum tail_policy m_tail_policy;
enum mask_policy m_mask_policy;
machine_mode m_dest_mode;
machine_mode m_mask_mode;
These variables I believe can cover all potential situations.
And the instruction generater wrapper is "emit_insn" which will add
operands and
emit instruction according to the variables I mentioned above.
After this is done. We will easily add helpers without changing any base
class "insn_expand".
Currently, we have "emit_vlmax_tany_many" and "emit_nonvlmax_tany_many".
For example, when we want to emit a binary operations:
We have
Then just use emit_vlmax_tany_many (...RVV_BINOP_NUM...)
So, if we support ternary operation in the future. It's quite simple:
emit_vlmax_tany_many (...RVV_BINOP_NUM...)
"*_tany_many" means we are using tail any and mask any.
We will definitely need tail undisturbed or mask undisturbed when we
support these patterns
in middle-end. It's very simple to extend such helper base on current
framework:
we can do that in the future like this:
void
emit_nonvlmax_tu_mu (unsigned icode, int op_num, rtx *ops)
{
machine_mode data_mode = GET_MODE (ops[0]);
machine_mode mask_mode = get_mask_mode (data_mode).require ();
/* The number = 11 is because we have maximum 11 operands for
RVV instruction patterns according to vector.md. */
insn_expander<11> e (/*OP_NUM*/ op_num,
/*HAS_DEST_P*/ true,
/*USE_ALL_TRUES_MASK_P*/ true,
/*USE_UNDEF_MERGE_P*/ true,
/*HAS_AVL_P*/ true,
/*VLMAX_P*/ false,
/*HAS_TAIL_POLICY_P*/ true,
/*HAS_MASK_POLICY_P*/ true,
/*TAIL_POLICY*/ TAIL_UNDISTURBED,
/*MASK_POLICY*/ MASK_UNDISTURBED,
/*DEST_MODE*/ data_mode,
/*MASK_MODE*/ mask_mode);
e.emit_insn ((enum insn_code) icode, ops);
}
That's enough (I have tested it fully in my downstream RVV GCC).
I didn't add it in this patch.
Kyrylo Tkachov [Tue, 23 May 2023 10:09:08 +0000 (11:09 +0100)]
aarch64: PR target/109855 Add predicate and constraints to define_subst in aarch64-simd.md
In this PR we ICE because the substituted pattern for mla "lost" its predicate and constraint for operand 0
because the define_subst template:
[(set (match_operand:<VDBL> 0)
(vec_concat:<VDBL>
(match_dup 1)
(match_operand:VDZ 2 "aarch64_simd_or_scalar_imm_zero")))])
Uses match_operand instead of match_dup for operand 0. We can't use match_dup 0 for it because we need to specify the widened mode.
The problem is fixed by adding a "register_operand" predicate and "=w" constraint to the match_operand.
This makes sense conceptually too as the transformation we're targeting only applies to instructions that write a "w" register.
With this change the mddump pattern that ICEs goes from:
(define_insn ("aarch64_mlav4hi_vec_concatz_le")
[
(set (match_operand:V8HI 0 ("") ("")) <<------ Missing constraint!
(vec_concat:V8HI (plus:V4HI (mult:V4HI (match_operand:V4HI 2 ("register_operand") ("w"))
(match_operand:V4HI 3 ("register_operand") ("w")))
(match_operand:V4HI 1 ("register_operand") ("0")))
(match_operand:V4HI 4 ("aarch64_simd_or_scalar_imm_zero") (""))))
] ("(!BYTES_BIG_ENDIAN) && (TARGET_SIMD)") ("mla\t%0.4h, %2.4h, %3.4h")
to the proper:
(define_insn ("aarch64_mlav4hi_vec_concatz_le")
[
(set (match_operand:V8HI 0 ("register_operand") ("=w")) <<-------- Constraint in the right place
(vec_concat:V8HI (plus:V4HI (mult:V4HI (match_operand:V4HI 2 ("register_operand") ("w"))
(match_operand:V4HI 3 ("register_operand") ("w")))
(match_operand:V4HI 1 ("register_operand") ("0")))
(match_operand:V4HI 4 ("aarch64_simd_or_scalar_imm_zero") (""))))
] ("(!BYTES_BIG_ENDIAN) && (TARGET_SIMD)") ("mla\t%0.4h, %2.4h, %3.4h")
This seems to do the right thing for multi-alternative patterns as well, the annotated pattern for aarch64_cmltv8qi is:
(define_insn ("aarch64_cmltv8qi")
[
(set (match_operand:V8QI 0 ("register_operand") ("=w,w"))
(neg:V8QI (lt:V8QI (match_operand:V8QI 1 ("register_operand") ("w,w"))
(match_operand:V8QI 2 ("aarch64_simd_reg_or_zero") ("w,ZDz")))))
]
Richard Biener [Thu, 18 May 2023 11:52:29 +0000 (13:52 +0200)]
tree-optimization/109849 - missed code hoisting
The following fixes code hoisting to properly consider ANTIC_OUT instead
of ANTIC_IN. That's a bit expensive to re-compute but since we no
longer iterate we're doing this only once per BB which should be
acceptable. This avoids missing hoistings to the end of blocks where
something in the block clobbers the hoisted value.
PR tree-optimization/109849
* tree-ssa-pre.cc (do_hoist_insertion): Compute ANTIC_OUT
and use that to determine what to hoist.
Eric Botcazou [Tue, 23 May 2023 08:15:35 +0000 (10:15 +0200)]
Fix handling of non-integral bit-fields in native_encode_initializer
The encoder for CONSTRUCTORs assumes that all bit-fields (DECL_BIT_FIELD)
have integral types, but that's not the case in Ada where they may have
pretty much any type, resulting in a wrong encoding for them
gcc/
* fold-const.cc (native_encode_initializer) <CONSTRUCTOR>: Apply the
specific treatment for bit-fields only if they have an integral type
and filter out non-integral bit-fields that do not start and end on
a byte boundary.
gcc/testsuite/
* gnat.dg/opt101.adb: New test.
* gnat.dg/opt101_pkg.ads: New helper.
Piotr Trojanek [Fri, 3 Feb 2023 21:15:44 +0000 (22:15 +0100)]
ada: Accept and analyze new aspect Exceptional_Cases
Add new aspect Exceptional_Cases, which is intended for SPARK and
describes in which cases an exception will be raised, and optionally
supply a postcondition that shall be verified in this case.
The implementation is heavily modeled after Subprogram_Variant, which in
turn was heavily modeled after Contract_Cases. Currently the aspect is
only analysed; the code infrastructure required to expand it is prepared
but empty. This is enough for the aspect to be verified by GNATprove.
gcc/ada/
* aspects.ads
(Aspect_Id): Add aspect identifier.
(Aspect_Argument): New aspect accepts an expression.
(Is_Representation_Aspect): New aspect is not a representation
aspect.
(Aspect_Names): Associate name with the new aspect identifier.
(Aspect_Delay): New aspect is never delayed.
* contracts.adb
(Add_Contract_Item): Store new aspect among contract items.
(Analyze_Entry_Or_Subprogram_Contract): Likewise.
(Analyze_Subprogram_Body_Stub_Contract): Likewise.
(Process_Contract_Cases): Expand new aspect, if present.
* contracts.ads
(Analyze_Entry_Or_Subprogram_Body_Contract): Mention new aspect in
spec.
(Analyze_Entry_Or_Subprogram_Contract): Likewise.
* einfo-utils.adb
(Get_Pragma): Allow new aspect to be picked by the backend.
* einfo-utils.ads
(Get_Pragma): Mention new aspect in spec.
* exp_prag.adb
(Expand_Pragma_Exceptional_Cases): Dummy expansion routine.
* exp_prag.ads
(Expand_Pragma_Exceptional_Cases): Add spec for expansion routine.
* inline.adb
(Remove_Aspects_And_Pragmas): Remove aspect from bodies to inline.
* par-prag.adb
(Par.Prag): Accept pragma in the parser, so it will be checked
later.
* sem_ch12.adb
(Implementation of Generic Contracts): Mention new aspect in
comment.
* sem_ch13.adb
(Analyze_Aspect_Specifications): Transform new aspect info a
corresponding pragma.
* sem_prag.adb
(Analyze_Exceptional_Cases_In_Decl_Part): Analyze aspect
expression; heavily inspired by the existing code for analysis of
Subprogram_Variant and exception handlers.
(Analyze_Pragma): Analyze pragma corresponding to the new aspect.
(Is_Non_Significant_Pragma_Reference): Add new pragma to the
table.
* sem_prag.ads
(Assertion_Expression_Pragma): New pragma acts as an assertion
expression, even though it is not currently expanded.
(Analyze_Exceptional_Cases_In_Decl_Part): Add spec.
* sem_util.adb
(Is_Subprogram_Contract_Annotation): Mark new annotation is a
subprogram contract, so the subprogram with it won't be inlined.
* sem_util.ads
(Is_Subprogram_Contract_Annotation): Mention new aspect in
comment.
* sinfo.ads
(Contract_Test_Cases): Mention new aspect in comment.
* snames.ads-tmpl: Add entries for the new name and pragma.
Eric Botcazou [Wed, 1 Mar 2023 21:28:51 +0000 (22:28 +0100)]
ada: Rework fix for internal error on quantified expression with predicated type
It turns out that skipping compiler-generated block scopes is problematic
when computing the public status of a subprogram, because this subprogram
may end up being nested in the elaboration procedure of a package spec or
body, in which case it may not be public.
This replaces the original fix with a pair of Push_Scope/Pop_Scope in the
Build_Predicate_Function procedure, as done elsewhere in similar cases.
gcc/ada/
* sem_ch13.adb (Build_Predicate_Functions): If the current scope
is not that of the type, push this scope and pop it at the end.
* sem_util.ads (Current_Scope_No_Loops_No_Blocks): Delete.
* sem_util.adb (Current_Scope_No_Loops_No_Blocks): Likewise.
(Set_Public_Status): Call again Current_Scope.
Gary Dismukes [Fri, 17 Feb 2023 23:16:55 +0000 (18:16 -0500)]
ada: ICE on BIP call in class-wide function return within instance
The compiler blows up (such as with a Storage_Error or Assert_Failure)
on a call to a limited build-in-place function occurring in the return
for a function with a limited class-wide result. Such a function
should include extra formals for a task master and activation chain
(because it's possible for a limited class-wide type to have values
with task parts), but when the enclosing function occurs within an
instantiation and the result subtype comes from a formal type, the
extra formals were missing for the enclosing function. As a result,
the attempt to retrieve the task master formal for passing along to
a BIP call in the return failed when calling Build_In_Place_Formal to
loop through the formals. When determining the need for the formals in
Create_Extra_Formals, Needs_BIP_Actual_Task_Actuals was returning False,
because Might_Have_Tasks incorrectly returned False due to the test
of Is_Limited_Record flag on the class-wide generic actual subtype's
Etype being False. Is_Limited_Record was not being properly inherited
by the class-wide type in the case of private extensions, because
Make_Class_Wide_Type was called in Analyze_Private_Extension_Declaration
before certain flags (such as Is_Limited_Record and Is_Controlled_Active)
are inherited later in Build_Derived_Record_Type (which will also call
Make_Class_Wide_Type). This is corrected by removing the early call
to Make_Class_Wide_Type.
gcc/ada/
* exp_ch6.adb (Might_Have_Tasks): Remove unneeded Etype call from
call to Is_Limited_Record, since that flag is now properly
inherited by class-wide types.
* sem_ch3.adb (Analyze_Private_Extension_Declaration): Remove call
to Make_Class_Wide_Type, which is done too early, and will later
be done in Build_Derived_Record_Type after flags such as
Is_Limited_Record and Is_Controlled_Active have been set on the
derived type.
Piotr Trojanek [Thu, 23 Feb 2023 23:47:47 +0000 (00:47 +0100)]
ada: Add tags to warnings controlled by Warn_On_Redundant_Constructs
Some of the calls to Error_Msg_N controlled by the flag
Warn_On_Redundant_Constructs missed the "?r?" tag in their message
string. This caused a misleading "[enabled by default]" label to appear
next to the error message.
Spotted while adding a warning about duplicated choices in exception
handlers.
gcc/ada/
* freeze.adb (Freeze_Record_Type): Add tag for redundant pragma Pack.
* sem_aggr.adb (Resolve_Record_Aggregate): Add tag for redundant OTHERS
choice.
* sem_ch8.adb (Use_One_Type): Add tag for redundant USE clauses.
Piotr Trojanek [Tue, 28 Feb 2023 09:36:54 +0000 (10:36 +0100)]
ada: Cleanup inconsistent iteration over exception handlers
When detecting duplicate choices in exception handlers we had
inconsistent pairs of First/Next_Non_Pragma and First_Non_Pragma/Next.
This was harmless, because exception choices don't allow pragmas at all,
e.g.:
when Program_Error | Constraint_Error | ...; -- pragma not allowed
and exception handlers only allow pragmas to appear as the first item
on the list, e.g.:
exception
pragma Inspection_Point; -- first item on the list of handlers
when Program_Error =>
<statements>
pragma Inspection_Point; -- last item on the list of statements
when Constraint_Error =>
...
However, it still seems cleaner to have consistent pairs of First/Next
and First_Non_Pragma/Next_Non_Pragma.
gcc/ada/
* sem_ch11.adb
(Check_Duplication): Fix inconsistent iteration.
(Others_Present): Iterate over handlers using First_Non_Pragma and
Next_Non_Pragma just like in Check_Duplication.
Eric Botcazou [Sat, 11 Feb 2023 12:12:53 +0000 (13:12 +0100)]
ada: Fix latent issue in support for protected entries
The problem is that, unlike for protected subprograms, the expansion of
cleanups for protected entries is not delayed when they contain package
instances with a body, so the cleanups are generated twice and this may
yield two finalizers if the secondary stack is used in the entry body.
This restores the delaying, which uncovers the missing propagation of the
Uses_Sec_Stack flag as is done for protected subprograms, which in turn
requires using a Corresponding_Spec field as for protected subprograms.
This also gets rid of the Delay_Subprogram_Descriptors flag on entities,
whose only remaining use in Expand_Cleanup_Actions was unreachable.
The last change is to unconditionally reset the scopes in the case of
protected subprograms when they are expanded, as is done in the case of
protected entries. This makes it possible to remove the code adjusting
the scope on the fly in Cleanup_Scopes but requires a few adjustments.
gcc/ada/
* einfo.ads (Delay_Subprogram_Descriptors): Delete.
* gen_il-fields.ads (Opt_Field_Enum): Remove
Delay_Subprogram_Descriptors.
* gen_il-gen-gen_entities.adb (Gen_Entities): Likewise.
* gen_il-gen-gen_nodes.adb (N_Entry_Body): Add Corresponding_Spec.
* sinfo.ads (Corresponding_Spec): Document new use.
(N_Entry_Body): Likewise.
* exp_ch6.adb (Expand_Protected_Object_Reference): Be prepared for
protected subprograms that have been expanded.
* exp_ch7.adb (Expand_Cleanup_Actions): Remove unreachable code.
* exp_ch9.adb (Build_Protected_Entry): Add a local variable for the
new block and propagate Uses_Sec_Stack from the corresponding spec.
(Expand_N_Protected_Body) <N_Subprogram_Body>: Unconditionally reset
the scopes of top-level entities in the new body.
* inline.adb (Cleanup_Scopes): Do not adjust the scope on the fly.
* sem_ch9.adb (Analyze_Entry_Body): Set Corresponding_Spec.
* sem_ch12.adb (Analyze_Package_Instantiation): Remove obsolete code
setting Delay_Subprogram_Descriptors and tidy up.
* sem_util.adb (Scope_Within): Deal with protected subprograms that
have been expanded.
(Scope_Within_Or_Same): Likewise.
Eric Botcazou [Fri, 24 Feb 2023 16:08:01 +0000 (17:08 +0100)]
ada: Fix address manipulation issue in the tasking runtime
The implementation of task attributes in the runtime defines an atomic clone
of System.Address, which is awkward for targets where addresses and pointers
have a specific representation, so this change replaces that with a pragma
Atomic_Components on the Attribute_Array type.
gcc/ada/
* libgnarl/s-taskin.ads (Atomic_Address): Delete.
(Attribute_Array): Add pragma Atomic_Components.
(Ada_Task_Control_Block): Adjust default value of Attributes.
* libgnarl/s-tasini.adb (Finalize_Attributes): Adjust type of local
variable.
* libgnarl/s-tataat.ads (Deallocator): Adjust type of parameter.
(To_Attribute): Adjust source type.
* libgnarl/a-tasatt.adb: Add clauses for System.Storage_Elements.
(New_Attribute): Adjust return type.
(Deallocate): Adjust type of parameter.
(To_Real_Attribute): Adjust source type.
(To_Address): Add target type.
(To_Attribute): Adjust source type.
(Fast_Path): Adjust tested type.
(Finalize): Compare with Null_Address.
(Reference): Likewise.
(Reinitialize): Likewise.
(Set_Value): Likewise. Add conversion to Integer_Address.
(Value): Likewise.
Claire Dross [Mon, 27 Feb 2023 10:51:45 +0000 (10:51 +0000)]
ada: Update ghost code for proof of integer input functions
Introduce new ghost helper functions to facilitate proof.
gcc/ada/
* libgnat/s-valueu.adb (Scan_Raw_Unsigned): Use new helpers.
* libgnat/s-vauspe.ads (Raw_Unsigned_Starts_As_Based_Ghost,
Raw_Unsigned_Is_Based_Ghost): New ghost helper functions.
(Is_Raw_Unsigned_Format_Ghost, Scan_Split_No_Overflow_Ghost,
Scan_Split_Value_Ghost, Raw_Unsigned_Last_Ghost): Use new
helpers.
Arnaud Charlet [Mon, 6 Feb 2023 09:06:28 +0000 (09:06 +0000)]
ada: Add new switch -gnatyz
Improve -gnatyx to check additional complete conditions,
and introduce a new switch -gnatyz to check for unnecessary
parentheses according to operator precedence rules.
Enable -gnatyz as part of -gnatyg.
gcc/ada/
* par-ch5.adb, style.ads, styleg.adb, styleg.ads
(Check_Xtra_Parens): Remove extra parameter Enable.
(Check_Xtra_Parens_Precedence): New.
(P_Case_Statement): Add -gnatyx style check.
* sem_ch4.adb: Replace calls to Check_Xtra_Parens by
Check_Xtra_Parens_Precedence.
* stylesw.ads, stylesw.adb, usage.adb: Add support for
-gnatyz.
* doc/gnat_ugn/building_executable_programs_with_gnat.rst:
Update -gnatyxzg doc.
* sem_prag.adb, libgnat/s-regpat.adb,
libgnarl/s-interr__hwint.adb, libgnarl/s-interr__vxworks.adb:
Remove extra parens.
* par-ch3.adb (P_Discrete_Range): Do not emit a style check if
the expression is not a simple expression.
* gnat_ugn.texi: Regenerate.
Eric Botcazou [Thu, 23 Feb 2023 18:13:36 +0000 (19:13 +0100)]
ada: Fix resolution of mod operator of System.Storage_Elements
This operator is special because the left operand is of Address type while
the right operand and the result are of Storage_Offset type (but we raise
Constraint_Error if the right operand is not positive) and it needs to be
resolved to the type of the left operand to implement the correct semantics.
gcc/ada/
* exp_ch4.adb (Expand_N_Op_Mod): Adjust the detection of the special
operator of System.Storage_Elements. Do not rewrite it into a rem.
* sem_res.adb (Resolve_Intrinsic_Operator): Use the base type of the
left operand for the special mod operator of System.Storage_Elements
Eric Botcazou [Wed, 22 Feb 2023 16:00:06 +0000 (17:00 +0100)]
ada: Fix address arithmetic issues in the expanded code
This is most notably the addition of addresses in Expand_Interface_Thunk.
There is also a small change to Expand_Dispatching_Call, which was directly
accessing a class-wide interface object as a tag, thus giving rise later to
unchecked conversions between either the root or the equivalent record type
and access types.
gcc/ada/
* exp_disp.adb (Expand_Dispatching_Call): In the abstract interface
class-wide case, use 'Tag of the object as the controlling tag.
(Expand_Interface_Thunk): Perform address arithmetic using operators
of System.Storage_Elements.
Eric Botcazou [Wed, 22 Feb 2023 13:43:37 +0000 (14:43 +0100)]
ada: Fix address arithmetic issues in the runtime
This is most notably the addition of addresses in Interfaces.C.Pointers and
System.Bitfield_Utils. There is also a change to System.Stream_Attributes,
which was representing a thin pointer as a record, which is not problematic
per se, but is in the end, because the expanded code performs an unchecked
conversion from it to the access type instead of accessing the component.
gcc/ada/
* libgnat/i-cpoint.adb: Add clauses for System.Storage_Elements.
(Addr): Delete.
(Offset): New subtype of Storage_Offset.
(To_Offset): New instance of Unchecked_Conversion.
(To_Pointer): Adjust.
(To_Addr): Likewise.
(To_Ptrdiff): Likewise.
("+"): Call To_Offset on the offset.
("-"): Likewise.
* libgnat/s-bituti.adb: Add clauses for System.Storage_Elements.
(Val_Bytes): Change type to Storage_Count.
(Get_Val_2): Add qualification to second operand of mod operator.
(Set_Val_2): Likewise.
(Copy_Bitfield): Likewise. Change type of Src_Adjust & Dest_Adjust.
* libgnat/s-stratt.ads (Thin_Pointer): Change to subtype of Address.
* libgnat/s-statxd.adb (I_AD): Adjust.
(I_AS): Likewise.
(W_AS): Likewise.
Steve Baird [Thu, 16 Feb 2023 00:13:06 +0000 (16:13 -0800)]
ada: A discriminant of a variable is not a variable
gcc/ada/
* sem_util.adb
(Is_Variable): Correctly return False for a selected component
name of the form Some_Object.Some_Discriminant, even if
Some_Object is a variable. We don't want to allow such a name as
an actual parameter in a call if the corresponding formal
parameter's mode is not "in".
Eric Botcazou [Sun, 19 Feb 2023 17:45:00 +0000 (18:45 +0100)]
ada: Remove the body of System.Storage_Elements
All the subprograms declared in the unit have convention Intrinsic and
their current implementation makes some implicit assumptions that are
not valid universally, so it is replaced by a direct expansion.
This is mostly straightforward because Resolve_Intrinsic_Operator already
contains the required circuitry, but a few adjustements are necessary.
gcc/ada/
* exp_ch4.adb (Expand_N_Op_Mod): Deal with the special mod
operator of System.Storage_Elements.
* exp_intr.adb (Expand_To_Integer): New procedure.
(Expand_Intrinsic_Call): Call Expand_To_Integer appropriately.
(Expand_To_Address): Deal with an argument with modular type.
* sem_ch3.adb (Derive_Subprogram): Also set convention Intrinsic
on a derived intrinsic subprogram.
* sem_res.adb (Resolve_Arithmetic_Op): Deal with intrinsic
operators not coming from source exactly as those coming from
source and also generate a reference in both cases.
(Resolve_Op_Expon): Likewise.
(Resolve_Intrinsic_Operator): Call Implementation_Base_Type to get
a nonprivate base type.
* snames.ads-tmpl (Name_To_Integer): New intrinsic name.
* libgnat/s-stoele.ads: Replace pragma Convention with pragma
Import throughout and remove pragma Inline_Always and
Pure_Function.
* libgnat/s-stoele.adb: Replace entire contents with pragma
No_Body.
* libgnat/s-atacco.adb: Adjust comment about pragma No_Body.
Javier Miranda [Fri, 17 Feb 2023 18:57:07 +0000 (18:57 +0000)]
ada: Spurious errors on class-wide preconditions of private types
The compiler reports spurious errors processing the class-wide
preconditions of a dispatching primitive of a private type T, when
the class-wide precondition invokes another dispatching primitive
of T that has the same name as a record component of T.
gcc/ada/
* sem_prag.adb (Analyze_Pre_Post_Condition_In_Decl_Part): Remove
call to preanalyze class-wide conditions since here it is too
early; they must be preanalyzed when full views of private types
have been analyzed.
* sem_ch7.adb (Analyze_Package_Specification): Preanalyze
class-wide conditions of dispatching primitives defined in nested
packages.
Piotr Trojanek [Mon, 20 Feb 2023 13:01:36 +0000 (14:01 +0100)]
ada: Turn assertions into defensive code in error locations
We pretty-print numeric literals that do not come from source by relying
on their Sloc. This generally works well, but sporadically the Sloc is
set wrongly. We might want to trace and fix such occurrences, but for
now it is simpler to replace an otherwise reasonable assertions with
defensive code.
gcc/ada/
* errout.adb (Last_Sloc): Refactor a heavily repeated "S := S + 1"
statement into a subprogram; replace assertions with defensive code;
fix few more off-by-one errors.
There are multiple possible interpretations of "LSP". For example,
"Language Server Protocol". This patch clarifies that the
occurrences of "LSP" in GNAT's source code refer to the Liskov
Substitution Principle.
Piotr Trojanek [Fri, 17 Feb 2023 23:02:08 +0000 (00:02 +0100)]
ada: Fix endings of pretty-printed numeric literals
When looking for the end of an numeric literal we consumed '+' and '-'
characters, because they might appear in the exponent part. This was too
aggressive when they separated the number from the subsequent operand,
like in "123+456". Now we skip past numeric literals by strictly
following their grammar and only consume '+' and '-' when they belong to
the exponent.
gcc/ada/
* errout.adb (Last_Sloc): Rewrite skipping past numeric literals.
Eric Botcazou [Wed, 15 Feb 2023 14:52:00 +0000 (15:52 +0100)]
ada: Fix internal error on quantified expression with predicated type
The problem is that the special function created by the compiler to check
the predicate does not inherit the public status of the type, because it
is generated as part of the freezing of the quantified expression, which
occurs from within a couple of intermediate internal scopes.
gcc/ada/
* sem_ch13.adb (Build_Predicate_Function_Declaration): Adjust the
commentary to the current implementation.
* sem_util.ads (Current_Scope_No_Loops): Move around.
(Current_Scope_No_Loops_No_Blocks): New declaration.
(Add_Block_Identifier): Fix formatting.
* sem_util.adb (Add_Block_Identifier): Likewise.
(Current_Scope_No_Loops_No_Blocks): New function.
(Set_Public_Status): Call Current_Scope_No_Loops_No_Blocks instead
of Current_Scope to get the current scope.
Eric Botcazou [Fri, 17 Feb 2023 17:01:52 +0000 (18:01 +0100)]
ada: Fix bogus error on predicated limited record declared in protected type
This happens when the limited record is initialized with a function call
because of a couple of issues: incorrect tree sharing when building the
predicate check and too late freezing for a compiler-generated subtype.
It turns out that building the predicate check manually is redundant here,
since predicate checks are automatically generated during the expansion of
assignment statements, and the late freezing can be easily fixed.
gcc/ada/
* exp_ch3.adb (Build_Record_Init_Proc.Build_Assignment): Do not
manually generate a predicate check. Call Unqualify before doing
pattern matching on the expression.
* sem_ch3.adb (Analyze_Object_Declaration): Also freeze the actual
subtype when it is built in the definite case.
Piotr Trojanek [Fri, 9 Sep 2022 15:49:39 +0000 (17:49 +0200)]
ada: Sync different variants of interrupt handler registration
This patch propagates the apparently cleanest solutions between various
variants of the runtime units for interrupt handler registration.
In particular, the unnecessary default expressions for list cells with
interrupt handler addresses are removed, the list is changed from
doubly-linked to singly-linked, and assertion preventing registration of
null addresses now appears in all runtimes.
Effectively, it is just a code cleanup and minor optimization; behavior
of the runtime unit is unaffected.
gcc/ada/
* libgnarl/s-interr.adb
(Registered_Handler): Remove default expression.
(Registered_Handlers): Switch to singly-linked list.
(Bind_Interrupt_To_Entry): Sync whitespace with other unit variants.
(Is_Registered): Use singly-linked list.
(Register_Interrupt_Handler): Use singly-linked list and initialized
allocator; sync assertion with other unit variants.
* libgnarl/s-interr__sigaction.adb: Likewise.
* libgnarl/s-interr__vxworks.adb: Likewise.
* libgnarl/s-interr__hwint.adb: Likewise.
(Is_Registered): Remove repeated declaration.
Piotr Trojanek [Tue, 14 Feb 2023 16:05:59 +0000 (17:05 +0100)]
ada: Revert to old pretty-printing of internal entities for CodePeer
Add some defensive code to get pretty-printed CodePeer outputs for ACATS
back to shape. At least some of this code appears to be redundant and
perhaps unnecessary, but we can this up later.
Expression pretty-printer should not be called with
N_Defining_Identifier nodes at all, since they are not expressions.
However, for those that come not from source, CodePeer expects that the
Ident_Image routine will convert the internal names like "xL" to their
corresponding human-readable representation like "x'Accesibility_Level".
gcc/ada/
* pprint.adb (Expression_Image): Restore some of the old pretty-printing
for CodePeer.
Piotr Trojanek [Mon, 13 Feb 2023 21:49:39 +0000 (22:49 +0100)]
ada: Ignore accessibility actuals in expression pretty-printer
Extra actual parameters for accessibility checks are confusing for the
expression pretty-printer that is used by CodePeer. It seems that nodes
created for the accessibility checks should use the Sloc of the source
expression of accessibility checks, not the target. However, this is
problematic to achieve with the current implementation of accessibility
checks, so with this patch we will simply ignore the accessibility
actuals when computing Slocs for expression pretty-printing.
Piotr Trojanek [Mon, 13 Feb 2023 21:13:32 +0000 (22:13 +0100)]
ada: Remove special-case for parentheses in expansion for GNATprove
When expanding of inequality operators for GNAT we were adding extra
parens, supposedly to "fix Sprint output" (source print); for GNATprove
we didn't, as these extra parens were leading to wrong columns for check
messages.
Adding these extra parens couldn't be a right, because Sprint should
produce reasonable output regardless of the parens, especially since we
don't care about parens when creating AST in expansion. Avoiding them
for GNATprove couldn't be right either, because source printing should
work regardless of the GNAT/GNATprove mode.
The proper fix for GNAT is rather to not add parens at all and tune
source printing, if necessary. The proper fix for GNATprove is not have
them either, as it confuses the heuristic in First_Sloc, which is then
used by Compute_Sloc.
gcc/ada/
* exp_ch4.adb (Expand_N_Op_Ne): Simply don't add extra parens.
Piotr Trojanek [Sat, 11 Feb 2023 20:09:11 +0000 (21:09 +0100)]
ada: Transfer fix for pretty-printed parentheses from GNATprove to GNAT
Expressions with parentheses are notoriously problematic to
pretty-print. In GNATprove we had a post-processing fix for them,
but it is better to have this fix in the GNAT frontend repository
and apply it for CodePeer as well.
gcc/ada/
* pprint.adb (Expression_Image): Move Count_Parentheses and
Fix_Parentheses routines from GNATprove and apply them before
returning the slice of a source code buffer.
Piotr Trojanek [Fri, 10 Feb 2023 23:43:41 +0000 (00:43 +0100)]
ada: Fix expression pretty-printer for SPARK counterexamples
The expression pretty-printer that is used for SPARK counterexamples was
essentially duplicating the logic of First_Node/Last_Node and
First_Sloc/Last_Sloc routines. Now it simply reuses those routines.
gcc/ada/
* errout.adb
(Paren_Required): New subsidiary routine for better handling of
parentheses in First_Node/Last_Node.
(First_Sloc, Last_Sloc): Use Get_Source_File_Index to correctly
handle generic instances and inlined subprograms; tune handling of
parentheses; improve handling of literals.
* pprint.adb (Expression_Image): Simplify using
First_Sloc/Last_Sloc.
* sem_ch6.adb (Analyze_Expression_Function): Remove parenthesis
when relocating expression from expression function to simple
return statement.
Piotr Trojanek [Wed, 15 Feb 2023 20:20:42 +0000 (21:20 +0100)]
ada: Suppress warning about Subprogram_Variant failing at run time
Warning about check failing at run time is likely spurious for mutually
recursive subprograms with multiple variant clauses. These will be
non-trivial to detect, so we simply suppress the warning altogether for
all subprogram variants.
gcc/ada/
* exp_prag.adb (Expand_Pragma_Check): Suppress warning for checks of
subprogram variants.
Javier Miranda [Sun, 12 Feb 2023 13:37:39 +0000 (13:37 +0000)]
ada: Crash on dispatching primitive referencing limited-with type
The compiler crashes processing a compilation unit has limited-with
context clauses, and the profile of some dispatching primitive
references a type visible through a limited-with clause, and
the dispatching primitive has class-wide preconditions.
gcc/ada/
* sem_ch10.adb
(Analyze_Required_Limited_With_Units): New subprogram.
(Depends_On_Limited_Views): New subprogram.
(Has_Limited_With_Clauses): New subprogram.
(Analyze_Compilation_Unit): Call the new subprogram that performs
the full analysis of required limited-with units.
Matthias Kretz [Thu, 23 Mar 2023 08:32:58 +0000 (09:32 +0100)]
libstdc++: Add missing constexpr to simd
The constexpr API is only available with -std=gnu++XX (and proposed for
C++26). The proposal is to have the complete simd API usable in constant
expressions.
This patch resolves several issues with using simd in constant
expressions.
Issues why constant_evaluated branches are necessary:
* subscripting vector builtins is not allowed in constant expressions
* if the implementation needs/uses memcpy
* if the implementation would otherwise call SIMD intrinsics/builtins
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