Bill Schmidt [Fri, 2 May 2014 21:51:09 +0000 (21:51 +0000)]
re PR tree-optimization/60930 (Wrong folding of - ((unsigned long long) a * (unsigned long long) (unsigned int)-1))
[gcc]
2014-05-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR tree-optimization/60930
* gimple-ssa-strength-reduction.c (create_mul_imm_cand): Reject
creating a multiply candidate by folding two constant
multiplicands when the result overflows.
[gcc/testsuite]
2014-05-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR tree-optimization/60930
* gcc.dg/torture/pr60930.c: New test.
* config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add
support for decimal floating point builtin functions.
(rs6000_expand_ternop_builtin): Add checks for the new builtin
functions that take constant arguments.
(rs6000_invalid_builtin): Add decimal floating point builtin
support.
(rs6000_init_builtins): Setup long double, _Decimal64, and
_Decimal128 types for new builtin functions.
(builtin_function_type): Set the unsigned flags appropriately for
the new builtin functions.
(rs6000_opt_masks): Add support for decimal floating point builtin
functions.
* config/rs6000/rs6000.h (RS6000_BTM_DFP): Add support for decimal
floating point builtin functions.
(RS6000_BTM_COMMON): Likewise.
(RS6000_BTI_long_double): Likewise.
(RS6000_BTI_dfloat64): Likewise.
(RS6000_BTI_dfloat128): Likewise.
(long_double_type_internal_node): Likewise.
(dfloat64_type_internal_node): Likewise.
(dfloat128_type_internal_node): Likewise.
* config/rs6000/altivec.h (UNSPEC_BCDADD): Add support for ISA
2.07 bcd arithmetic instructions.
(UNSPEC_BCDSUB): Likewise.
(UNSPEC_BCD_OVERFLOW): Likewise.
(UNSPEC_BCD_ADD_SUB): Likewise.
(bcd_add_sub): Likewise.
(BCD_TEST): Likewise.
(bcd<bcd_add_sub>): Likewise.
(bcd<bcd_add_sub>_test): Likewise.
(bcd<bcd_add_sub>_test2): Likewise.
(bcd<bcd_add_sub>_<code>): Likewise.
(peephole2 for combined bcd ops): Likewise.
* config/rs6000/dfp.md (UNSPEC_DDEDPD): Add support for new
decimal floating point builtin functions.
(UNSPEC_DENBCD): Likewise.
(UNSPEC_DXEX): Likewise.
(UNSPEC_DIEX): Likewise.
(UNSPEC_DSCLI): Likewise.
(UNSPEC_DSCRI): Likewise.
(D64_D128): Likewise.
(dfp_suffix): Likewise.
(dfp_ddedpd_<mode>): Likewise.
(dfp_denbcd_<mode>): Likewise.
(dfp_dxex_<mode>): Likewise.
(dfp_diex_<mode>): Likewise.
(dfp_dscli_<mode>): Likewise.
(dfp_dscri_<mode>): Likewise.
* config/rs6000/rs6000.md (UNSPEC_ADDG6S): Add support for new BCD
builtin functions.
(UNSPEC_CDTBCD): Likewise.
(UNSPEC_CBCDTD): Likewise.
(UNSPEC_DIVE): Add support for new extended divide builtin
functions.
(UNSPEC_DIVEO): Likewise.
(UNSPEC_DIVEU): Likewise.
(UNSPEC_DIVEUO): Likewise.
(UNSPEC_UNPACK_128BIT): Add support for new builtin functions to
pack/unpack 128-bit types.
(UNSPEC_PACK_128BIT): Likewise.
(idiv_ldiv): New mode attribute to set the 32/64-bit divide type.
(udiv<mode>3): Use idiv_ldiv mode attribute.
(div<mode>3): Likewise.
(addg6s): Add new BCD builtin functions.
(cdtbcd): Likewise.
(cbcdtd): Likewise.
(UNSPEC_DIV_EXTEND): Add support for new extended divide
instructions.
(div_extend): Likewise.
(div<div_extend>_<mode>"): Likewise.
(FP128_64): Add support for new builtin functions to pack/unpack
128-bit types.
(unpack<mode>): Likewise.
(unpacktf_0): Likewise.
(unpacktf_1): Likewise.
(unpack<mode>_dm): Likewise.
(unpack<mode>_nodm): Likewise.
(pack<mode>): Likewise.
(unpackv1ti): Likewise.
(packv1ti): Likewise.
[gcc/testsuite]
2014-04-30 Michael Meissner <meissner@linux.vnet.ibm.com>
Back port from mainline
2014-04-24 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/pack01.c: New test to test the new pack and
unpack builtin functionss for 128-bit types.
* gcc.target/powerpc/pack02.c: Likewise.
* gcc.target/powerpc/pack03.c: Likewise.
* gcc.target/powerpc/extend-divide-1.c: New test to test extended
divide builtin functionss.
* gcc.target/powerpc/extend-divide-2.c: Likewise.
* gcc.target/powerpc/bcd-1.c: New test for the new BCD builtin
functions.
* gcc.target/powerpc/bcd-2.c: Likewise.
* gcc.target/powerpc/bcd-3.c: Likewise.
* gcc.target/powerpc/dfp-builtin-1.c: New test for the new DFP
builtin functionss.
* gcc.target/powerpc/dfp-builtin-2.c: Likewise.
Eric Botcazou [Mon, 28 Apr 2014 10:05:29 +0000 (10:05 +0000)]
configure.ac: Tweak GAS check for LEON instructions on SPARC.
* configure.ac: Tweak GAS check for LEON instructions on SPARC.
* configure: Regenerate.
* config/sparc/sparc.opt (muser-mode): New option.
* config/sparc/sync.md (atomic_compare_and_swap<mode>_1): Do not enable
for LEON3.
(atomic_compare_and_swap_leon3_1): New instruction for LEON3.
* doc/invoke.texi (SPARC options): Document -muser-mode.
* config/rs6000/altivec.md (UNSPEC_VBPERMQ): Add support for the
vbpermq instruction.
(altivec_vbpermq): Likewise.
PR target/60672
* config/rs6000/altivec.h (vec_xxsldwi): Add missing define to
enable use of xxsldwi and xxpermdi builtin functions.
(vec_xxpermdi): Likewise.
* doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
Document use of vec_xxsldwi and vec_xxpermdi builtins.
[gcc/testsuite]
2014-04-23 Michael Meissner <meissner@linux.vnet.ibm.com>
Back port from main line:
2014-03-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p8vector-vbpermq.c: New test to test the
vbpermq builtin.
* config/rs6000/altivec.md (UNSPEC_VBPERMQ): Add support for the
vbpermq instruction.
(altivec_vbpermq): Likewise.
PR target/60672
* config/rs6000/altivec.h (vec_xxsldwi): Add missing define to
enable use of xxsldwi and xxpermdi builtin functions.
(vec_xxpermdi): Likewise.
* doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
Document use of vec_xxsldwi and vec_xxpermdi builtins.
[gcc/testsuite]
2014-04-23 Michael Meissner <meissner@linux.vnet.ibm.com>
Back port from main line:
2014-03-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p8vector-vbpermq.c: New test to test the
vbpermq builtin.
Bill Schmidt [Tue, 15 Apr 2014 18:30:21 +0000 (18:30 +0000)]
revert: [multiple changes]
2014-04-15 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR target/60839
Revert the following patch
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Back port mainline subversion id 209025.
2014-04-02 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/60735
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have
software floating point or no floating point registers, do not
allow any type in the FPRs. Eliminate a test for SPE SIMD types
in GPRs that occurs after we tested for GPRs that would never be
true.
* config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):
Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE,
since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE,
specifically allow DDmode, since that does not use the SPE SIMD
instructions.
Andreas Krebbel [Fri, 11 Apr 2014 10:47:36 +0000 (10:47 +0000)]
htm-nofloat-1.c: Rename to ...
2014-04-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* gcc.target/s390/htm-nofloat-1.c: Rename to ...
* gcc.target/s390/htm-nofloat-compile-1.c: ... this one.
* gcc.target/s390/htm-nofloat-2.c: Add check for htm target and
rename to ...
* gcc.target/s390/htm-nofloat-1.c: ... this one.
* gcc.target/s390/s390.exp: Make sure the assembler supports htm
instructions as well.
Jakub Jelinek [Thu, 10 Apr 2014 07:47:55 +0000 (09:47 +0200)]
backport: re PR middle-end/36282 (Spurious warning "asm declaration ignored due to conflict with previous rename")
Backport from mainline
2014-03-13 Jakub Jelinek <jakub@redhat.com>
PR middle-end/36282
* c-pragma.c (apply_pragma_weak): Only look at
TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)) if
DECL_ASSEMBLER_NAME_SET_P (decl).
(maybe_apply_pending_pragma_weaks): Exit early if
vec_safe_is_empty (pending_weaks) rather than only when
!pending_weaks.
(maybe_apply_pragma_weak): Likewise. If !DECL_ASSEMBLER_NAME_SET_P,
set assembler name back to NULL afterwards.
* c-c++-common/pr36282-1.c: New test.
* c-c++-common/pr36282-2.c: New test.
* c-c++-common/pr36282-3.c: New test.
* c-c++-common/pr36282-4.c: New test.
Bill Schmidt [Wed, 9 Apr 2014 20:15:57 +0000 (20:15 +0000)]
backport: [multiple changes]
2014-04-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline r208750
2014-03-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_expand_vector_set): Generate a
pattern for vector nor instead of subtract from splat(-1).
(altivec_expand_vec_perm_const_le): Likewise.
Backport from mainline r209235
2014-04-08 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_expand_vector_set): Use vnand
instead of vnor to exploit possible fusion opportunity in the
future.
(altivec_expand_vec_perm_const_le): Likewise.
Backport from mainline
2013-09-14 Iain Sandoe <iains@gcc.gnu.org>
gcc:
PR target/48094
* config/darwin.c (darwin_objc2_section): Note if ObjC Metadata is seen.
(darwin_objc1_section): Likewise.
(darwin_file_end): Emit Image Info section when required.
PR target/54083
* gcc.dg/attr-weakref-1.c: Allow the test on darwin with
the additional options -Wl,-undefined,dynamic_lookup and
-Wl,-flat_namespace
* gcc.dg/torture/pr53922.c: Additional option
-Wl,-flat_namespace for darwin[89].
Alan Modra [Sat, 5 Apr 2014 10:26:19 +0000 (20:56 +1030)]
Apply from mainline 2014-01-28 Alan Modra <amodra@gmail.com>
Apply from mainline
2014-01-28 Alan Modra <amodra@gmail.com>
* Makefile.in (BUILD_CPPFLAGS): Do not use ALL_CPPFLAGS.
* configure.ac <recursive call for build != host>: Define
GENERATOR_FILE. Comment. Use CXX_FOR_BUILD, CXXFLAGS_FOR_BUILD
and LD_FOR_BUILD too.
* configure: Regenerate.
Bill Schmidt [Fri, 4 Apr 2014 15:14:01 +0000 (15:14 +0000)]
backport: re PR target/60735 (GCC targeting E500 with SPE has errors with the _Decimal64 type)
[gcc]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Back port mainline subversion id 209025.
2014-04-02 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/60735
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): If we have
software floating point or no floating point registers, do not
allow any type in the FPRs. Eliminate a test for SPE SIMD types
in GPRs that occurs after we tested for GPRs that would never be
true.
* config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):
Rewrite tests to use TARGET_DOUBLE_FLOAT and TARGET_E500_DOUBLE,
since the FMOVE64 type is DFmode/DDmode. If TARGET_E500_DOUBLE,
specifically allow DDmode, since that does not use the SPE SIMD
instructions.
Bill Schmidt [Fri, 4 Apr 2014 15:12:10 +0000 (15:12 +0000)]
backport: rs6000.c (IN_NAMED_SECTION): New macro.
[gcc]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline r205308
2013-11-23 David Edelsohn <dje.gcc@gmail.com>
* config/rs6000/rs6000.c (IN_NAMED_SECTION): New macro.
(rs6000_xcoff_select_section): Place decls with stricter alignment
into named sections.
(rs6000_xcoff_unique_section): Allow unique sections for
uninitialized data with strict alignment.
[gcc/testsuite]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline
2013-04-05 David Edelsohn <dje.gcc@gmail.com>
* gcc.target/powerpc/sd-vsx.c: Skip on AIX.
* gcc.target/powerpc/sd-pwr6.c: Same.
Bill Schmidt [Fri, 4 Apr 2014 15:10:24 +0000 (15:10 +0000)]
backport: [multiple changes]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Back port from trunk
2013-04-25 Alan Modra <amodra@gmail.com>
PR target/57052
* config/rs6000/rs6000.md (rotlsi3_internal7): Rename to
rotlsi3_internal7le and condition on !BYTES_BIG_ENDIAN.
(rotlsi3_internal8be): New BYTES_BIG_ENDIAN insn.
Repeat for many other rotate/shift and mask patterns using subregs.
Name lshiftrt insns.
(ashrdisi3_noppc64): Rename to ashrdisi3_noppc64be and condition
on WORDS_BIG_ENDIAN.
2013-06-07 Alan Modra <amodra@gmail.com>
* config/rs6000/rs6000.c (rs6000_option_override_internal): Don't
override user -mfp-in-toc.
(offsettable_ok_by_alignment): Consider just the current access
rather than the whole object, unless BLKmode. Handle
CONSTANT_POOL_ADDRESS_P constants that lack a decl too.
(use_toc_relative_ref): Allow CONSTANT_POOL_ADDRESS_P constants
for -mcmodel=medium.
* config/rs6000/linux64.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Don't
override user -mfp-in-toc or -msum-in-toc. Default to
-mno-fp-in-toc for -mcmodel=medium.
Bill Schmidt [Fri, 4 Apr 2014 15:08:45 +0000 (15:08 +0000)]
backport: vector.md (VEC_L): Add V1TI mode to vector types.
[gcc]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Back port from trunk
2014-03-12 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vector.md (VEC_L): Add V1TI mode to vector types.
(VEC_M): Likewise.
(VEC_N): Likewise.
(VEC_R): Likewise.
(VEC_base): Likewise.
(mov<MODE>, VEC_M modes): If we are loading TImode into VSX
registers, we need to swap double words in little endian mode.
* config/rs6000/rs6000-modes.def (V1TImode): Add new vector mode
to be a container mode for 128-bit integer operations added in ISA
2.07. Unlike TImode and PTImode, the preferred register set is
the Altivec/VMX registers for the 128-bit operations.
* config/rs6000/rs6000-builtin.def (BU_P8V_AV_3): Add new support
macros for creating ISA 2.07 normal and overloaded builtin
functions with 3 arguments.
(BU_P8V_OVERLOAD_3): Likewise.
(VPERM_1T): Add support for V1TImode in 128-bit vector operations
for use as overloaded functions.
(VPERM_1TI_UNS): Likewise.
(VSEL_1TI): Likewise.
(VSEL_1TI_UNS): Likewise.
(ST_INTERNAL_1ti): Likewise.
(LD_INTERNAL_1ti): Likewise.
(XXSEL_1TI): Likewise.
(XXSEL_1TI_UNS): Likewise.
(VPERM_1TI): Likewise.
(VPERM_1TI_UNS): Likewise.
(XXPERMDI_1TI): Likewise.
(SET_1TI): Likewise.
(LXVD2X_V1TI): Likewise.
(STXVD2X_V1TI): Likewise.
(VEC_INIT_V1TI): Likewise.
(VEC_SET_V1TI): Likewise.
(VEC_EXT_V1TI): Likewise.
(EQV_V1TI): Likewise.
(NAND_V1TI): Likewise.
(ORC_V1TI): Likewise.
(VADDCUQ): Add support for 128-bit integer arithmetic instructions
added in ISA 2.07. Add both normal 'altivec' builtins, and the
overloaded builtin.
(VADDUQM): Likewise.
(VSUBCUQ): Likewise.
(VADDEUQM): Likewise.
(VADDECUQ): Likewise.
(VSUBEUQM): Likewise.
(VSUBECUQ): Likewise.
* config/rs6000/rs6000-c.c (__int128_type): New static to hold
__int128_t and __uint128_t types.
(__uint128_type): Likewise.
(altivec_categorize_keyword): Add support for vector __int128_t,
vector __uint128_t, vector __int128, and vector unsigned __int128
as a container type for TImode operations that need to be done in
VSX/Altivec registers.
(rs6000_macro_to_expand): Likewise.
(altivec_overloaded_builtins): Add ISA 2.07 overloaded functions
to support 128-bit integer instructions vaddcuq, vadduqm,
vaddecuq, vaddeuqm, vsubcuq, vsubuqm, vsubecuq, vsubeuqm.
(altivec_resolve_overloaded_builtin): Add support for V1TImode.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Add support
for V1TImode, and set up preferences to use VSX/Altivec
registers. Setup VSX reload handlers.
(rs6000_debug_reg_global): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_preferred_simd_mode): Likewise.
(vspltis_constant): Do not allow V1TImode as easy altivec
constants.
(easy_altivec_constant): Likewise.
(output_vec_const_move): Likewise.
(rs6000_expand_vector_set): Convert V1TImode set and extract to
simple move.
(rs6000_expand_vector_extract): Likewise.
(reg_offset_addressing_ok_p): Setup V1TImode to use VSX reg+reg
addressing.
(rs6000_const_vec): Add support for V1TImode.
(rs6000_emit_le_vsx_load): Swap double words when loading or
storing TImode/V1TImode.
(rs6000_emit_le_vsx_store): Likewise.
(rs6000_emit_le_vsx_move): Likewise.
(rs6000_emit_move): Add support for V1TImode.
(altivec_expand_ld_builtin): Likewise.
(altivec_expand_st_builtin): Likewise.
(altivec_expand_vec_init_builtin): Likewise.
(altivec_expand_builtin): Likewise.
(rs6000_init_builtins): Add support for V1TImode type. Add
support for ISA 2.07 128-bit integer builtins. Define type names
for the VSX/Altivec vector types.
(altivec_init_builtins): Add support for overloaded vector
functions with V1TImode type.
(rs6000_preferred_reload_class): Prefer Altivec registers for
V1TImode.
(rs6000_move_128bit_ok_p): Move 128-bit move/split validation to
external function.
(rs6000_split_128bit_ok_p): Likewise.
(rs6000_handle_altivec_attribute): Create V1TImode from vector
__int128_t and vector __uint128_t.
* config/rs6000/vsx.md (VSX_L): Add V1TImode to vector iterators
and mode attributes.
(VSX_M): Likewise.
(VSX_M2): Likewise.
(VSm): Likewise.
(VSs): Likewise.
(VSr): Likewise.
(VSv): Likewise.
(VS_scalar): Likewise.
(VS_double): Likewise.
(vsx_set_v1ti): New builtin function to create V1TImode from
TImode.
* config/rs6000/rs6000.h (TARGET_VADDUQM): New macro to say
whether we support the ISA 2.07 128-bit integer arithmetic
instructions.
(ALTIVEC_OR_VSX_VECTOR_MODE): Add V1TImode.
(enum rs6000_builtin_type_index): Add fields to hold V1TImode
and TImode types for use with the builtin functions.
(V1TI_type_node): Likewise.
(unsigned_V1TI_type_node): Likewise.
(intTI_type_internal_node): Likewise.
(uintTI_type_internal_node): Likewise.
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Back port from trunk
2014-03-12 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p8vector-int128-1.c: New test to test ISA
2.07 128-bit arithmetic.
* gcc.target/powerpc/p8vector-int128-2.c: Likewise.
* gcc.target/powerpc/timode_off.c: Restrict cpu type to power5,
due to when TImode is allowed in VSX registers, the allowable
address modes for TImode is just a single indirect address in
order for the value to be loaded and store in either GPR or VSX
registers. This affects the generated code, and it would cause
this test to fail, when such an option is used.
Bill Schmidt [Fri, 4 Apr 2014 15:05:34 +0000 (15:05 +0000)]
backport: [multiple changes]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Apply mainline r207798
2014-02-26 Alan Modra <amodra@gmail.com>
PR target/58675
PR target/57935
* config/rs6000/rs6000.c (rs6000_secondary_reload_inner): Use
find_replacement on parts of insn rtl that might be reloaded.
Backport from mainline r208287
2014-03-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_preferred_reload_class): Disallow
reload of PLUS rtx's outside of GENERAL_REGS or BASE_REGS; relax
constraint on constants to permit them being loaded into
GENERAL_REGS or BASE_REGS.
Bill Schmidt [Fri, 4 Apr 2014 15:02:38 +0000 (15:02 +0000)]
backport: re PR target/60137 (Code fails with -mcpu=power8 -O3 -mno-vsx)
[gcc]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline r207699.
2014-02-11 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/60137
* config/rs6000/rs6000.md (128-bit GPR splitter): Add a splitter
for VSX/Altivec vectors that land in GPR registers.
Backport from mainline r207808.
2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/60203
* config/rs6000/rs6000.md (rreg): Add TFmode, TDmode constraints.
(mov<mode>_internal, TFmode/TDmode): Split TFmode/TDmode moves
into 64-bit and 32-bit moves. On 64-bit moves, add support for
using direct move instructions on ISA 2.07. Also adjust
instruction length for 64-bit.
(mov<mode>_64bit, TFmode/TDmode): Likewise.
(mov<mode>_32bit, TFmode/TDmode): Likewise.
Backport from mainline r207868.
2014-02-18 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/60203
* config/rs6000/rs6000.md (mov<mode>_64bit, TF/TDmode moves):
Split 64-bit moves into 2 patterns. Do not allow the use of
direct move for TDmode in little endian, since the decimal value
has little endian bytes within a word, but the 64-bit pieces are
ordered in a big endian fashion, and normal subreg's of TDmode are
not allowed.
(mov<mode>_64bit_dm): Likewise.
(movtd_64bit_nodm): Likewise.
[gcc/testsuite]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline r207699.
2014-02-11 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/60137
* gcc.target/powerpc/pr60137.c: New file.
Backport from mainline r207808.
2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/60203
* gcc.target/powerpc/pr60203.c: New testsuite.
Bill Schmidt [Fri, 4 Apr 2014 14:49:08 +0000 (14:49 +0000)]
backport: rs6000-c.c (altivec_overloaded_builtins): Remove two duplicate entries.
[gcc]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline r206443
2014-01-08 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Remove
two duplicate entries.
Backport from mainline r206494
2014-01-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* doc/invoke.texi: Add -maltivec={be,le} options, and document
default element-order behavior for -maltivec.
* config/rs6000/rs6000.opt: Add -maltivec={be,le} options.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Ensure
that -maltivec={le,be} implies -maltivec; disallow -maltivec=le
when targeting big endian, at least for now.
* config/rs6000/rs6000.h: Add #define of VECTOR_ELT_ORDER_BIG.
Backport from mainline r206541
2014-01-10 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000-builtin.def: Fix pasto for VPKSDUS.
Backport from mainline r206590
2014-01-13 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
Implement -maltivec=be for vec_insert and vec_extract.
Backport from mainline r206641
2014-01-15 Bill Schmidt <wschmidt@vnet.linux.ibm.com>
* config/rs6000/altivec.md (mulv8hi3): Explicitly generate vmulesh
and vmulosh rather than call gen_vec_widen_smult_*.
(vec_widen_umult_even_v16qi): Test VECTOR_ELT_ORDER_BIG rather
than BYTES_BIG_ENDIAN to determine use of even or odd instruction.
(vec_widen_smult_even_v16qi): Likewise.
(vec_widen_umult_even_v8hi): Likewise.
(vec_widen_smult_even_v8hi): Likewise.
(vec_widen_umult_odd_v16qi): Likewise.
(vec_widen_smult_odd_v16qi): Likewise.
(vec_widen_umult_odd_v8hi): Likewise.
(vec_widen_smult_odd_v8hi): Likewise.
(vec_widen_umult_hi_v16qi): Explicitly generate vmuleub and
vmuloub rather than call gen_vec_widen_umult_*.
(vec_widen_umult_lo_v16qi): Likewise.
(vec_widen_smult_hi_v16qi): Explicitly generate vmulesb and
vmulosb rather than call gen_vec_widen_smult_*.
(vec_widen_smult_lo_v16qi): Likewise.
(vec_widen_umult_hi_v8hi): Explicitly generate vmuleuh and vmulouh
rather than call gen_vec_widen_umult_*.
(vec_widen_umult_lo_v8hi): Likewise.
(vec_widen_smult_hi_v8hi): Explicitly gnerate vmulesh and vmulosh
rather than call gen_vec_widen_smult_*.
(vec_widen_smult_lo_v8hi): Likewise.
Backport from mainline r207062
2014-01-24 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_expand_vec_perm_const_1): Remove
correction for little endian...
* config/rs6000/vsx.md (vsx_xxpermdi2_<mode>_1): ...and move it to
here.
Backport from mainline r207262
2014-01-29 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Use
CODE_FOR_altivec_vmrg*_direct rather than CODE_FOR_altivec_vmrg*.
* config/rs6000/vsx.md (vsx_mergel_<mode>): Adjust for
-maltivec=be with LE targets.
(vsx_mergeh_<mode>): Likewise.
* config/rs6000/altivec.md (UNSPEC_VMRG[HL]_DIRECT): New
unspecs.
(mulv8hi3): Use gen_altivec_vmrg[hl]w_direct.
(altivec_vmrghb): Replace with define_expand and new
*altivec_vmrghb_internal insn; adjust for -maltivec=be with LE
targets.
(altivec_vmrghb_direct): New define_insn.
(altivec_vmrghh): Replace with define_expand and new
*altivec_vmrghh_internal insn; adjust for -maltivec=be with LE
targets.
(altivec_vmrghh_direct): New define_insn.
(altivec_vmrghw): Replace with define_expand and new
*altivec_vmrghw_internal insn; adjust for -maltivec=be with LE
targets.
(altivec_vmrghw_direct): New define_insn.
(*altivec_vmrghsf): Adjust for endianness.
(altivec_vmrglb): Replace with define_expand and new
*altivec_vmrglb_internal insn; adjust for -maltivec=be with LE
targets.
(altivec_vmrglb_direct): New define_insn.
(altivec_vmrglh): Replace with define_expand and new
*altivec_vmrglh_internal insn; adjust for -maltivec=be with LE
targets.
(altivec_vmrglh_direct): New define_insn.
(altivec_vmrglw): Replace with define_expand and new
*altivec_vmrglw_internal insn; adjust for -maltivec=be with LE
targets.
(altivec_vmrglw_direct): New define_insn.
(*altivec_vmrglsf): Adjust for endianness.
(vec_widen_umult_hi_v16qi): Use gen_altivec_vmrghh_direct.
(vec_widen_umult_lo_v16qi): Use gen_altivec_vmrglh_direct.
(vec_widen_smult_hi_v16qi): Use gen_altivec_vmrghh_direct.
(vec_widen_smult_lo_v16qi): Use gen_altivec_vmrglh_direct.
(vec_widen_umult_hi_v8hi): Use gen_altivec_vmrghw_direct.
(vec_widen_umult_lo_v8hi): Use gen_altivec_vmrglw_direct.
(vec_widen_smult_hi_v8hi): Use gen_altivec_vmrghw_direct.
(vec_widen_smult_lo_v8hi): Use gen_altivec_vmrglw_direct.
Backport from mainline r207318
2014-01-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* gcc/config/rs6000/rs6000.c (rs6000_expand_vector_init): Use
gen_vsx_xxspltw_v4sf_direct instead of gen_vsx_xxspltw_v4sf;
remove element index adjustment for endian (now handled in vsx.md
and altivec.md).
(altivec_expand_vec_perm_const): Use
gen_altivec_vsplt[bhw]_direct instead of gen_altivec_vsplt[bhw].
* gcc/config/rs6000/vsx.md (UNSPEC_VSX_XXSPLTW): New unspec.
(vsx_xxspltw_<mode>): Adjust element index for little endian.
* gcc/config/rs6000/altivec.md (altivec_vspltb): Divide into a
define_expand and a new define_insn *altivec_vspltb_internal;
adjust for -maltivec=be on a little endian target.
(altivec_vspltb_direct): New.
(altivec_vsplth): Divide into a define_expand and a new
define_insn *altivec_vsplth_internal; adjust for -maltivec=be on a
little endian target.
(altivec_vsplth_direct): New.
(altivec_vspltw): Divide into a define_expand and a new
define_insn *altivec_vspltw_internal; adjust for -maltivec=be on a
little endian target.
(altivec_vspltw_direct): New.
(altivec_vspltsf): Divide into a define_expand and a new
define_insn *altivec_vspltsf_internal; adjust for -maltivec=be on
a little endian target.
Backport from mainline r207326
2014-01-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline r207414
2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/altivec.md (UNSPEC_VSUMSWS_DIRECT): New unspec.
(altivec_vsumsws): Add handling for -maltivec=be with a little
endian target.
(altivec_vsumsws_direct): New.
(reduc_splus_<mode>): Call gen_altivec_vsumsws_direct instead of
gen_altivec_vsumsws.
Backport from mainline r207415
2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (altivec_expand_vec_perm_le): Generalize
for vector types other than V16QImode.
* config/rs6000/altivec.md (altivec_vperm_<mode>): Change to a
define_expand, and call altivec_expand_vec_perm_le when producing
code with little endian element order.
(*altivec_vperm_<mode>_internal): New insn having previous
behavior of altivec_vperm_<mode>.
(altivec_vperm_<mode>_uns): Change to a define_expand, and call
altivec_expand_vec_perm_le when producing code with little endian
element order.
(*altivec_vperm_<mode>_uns_internal): New insn having previous
behavior of altivec_vperm_<mode>_uns.
Backport from mainline r207520
2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* altivec.md (UNSPEC_VPACK_UNS_UNS_MOD_DIRECT): New unspec.
(UNSPEC_VUNPACK_HI_SIGN_DIRECT): Likewise.
(UNSPEC_VUNPACK_LO_SIGN_DIRECT): Likewise.
(mulv8hi3): Use gen_altivec_vpkuwum_direct instead of
gen_altivec_vpkuwum.
(altivec_vpkpx): Test for VECTOR_ELT_ORDER_BIG instead of for
BYTES_BIG_ENDIAN.
(altivec_vpks<VI_char>ss): Likewise.
(altivec_vpks<VI_char>us): Likewise.
(altivec_vpku<VI_char>us): Likewise.
(altivec_vpku<VI_char>um): Likewise.
(altivec_vpku<VI_char>um_direct): New (copy of
altivec_vpku<VI_char>um that still relies on BYTES_BIG_ENDIAN, for
internal use).
(altivec_vupkhs<VU_char>): Emit vupkls* instead of vupkhs* when
target is little endian and -maltivec=be is not specified.
(*altivec_vupkhs<VU_char>_direct): New (copy of
altivec_vupkhs<VU_char> that always emits vupkhs*, for internal
use).
(altivec_vupkls<VU_char>): Emit vupkhs* instead of vupkls* when
target is little endian and -maltivec=be is not specified.
(*altivec_vupkls<VU_char>_direct): New (copy of
altivec_vupkls<VU_char> that always emits vupkls*, for internal
use).
(altivec_vupkhpx): Emit vupklpx instead of vupkhpx when target is
little endian and -maltivec=be is not specified.
(altivec_vupklpx): Emit vupkhpx instead of vupklpx when target is
little endian and -maltivec=be is not specified.
Backport from mainline r207521
2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline r207525
2014-02-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Change
CODE_FOR_altivec_vpku[hw]um to
CODE_FOR_altivec_vpku[hw]um_direct.
* config/rs6000/altivec.md (vec_unpacks_hi_<VP_small_lc>): Change
UNSPEC_VUNPACK_HI_SIGN to UNSPEC_VUNPACK_HI_SIGN_DIRECT.
(vec_unpacks_lo_<VP_small_lc>): Change UNSPEC_VUNPACK_LO_SIGN to
UNSPEC_VUNPACK_LO_SIGN_DIRECT.
Backport from mainline r207814.
2014-02-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/vsx.md (vsx_xxpermdi_<mode>): Handle little
endian targets.
Backport from mainline r207815.
2014-02-16 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/altivec.md (p8_vmrgew): Handle little endian
targets.
(p8_vmrgow): Likewise.
Backport from mainline r207919.
2014-02-19 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (vspltis_constant): Fix most significant
bit of zero.
Backport from mainline 208019
2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/altivec.md (altivec_lvxl): Rename as
*altivec_lvxl_<mode>_internal and use VM2 iterator instead of
V4SI.
(altivec_lvxl_<mode>): New define_expand incorporating
-maltivec=be semantics where needed.
(altivec_lvx): Rename as *altivec_lvx_<mode>_internal.
(altivec_lvx_<mode>): New define_expand incorporating -maltivec=be
semantics where needed.
(altivec_stvx): Rename as *altivec_stvx_<mode>_internal.
(altivec_stvx_<mode>): New define_expand incorporating
-maltivec=be semantics where needed.
(altivec_stvxl): Rename as *altivec_stvxl_<mode>_internal and use
VM2 iterator instead of V4SI.
(altivec_stvxl_<mode>): New define_expand incorporating
-maltivec=be semantics where needed.
* config/rs6000/rs6000-builtin.def: Add new built-in definitions
LVXL_V2DF, LVXL_V2DI, LVXL_V4SF, LVXL_V4SI, LVXL_V8HI, LVXL_V16QI,
LVX_V2DF, LVX_V2DI, LVX_V4SF, LVX_V4SI, LVX_V8HI, LVX_V16QI,
STVX_V2DF, STVX_V2DI, STVX_V4SF, STVX_V4SI, STVX_V8HI, STVX_V16QI,
STVXL_V2DF, STVXL_V2DI, STVXL_V4SF, STVXL_V4SI, STVXL_V8HI,
STVXL_V16QI.
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Replace
ALTIVEC_BUILTIN_LVX with ALTIVEC_BUILTIN_LVX_<MODE> throughout;
similarly for ALTIVEC_BUILTIN_LVXL, ALTIVEC_BUILTIN_STVX, and
ALTIVEC_BUILTIN_STVXL.
* config/rs6000/rs6000-protos.h (altivec_expand_lvx_be): New
prototype.
(altivec_expand_stvx_be): Likewise.
* config/rs6000/rs6000.c (swap_selector_for_mode): New function.
(altivec_expand_lvx_be): Likewise.
(altivec_expand_stvx_be): Likewise.
(altivec_expand_builtin): Add cases for
ALTIVEC_BUILTIN_STVX_<MODE>, ALTIVEC_BUILTIN_STVXL_<MODE>,
ALTIVEC_BUILTIN_LVXL_<MODE>, and ALTIVEC_BUILTIN_LVX_<MODE>.
(altivec_init_builtins): Add definitions for
__builtin_altivec_lvxl_<mode>, __builtin_altivec_lvx_<mode>,
__builtin_altivec_stvx_<mode>, and
__builtin_altivec_stvxl_<mode>.
Backport from mainline 208021
2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/altivec.md (altivec_vsumsws): Replace second
vspltw with vsldoi.
(reduc_uplus_v16qi): Use gen_altivec_vsumsws_direct instead of
gen_altivec_vsumsws.
Backport from mainline 208049
2014-02-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/altivec.md (altivec_lve<VI_char>x): Replace
define_insn with define_expand and new define_insn
*altivec_lve<VI_char>x_internal.
(altivec_stve<VI_char>x): Replace define_insn with define_expand
and new define_insn *altivec_stve<VI_char>x_internal.
* config/rs6000/rs6000-protos.h (altivec_expand_stvex_be): New
prototype.
* config/rs6000/rs6000.c (altivec_expand_lvx_be): Document use by
lve*x built-ins.
(altivec_expand_stvex_be): New function.
Backport from mainline
2014-02-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_emit_le_vsx_move): Relax assert
to permit subregs.
Backport from mainline
2014-02-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/vector.md (*vector_unordered<mode>): Change split
to use canonical form for nor<mode>3.
[gcc/testsuite]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline r206590
2014-01-13 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline r207318
2014-01-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* gcc.dg/vmx/splat.c: New.
* gcc.dg/vmx/splat-vsx.c: New.
* gcc.dg/vmx/splat-be-order.c: New.
* gcc.dg/vmx/splat-vsx-be-order.c: New.
* gcc.dg/vmx/eg-5.c: Remove special casing for little endian.
* gcc.dg/vmx/sn7153.c: Add special casing for little endian.
Backport from mainline r207414
2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline 208019
2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* gcc.dg/vmx/ld.c: New test.
* gcc.dg/vmx/ld-be-order.c: New test.
* gcc.dg/vmx/ld-vsx.c: New test.
* gcc.dg/vmx/ld-vsx-be-order.c: New test.
* gcc.dg/vmx/ldl.c: New test.
* gcc.dg/vmx/ldl-be-order.c: New test.
* gcc.dg/vmx/ldl-vsx.c: New test.
* gcc.dg/vmx/ldl-vsx-be-order.c: New test.
* gcc.dg/vmx/st.c: New test.
* gcc.dg/vmx/st-be-order.c: New test.
* gcc.dg/vmx/st-vsx.c: New test.
* gcc.dg/vmx/st-vsx-be-order.c: New test.
* gcc.dg/vmx/stl.c: New test.
* gcc.dg/vmx/stl-be-order.c: New test.
* gcc.dg/vmx/stl-vsx.c: New test.
* gcc.dg/vmx/stl-vsx-be-order.c: New test.
Backport from mainline 208021
2014-02-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* gcc.dg/vmx/vsums.c: Check entire result vector.
* gcc.dg/vmx/vsums-be-order.c: Likewise.
Backport from mainline 208049
2014-02-23 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* gcc.dg/vmx/lde.c: New test.
* gcc.dg/vmx/lde-be-order.c: New test.
* gcc.dg/vmx/ste.c: New test.
* gcc.dg/vmx/ste-be-order.c: New test.
Backport from mainline 208120
2014-02-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Bill Schmidt [Fri, 4 Apr 2014 14:44:21 +0000 (14:44 +0000)]
backport: rs6000.opt (-mlra): Add switch to enable the LRA register allocator.
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline
2014-02-04 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.opt (-mlra): Add switch to enable the LRA
register allocator.
* config/rs6000/rs6000.c (TARGET_LRA_P): Add support for -mlra to
enable the LRA register allocator. Back port the changes from the
trunk to enable LRA.
(rs6000_legitimate_offset_address_p): Likewise.
(legitimate_lo_sum_address_p): Likewise.
(use_toc_relative_ref): Likewise.
(rs6000_legitimate_address_p): Likewise.
(rs6000_emit_move): Likewise.
(rs6000_secondary_memory_needed_mode): Likewise.
(rs6000_alloc_sdmode_stack_slot): Likewise.
(rs6000_lra_p): Likewise.
* config/rs6000/sync.md (load_lockedti): Copy TI/PTI variables by
64-bit parts to force the register allocator to allocate even/odd
register pairs for the quad word atomic instructions.
(store_conditionalti): Likewise.
Bill Schmidt [Fri, 4 Apr 2014 14:42:18 +0000 (14:42 +0000)]
backport: re PR target/59909 (Quad memory bootstrap issues on little endian powerpc64 power8 systems)
[gcc/testsuite]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Back port from mainline
2014-01-23 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/59909
* gcc.target/powerpc/quad-atomic.c: New file to test power8 quad
word atomic functions at runtime.
[gcc]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Back port from mainline
2014-01-23 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/59909
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mquad-memory-atomic. Update -mquad-memory documentation to say
it is only used for non-atomic loads/stores.
* config/rs6000/predicates.md (quad_int_reg_operand): Allow either
-mquad-memory or -mquad-memory-atomic switches.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add
-mquad-memory-atomic to ISA 2.07 support.
* config/rs6000/rs6000.opt (-mquad-memory-atomic): Add new switch
to separate support of normal quad word memory operations (ldq,
stq) from the atomic quad word memory operations.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
support to separate non-atomic quad word operations from atomic
quad word operations. Disable non-atomic quad word operations in
little endian mode so that we don't have to swap words after the
load and before the store.
(quad_load_store_p): Add comment about atomic quad word support.
(rs6000_opt_masks): Add -mquad-memory-atomic to the list of
options printed with -mdebug=reg.
* config/rs6000/rs6000.h (TARGET_SYNC_TI): Use
-mquad-memory-atomic as the test for whether we have quad word
atomic instructions.
(TARGET_SYNC_HI_QI): If either -mquad-memory-atomic,
-mquad-memory, or -mp8-vector are used, allow byte/half-word
atomic operations.
* config/rs6000/sync.md (load_lockedti): Insure that the address
is a proper indexed or indirect address for the lqarx instruction.
On little endian systems, swap the hi/lo registers after the lqarx
instruction.
(load_lockedpti): Use indexed_or_indirect_operand predicate to
insure the address is valid for the lqarx instruction.
(store_conditionalti): Insure that the address is a proper indexed
or indirect address for the stqcrx. instruction. On little endian
systems, swap the hi/lo registers before doing the stqcrx.
instruction.
(store_conditionalpti): Use indexed_or_indirect_operand predicate to
insure the address is valid for the stqcrx. instruction.
* gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros):
Define __QUAD_MEMORY__ and __QUAD_MEMORY_ATOMIC__ based on what
type of quad memory support is available.
Bill Schmidt [Fri, 4 Apr 2014 14:39:26 +0000 (14:39 +0000)]
Apply mainline r202190, powerpc64le multilibs and multiarch dir 2013-09-03 Alan Modra <amodra@gmail.com>
[gcc]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Apply mainline r202190, powerpc64le multilibs and multiarch dir
2013-09-03 Alan Modra <amodra@gmail.com>
* config.gcc (powerpc*-*-linux*): Add support for little-endian
multilibs to big-endian target and vice versa.
* config/rs6000/t-linux64: Use := assignment on all vars.
(MULTILIB_EXTRA_OPTS): Remove fPIC.
(MULTILIB_OSDIRNAMES): Specify using mapping from multilib_options.
* config/rs6000/t-linux64le: New file.
* config/rs6000/t-linux64bele: New file.
* config/rs6000/t-linux64lebe: New file.
[libsanitizer]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline r208290
2014-03-03 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* configure.tgt: Unsupported for little endian PowerPC for now.
Bill Schmidt [Fri, 4 Apr 2014 14:29:23 +0000 (14:29 +0000)]
backport: re PR target/56843 (PowerPC Newton-Raphson reciprocal estimates can be improved)
[gcc]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline
2013-04-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR target/56843
* config/rs6000/rs6000.c (rs6000_emit_swdiv_high_precision): Remove.
(rs6000_emit_swdiv_low_precision): Remove.
(rs6000_emit_swdiv): Rewrite to handle between one and four
iterations of Newton-Raphson generally; modify required number of
iterations for some cases.
* config/rs6000/rs6000.h (RS6000_RECIP_HIGH_PRECISION_P): Remove.
[gcc/testsuite]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline
2013-04-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Bill Schmidt [Fri, 4 Apr 2014 14:20:31 +0000 (14:20 +0000)]
[multiple changes]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Apply mainline r205060.
2013-11-20 Alan Modra <amodra@gmail.com>
* config/rs6000/sysv4.h (CC1_ENDIAN_LITTLE_SPEC): Define as empty.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Default
to strict alignment on older processors when little-endian.
* config/rs6000/linux64.h (PROCESSOR_DEFAULT64): Default to power8
for ELFv2.
projects / thirdparty / gcc.git / log
