PR c++/30044
* pt.c (begin_template_parm_list): Add a dummy parameter level
to current_template_parms.
(end_template_parm_list): Remove the dummy parameter level
before adding the real one.
(tsubst): Don't attempt to substitute for template parameters
corresponding to a dummy argument level.
(template_parms_to_args): Remove obsolete hack for
giving template template arguments the proper level.
(splite_late_return_type): Remove obsolete hack for giving
template template arguments the proper level.
* error.c (dump_template_decl): Don't print dummy template
levels.
gcc/testsuite/ChangeLog
PR c++/30044
* g++.dg/cpp0x/auto46.C: New test.
* g++.dg/template/pr30044.C: New test.
* g++.dg/template/shadow2.C: New test.
* g++.dg/template/error55.C: New test.
* g++.dg/template/crash83.C: Accept any error string.
* g++.dg/cpp0x/variadic18.C: Adjust to avoid shadowing template
parameters.
* g++.dg/cpp0x/variadic18.C: Likewise
* g++.dg/template/canon-type-13.C: Likewise.
* g++.old-deja/g++.pt/ttp42.C: Likewise.
* g++.dg/torture/20070621-1.C: Likewise.
Indirect sibcall with register arguments is OK when there is register
available for argument passing.
gcc/
PR target/66819
* config/i386/i386.c (ix86_function_ok_for_sibcall): Allow
indirect sibcall with register arguments if register available
for argument passing.
(init_cumulative_args): Set cfun->machine->arg_reg_available
to (cum->nregs > 0) or to true if function has a variable
argument list.
(function_arg_advance_32): Set cfun->machine->arg_reg_available
to false if cum->nregs <= 0.
* config/i386/i386.h (machine_function): Add arg_reg_available.
* config/i386/sse.md (movdi_to_sse): Use gen_lowpart
and gen_higpart instead of gen_rtx_SUBREG.
* config/i386/i386.md
(floatdi<X87MODEF:mode>2_i387_with_xmm splitter): Ditto.
(read-modify peephole2): Use gen_lowpart instead of
gen_rtx_SUBREG for operand 5.
PR target/66703
* gcc.target/i386/readeflags-1.c (readeflags_test): Declare with
__attribute__((noinline, noclone)). Change "x" to "volatile char"
type to prevent possible flag-clobbering zero-extensions.
* config/tilepro/gen-mul-tables.cc (main): Change include list for
generated files.
* config/tilepro/mul-tables.c: Regenerate.
* config/tilegx/mul-tables.c: Regenerate.
* fold-const.c (distribute_bit_expr): Remove.
(fold_binary_loc): Move simplifying (A & C1) + (B & C2)
to (A & C1) | (B & C2), distributing (A & B) | (A & C)
to A & (B | C) and simplifying A << C1 << C2 to ...
* match.pd: ... patterns here.
jakub [Fri, 10 Jul 2015 10:26:19 +0000 (10:26 +0000)]
PR middle-end/66820
* gimplify.c (maybe_fold_stmt): Don't fold in ORT_PARALLEL
or ORT_TASK contexts.
* omp-low.c (lower_omp): Call fold_stmt even if taskreg_nesting_level
is non-zero.
* tree-if-conv.c (if_convertible_gimple_assign_stmt_p):
Use ifcvt_could_trap_p also when not flag_tree_loop_if_convert_stores.
(if_convertible_loop_p_1): For this always compute bb predicates.
(if_convertible_loop_p): And free them.
jakub [Thu, 9 Jul 2015 21:14:11 +0000 (21:14 +0000)]
PR middle-end/66633
* tree-nested.c (get_static_chain): Or in a flag into
info->static_chain_added.
(get_frame_field, get_nonlocal_debug_decl): Likewise.
(convert_nonlocal_omp_clauses, convert_local_omp_clauses): Revert
2015-07-01 changes.
(convert_tramp_reference_stmt): If a frame_decl or chain_decl
is needed newly inside of GIMPLE_OMP_{PARALLEL,TASK,TARGET} body,
add it to clauses.
* gcc.dg/gomp/pr66633-1.c: New test.
* gcc.dg/gomp/pr66633-2.c: New test.
* gcc.dg/gomp/pr66633-3.c: New test.
* gcc.dg/gomp/pr66633-4.c: New test.
jakub [Thu, 9 Jul 2015 21:11:28 +0000 (21:11 +0000)]
PR tree-optimization/66718
* tree-vect-stmts.c (struct simd_call_arg_info): Add simd_lane_linear
field.
(vect_simd_lane_linear): New function.
(vectorizable_simd_clone_call): Support using linear arguments for
addresses of arrays elements indexed by GOMP_SIMD_LANE result.
2015-07-09 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-protos.h (rs6000_secondary_reload_memory):
Use machine mode, not enum machine_mode in the prototype.
* config/rs6000/rs6000.h (FLOAT128_IEEE_P): New helper macros to
classify 128-bit floating point support.
(FLOAT128_IBM_P): Likewise.
(FLOAT128_VECTOR_P): Likewise.
(FLOAT128_2REG_P): Likewise.
(SCALAR_FLOAT_MODE_NOT_VECTOR_P): Likewise.
(SLOW_UNALIGNED_ACCESS): Add IEEE 128-bit floating point support.
(HARD_REGNO_CALLER_SAVE_MODE): Likewise.
(HARD_REGNO_CALL_PART_CLOBBERED): Likewise.
* config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Drop
tests against TFmode/TDmode, since those modes do not use VSX
addresses.
(rs6000_hard_regno_mode_ok): Add IEEE 128-bit floating point
support.
(rs6000_init_hard_regno_mode_ok): Use new helper macros instead of
tests against TFmode, etc.
(invalid_e500_subreg): Add tests against IFmode/KFmode.
(reg_offset_addressing_ok_p): Likewise.
(rs6000_legitimate_offset_address_p): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_legitimize_reload_address): Likewise.
(rs6000_legitimate_address_p): Clean up tests against TFmode and
TDmode to use the new helper macros, which will include IFmode and
KFmode.
(rs6000_emit_move): Likewise.
(rs6000_darwin64_record_arg_recurse): Likewise.
(print_operand): Likewise.
(rs6000_member_type_forces_blk): Treat IEEE 128-bit floating point
that uses a single vector register as a vector and not as a
floating point register in terms of the calling sequence.
(rs6000_discover_homogeneous_aggregate): Likewise.
(rs6000_return_in_memory): Likewise.
(init_cumulative_args): Likewise.
(rs6000_function_arg_boundary): Likewise.
(rs6000_function_arg_advance_1): Likewise.
(rs6000_function_arg): Likewise.
(rs6000_pass_by_reference): Likewise.
(rs6000_gimplify_va_arg): Likewise.
(rs6000_secondary_reload_memory): Use machine_mode not enum
machine mode.
(rs6000_split_multireg_move): Use new helper macros.
(spe_func_has_64bit_regs_p): Likewise.
(rs6000_output_function_epilogue): Add IFmode/KFmode support.
(output_toc): Use new helper macros.
(rs6000_register_move_cost): Likewise.
(rs6000_function_value): Add IEEE 128-bit floating point calling
sequence support.
(rs6000_libcall_value): Likewise.
(rs6000_scalar_mode_supported_p): Add support for IEEE 128-bit
floating point support.
(rs6000_vector_mode_supported_p): Likewise.
2015-07-09 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-protos.h (rs6000_secondary_reload_memory):
Use machine mode, not enum machine_mode in the prototype.
* config/rs6000/rs6000.h (FLOAT128_IEEE_P): New helper macros to
classify 128-bit floating point support.
(FLOAT128_IBM_P): Likewise.
(FLOAT128_VECTOR_P): Likewise.
(FLOAT128_2REG_P): Likewise.
(SCALAR_FLOAT_MODE_NOT_VECTOR_P): Likewise.
(SLOW_UNALIGNED_ACCESS): Add IEEE 128-bit floating point support.
(HARD_REGNO_CALLER_SAVE_MODE): Likewise.
(HARD_REGNO_CALL_PART_CLOBBERED): Likewise.
* config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Drop
tests against TFmode/TDmode, since those modes do not use VSX
addresses.
(rs6000_hard_regno_mode_ok): Add IEEE 128-bit floating point
support.
(rs6000_init_hard_regno_mode_ok): Use new helper macros instead of
tests against TFmode, etc.
(invalid_e500_subreg): Add tests against IFmode/KFmode.
(reg_offset_addressing_ok_p): Likewise.
(rs6000_legitimate_offset_address_p): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_legitimize_reload_address): Likewise.
(rs6000_legitimate_address_p): Clean up tests against TFmode and
TDmode to use the new helper macros, which will include IFmode and
KFmode.
(rs6000_emit_move): Likewise.
(rs6000_darwin64_record_arg_recurse): Likewise.
(print_operand): Likewise.
(rs6000_member_type_forces_blk): Treat IEEE 128-bit floating point
that uses a single vector register as a vector and not as a
floating point register in terms of the calling sequence.
(rs6000_discover_homogeneous_aggregate): Likewise.
(rs6000_return_in_memory): Likewise.
(init_cumulative_args): Likewise.
(rs6000_function_arg_boundary): Likewise.
(rs6000_function_arg_advance_1): Likewise.
(rs6000_function_arg): Likewise.
(rs6000_pass_by_reference): Likewise.
(rs6000_gimplify_va_arg): Likewise.
(rs6000_secondary_reload_memory): Use machine_mode not enum
machine mode.
(rs6000_split_multireg_move): Use new helper macros.
(spe_func_has_64bit_regs_p): Likewise.
(rs6000_output_function_epilogue): Add IFmode/KFmode support.
(output_toc): Use new helper macros.
(rs6000_register_move_cost): Likewise.
(rs6000_function_value): Add IEEE 128-bit floating point calling
sequence support.
(rs6000_libcall_value): Likewise.
(rs6000_scalar_mode_supported_p): Add support for IEEE 128-bit
floating point support.
(rs6000_vector_mode_supported_p): Likewise.
PR rtl-optimization/66782
* lra-int.h (struct lra_insn_recog_data): Add comment about
clobbered hard regs for arg_hard_regs.
* lra.c (lra_set_insn_recog_data): Add clobbered hard regs.
* lra-lives.c (process_bb_lives): Process clobbered hard regs.
Add condition for processing used hard regs.
* lra-constraints.c (update_ebb_live_info, inherit_in_ebb):
Process clobbered hard regs.
PR target/66814
* config/i386/predicates.md (nonimmediate_gr_operand): New predicate.
* config/i386/i386.md (not peephole2): Use nonimmediate_gr_operand.
(varous peephole2s): Use {GENERAL,SSE,MMX}_REGNO_P instead of
{GENERAL_SSE_MMX}_REG_P where appropriate.
testsuite/ChangeLog:
PR target/66814
* gcc.target/i386/pr66814.c: New test.
* genmatch.c (struct expr): Add force_single_use flag.
(expr::expr): Add copy constructor.
(capture_info::walk_match): Gather force_single_use captures.
(expr::gen_transform): Use possibly NULLified sequence.
(dt_simplify::gen): Apply single-use restrictions by NULLifying
seq if any constrained expr is not single-use.
(parser::parse_expr): Refactor to allow multiple flags. Handle
's' flag to force an expression have a single-use if the pattern
simplifies to more than one statement.
* match.pd: Convert most single_use conditionals to :s flags.
* combine.c (do_SUBST_MODE): Don't check the value of HAVE_cc0
with the preprocessor.
(combine_instructions): Likewise.
(try_combine): Likewise.
(subst): Likewise.
(distribute_notes): Likewise.
Provide a default in files where that is possible, so that everything
else there can be unconditionally compiled. However rtlanal.c and
reload.c do tricky things that break providing a global default, so we
can't do that yet.
* g++.dg/vect/vect.exp: Run also simd* tests.
* gcc.dg/vect/tree-vect.h (abort, exit): For C++ use extern "C".
(check_vect): Fix up get_cpuid call for C++.
* g++.dg/vect/simd-clone-1.cc: New test.
On x86, the "long double" type is platforma specific, which may be the
same as double or __float128. Since pr37870.c requires 80-bit floating
point type, it should be compiled with -mlong-double-80.
Vectors should be passed in memory for IAMCU. No warning for vector ABI
change for IAMCU since IAMCU ABI won't change.
gcc/
PR target/66806
* config/i386/i386.c (type_natural_mode): Don't warn vector ABI
change for IAMCU.
(function_arg_advance_32): Don't pass vectors in registers for
IAMCU.
(function_arg_32): Likewise.
(ix86_return_in_memory): Don't return vectors in registers for
IAMCU.
gcc/testsuite/
PR target/66806
* gcc.target/i386/pr66806.c: New test.
libtool: compile: [...]/build-gcc/./gcc/xg++ [...] -c [...]/source-gcc/liboffloadmic/plugin/libgomp-plugin-intelmic.cpp [...]
In file included from [...]/source-gcc/liboffloadmic/plugin/libgomp-plugin-intelmic.cpp:40:0:
[...]/install/offload-x86_64-intelmicemul-linux-gnu/lib/gcc/x86_64-intelmicemul-linux-gnu/6.0.0/include/main_target_image.h:8628:1: error: narrowing conversion of '192' from 'int' to 'char' inside { } [-Wnarrowing]
};
^
[...]/install/offload-x86_64-intelmicemul-linux-gnu/lib/gcc/x86_64-intelmicemul-linux-gnu/6.0.0/include/main_target_image.h:8628:1: error: narrowing conversion of '192' from 'int' to 'char' inside { } [-Wnarrowing]
[...]/install/offload-x86_64-intelmicemul-linux-gnu/lib/gcc/x86_64-intelmicemul-linux-gnu/6.0.0/include/main_target_image.h:8628:1: error: narrowing conversion of '164' from 'int' to 'char' inside { } [-Wnarrowing]
[many more]
liboffloadmic/
* plugin/Makefile.am (main_target_image.h): Change type of data
member in struct MainTargetImage to uint8_t.
* plugin/Makefile.in: Regenerate.
PR middle-end/66334
* ira-lives.c (process_bb_node_lives): Make conflicts with PIC
hard regno live at the start of BB with incoming abnormal edges.
* lra-lives.c (process_bb_lives): Ditto.
[nvptx offloading] Only 64-bit configurations are currently supported
PR libgomp/65099
gcc/
* config/nvptx/mkoffload.c (main): Create an offload image only in
64-bit configurations.
libgomp/
* plugin/plugin-nvptx.c (nvptx_get_num_devices): Return 0 if not
in a 64-bit configuration.
* testsuite/libgomp.oacc-c++/c++.exp: Don't attempt nvidia
offloading testing if no such device is available.
* testsuite/libgomp.oacc-c/c.exp: Likewise.
* testsuite/libgomp.oacc-fortran/fortran.exp: Likewise.
gcc/jit/ChangeLog:
PR jit/66783
* libgccjit.c (gcc_jit_context_new_field): Show name of field in
"unknown size" error message.
(gcc_jit_struct_set_fields): Show name of struct in error message.
(gcc_jit_context_new_global): Show name of global in
"unknown size" error message.
(gcc_jit_function_new_local): Likewise for local.
MIPS: Fix failing branch range checks for micromips.
The current branch range tests assume that the MIPS branch instructions
have a 16 bit branch offset which is shifted by 2. Unfortunately for microMIPS
this offset is shifted by 1 which reduces the branch range and caused the
branch-*.c tests to fail.
testsuite/
* gcc.target/mips/branch-2.c: Change NOMIPS16 to NOCOMPRESSION.
* gcc.target/mips/branch-3.c: Ditto
* gcc.target/mips/branch-4.c: Ditto.
* gcc.target/mips/branch-5.c: Ditto.
* gcc.target/mips/branch-6.c: Ditto.
* gcc.target/mips/branch-7.c: Ditto.
* gcc.target/mips/branch-8.c: Ditto.
* gcc.target/mips/branch-9.c: Ditto.
* gcc.target/mips/branch-10.c: Ditto.
* gcc.target/mips/branch-11.c: Ditto.
* gcc.target/mips/branch-12.c: Ditto.
* gcc.target/mips/branch-13.c: Ditto.
* gcc.target/mips/umips-branch-5.c: New file.
* gcc.target/mips/umips-branch-6.c: New file.
* gcc.target/mips/umips-branch-7.c: New file.
* gcc.target/mips/umips-branch-8.c: New file.
* gcc.target/mips/umips-branch-9.c: New file.
* gcc.target/mips/umips-branch-10.c: New file.
* gcc.target/mips/umips-branch-11.c: New file.
* gcc.target/mips/umips-branch-12.c: New file.
* gcc.target/mips/umips-branch-13.c: New file.
* gcc.target/mips/umips-branch-14.c: New file.
* gcc.target/mips/umips-branch-15.c: New file.
* gcc.target/mips/umips-branch-16.c: New file.
* gcc.target/mips/branch-helper.h (OCCUPY_0x10000): New define.
(OCCUPY_0xfffc): New define.
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