Max Krummenacher [Tue, 11 Nov 2025 15:16:14 +0000 (16:16 +0100)]
arm64: dts: freescale: add Toradex SMARC iMX95
Add DT support for Toradex SMARC iMX95 SoM and Development carrier
board.
The module consists of an NXP i.MX95 family SoC, up to 16GB of LPDDR5
RAM and up to 128GB of storage, a USB 3.0 Host Hub and 2.0 OTG, two
Gigabit Ethernet PHYs, a 10 Gigabit Ethernet interface, an I2C EEPROM
and Temperature Sensor, an RX8130 RTC, a Quad/Dual lane CSI interface,
and some optional addons: TPM 2.0, DSI, LVDS, DisplayPort (through a
DSI-DP bridge), and Wi-Fi/BT module.
Link: https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95 Link: https://www.toradex.com/products/carrier-board/smarc-development-board-kit Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Co-developed-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com> Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com> Co-developed-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Co-developed-by: João Paulo Gonçalves <joao.goncalves@toradex.com> Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com> Co-developed-by: Vitor Soares <vitor.soares@toradex.com> Signed-off-by: Vitor Soares <vitor.soares@toradex.com> Co-developed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arm64: dts: imx8mp: make 'dsp' node depend on 'aips5'
The DSP needs to access peripherals on AIPSTZ5 (to communicate with
the AP using AUDIOMIX MU, for instance). To do so, the security-related
registers of the bridge have to be configured before the DSP is started.
Enforce a dependency on AIPSTZ5 by adding the 'access-controllers'
property to the 'dsp' node.
Change the programming model of the "aips5" node to allow configuring
the security-related registers exposed by the AIPSTZ5 bridge. Without
this, masters such as the HIFI4 DSP will have their access to the
peripherals connected to the bridge denied after power cycling the
AUDIOMIX domain.
Co-developed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marco Felsch [Fri, 7 Nov 2025 14:49:52 +0000 (15:49 +0100)]
arm64: dts: imx8mp-skov: add Rev.C HDMI support
From software perspective, Rev.C HDMI and Rev.B HDMI don't differ since
the panel is connected via HDMI and the touchscreen is connected via
USB. However, the bootloader firmware expects to find a dts with the
correct revc-hdmi compatible.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marek Vasut [Tue, 4 Nov 2025 01:50:13 +0000 (02:50 +0100)]
arm64: dts: imx8mp: Add missing LED enumerators for DH electronics i.MX8M Plus DHCOM on PDK2
The LED enumerators are missing, which prevents the LEDs from being
accurately told apart by label. Fill in the enumerators the same way
they are already present on PDK3.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Stefano Radaelli [Thu, 30 Oct 2025 12:01:24 +0000 (13:01 +0100)]
arm64: dts: freescale: imx93-var-som: Add support for ADS7846 touchscreen
The VAR-SOM-MX93 integrates an ADS7846 resistive touchscreen controller.
The controller is physically located on the SOM, and its signals are
routed to the SOM pins, allowing carrier boards to make use of it.
This patch adds the ADS7846 node and the appropriate SPI controller.
Stefano Radaelli [Thu, 30 Oct 2025 12:01:23 +0000 (13:01 +0100)]
arm64: dts: freescale: imx93-var-som: Add support for WM8904 audio codec
The VAR-SOM-MX93 can integrate the WM8904, a high-performance
ultra-low-power stereo codec optimized for portable audio applications.
This patch adds the WM8904 device to the appropriate I2C bus, enables
the SAI peripheral, and introduces the sound node to expose the
sound card to the system.
Stefano Radaelli [Thu, 30 Oct 2025 12:01:22 +0000 (13:01 +0100)]
arm64: dts: freescale: imx93-var-som: Add PMIC support
The VAR-SOM-MX93 features Dual Freescale/NXP PCA9541 chip as a Power
Management Integrated circuit (PMIC).
The PMIC is programmable via the I2C interface and its associated
register map, and this patch adds its support.
Stefano Radaelli [Thu, 30 Oct 2025 12:01:21 +0000 (13:01 +0100)]
arm64: dts: freescale: imx93-var-som: Add WiFi and Bluetooth support
Add device tree nodes for the WiFi and Bluetooth module mounted on the
VAR-SOM-MX93. The module can be based on either the NXP IW612 or IW611
chipset, depending on the configuration chosen by the customer.
Regardless of the chipset used, WiFi communicates over SDIO and Bluetooth
over UART.
Add overlay to support PWM fan on the phyBOARD-Nash-i.MX93 board. Fan
can be connected to the FAN (X48) connector on the board and will be
controlled according to the following CPU temperature trips table:
- bellow 50 degrees - fan is off (<1% duty cycle)
- between 50 and 58 degrees - low fan speed (~35% duty cycle)
- between 58 and 65 degrees - fan medium speed (~60% duty cycle)
- above 65 degrees - fan at full speed (>99% duty cycle)
The output frequency of PWM signal is set to 25 kHz.
The PEB-AV-10 board can be used with different displays or in audio-only
mode.
Split the device tree overlays to reflect these use cases. To use the
board with the EDT ETML1010G3DRA display, the overlay
imx8mm-phyboard-polis-peb-av-10-etml1010g3dra.dtbo must now be used
instead of imx8mm-phyboard-polis-peb-av-10.dtbo.
Signed-off-by: Jan Remmet <j.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Shengjiu Wang [Tue, 23 Sep 2025 05:30:01 +0000 (13:30 +0800)]
arm64: dts: imx8mp-evk: enable hdmi_pai device
Enable hdmi_pai device.
Aud2htx module, hdmi_pai and hdmi controller compose the hdmi audio
pipeline.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The HDMI TX Parallel Audio Interface (HTX_PAI) is a bridge between the
Audio Subsystem to the HDMI TX Controller.
Shrink register map size of hdmi_pvi to avoid overlapped hdmi_pai device.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Fri, 24 Oct 2025 07:31:52 +0000 (15:31 +0800)]
arm64: dts: imx95-19x19-evk: Add vpcie3v3aux regulator for PCIe[0,1]
Refer to PCI Express M.2 Specification r5.1 sec3.1.1 Power Sources and
Grounds.
PCI Express M.2 Socket 1 utilizes a 3.3 V power source. The voltage
source, 3.3 V, is expected to be available during the system’s
stand-by/suspend state to support wake event processing on the
communications card.
Add vpcie3v3aux regulator to let this 3.3 V power source always on for
PCIe M.2 Key E connector(PCIe0) on i.MX95 19x19 EVK board.
PCIe1 uses one standard PCIe slot connector, but combines the +3.3v and
+3.3Vaux into a same 3.3v power source, and intends to let it always on.
Add vpcie3v3aux regulator to let this 3.3 V power source always on for
PCIe1 on i.MX95 19x19 EVK board too.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Fri, 24 Oct 2025 07:31:51 +0000 (15:31 +0800)]
arm64: dts: imx95-15x15-evk: Add vpcie3v3aux regulator for PCIe M.2 connector
Refer to PCI Express M.2 Specification r5.1 sec3.1.1 Power Sources and
Grounds.
PCI Express M.2 Socket 1 utilizes a 3.3 V power source. The voltage
source, 3.3 V, is expected to be available during the system’s
stand-by/suspend state to support wake event processing on the
communications card.
Add vpcie3v3aux regulator to let this 3.3 V power source always on for
PCIe M.2 Key E connector on i.MX95 15x15 EVK board.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Fri, 24 Oct 2025 07:31:50 +0000 (15:31 +0800)]
arm64: dts: imx8qxp-mek: Add vpcie3v3aux regulator for PCIe M.2 connector
Refer to PCI Express M.2 Specification r5.1 sec3.1.1 Power Sources and
Grounds.
PCI Express M.2 Socket 1 utilizes a 3.3 V power source. The voltage
source, 3.3 V, is expected to be available during the system’s
stand-by/suspend state to support wake event processing on the
communications card.
Add vpcie3v3aux regulator to let this 3.3 V power source always on for
PCIe M.2 Key E connector on i.MX8QXP MEK board.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Fri, 24 Oct 2025 07:31:49 +0000 (15:31 +0800)]
arm64: dts: imx8qm-mek: Add vpcie3v3aux regulator for PCIe M.2 connector
Refer to PCI Express M.2 Specification r5.1 sec3.1.1 Power Sources and
Grounds.
PCI Express M.2 Socket 1 utilizes a 3.3 V power source. The voltage
source, 3.3 V, is expected to be available during the system’s
stand-by/suspend state to support wake event processing on the
communications card.
Add vpcie3v3aux regulator to let this 3.3 V power source always on for
PCIe M.2 Key E connector on i.MX8QM MEK board.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Fri, 24 Oct 2025 07:31:48 +0000 (15:31 +0800)]
arm64: dts: imx8mq-evk: Add vpcie3v3aux regulator for PCIe M.2 connector
Refer to PCI Express M.2 Specification r5.1 sec3.1.1 Power Sources and
Grounds.
PCI Express M.2 Socket 1 utilizes a 3.3 V power source. The voltage
source, 3.3 V, is expected to be available during the system’s
stand-by/suspend state to support wake event processing on the
communications card.
Add vpcie3v3aux regulator to let this 3.3 V power source always on for
PCIe M.2 Key E connector on i.MX8MQ EVK board.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Fri, 24 Oct 2025 07:31:47 +0000 (15:31 +0800)]
arm64: dts: imx8mp-evk: Add vpcie3v3aux regulator for PCIe M.2 connector
Refer to PCI Express M.2 Specification r5.1 sec3.1.1 Power Sources and
Grounds.
PCI Express M.2 Socket 1 utilizes a 3.3 V power source. The voltage
source, 3.3 V, is expected to be available during the system’s
stand-by/suspend state to support wake event processing on the
communications card.
Add vpcie3v3aux regulator to let this 3.3 V power source always on for
PCIe M.2 Key E connector on i.MX8MP EVK board.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Fri, 24 Oct 2025 07:31:46 +0000 (15:31 +0800)]
arm64: dts: imx8dxl-evk: Add vpcie3v3aux regulator for PCIe M.2 connector
Refer to PCI Express M.2 Specification r5.1 sec3.1.1 Power Sources and
Grounds.
PCI Express M.2 Socket 1 utilizes a 3.3 V power source. The voltage
source, 3.3 V, is expected to be available during the system’s
stand-by/suspend state to support wake event processing on the
communications card.
Add vpcie3v3aux regulator to let this 3.3 V power source always on for
PCIe M.2 Key E connector on i.MX8DXL EVK board.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Wed, 15 Oct 2025 03:04:24 +0000 (11:04 +0800)]
arm64: dts: imx8qxp-mek: Add supports-clkreq property to PCIe M.2 port
According to PCIe r6.1, sec 5.5.1.
The following rules define how the L1.1 and L1.2 substates are entered:
Both the Upstream and Downstream Ports must monitor the logical state of
the CLKREQ# signal.
Typical implement is using open drain, which connect RC's clkreq# to
EP's clkreq# together and pull up clkreq#.
imx8qxp-mek matches this requirement, so add supports-clkreq to allow
PCIe device enter ASPM L1 Sub-State.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Wed, 15 Oct 2025 03:04:23 +0000 (11:04 +0800)]
arm64: dts: imx8qm-mek: Add supports-clkreq property to PCIe M.2 port
According to PCIe r6.1, sec 5.5.1.
The following rules define how the L1.1 and L1.2 substates are entered:
Both the Upstream and Downstream Ports must monitor the logical state of
the CLKREQ# signal.
Typical implement is using open drain, which connect RC's clkreq# to
EP's clkreq# together and pull up clkreq#.
imx8qm-mek matches this requirement, so add supports-clkreq to allow
PCIe device enter ASPM L1 Sub-State.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Wed, 15 Oct 2025 03:04:22 +0000 (11:04 +0800)]
arm64: dts: imx8mq-evk: Add supports-clkreq property to PCIe M.2 port
According to PCIe r6.1, sec 5.5.1.
The following rules define how the L1.1 and L1.2 substates are entered:
Both the Upstream and Downstream Ports must monitor the logical state of
the CLKREQ# signal.
Typical implement is using open drain, which connect RC's clkreq# to
EP's clkreq# together and pull up clkreq#.
imx8mq-evk matches this requirement, so add supports-clkreq to allow
PCIe device enter ASPM L1 Sub-State.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Wed, 15 Oct 2025 03:04:21 +0000 (11:04 +0800)]
arm64: dts: imx8mp-evk: Add supports-clkreq property to PCIe M.2 port
According to PCIe r6.1, sec 5.5.1.
The following rules define how the L1.1 and L1.2 substates are entered:
Both the Upstream and Downstream Ports must monitor the logical state of
the CLKREQ# signal.
Typical implement is using open drain, which connect RC's clkreq# to
EP's clkreq# together and pull up clkreq#.
imx8mp-evk matches this requirement, so add supports-clkreq to allow
PCIe device enter ASPM L1 Sub-State.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Wed, 15 Oct 2025 03:04:20 +0000 (11:04 +0800)]
arm64: dts: imx8mm-evk: Add supports-clkreq property to PCIe M.2 port
According to PCIe r6.1, sec 5.5.1.
The following rules define how the L1.1 and L1.2 substates are entered:
Both the Upstream and Downstream Ports must monitor the logical state of
the CLKREQ# signal.
Typical implement is using open drain, which connect RC's clkreq# to
EP's clkreq# together and pull up clkreq#.
imx8mm-evk matches this requirement, so add supports-clkreq to allow
PCIe device enter ASPM L1 Sub-State.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Wed, 15 Oct 2025 03:04:19 +0000 (11:04 +0800)]
arm64: dts: imx95-19x19-evk: Add supports-clkreq property to PCIe M.2 port
According to PCIe r6.1, sec 5.5.1.
The following rules define how the L1.1 and L1.2 substates are entered:
Both the Upstream and Downstream Ports must monitor the logical state of
the CLKREQ# signal.
Typical implement is using open drain, which connect RC's clkreq# to
EP's clkreq# together and pull up clkreq#.
imx95-19x19-evk matches this requirement, so add supports-clkreq to
allow PCIe device enter ASPM L1 Sub-State.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Richard Zhu [Wed, 15 Oct 2025 03:04:18 +0000 (11:04 +0800)]
arm64: dts: imx95-15x15-evk: Add supports-clkreq property to PCIe M.2 port
According to PCIe r6.1, sec 5.5.1.
The following rules define how the L1.1 and L1.2 substates are entered:
Both the Upstream and Downstream Ports must monitor the logical state of
the CLKREQ# signal.
Typical implement is using open drain, which connect RC's clkreq# to
EP's clkreq# together and pull up clkreq#.
imx95-15x15-evk matches this requirement, so add supports-clkreq to
allow PCIe device enter ASPM L1 Sub-State.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Frank Li [Wed, 22 Oct 2025 20:43:21 +0000 (16:43 -0400)]
arm64: dts: imx8: add vdd-supply and vddio-supply for fsl,mpl3115
Add vdd-supply and vddio-supply for fsl,mpl3115 to fix CHECK_DTBS warning:
arch/arm64/boot/dts/freescale/imx8qm-mek.dtb: pressure-sensor@60 (fsl,mpl3115): 'vdd-supply' is a required property
from schema $id: http://devicetree.org/schemas/iio/pressure/fsl,mpl3115.yaml#
Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Frank Li [Mon, 29 Sep 2025 14:24:17 +0000 (10:24 -0400)]
arm64: dts: layerscape: add dma-coherent for usb node
Add SOC special compatible string, remove fallback snps,dwc3 to let flatten
dwc3-layerscape driver to be probed and enable dma-coherence for usb node
since commit add layerscape dwc3 support, which set correct gsbustcfg0
value.
Add iommus property to run at old uboot, which use fixup add iommus by
check compatible string snsp,dwc3 compatible string.
Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Yannic Moog [Mon, 20 Oct 2025 12:49:27 +0000 (14:49 +0200)]
arm64: dts: imx8mp pollux: add displays for expansion board
The same displays that can be connected directly to the
imx8mp-phyboard-pollux can also be connected to the expansion board
PEB-AV-10. For displays connected to the expansion board, a second LVDS
channel of the i.MX 8M Plus SoC is used and only a single display
connected to the SoC LVDS display bridge at a given time is supported.
An expansion board (PEB-AV-10) may be connected to the
imx8mp-phyboard-pollux. Its main purpose is to provide multimedia
interfaces, featuring a 3.5mm headphone jack, a USB-A port and LVDS as
well as backlight connectors.
Introduce the expansion board as dtsi, as it may be used standalone as
an expansion board, as well as in combination with display panels. These
display panels will include the dtsi.
Yannic Moog [Mon, 20 Oct 2025 12:49:25 +0000 (14:49 +0200)]
arm64: dts: imx8mp pollux: add display overlays
imx8mp-phyboard-pollux had a display baked into its board dts file.
However this approach does not truly discribe the hardware and is not
suitable when using different displays.
Move display specific description into an overlay and add the successor
display for the phyboard-pollux as an additional overlay.
Ioana Ciornei [Tue, 14 Oct 2025 15:53:56 +0000 (18:53 +0300)]
arm64: dts: ls1046a-qds: describe the FPGA based GPIO controller
The QIXIS FPGA node is extended so that it describes the GPIO controller
responsible for all the status presence lines on both SFP+ cages as well
as the IO SLOTs present on the board.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Ioana Ciornei [Tue, 14 Oct 2025 15:53:55 +0000 (18:53 +0300)]
arm64: dts: lx2160a-rdb: describe the QIXIS FPGA and two child GPIO controllers
Describe the FPGA present on the LX2160ARDB board as a simple-mfd I2C
device. The FPGA presents registers that deal with power-on-reset
timing, muxing, SFP cage monitoring and control etc.
Also add the two GPIO controllers responsible for monitoring and
controlling the SFP+ cages used for MAC5 and MAC6.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Jonas Rebmann [Tue, 14 Oct 2025 13:09:32 +0000 (15:09 +0200)]
arm64: dts: add Protonic PRT8ML board
Add devicetree for the Protonic PRT8ML.
The board is similar to the Protonic PRT8MM but i.MX8MP based.
Some features have been removed as the drivers haven't been mainlined
yet or other issues where encountered:
- Stepper motors to be controlled using motion control subsystem
- MIPI/DSI to eDP USB alt-mode
- Onboard T1 ethernet (10BASE-T1L+PoDL, 100BASE-T1+PoDL, 1000BASE-T1)
Signed-off-by: David Jander <david@protonic.nl> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Jonas Rebmann <jre@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
projects / thirdparty / kernel / linux.git / log
