Jani Nikula [Tue, 6 May 2025 13:06:49 +0000 (16:06 +0300)]
drm/i915/rps: refactor display rps support
Make the gt rps code and display irq code interact via
intel_display_rps.[ch], instead of direct access. Add no-op static
inline stubs for xe instead of having a separate build unit doing
nothing. All of this clarifies the interfaces between i915 core and
display.
All users of vlv_display_irq_postinstall() outside of
intel_display_irq.c have a lock/unlock pair. Move the locking inside the
function. Add an unlocked variant for internal use, similar to the
_vlv_display_irq_reset() and vlv_display_irq_reset() functions.
As per the WA, fbc stride need to be programmed always for bmg.
Display driver handles the need to program the fbc stride using
the override stride. So ensure that we always get the override
stride in case of bmg
Jani Nikula [Thu, 24 Apr 2025 20:01:41 +0000 (23:01 +0300)]
drm/i915/hdcp: pass struct drm_device to driver specific HDCP GSC code
The driver specific HDCP GSC code will eventually be part of the driver
cores rather than display. Remove the struct intel_display references
from them, and pass struct drm_device instead.
Jani Nikula [Thu, 24 Apr 2025 20:01:38 +0000 (23:01 +0300)]
drm/i915/hdcp: pass the context to the HDCP GSC message interface
The opaque HDCP GSC context nicely abstracts the differences between
drivers. Pass that instead of struct drm_i915_private or struct
xe_device to intel_hdcp_gsc_msg_send(). We can store the driver specific
data in the context.
This lets us drop the dependency on i915_drv.h from
intel_hdcp_gsc_message.c.
Allocate and initialize the HDCP GSC message in
intel_hdcp_gsc_hdcp2_init() as before, but store the pointer to
display->hdcp.hdcp_message in the caller. Similarly, pass in the pointer
to intel_hdcp_gsc_free_message().
Jani Nikula [Thu, 24 Apr 2025 20:01:34 +0000 (23:01 +0300)]
drm/i915/hdcp: deduplicate and refactor HDCP GSC ops initialization
The gsc_hdcp_ops is duplicated and initialized exactly the same way in
two different places (for i915 and xe), and requires forward
declarations for all the hooks. Deduplicate, and make the functions
static.
There are slight differences in the i915 and xe implementations of
intel_hdcp_gsc_init() and intel_hdcp_gsc_fini(). Take the best of both,
and improve.
We need to expose intel_hdcp_gsc_hdcp2_init() and
intel_hdcp_gsc_free_message() for this, and create the latter for xe.
Jani Nikula [Tue, 29 Apr 2025 11:50:55 +0000 (14:50 +0300)]
drm/i915/error: drop dmesg suggestion to file bugs on GPU hangs
We haven't updated the DRIVER_TIMESTAMP since commit 3570bd989acc
("drm/i915: Update DRIVER_DATE to 20230929") 1½ years ago. Before then,
the previous update was commit 139caf7ca286 ("drm/i915: Update
DRIVER_DATE to 20201103") 4+ years ago. The DRIVER_DATE has also been
removed altogether.
We've used the DRIVER_TIMESTAMP to log suggestions to file bugs on GPU
hangs when they happen on a driver less than six months old. Combined
with the sporadic DRIVER_TIMESTAMP updates, we really haven't logged the
suggestions for years.
Just stop logging the suggestion to file bugs altogether, and remove
DRIVER_TIMESTAMP. This doesn't really change anything wrt to logging GPU
errors or how we handle bugs. And effectively we already stopped logging
the message a year ago when we stopped updating DRIVER_TIMESTAMP.
Instead, add an unconditional message about the GPU error state
location.
Jani Nikula [Tue, 29 Apr 2025 11:25:34 +0000 (14:25 +0300)]
drm/i915/backlight: drop dmesg suggestion to file bugs
Drop the FDO_BUG_URL from the source, and stop suggesting to file bugs
on DPCD backlight issues. We don't do this anywhere else in display,
this isn't a special snowflake.
As a consequence, also drop the dependency on i915_utils.h from
intel_dp_aux_backlight.c.
drm/i915/display: move min_hblank from dp_mst.c to dp.c
Minimum HBlank is programmed to address jitter for high resolutions with
high refresh rates that have small Hblank, specifically where Hblank is
smaller than one MTP.
TODO: Add the min_hblank calculation for hdmi as well.
v2: move from intel_audio.c to intel_dp.c
some correction in link_bpp_x16 (Imre)
v3: min_hblank for 8b/10b MST and 128b/132b SST/MST
handle error for intel_dp_mst_dsc_get_slice_count
reset min_hblank before disabling transcoder (Imre)
v4: compute link_bpp_x16 within compute_min_hblank,
return error in case of compute failure
call compute_min_hblank() before vrr_compute_config (Imre)
v5: readout MIN_HBLAN reg for Xe3+
drm/display/dp: Export fn to calculate link symbol cycles
Unify the function to calculate the link symbol cycles for both dsc and
non-dsc case and export the function so that it can be used in the
respective platform display drivers for other calculations.
v2: unify the fn for both dsc and non-dsc case (Imre)
v3: rename drm_dp_link_symbol_cycles to drm_dp_link_data_symbol_cycles
retain slice_eoc_cycles as is (Imre)
v4: Expose only drm_dp_link_symbol_cycles() (Imre)
v6: Add slice pixels which was removed unknowingly (Vinod)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250424-hblank-v7-1-8b002f1506cc@intel.com
Jiajia Liu [Wed, 23 Apr 2025 07:37:30 +0000 (15:37 +0800)]
drm/i915/pch: fix warning for coffeelake on SunrisePoint PCH
i915/pch reports a warning on a mini PC which has a CoffeeLake-S GT2
[UHD Graphics 630] [8086:3e92] and an ISA bridge - H110 LPC Controller
[8086:a143].
[5.608723] i915 0000:00:02.0: [drm] Found coffeelake (device ID 3e92) integrated display version 9.00 stepping N/A
[5.608969] ------------[ cut here ]------------
[5.608972] i915 0000:00:02.0: [drm] drm_WARN_ON(!display->platform.skylake && !display->platform.kabylake)
[5.608995] WARNING: CPU: 3 PID: 440 at drivers/gpu/drm/i915/display/intel_pch.c:126 intel_pch_type+0x1af/0xae0 [i915]
[5.609317] CPU: 3 UID: 0 PID: 440 Comm: (udev-worker) Not tainted 6.15.0-rc3-drm-tip-2fa6469c618d #3 PREEMPT(voluntary)
Imre Deak [Mon, 28 Apr 2025 13:47:16 +0000 (16:47 +0300)]
drm/i915/hdmi: Use an intel_connector pointer everywhere
Following the convention, convert intel_hdmi.c to use an intel_connector
pointer everywhere, calling this pointer connector. If the intel
connector must be casted from a drm_connector, call this pointer
_connector and use this pointer only for the casting.
v2: Use for_each_new_intel_connector_in_state(). (Jani)
Imre Deak [Mon, 28 Apr 2025 13:47:15 +0000 (16:47 +0300)]
drm/i915/dp: Use an intel_connector pointer everywhere
Following the convention, convert intel_dp.c to use an intel_connector
pointer everywhere, calling this pointer connector. If the intel
connector must be casted from a drm_connector, call this pointer
_connector and use this pointer only for the casting.
drm/i915/display: Ensure enough lines between delayed VBlank and VBlank
To deterministically capture the transition of the state machine going from
SRDOFFACK to IDLE, the delayed V. Blank should be at least one line after
the non-delayed V. Blank.
Ensure this by adding new interface into intel_psr to query number of lines
needed for vblank delay and call it from intel_crtc_vblank_delay.
v3: use existing intel_crtc_vblank_delay mechanism
v2: apply limits only when needed (VRR TG vs. Legacy TG)
Animesh Manna [Fri, 25 Apr 2025 13:21:07 +0000 (18:51 +0530)]
drm/i915/alpm: Check for alpm support before accessing alpm register
Currently, only EDP supports alpm. So, check for alpm support and prevent
the DP connector from accessing the alpm register if doing so is unsupported.
Currently we disable the VGA plane from various places, sometimes
multiple times in the same init/resume sequence. Get rid of all this
mess and do it just once. The most correct place seems to be just
after intel_early_display_was() as that one applies various workarounds
that need to be in place before we touch any planes (including the
VGA plane).
Actually, we do still have a second caller in
vlv_display_power_well_init(). I think we still need that as the reset
value of VGACNTR is 0x0 and thus technically the VGA plane will be
(at least partially) enabled after the power well has been toggled.
In both cases we have the necessary power reference already held
(INIT power domain for load/resume case, and the display power well
itself being what we need for vlv_display_power_well_init()).
Ville Syrjälä [Thu, 17 Apr 2025 11:44:52 +0000 (14:44 +0300)]
drm/i915/vga: Include the current pipe in the VGA disable debug message
Add some debugs to the VGA plane disable so that we can at least
see from the logs when it happens (and on which pipe). I was curious
about this at some point when I was seeing some random underruns
near the time when we disable the VGA plane, but I think in the end
that turned out to be a red herring.
Ville Syrjälä [Thu, 17 Apr 2025 11:44:50 +0000 (14:44 +0300)]
drm/i915/vga: Add more VGACNTRL bits
Define a pile of extra VGACNTRL bits. We don't really have
any real use for most of these but nicer to have them all
in one place rather than trawling the specs when one wants
to know what's in there.
I will have some real use for the CHV pipe select bits later.
Animesh Manna [Wed, 23 Apr 2025 09:23:30 +0000 (14:53 +0530)]
drm/i915/lobf: Add debug interface for lobf
Add an interface in debugfs which will help in debugging LOBF
feature.
v1: Initial version.
v2:
- Remove FORCE_EN flag. [Jouni]
- Change prefix from I915 to INTEL. [Jani]
- Use u8 instead of bool for lobf-debug flag. [Jani]
v3:
- Use intel_connector instead of display. [Jani]
- Remove edp connector check as it was already present
in caller function. [Jani]
- Remove loop of searching edp encoder which is directly
accessible from intel_connector. [Jani]
v4:
- Simplify alpm debug to bool instead of bit-mask. [Jani]
v5:
- Remove READ_ONCE(). [Jani]
- Modify variable name to *_disable_*. [Jouni]
v6: Improved debug print. [Jouni]
Animesh Manna [Wed, 23 Apr 2025 09:23:29 +0000 (14:53 +0530)]
drm/i915/lobf: Update lobf if any change in dependent parameters
For every commit the dependent condition for LOBF is checked
and accordingly update has_lobf flag which will be used
to update the ALPM_CTL register during commit.
v1: Initial version.
v2: Avoid reading h/w register without has_lobf check. [Jani]
v3: Update LOBF in post plane update instead of separate function. [Jouni]
v4:
- Add lobf disable print. [Jouni]
- Simplify condition check for enabling/disabling lobf. [Jouni]
v5: Disable LOBF in pre_plane_update(). [Jouni]
v6: use lobf flag of old_crtc_state and write 0 into ALPM_CTL. [Jouni]
Animesh Manna [Wed, 23 Apr 2025 09:23:27 +0000 (14:53 +0530)]
drm/i915/lobf: Disintegrate alpm_disable from psr_disable
Currently clearing of alpm registers is done through psr_disable()
which is always not correct, without psr also alpm can exist. So
dis-integrate alpm_disable() from psr_disable().
Animesh Manna [Wed, 23 Apr 2025 09:23:26 +0000 (14:53 +0530)]
drm/i915/lobf: Add debug print for LOBF
Lobf is enabled part of ALPM configuration and if has_lobf
is set to true respective bit for LOBF will be set. Add debug
print while setting the bitfield of LOBF.
Animesh Manna [Wed, 23 Apr 2025 09:23:25 +0000 (14:53 +0530)]
drm/i915/lobf: Add lobf enablement in post plane update
Enablement of LOBF is added in post plane update whenever
has_lobf flag is set. As LOBF can be enabled in non-psr
case as well so adding in post plane update. There is no
change of configuring alpm with psr path.
v1: Initial version.
v2: Use encoder-mask to find the associated encoder from
crtc-state. [Jani]
v3: Remove alpm_configure from intel_psr.c. [Jouni]
drm/i915/alpm: use variable from intel_crtc_state instead of intel_psr
Currently code is making assumption that PSR is enabled when
intel_alpm_configure is called. This doesn't work if alpm is configured
before PSR is enabled.
Jani Nikula [Wed, 23 Apr 2025 10:02:13 +0000 (13:02 +0300)]
drm/i915/reg: Add/remove some extra blank lines
Add/remove some blank lines to/from i915_reg.h primarily to help the
scripted refactoring coming up, separating unrelated registers and
keeping the comments together.
Jani Nikula [Wed, 23 Apr 2025 10:02:12 +0000 (13:02 +0300)]
drm/i915/reg: use REG_BIT and friends to define DP registers
Define the DP register contents using the REG_BIT, REG_GENMASK,
etc. macros. Ditch the unhelpful comments. Rename eDP related register
content macros to have EDP_ prefix.
Scope of intel_psr_needs_block_dc_vblank has changed now. Rename it as
intel_psr_needs_vblank_notification. Also rename
intel_crtc::block_dc_for_vblank as intel_crtc:vblank_psr_notify
drm/i915/psr: Apply underrun on PSR idle workaround
This patch is applying workaround for underrun on idle PSR HW issue
(Wa_16025596647) when PSR is getting enabled. It uses vblank enable/disable
status, DC5/6 enabled disabled and enabled pipes count information made
available.
This patch is also adding calls to dc5/dc6, vblank enable/disable and pipe
enable/disable notification functions as needed.
intel_psr_needs_block_dc_vblank is modified to get vblank enable/disable
notification on PSR capable system.
v2: use intel_dmc interface instead of directly writing dmc register
drm/i915/dmc: Add interface to control start of PKG C-state exit
Add interface to control if package C exit starts at the start of the
undelayed vblank. This is needed to implement workaround for underrun on
idle PSR HW issue (Wa_16025596647).
drm/i915/psr: Add mechanism to notify PSR of DC5/6 enable disable
We need to apply/remove workaround for underrun on idle PSR HW issue
(Wa_16025596647) when DC5/6 is enabled/disabled. This patch implements
mechanism to notify PSR about DC5/6 enable/disable and applies/removes the
workaround using this notification.
drm/i915/psr: Add mechanism to notify PSR of pipe enable/disable
We need to apply/remove workaround for underrun on idle PSR HW issue
(Wa_16025596647) when new pipe is enabled or pipe is getting disabled. This
patch implements mechanism to notify PSR about pipe enable/disable and
applies/removes the workaround using this notification.
We need PIPEDMC_BLOCK_PKGC_SW definitions to implement workaround for
underrun on idle PSR HW issue (Wa_16025596647). Add PIPEDMC_BLOCK_PKGC_SW
register definitions.
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647)
we need PIPEDMC_EVT_CTL_4 register. Add PIPEDMC_EVT_CTL_4 register
definitions.
drm/i915/psr: Store enabled non-psr pipes into intel_crtc_state
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647)
we need to know enabled. Figure out which non-PSR pipes we will have active
and store it into intel_crtc_state->active_non_psr_pipes. This is currently
assuming only one eDP on a time. I.e. possible secondary eDP with PSR
capable panel is not considered.
drm/i915/display: Add new interface for getting dc_state
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647)
we need to have current configured DC state available. Add new interface
for this purpose.
Jani Nikula [Thu, 17 Apr 2025 09:10:38 +0000 (12:10 +0300)]
drm/i915/pch: abstract fake PCH detection better
Abstract detection of platforms with south display on the same PCI
device or SoC die as north display, and all around clarify what this
means. Debug log about it for good measure.
Jani Nikula [Thu, 17 Apr 2025 09:10:37 +0000 (12:10 +0300)]
drm/i915/display: drop lots of unnecessary #include i915_drv.h
With the PCH macros switched to use struct intel_display, we have a
number of files that no longer need struct drm_i915_private or anything
else from i915_drv.h anymore. Remove the #include, and add the missing
includes that were previously implicit.
Jani Nikula [Thu, 17 Apr 2025 09:10:36 +0000 (12:10 +0300)]
drm/i915/display: pass struct intel_display to PCH macros
Now that INTEL_PCH_TYPE() and HAS_PCH_*() macros are under display, and
accept a struct intel_display pointer, use that instead of struct
drm_i915_private pointer in display code.
This is done naively by running:
$ sed -i 's/\(INTEL_PCH_TYPE\|HAS_PCH_[A-Z0-9_-]*\)([^)]*)/\1(display)/g' \
$(find drivers/gpu/drm/i915/display -name "*.c")
and fixing the fallout, i.e. removing unused local i915 variables and
adding display variables where needed.
Jani Nikula [Wed, 9 Apr 2025 18:17:55 +0000 (21:17 +0300)]
drm/xe/compat: clean up unused platform check macros
Clean up unused platform check macros from compat i915_drv.h. Display no
longer uses any of the IS_*() platform checks. The remaining users are
part of the soc/ code. Note that in a comment.
Jani Nikula [Wed, 9 Apr 2025 18:17:42 +0000 (21:17 +0300)]
drm/i915/fb: convert intel_fbdev.[ch] and intel_fbdev_fb.[ch] to struct intel_display
Going forward, struct intel_display is the main display device data
pointer. Convert intel_fbdev.[ch] and as much as possible of
intel_fbdev_fb.[ch] to struct intel_display.
drm/i915/pxp: fix undefined reference to `intel_pxp_gsccs_is_ready_for_sessions'
On x86_64 with gcc version 13.3.0, I compile kernel with:
make defconfig
./scripts/kconfig/merge_config.sh .config <(
echo CONFIG_COMPILE_TEST=y
)
make KCFLAGS="-fno-inline-functions -fno-inline-small-functions -fno-inline-functions-called-once"
Then I get a linker error:
ld: vmlinux.o: in function `pxp_fw_dependencies_completed':
kintel_pxp.c:(.text+0x95728f): undefined reference to `intel_pxp_gsccs_is_ready_for_sessions'
This is caused by not having a intel_pxp_gsccs_is_ready_for_sessions()
header stub for CONFIG_DRM_I915_PXP=n. Add it.
Signed-off-by: Chen Linxuan <chenlinxuan@uniontech.com> Fixes: 99afb7cc8c44 ("drm/i915/pxp: Add ARB session creation and cleanup") Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://lore.kernel.org/r/20250415090616.2649889-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Jani Nikula [Wed, 9 Apr 2025 18:47:02 +0000 (21:47 +0300)]
drm/i915/irq: convert ibx_irq_reset() into ibx_display_irq_reset()
Observe that ibx_irq_reset() is really ibx_display_irq_reset(). Make it
so. Move to display, and call it directly from gen8_display_irq_reset()
instead of gen8_irq_reset().
Remove a nearby ancient stale comment while at it.
drm/i915/display: Add link rate and lane count to i915_display_info
Adding link rate and lane count information to i915_display_info makes it
easier and faster to access this data compared to checking kernel logs.
This is particularly beneficial for individuals who are not familiar with
i915 in the following scenarios:
* Debugging DP tunnel bandwidth usage in the Thunderbolt driver.
* During USB4 certification, it is necessary to know the link rate used by
the monitor to prove that the DP tunnel can handle required rates.
* In PHY CTS, when the connector probes are not mounted correctly,
some display lanes may not appear in the DP Oscilloscope, leading to CTS
failures.
This change provides validation teams with an easy way to identify and
troubleshoot issues.
v2: separate seq_printf line (Jani)
v3: separate output line (Jani)
Cc: Imre Deak <imre.deak@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://lore.kernel.org/r/20250409230214.963999-1-khaled.almahallawy@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drm/i915/dp: Check for HAS_DSC_3ENGINES while configuring DSC slices
DSC 12 slices configuration is used for some specific cases with
Ultrajoiner. This can be supported only when each of the 4 joined pipes
have 3 DSC engines each.
Add the missing check for 3 DSC engines support before using 3 DSC
slices per pipe.
Jani Nikula [Mon, 14 Apr 2025 11:29:46 +0000 (14:29 +0300)]
drm/i915: use display snapshot mechanism for display irq regs
Move more display specific parts of GPU error logging behind the display
snapshot interface.
With the display register capture reduced to just one register, DERRMR,
there's quite a bit of boilerplate here. However, it's still a nice
abstraction and removes a DISPLAY_VER() usage from core i915. With this
approach, it's also easy to add to xe as needed.
Jani Nikula [Fri, 11 Apr 2025 10:27:15 +0000 (13:27 +0300)]
drm/i915/dpio: have chv_data_lane_soft_reset() get/put dpio internally
Have chv_data_lane_soft_reset() get/put dpio internally, and use a
locked version of it within intel_dpio_phy.c. This drops the dependency
on vlv sideband from g4x_dp.c and g4x_hdmi.c, and makes that a DPIO PHY
implementation detail.
drm/i915/vrr: Stop writing VRR_CTL_IGN_MAX_SHIFT for MTL onwards
According to Bspec VRR_CTL_IGN_MAX_SHIFT doesn't exist for MTL and
onwards. On LunarLake and onwards Bit 30 is "Mask Block PkgC" instead. Stop
writing the bit for MeteorLake and onwards
v2: "Ignore Max Shift" bit doesn't exist on MeteorLake either
Jani Nikula [Fri, 11 Apr 2025 09:54:14 +0000 (12:54 +0300)]
drm/i915/pch: clean up includes
We no longer need i915_drv.h in intel_pch.c, and we no longer need
intel_pch.h universally.
With intel_pch.h being included from intel_display_core.h, it's still
included pretty much everywhere, but there's no need to include it
explicitly from i915_drv.h or xe_device_types.h.
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