Andrew Pinski [Tue, 22 Apr 2025 16:40:28 +0000 (09:40 -0700)]
gimple-fold: Don't replace `tmp = FP0 CMP FP1; if (tmp != 0)` over and over again when comparison can throw
with -ftrapping-math -fnon-call-exceptions and:
```
tmp = FP0 CMP FP1;
if (tmp != 0) ...
```
a call fold_stmt on the GIMPLE_COND will replace the above with
a new tmp each time and we even lose the eh informatin on the
previous comparison too.
Changes since v1:
* v2: Use INTEGRAL_TYPE_P instead of a check against BOOLEAN_TYPE.
Add testcase which shows where losing of landing pad happened.
PR tree-optimization/119903
gcc/ChangeLog:
* gimple-fold.cc (replace_stmt_with_simplification): Reject for
noncall exceptions replacing comparison with itself.
gcc/testsuite/ChangeLog:
* g++.dg/tree-ssa/pr119903-1.C: New test.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Andrew Pinski [Tue, 13 May 2025 01:58:32 +0000 (18:58 -0700)]
verifier: Fix up PAREN_EXPR verification [PR118868]
The verification added in r12-1608-g2f1686ff70b25f, was incorrect
for PAREN_EXPR, pointer types should be valid for PAREN_EXPR.
Also for PAREN_EXPR, aggregate types don't make sense (currently
they ICE much earlier in the gimplifier rather than error message) so
we should disallow them here too.
Bootstrapped and tested on x86_64-linux-gnu.
PR middle-end/118868
gcc/ChangeLog:
* tree-cfg.cc (verify_gimple_assign_unary): Allow pointers
but disallow aggregate types for PAREN_EXPR.
gcc/testsuite/ChangeLog:
* c-c++-common/pr118868-1.c: New test.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Andrew Pinski [Wed, 4 Dec 2024 02:57:45 +0000 (18:57 -0800)]
cfgexpand: Update cache during the original DFS walk
This is a small optimization which can improve how many times are need through the update loop.
It can reduce the number of times in the update loop by maybe 1 times.
Bootstrapped and tested on x86_64-linux-gnu.
gcc/ChangeLog:
* cfgexpand.cc (vars_ssa_cache::operator()): Update the cache if the use is already
has a cache.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Andrew Pinski [Tue, 3 Dec 2024 23:57:42 +0000 (15:57 -0800)]
cfgexpand: Reverse the order of going through the update_cache_list queue.
This is a small optimization, the reversed order of the walk of update_cache_list queue.
The queue is pushed in Pre-order/NLR, reversing the order will reduce how many times we
need to go through the loop as we update the nodes which might have a link back to another
one first.
Bootstrapped and tested on x86_64-linux-gnu.
gcc/ChangeLog:
* cfgexpand.cc (vars_ssa_cache::operator()): Reverse the order of the going
through the update list.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Richard Biener [Tue, 13 May 2025 12:16:57 +0000 (14:16 +0200)]
Remove non-SLP path from vectorizable_induction
This removes the non-SLP path from vectorizable_induction.
* tree-vect-loop.cc (vectorizable_nonlinear_induction):
Remove non-SLP path, use SLP_TREE_VECTYPE.
(vectorizable_induction): Likewise. Drop ncopies variable
which is always 1.
Gaius Mulley [Tue, 13 May 2025 12:35:00 +0000 (13:35 +0100)]
PR modula2/120188: Use existing test for plugin
This is a cleanup patch which to use the existing plugin test
rather than check the configure build options.
gcc/testsuite/ChangeLog:
PR modula2/120188
* gm2.dg/doc/examples/plugin/fail/doc-examples-plugin-fail.exp:
Remove call to gm2-dg-frontend-configure-check and replace with
tests for whether plugin variables exist.
Jakub Jelinek [Tue, 13 May 2025 12:20:22 +0000 (14:20 +0200)]
libfortran: Fix up _gfortran_{,m,s}findloc2_s{1,4} [PR120196]
As mentioned in the PR, _gfortran_{,m,s}findloc2_s{1,4} iterate too many
times in the back case if nothing is found.
For !back, the loops are for (i = 1; i <= extent; i++) so i is in the
body [1, extent] if nothing is found, but for back it is
for (i = extent; i >= 0; i--) so i is in the body [0, extent] and compares
one element before the start of the array.
Note, findloc1_s{1,4} uses
for (n = len; n > 0; n--, src -= delta * len_array)
for the back loop and
for (n = 1; n <= len; n++, src += delta * len_array)
for !back. This patch fixes that.
The testcase fails under valgrind without the libgfortran changes and
succeeds with those.
2025-05-13 Jakub Jelinek <jakub@redhat.com>
PR libfortran/120196
* m4/ifindloc2.m4 (header1, header2): For back use i > 0 rather than
i >= 0 as for condition.
* generated/findloc2_s1.c: Regenerate.
* generated/findloc2_s4.c: Regenerate.
Jakub Jelinek [Tue, 13 May 2025 12:19:25 +0000 (14:19 +0200)]
libfortran: Fix up _gfortran_s{max,min}loc1_{4,8,16}_s{1,4} [PR120191]
There is a bug in _gfortran_s{max,min}loc1_{4,8,16}_s{1,4} which the
following testcase shows.
The functions return but then crash in the caller.
Seems that is because buffer overflows, I believe those functions for
if (mask == NULL || *mask) condition being false are supposed to fill in
the result array with all zeros (or allocate it and fill it with zeros).
My understanding is the result array in that case is integer(kind={4,8,16})
and should have the extents the character input array has.
The problem is that it uses * string_len in the extent multiplication:
extent[n] = GFC_DESCRIPTOR_EXTENT(array,n) * string_len;
and
extent[n] =
GFC_DESCRIPTOR_EXTENT(array,n + 1) * string_len;
which is I guess fine and desirable for the extents of the character array,
but not for the extents of the destination array. Yet the code uses
that extent array for that purpose (and no other purposes).
Here it uses it to set the dimensions for the case where it needs to
allocate (as well as size):
for (n = 0; n < rank; n++)
{
if (n == 0)
str = 1;
else
str = GFC_DESCRIPTOR_STRIDE(retarray,n-1) * extent[n-1];
GFC_DIMENSION_SET(retarray->dim[n], 0, extent[n] - 1, str);
}
Here it uses it for bounds checking of the destination:
if (unlikely (compile_options.bounds_check))
{
for (n=0; n < rank; n++)
{
index_type ret_extent;
ret_extent = GFC_DESCRIPTOR_EXTENT(retarray,n);
if (extent[n] != ret_extent)
runtime_error ("Incorrect extent in return value of"
" MAXLOC intrinsic in dimension %ld:"
" is %ld, should be %ld", (long int) n + 1,
(long int) ret_extent, (long int) extent[n]);
}
}
and here to find out how many retarray elements to actually fill in each
dimension:
while(1)
{
*dest = 0;
count[0]++;
dest += dstride[0];
n = 0;
while (count[n] == extent[n])
{
/* When we get to the end of a dimension, reset it and increment
the next dimension. */
count[n] = 0;
/* We could precalculate these products, but this is a less
frequently used path so probably not worth it. */
dest -= dstride[n] * extent[n];
Seems maxloc1s.m4 and minloc1s.m4 are the only users of ifunction-s.m4,
so we can change SCALAR_ARRAY_FUNCTION in there without breaking anything
else.
Jakub Jelinek [Tue, 13 May 2025 12:18:10 +0000 (14:18 +0200)]
libfortran: Fix up _gfortran_s{max,min}loc2_{4,8,16}_s{1,4} [PR120191]
I've tried to write a testcase for the BT_CHARACTER maxloc/minloc with named
or unnamed arguments and indeed the just posted patch fixed the arguments
in there in multiple cases to match what the library expects.
But the testcase still fails, due to library problems.
One dealt with in this patch are _gfortran_s{max,min}loc2_{4,8,16}_s{1,4}
functions. Those are trivial wrappers around
_gfortrani_{max,min}loc2_{4,8,16}_s{1,4} which should call those functions
if the scalar mask is true and just return 0 otherwise.
The two bugs I see there is that the back, len arguments are swapped,
which means that it always acts as back=.true. and for len will use
character length of 1 or 0 instead of the desired one.
The _gfortrani_{max,min}loc2_{4,8,16}_s{1,4} functions have prototypes like
GFC_INTEGER_4
maxloc2_4_s1 (gfc_array_s1 * const restrict array, GFC_LOGICAL_4 back, gfc_charlen_type len)
so back comes before len, ditto for the
GFC_INTEGER_4
smaxloc2_4_s1 (gfc_array_s1 * const restrict array,
GFC_LOGICAL_4 *mask, GFC_LOGICAL_4 back, gfc_charlen_type len)
The other problem is that it was just testing if (mask). In my limited
Fortran understanding that means that the optional argument mask was
supplied but nothing about its actual value. Other scalar mask generated
routines use if (mask == NULL || *mask) as the condition when to call the
non-masked function, i.e. when mask is not supplied (then it should act like
.true. mask) or when it is supplied and evaluates to .true.).
2025-05-13 Jakub Jelinek <jakub@redhat.com>
PR fortran/120191
* m4/maxloc2s.m4: For smaxloc2 call maxloc2 if mask is NULL or *mask.
Swap back and len arguments.
* m4/minloc2s.m4: Likewise.
* generated/maxloc2_4_s1.c: Regenerate.
* generated/maxloc2_4_s4.c: Regenerate.
* generated/maxloc2_8_s1.c: Regenerate.
* generated/maxloc2_8_s4.c: Regenerate.
* generated/maxloc2_16_s1.c: Regenerate.
* generated/maxloc2_16_s4.c: Regenerate.
* generated/minloc2_4_s1.c: Regenerate.
* generated/minloc2_4_s4.c: Regenerate.
* generated/minloc2_8_s1.c: Regenerate.
* generated/minloc2_8_s4.c: Regenerate.
* generated/minloc2_16_s1.c: Regenerate.
* generated/minloc2_16_s4.c: Regenerate.
Jakub Jelinek [Tue, 13 May 2025 12:14:55 +0000 (14:14 +0200)]
fortran: Fix up minloc/maxloc lowering [PR120191]
We need to drop the kind argument from what is passed to the
library, but need to do it not only when one uses the argument name
for it (so kind=4 etc.) but also when one passes all the arguments
to the intrinsics.
The following patch uses what gfc_conv_intrinsic_findloc uses,
which looks more efficient and cleaner, we already set automatic
vars to point to the kind and back actual arguments, so we can just
free/clear expr on the former and set name to "%VAL" on the latter.
And similarly clears dim argument for the BT_CHARACTER case when using
maxloc2/minloc2, again regardless of whether it was named or not.
2025-05-13 Jakub Jelinek <jakub@redhat.com>
Daniil Kochergin <daniil2472s@gmail.com>
Tobias Burnus <tburnus@baylibre.com>
PR fortran/120191
* trans-intrinsic.cc (strip_kind_from_actual): Remove.
(gfc_conv_intrinsic_minmaxloc): Don't call strip_kind_from_actual.
Free and clear kind_arg->expr if non-NULL. Set back_arg->name to
"%VAL" instead of a loop looking for last argument. Remove actual
variable, use array_arg instead. Free and clear dim_arg->expr if
non-NULL for BT_CHARACTER cases instead of using a loop.
Andreas Schwab [Wed, 7 May 2025 07:46:19 +0000 (09:46 +0200)]
libiberty: Fix off-by-one when collecting range expression
Fixes this error during build of fixincludes:
In function ‘byte_regex_compile’,
inlined from ‘xregcomp’ at ../libiberty/../../libiberty/regex.c:7973:11:
../libiberty/../../libiberty/regex.c:3477:29: warning: writing 1 byte into a region of size 0 [-Wstringop-overflow=]
3477 | str[c1] = '\0';
| ^
../libiberty/../../libiberty/regex.c: In function ‘xregcomp’:
../libiberty/../../libiberty/regex.c:3454:35: note: at offset 128 into destination object ‘str’ of size 128
3454 | unsigned char str[128]; /* Should be large enough. */
| ^
* regex.c (regex_compile): Don't write beyond array bounds when
collecting range expression.
Rainer Orth [Tue, 13 May 2025 07:43:48 +0000 (09:43 +0200)]
libgcobol: Allow for lack of LOG_PERROR
The libgcobol build is broken again on Solaris:
/vol/gcc/src/hg/master/local/libgcobol/libgcobol.cc: In function ‘void
default_exception_handler(ec_type_t)’:
/vol/gcc/src/hg/master/local/libgcobol/libgcobol.cc:11196:44: error:
‘LOG_PERROR’ was not declared in this scope; did you mean ‘LOG_ERR’?
11196 | static int priority = LOG_INFO, option = LOG_PERROR, facility =
LOG_USER;
| ^~~~~~~~~~
| LOG_ERR
/vol/gcc/src/hg/master/local/libgcobol/libgcobol.cc:11202:28: error:
‘facility’ was not declared in this scope
11202 | openlog(ident, option, facility);
| ^~~~~~~~
LOG_PERROR is a BSD extension not present on Solaris due to its System V
heritage, and Linux syslog(3) documents:
LOG_PERROR (Not in POSIX.1-2001 or POSIX.1-2008.) Also log the
message to stderr.
This patch provides a fallback definition, just the minimum to unbreak
the build.
Tested on amd64-pc-solaris2.11, sparcv9-sun-solaris2.11, and
x86_64-pc-linux-gnu.
Kito Cheng [Wed, 7 May 2025 13:27:20 +0000 (21:27 +0800)]
RISC-V: Drop riscv_ext_flag_table in favor of riscv_ext_info_t data
Refactor extension flag handling by removing the old riscv_ext_flag_table and
sourcing all flag definitions directly from the flags field of the unified
riscv_ext_info_t structures generated from riscv-ext.def.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_extra_ext_flag_table_t):
New.
(riscv_ext_flag_table): Rename to ...
(riscv_extra_ext_flag_table): this, and drop most of definitions
that can obtained from the flags field of the riscv_ext_info_t
structures.
(apply_extra_extension_flags): Use riscv_ext_info_t.
(riscv_ext_is_subset): Ditto.
Kito Cheng [Thu, 8 May 2025 08:23:29 +0000 (16:23 +0800)]
RISC-V: Drop riscv_ext_version_table in favor of riscv_ext_info_t data
This commit drops the riscv_ext_version_table and instead uses the
riscv_ext_info_t data structure to provide the version information
for RISC-V extensions.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_ext_version_table):
Remove.
(standard_extensions_p): Use riscv_ext_info_t.
(get_default_version): Use riscv_ext_info_t.
(riscv_arch_help): Ditto.
Kito Cheng [Wed, 7 May 2025 13:21:01 +0000 (21:21 +0800)]
RISC-V: Drop riscv_implied_info and riscv_combine_info in favor of riscv_ext_info_t data
Consolidate implied-extension logic by removing the old `riscv_implied_info`
array and using the `implied_exts` field in the unified riscv_ext_info_t
structures generated from `riscv-ext.def`.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_implied_info::riscv_implied_info_t): Remove unused
variant.
(struct riscv_implied_info_t): Remove unsued field.
(riscv_implied_info::match): Remove unused variant, and adjust
the logic.
(get_riscv_ext_info): New.
(riscv_implied_info): Remove.
(riscv_ext_info_t::apply_implied_ext): New.
(riscv_combine_info). Remove.
(riscv_subset_list::handle_implied_ext): Use riscv_ext_info_t
rather than riscv_implied_info.
(riscv_subset_list::check_implied_ext): Ditto.
(riscv_subset_list::handle_combine_ext): Use riscv_ext_info_t
rather than riscv_combine_info.
(riscv_minimal_hwprobe_feature_bits): Use riscv_ext_info_t
rather than riscv_implied_info.
Kito Cheng [Wed, 7 May 2025 12:59:15 +0000 (20:59 +0800)]
RISC-V: Introduce riscv_ext_info_t to hold extension metadata
Define a new riscv_ext_info_t struct to aggregate all ISA extension fields
(name, version, flags, implied extensions, bitmask and extra flags) generated
from riscv-ext.def.
Also adjust riscv_ext_flag_table_t and riscv_implied_info_t to make it
able to not hold extension name, this part will refactor in later
patchs.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_ext_info_t): New
struct.
(opt_var_ref_t): Adjust order.
(cl_opt_var_ref_t): Ditto.
(riscv_ext_flag_table_t): Adjust order, and add a new construct
that not hold the extension name.
(riscv_version_t): New struct.
(riscv_implied_info_t): Adjust order, and add a new construct that not
hold the extension name.
(apply_extra_extension_flags): New function.
(riscv_ext_infos): New.
(riscv_implied_info): Adjust.
* config/riscv/riscv-opts.h (EXT_FLAG_MACRO): New macro.
(BITMASK_NOT_YET_ALLOCATED): New macro.
Kito Cheng [Wed, 7 May 2025 13:10:53 +0000 (21:10 +0800)]
RISC-V: Generate extension table in documentation from riscv-ext.def
Automatically build the ISA extension reference table in invoke.texi from
the unified riscv-ext.def metadata, ensuring documentation stays in sync
with extension definitions and reducing manual maintenance.
gcc/ChangeLog:
* doc/invoke.texi: Replace hand‑written extension table with
`@include riscv-ext.texi` to pull in auto‑generated entries.
* doc/riscv-ext.texi: New generated definition file
containing formatted documentation entries for each extension.
* Makefile.in: Add riscv-ext.texi to the list of files to be
processed by the Texinfo generator.
* config/riscv/gen-riscv-ext-texi.cc: New.
* config/riscv/t-riscv: Add rule for generating riscv-ext.texi.
Kito Cheng [Wed, 7 May 2025 10:28:18 +0000 (18:28 +0800)]
RISC-V: Use riscv-ext.def to generate target options and variables
Leverage the centralized riscv-ext.def definitions to auto-generate
the target option parsing and associated internal flags, replacing
manual listings in riscv.opt; `riscv_ext_flag_table` part will remove in
later patch.
gcc/ChangeLog:
* config/riscv/gen-riscv-ext-opt.cc: New.
* config/riscv/riscv.opt: Drop manual entries for target
options, and include riscv-ext.opt.
* config/riscv/riscv-ext.opt: New.
* config/riscv/riscv-ext.opt.urls: New.
* config.gcc: Add riscv-ext.opt to the list of target options files.
* common/config/riscv/riscv-common.cc (riscv_ext_flag_table): Adjsut target
option variable entry.
(riscv_set_arch_by_subset_list): Adjust target option variable.
* config/riscv/riscv-c.cc (riscv_ext_flag_table): Adjust target
option variable entry.
* config/riscv/riscv-vector-builtins.cc (pragma_intrinsic_flags):
Adjust variable name.
(riscv_pragma_intrinsic_flags_pollute): Adjust variable name.
(riscv_pragma_intrinsic_flags_restore): Ditto.
* config/riscv/t-riscv: Add the rule for generating
riscv-ext.opt.
* config/riscv/riscv-opts.h (TARGET_MIN_VLEN): Update.
(TARGET_MIN_VLEN_OPTS): Update.
Kito Cheng [Wed, 7 May 2025 10:02:10 +0000 (18:02 +0800)]
RISC-V: Introduce riscv-ext*.def to define extensions
Adding a new ISA extension to RISC-V GCC requires modifying several places:
1. riscv_ext_version_table for the extension version.
2. riscv.opt for the target option and variable.
3. riscv_ext_flag_table to bind the extension to its target option.
4. riscv_combine_info if this extension is just a macro extension.
5. riscv_implied_info if this extension implies other extensions.
6. invoke.texi for documentation (this one is often forgotten - even by me...).
7. riscv-ext-bitmask.def if this extension has been allocated a bitmask in
`__riscv_feature_bits`.
And now, we've integrated all the information into riscv-ext.def and generate
(almost) everything from that!
Some of the fields, like URL, are not used yet. They are planned to be updated
later and used for improving the documentation.
Changes since v1:
- Rebase for including new extensions
- Fix MASK_VECTOR handling
David Malcolm [Tue, 13 May 2025 01:45:36 +0000 (21:45 -0400)]
diagnostics: improvements to experimental-html output [PR116792]
Add barebones support for
* diagnostic metadata rules
* quoted source
* generated patches
* execution paths
gcc/ChangeLog:
PR other/116792
* diagnostic-format-html.cc: Include "diagnostic-format-text.h",
"pretty-print-urlifier.h" and "edit-context.h".
(html_builder::html_builder): Fix indentation in decl.
(html_builder::make_element_for_diagnostic): Split out metadata
code into make_element_for_metadata. Call
make_element_for_source, make_element_for_path, and
make_element_for_patch.
(html_builder::make_element_for_source): New.
(html_builder::make_element_for_path): New.
(html_builder::make_element_for_patch): New.
(html_builder::make_metadata_element): New.
(html_builder::make_element_for_metadata): New.
(html_output_format::get_builder): New.
(selftest::test_html_diagnostic_context::get_builder): New.
(selftest::test_simple_log): Update test to print a quoted string,
and verify that it uses a "gcc-quoted-text" span.
(selftest::test_metadata): New.
(selftest::diagnostic_format_html_cc_tests): Call it.
gcc/testsuite/ChangeLog:
PR other/116792
* gcc.dg/html-output/missing-semicolon.py: Verify that we don't
have an empty "gcc-annotated-source" and we do have a
"gcc-generated-patch".
* gcc.dg/plugin/diagnostic-test-metadata-html.c: New test.
* gcc.dg/plugin/diagnostic-test-metadata-html.py: New test script.
* gcc.dg/plugin/diagnostic-test-paths-2.c: Add
"-fdiagnostics-add-output=experimental-html" to options. Add
invocation of diagnostic-test-paths-2.py.
* gcc.dg/plugin/diagnostic-test-paths-2.py: New test script.
* gcc.dg/plugin/plugin.exp (plugin_test_list): Add
diagnostic-test-metadata-html.c.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
Andrew MacLeod [Fri, 9 May 2025 00:28:11 +0000 (20:28 -0400)]
Remove negative ranges using trailing zero masks.
When there are trailing 0's in the bitmask, set_range_from_bitmask () removes
the lower positive ranges which do not match the value. This reworks it to
provide the same functionailty for the negative ranges in signed types.
If the lower 4 bits are all 0:
int [-INF, +INF] MASK 0xfffffff0 VALUE 0x0
becomes:
int [-INF, -16][0, 0][16, 2147483632] MASK 0xfffffff0 VALUE 0x0
gcc/
* tree-ssanames.cc (set_bitmask): Use int_range_max for temps.
* value-range.cc (irange::set_range_from_bitmask): Handle all
trailing zero values.
Pan Li [Mon, 28 Apr 2025 12:35:10 +0000 (20:35 +0800)]
RISC-V: Add testcases for vector unsigned integer SAT_ADD form 7
This patch will add testcase for unsigned integer SAT_ADD form 7:
#define DEF_VEC_SAT_U_ADD_FMT_9(WT, T) \
void __attribute__((noinline)) \
vec_sat_u_add_##WT##_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
T max = -1; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
WT val = (WT)x + (WT)y; \
out[i] = val > max ? max : (T)val; \
} \
}
DEF_VEC_SAT_U_ADD_FMT_9(uint64_t, uint32_t)
The below test are passed for this patch.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: Add test helper macros.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u32-from-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u32-from-u64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u64.c: New test.
Pan Li [Mon, 28 Apr 2025 12:35:09 +0000 (20:35 +0800)]
RISC-V: Add testcases for scalar unsigned integer SAT_ADD form 7
This patch will add testcase for unsigned integer SAT_ADD form 7:
#define DEF_SAT_U_ADD_FMT_7(WT, T) \
T __attribute__((noinline)) \
sat_u_add_##WT##_##T##_fmt_7(T x, T y) \
{ \
T max = -1; \
WT val = (WT)x + (WT)y; \
return val > max ? max : (T)val; \
}
DEF_SAT_U_ADD_FMT_7(uint64_t, uint32_t)
The below test are passed for this patch.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c: New test.
* gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c: New test.
* gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c: New test.
* gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c: New test.
* gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c: New test.
* gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c: New test.
* gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c: New test.
Pan Li [Mon, 28 Apr 2025 12:35:08 +0000 (20:35 +0800)]
Match: Support form 7 for unsigned integer SAT_ADD
This patch would like to support the form 7 of the unsigned
integer SAT_ADD, aka below example.
#define DEF_SAT_U_ADD_FMT_7(WT, T) \
T __attribute__((noinline)) \
sat_u_add_##WT##_##T##_fmt_7(T x, T y) \
{ \
T max = -1; \
WT val = (WT)x + (WT)y; \
return val > max ? max : (T)val; \
}
DEF_SAT_U_ADD_FMT_7(uint64_t, uint32_t)
If we take -O3 build with -fdump-tree-optimized, we will have
Andrew Pinski [Mon, 12 May 2025 05:11:38 +0000 (22:11 -0700)]
optabs: Remove cmov optab [PR120230]
cmov optab was added back in r0-24110-g1c0290eaac4094
(https://gcc.gnu.org/pipermail/gcc-patches/1999-September/018596.html)
but it was never used. movcc is used instead and since r0-93453-gf90b7a5a7913cc (cond-optab),
movcc becomes what cmov_optab was going to be; in having a combined compare and move optab.
Note the only target which seems to have implemented this optab is aarch64; will remove
that in a different patch.
Bootstrapped and tested on x86_64-linux-gnu.
PR middle-end/120230
gcc/ChangeLog:
* optabs.cc (can_compare_p): Remove support for ccp_cmov.
* optabs.def (cmov_optab): Remove.
* optabs.h (can_compare_purpose): Remove ccp_cmov.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Andrew MacLeod [Mon, 12 May 2025 15:41:37 +0000 (11:41 -0400)]
Add dispatch for casts between integer and float.
GCC currently does not implement range operators for casting between
integers and float. This patch adds the missing dispatch patterns and
routines to facilitate implmenting these casts.
PR tree-optimization/120231
* range-op-float.cc (operator_cast::fold_range): New variants.
(operator_cast::op1_range): Likewise.
* range-op-mixed.h (operator_cast::fold_range): Likewise.
(operator_cast::op1_range): Likewise
* range-op.cc (range_op_handler::fold_range): Add RO_FIF dispatch.
(range_op_handler::op1_range): Add RO_IFF and RO_FII patterns.
(range_operator::fold_range): Provide new variant default.
(range_operator::op1_range): Likewise.
* range-op.h (range_operator): Add new variant methods.
Jason Merrill [Mon, 12 May 2025 15:53:03 +0000 (11:53 -0400)]
c+: -Wabi false positive [PR120012]
The warning compares the position of a field depending on whether or not the
previous base/field is considered a POD for layout, but failed to consider
whether the previous base/field is empty; layout of an empty base doesn't
consider PODness.
Gaius Mulley [Mon, 12 May 2025 16:59:00 +0000 (17:59 +0100)]
PR modula2/120188: documented example does not work assignvalue m2plugin
This patch corrects the gm2 command line used in the documentation
to invoke the m2-plugin. The patch also includes the documentation
example in dejagnu test code with an expect script to check whether
plugins were enabled.
PR modula2/120188
* lib/gm2-dg.exp (gm2-dg-frontend-configure-check): New function.
(gm2-dg-runtest): Add -O2 to the option_list.
* gm2.dg/doc/examples/plugin/fail/assignvalue.mod: New test.
* gm2.dg/doc/examples/plugin/fail/doc-examples-plugin-fail.exp: New test.
+configure:16060: checking for atomic builtins for _Atomic_word
+[...]
+configure:16073: result: yes
..., and thus may revert the 'atomicity_dir=cpu/generic/atomicity_builtins'
hard-coding added in commit 059b5509c14904b55c37f659170240ae0d2c1c8e
"GCN, nvptx libstdc++: Force use of '__atomic' builtins [PR119645]".
The test was designed to pass with thumb2, but code generation changed
with the introduction of Low Overhead Loops, so the test can fail if
one overrides the flags when running the testsuite.
In addition, useless subtract / extension instructions require -O2 to
remove them (-O is not sufficient), so replace -O with -O2 in
dg-options.
arm_thumb2_ok_no_arm_v8_1m_lob does not do what the test needs (it can
fail because some flags conflict, rather than because lob are
supported, and we do not need to check runtime support in this test
anyway), so the patch reverts back to arm_thumb2_ok.
Finally, replace the scan-assembler directives with
check-function-bodies, checking both types of code generation (with
and without LOL). Depending on architecture version, the two insns
and r0, r1, r0, lsr #1
ands r3, r3, #255
can be swapped, so accept both orders.
Dongyan Chen [Mon, 12 May 2025 09:19:24 +0000 (17:19 +0800)]
RISC-V: Minimal support for ssnpm, smnpm and smmpm extensions.
This patch support ssnpm, smnpm, smmpm, sspm and supm extensions[1].
To enable GCC to recognize and process ssnpm, smnpm, smmpm, sspm and
supm extensions correctly at compile time.
Changes for v5:
- Fix the testsuite error in arch-50.c.
Changes for v4:
- Fix the code based on the commit id 9b13bea07706a7cae0185f8a860d67209308c050.
Changes for v3:
- Fix the error messages in gcc/testsuite/gcc.target/riscv/arch-46.c
Changes for v2:
- Add the sspm and supm extensions.
- Add the check_conflict_ext function to check the compatibility of ssnpm, smnpm, smmpm, sspm and supm extensions.
- Add the test cases for ssnpm, smnpm, smmpm, sspm and supm extensions.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::check_conflict_ext): New extension.
* config/riscv/riscv.opt: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-ss-1.c: New test.
* gcc.target/riscv/arch-ss-2.c: New test.
Dongyan Chen [Mon, 17 Mar 2025 14:23:18 +0000 (22:23 +0800)]
RISC-V: Support for zilsd and zclsd extensions.
This patch support zilsd and zclsd[1] extensions.
To enable GCC to recognize and process zilsd and zclsd extension correctly at compile time.
[1] https://github.com/riscv/riscv-zilsd
Changes for v2:
- Remove the addition of zilsd extension in gcc/common/config/riscv/riscv-ext-bitmask.def
- Fix a bug with zilsd and zclsd extension dependency in gcc/common/config/riscv/riscv-common.cc
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::check_conflict_ext): New extension.
* config/riscv/riscv.opt: Ditto.
Patrick Palka [Mon, 12 May 2025 13:15:34 +0000 (09:15 -0400)]
libstdc++: Fix constraint recursion in std::expected's operator== [PR119714]
This std::expected friend operator== is prone to constraint recursion
after CWG 2369 for the same reason as basic_const_iterator's comparison
operators were before the r15-7757-g4342c50ca84ae5 workaround. This
patch works around the constraint recursion here in a similar manner,
by making the function parameter of type std::expected dependent in a
trivial way.
PR libstdc++/119714
PR libstdc++/112490
libstdc++-v3/ChangeLog:
* include/std/expected (expected::operator==): Replace
non-dependent std::expected function parameter with a dependent
one of type expected<_Vp, _Er> where _Vp matches _Tp.
* testsuite/20_util/expected/119714.cc: New test.
Reviewed-by: Tomasz Kamiński <tkaminsk@redhat.com> Reviewed-by: Jonathan Wakely <jwakely@redhat.com>
Jonathan Wakely [Fri, 9 May 2025 09:23:05 +0000 (10:23 +0100)]
libstdc++: Remove #warning from <ciso646> for C++17 [PR120187]
Although <ciso646> was removed from C++20, it was not formally
deprecated in C++17. In contrast, <ctgmath>, <cstdalign>, etc. were
formally deprecated in C++17 before being removed in C++20.
Due to the widespread convention of including <ciso646> to detect
implementation-specific macros (such as _GLIBCXX_RELEASE) it causes
quite a lot of noise to issue deprecation warnings in C++17 mode. The
recommendation to include <version> instead does work for recent
compilers, even in C++17 mode, but isn't portable to older compilers
that don't provide <version> yet (e.g. GCC 8).
There are also potential objections to including <version> pre-C++20
when it wasn't defined by the standard. I don't have much sympathy for
this position, because including <ciso646> for implementation-specific
macros wasn't part of the C++17 standard either. It's no more
non-standard to rely on <version> being present and defining those
macros than to rely on <ciso646> defining them, and __has_include can be
used to detect whether <version> is present. However, <ciso646> is being
used in the wild by popular libraries like Abseil and we can't change
versions of those that have already been released.
This removes the #warning in <ciso646> for C++17 mode, so that we only
emit diagnostics for C++20 and later. With this change, including
<ciso646> in C++20 or later gives an error if _GLIBCXX_USE_DEPRECATED is
defined to zero, otherwise a warning if -Wdeprecated is enabled,
otherwise no diagnostic is given.
This also adds "@since C++11 (removed in C++20)" to the Doxygen @file
comments in all the relevant headers.
The test for <ciso646> needs to be updated to no longer expect a warning
for c++17_only. A new test is added to ensure that we get a warning
instead of an error when -D_GLIBCXX_USE_DEPRECATED=0 is not used.
libstdc++-v3/ChangeLog:
PR libstdc++/120187
* include/c_global/ciso646: Only give deprecated warning for
C++20 and later.
* include/c_global/ccomplex: Add @since to Doxygen comment.
* include/c_global/cstdalign: Likewise.
* include/c_global/cstdbool: Likewise.
* include/c_global/ctgmath: Likewise.
* testsuite/18_support/headers/ciso646/macros.cc: Remove
dg-warning for c++17_only effective target.
* testsuite/18_support/headers/ciso646/macros-2.cc: New test.
Reviewed-by: Tomasz Kamiński <tkaminsk@redhat.com>
Jonathan Wakely [Fri, 9 May 2025 16:50:52 +0000 (17:50 +0100)]
libstdc++: Restore std::scoped_lock for non-gthreads targets [PR120198]
This was a regression introduced with using version.def to define
feature test macros (r14-3248-g083b7f2833d71d). std::scoped_lock doesn't
need to depend on gthreads and so can be defined unconditionally, even
for freestanding.
libstdc++-v3/ChangeLog:
PR libstdc++/120198
* include/bits/version.def (scoped_lock): Do not depend on
gthreads or hosted.
* include/bits/version.h: Regenerate.
* include/std/mutex (scoped_lock): Update comment.
* testsuite/30_threads/scoped_lock/requirements/typedefs.cc:
Remove dg-require-gthreads and use custom lockable type instead
of std::mutex. Check that typedef is only present for a single
template argument.
Reviewed-by: Tomasz Kamiński <tkaminsk@redhat.com>
Richard Biener [Mon, 3 Mar 2025 09:09:25 +0000 (10:09 +0100)]
sync LTO streaming and hashing for accelerators and vector type mode
The following syncs up LTO tree hashing and streaming of TYPE_MODE
and DECL_MODE which long had a discrepancy for vector types and
recently got special-casing of streaming for offloading. Failure
to handle this results in less possible type merging to occur.
Note the compare step will still use TYPE_MODE and DECL_MODE.
* lto-streamer-out.cc (hash_tree): Hash TYPE_MODE_RAW.
When offloading hash modes as VOIDmode for aggregates
and vectors.
arm: doc: cleanup documentation references to iWMMXT extensions
Now that the iwmmxt extensions have been removed, clean up the
references to it in the documentation. We keep the
-mcpu/-mtune/-march references as these are still accepted by the
driver.
gcc/ChangeLog:
* doc/extend.texi: Remove the iwmmxt intrinsics.
* doc/md.texi: Remove the iwmmxt-related constraints.
Richard Earnshaw [Wed, 30 Apr 2025 10:45:28 +0000 (11:45 +0100)]
arm: remove iwmmxt-related attributes from machine description
Since we no-longer have any iwmxxt instructions, the iwmmxt-related
attributes can never be set. Consequently, the marvel-f-iwmmxt
scheduler is redundant as none of the pipes are ever used now.
Richard Earnshaw [Mon, 28 Apr 2025 16:15:45 +0000 (17:15 +0100)]
arm: remove support for the iwmmxt ABI variant.
The iwmmxt ABI is a variant of the ABI that supported passing certain
parameters and results in iwmmxt registers. But since we no-longer
support the instructions that can read and write these registers, the
ABI variant can no-longer be used.
gcc/ChangeLog:
* config.gcc (arm, --with-abi): Remove iwmmxt abi option.
* config/arm/arm.opt (enum ARM_ABI_IWMMXT): Remove.
* config/arm/arm.h (TARGET_IWMMXT_ABI): Delete.
(enum arm_pcs): Remove ARM_PCS_AAPCS_IWMMXT.
(FUNCTION_ARG_REGNO_P): Remove IWMMXT ABI support.
(CUMULATIVE_ARGS): Remove iwmmxt_nregs.
* config/arm/arm.cc (arm_options_perform_arch_sanity_checks):
Remove IWMMXT ABI checks.
(arm_libcall_value_1): Likewise.
(arm_function_value_regno_p): Likewise.
(arm_apply_result_size): Remove adjustment for IWMMXT ABI.
(arm_function_arg): Remove IWMMXT ABI support.
(arm_arg_partial_bytes): Likewise.
(arm_function_arg_advance): Likewise.
(arm_init_cumulative_args): Don't initialize iwmmxt_nregs.
* doc/invoke.texi (arm -mabi): Remove mention of the iwmmxt
ABI option.
* config/arm/arm-opts.h (enum arm_abi_type): Remove ARM_ABI_IWMMXT.
Richard Earnshaw [Mon, 28 Apr 2025 13:17:41 +0000 (14:17 +0100)]
arm: remove IWMMXT checks from MD files.
Remove the various checks for TARGET_IWMMXT{,2} and
TARGET_REALLY_IWMMXT{,2} from the remaining machine description files.
These flags can never be true now.
gcc/ChangeLog:
* config/arm/arm.md(attr arch): Remove iwmmxt and iwmmxt2.
Remove checks based on TARGET_REALLY_IWMMXT2 from all split
patterns.
(arm_movdi): Likewise.
(*arm_movt): Likewise.
(arch_enabled): Remove test for iwmmxt2.
* config/arm/constraints.md (y, z): Remove register constraints.
(Uy): Remove memory constraint.
* config/arm/thumb2.md (thumb2_pop_single): Remove check for
IWMMXT.
* config/arm/vec-common.md (mov<mode>): Remove check for IWMMXT.
(mul<mode>3): Likewise.
(xor<mode>3): Likewise.
(<absneg_str><mode>2): Likewise.
(@movmisalign<mode>): Likewise.
(@mve_<mve_insn>q_<supf><mode>): Likewise.
(vashl<mode>3): Likewise.
(vashr<mode>3): Likewise.
(vlshr<mode>3): Likewise.
(uavg<mode>3_ceil): Likewise.
Richard Earnshaw [Mon, 28 Apr 2025 10:03:34 +0000 (11:03 +0100)]
arm: remove iWMMX builtins support.
This is the first step of removing the various builtins for iwmmxt,
removing the builtins expansion code. It leaves a lot of code
elsewhere, but we'll clean that up in subsequent patches.
I'm not sure why safe_vector_operand would unconditionally try to
expand to an iwmmxt instruction if passed (const_int 0). Clearly
that's meaningless on other architectures, but perhaps this can't
happen elsewhere. Anyway, for now, just mark this as unreachable so
that we'll know about it if it ever happens.
Richard Earnshaw [Mon, 28 Apr 2025 13:55:43 +0000 (14:55 +0100)]
arm: treat -mcpu/arch=iwmmxt{,2} like XScale
Treat options that select iwmmxt variants as we would for xscale. We
leave the feature bits in for now, since they are still needed
elsewhere, but they are never enabled.
Also remove the remaining testsuite framework support for iwmmxt,
since this will never trigger now.
gcc/
* config/arm/arm-cpus.in (arch iwmmxt): treat in the same
way as we would treat XScale.
(arch iwmmxt2): Likewise.
(cpu xscale): Add aliases for iwmmxt and iwmmxt2.
(cpu iwmmxt): Delete.
(cpu iwmmxt2): Delete.
* config/arm/arm-generic.md (load_ldsched_xscale): Remove references
to iwmmxt.
(load_ldsched): Likewise.
* config/arm/arm-tables.opt: Regenerated.
* config/arm/arm-tune.md: Regenerated.
* doc/sourcebuild.texi (arm_iwmmxt_ok): Delete.
gcc/testsuite/ChangeLog:
* gcc.target/arm/ivopts.c: Remove test for iwmmxt
* lib/target-supports.exp
(check_effective_target_arm_iwmmxt_ok): Delete.
Richard Earnshaw [Mon, 28 Apr 2025 17:43:49 +0000 (18:43 +0100)]
arm: clarify the logic of SECONDARY_(INPUT/OUTPUT)_RELOAD_CLASS
The flattened logic of these functions and the complexity of the
numerous clauses makes it very difficult to understand what's written
in these macros. Additionally, SECONDARY_INPUT_RELOAD_CLASS was not
laid out with the correct formatting.
Add some parenthesis and re-indent to make the logic clearer.
No functional change.
gcc:
* config/arm/arm.h (SECONDARY_OUTPUT_RELOAD_CLASS): Add parentheis
and re-indent.
(SECONDARY_INPUT_RELOAD_CLASS): Likewise.
Thomas Schwinge [Mon, 12 May 2025 08:35:11 +0000 (10:35 +0200)]
libstdc++: Rewrite atomic builtin checks: Fix up 'GLIBCXX_ENABLE_BACKTRACE' check with 'size_t' [PR119667]
Fix-up for commit 86627faec10da53d7532805019e5296fcf15ac09
"libstdc++: Rewrite atomic builtin checks [PR70560]", which, for example, for
x86_64-pc-linux-gnu lost '-DHAVE_ATOMIC_FUNCTIONS=1' from 'BACKTRACE_CPPFLAGS'
due to:
configure:53554: checking for atomic builtins for libbacktrace
configure:53587: [...]/./gcc/xgcc -shared-libgcc -B[...]/./gcc -nostdinc++ -L[...]/x86_64-pc-linux-gnu/libstdc++-v3/src -L[...]/x86_64-pc-linux-gnu/libstdc++-v3/src/.libs -L[...]/x86_64-pc-linux-gnu/libstdc++-v3/libsupc++/.libs -B/x86_64-pc-linux-gnu/bin/ -B/x86_64-pc-linux-gnu/lib/ -isystem /x86_64-pc-linux-gnu/include -isystem /x86_64-pc-linux-gnu/sys-include -o conftest -O0 conftest.cpp >&5
conftest.cpp: In function 'int main()':
conftest.cpp:265:13: error: 'size_t' was not declared in this scope
265 | size_t s = 0;
| ^~~~~~
conftest.cpp:1:1: note: 'size_t' is defined in header '<cstddef>'; this is probably fixable by adding '#include <cstddef>'
1 | /* confdefs.h */
conftest.cpp:273:31: error: 's' was not declared in this scope
273 | __atomic_store_n(&s, s, __ATOMIC_RELEASE);
| ^
configure:53587: $? = 1
configure: failed program was:
| /* confdefs.h */
[...]
| int
| main ()
| {
|[...]
| size_t s = 0;
|[...]
| // backtrace_atomic_store_size_t
| __atomic_store_n(&s, s, __ATOMIC_RELEASE);
|[...]
| }
configure:53595: result: no
PR libstdc++/70560
PR libstdc++/119667
libstdc++-v3/
* acinclude.m4 (GLIBCXX_ENABLE_BACKTRACE): Use '__SIZE_TYPE__'
instead of 'size_t'.
* configure: Regenerate.
Jonathan Wakely [Fri, 9 May 2025 10:39:39 +0000 (11:39 +0100)]
libstdc++: Suppress GDB output from new 'skip' commands [PR118260]
I added some gdb.execute('skip -rfu ...') commands to the Python hook
loaded with libstdc++.so but this makes GDB print output like:
Function(s) ^std::(move|forward|as_const|(__)?addressof) will be skipped when stepping.
This probably aren't interesting to users, so this change suppresses
that output by capturing the output into the gdb.execute return value
(which is then ignored). An exception is thrown if the gdb.execute
command fails, so this doesn't suppress any errors which might be
meaningful to users or libstdc++ developers.
libstdc++-v3/ChangeLog:
PR libstdc++/118260
* python/hook.in: Suppress output from gdb.execute calls to
register skips.
Reviewed-by: Tomasz Kamiński <tkaminsk@redhat.com>
Jonathan Wakely [Thu, 8 May 2025 08:57:28 +0000 (09:57 +0100)]
libstdc++: Make dg-require-namedlocale work for more targets [PR65909]
As noted in the PR, some embedded targets do not support command-line
arguments, which means that the dg-require-namedlocale check always
fails. Use Sandra's suggestion of hardcoding the argument into the
executable instead of passing it as a command-line argument.
Realistically, those embedded targets probably don't support the named
locales anyway, but at least now the tests will be UNSUPPORTED for the
right reason.
libstdc++-v3/ChangeLog:
PR libstdc++/65909
* testsuite/lib/libstdc++.exp (check_v3_target_namedlocale):
Hardcode the locale name instead of passing it to the
executable. Do not hardcode buffer size for string.
Reviewed-by: Tomasz Kamiński <tkaminsk@redhat.com>
Jan Hubicka [Sun, 11 May 2025 21:49:11 +0000 (23:49 +0200)]
i386: Fix move costs in vectorizer cost model.
This patch complements the change to stv and uses COSTS_N_INSNS (...)/2
to convert move costs to COSTS_N_INSNS based costs used by vectorizer.
The patch makes pr9981 to XPASS so I removed xfail but it also makes
pr91446 fail. This is about SLP
typedef struct
{
unsigned long long width, height;
long long x, y;
} info;
extern void bar (info *);
void
foo (unsigned long long width, unsigned long long height,
long long x, long long y)
{
info t;
t.width = width;
t.height = height;
t.x = x;
t.y = y;
bar (&t);
}
With fixed cost the construction cost is now too large so vectorization does
not happen. This is the hack increasing cost to account integer->sse move which
I think we can handle incrementally.
gcc/ChangeLog:
* config/i386/i386.cc (ix86_widen_mult_cost): Use sse_op to cost
SSE integer addition.
(ix86_multiplication_cost): Use COSTS_N_INSNS (...)/2 to cost sse
loads.
(ix86_shift_rotate_cost): Likewise.
(ix86_vector_costs::add_stmt_cost): Likewise.
Max Filippov [Mon, 28 Apr 2025 01:05:20 +0000 (18:05 -0700)]
testsuite: xtensa: add support for effective_target_sync_*
Add new function check_effective_target_xtensa_atomic and use it in the
check_effective_target_sync_int_long and
check_effective_target_sync_char_short.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp
(check_effective_target_xtensa_atomic): New function.
(check_effective_target_sync_int_long)
(check_effective_target_sync_char_short): Add test for xtensa.
xtensa: Fix up unwanted spills of SFmode hard registers holding function arguments/returns
Until now (presumably after transition to LRA), hard registers storing
function arguments or return values were spilling undesirably when
TARGET_HARD_FLOAT is enabled.
/* example */
float test0(float a, float b) {
return a + b;
}
extern float foo(void);
float test1(void) {
return foo() * 3.14f;
}
Ultimately, that is because the costs of moving between integer and
floating-point hard registers are undefined and the default (large value)
is used. This patch fixes this.
Robert Dubner [Sun, 11 May 2025 17:43:32 +0000 (13:43 -0400)]
cobol: Eliminate padding bytes from cbl_declarative_t. [PR119377]
By changing the type of a variable in the cbl_declarative_t structure from "bool"
to "uint32_t", three uninitialized padding bytes were turned into initialized
bytes. This eliminates the valgrind error caused by those uninitialized values.
This is an interim fix, which expediently eliminates the valgrind problem. The
underlying design flaw, which involves turning a host-side C++ structure into
a run-time data block, is slated for complete replacement in the next few weeks.
Richard Biener [Sun, 11 May 2025 12:03:12 +0000 (14:03 +0200)]
tree-optimization/120211 - constrain LOOP_VINFO_EARLY_BREAKS_LIVE_IVS more
The PR120089 fix added more PHIs to LOOP_VINFO_EARLY_BREAKS_LIVE_IVS
but not checking that we only add PHIs with a latch argument. The
following adds this missing check.
PR tree-optimization/120211
* tree-vect-stmts.cc (vect_stmt_relevant_p): Only add PHIs
from the loop header to LOOP_VINFO_EARLY_BREAKS_LIVE_IVS.
* gcc.dg/vect/vect-early-break_135-pr120211.c: New testcase.
* gcc.dg/torture/pr120211-1.c: Likewise.
Thomas Koenig [Sun, 11 May 2025 05:40:23 +0000 (07:40 +0200)]
Do not generate formal arglist from actual if we have already resolved it.
This bug was another case of generating a formal arglist from
an actual one where we should not have done so. The fix is
straightforward: If we have resolved the formal arglist, we should
not generare a new one.
OK for trunk and backport?
gcc/fortran/ChangeLog:
PR fortran/120163
* gfortran.h: Add formal_resolved to gfc_symbol.
* resolve.cc (gfc_resolve_formal_arglist): Set it.
(resolve_function): Do not call gfc_get_formal_from_actual_arglist
if we already resolved a formal arglist.
(resolve_call): Likewise.
gcc/testsuite/ChangeLog:
PR fortran/120163
* gfortran.dg/interface_61.f90: New test.
Version log:
Using lowercase letters to present Profiles.
Using '_' as divsor between Profiles and other RISC-V extension.
Add descriptions in invoke.texi.
Checking if there exist '_' between Profiles and additional extensions.
Using std::string to avoid memory problems.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (struct riscv_profiles): New struct.
(riscv_subset_list::parse_profiles): New parser.
(riscv_subset_list::parse_base_ext): Ditto.
* config/riscv/riscv-subset.h: New def.
* doc/invoke.texi: New option descriptions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-49.c: New test.
* gcc.target/riscv/arch-50.c: New test.
* gcc.target/riscv/arch-51.c: New test.
* gcc.target/riscv/arch-52.c: New test.
Andrew Pinski [Sun, 11 May 2025 00:13:05 +0000 (17:13 -0700)]
testsuite: Fix pr119131-1.c for targets which emit a psabi warning for vectors of DFP [PR119909]
On PowerPC, there is a psabi warning for argument passing of a DFP vector.
We are not expecting this warning and we get a failure due to it.
Adding -Wno-psabi fixes the testcase.
Robert Dubner [Sat, 10 May 2025 22:05:29 +0000 (18:05 -0400)]
cobol: Auto-detect source format; some FldLiteralN; infer gcobc name. [PR119337]
This commit includes changes to the parser's auto-detection heuristic for source
code formatting. The heuristic now examines the line containing "program-id" to
determine whether the code is in ISO "fixed-form reference format", or ISO
"free-form reference format", or the IBM "extended source format".
Changes to the parser also changes to token processing.
On the code generation side, there are some changes that begin to process
numeric literals in order generate more efficient code using information known
at compilation time.
gcc/cobol/ChangeLog:
PR cobol/119337
* Make-lang.in: Change how $(FLEX) is invoked.
* cdf.y: Change parser tokens.
* gcobc: Changed how name is inferred for PR119337
* gcobol.1: Documentation for SOURCE format heuristic
* genapi.cc: Eliminate __gg__odo_violation.
(parser_display_field): Change comment.
* genutil.cc:Eliminate __gg__odo_violation.
(REFER): New macro for analyzing subscript/refmod calculations.
(get_integer_value): Likewise.
(get_data_offset): Eliminate __gg__odo_violation.
(scale_by_power_of_ten_N): Eliminate unnecessary var_decl_rdigits operation.
(refer_is_clean): Check for FldLiteralN.
(REFER_CHECK): Eliminate.
(refer_refmod_length): Streamline var_decl_rdigits processing.
(refer_fill_depends): Likewise.
(refer_offset): Streamline processing when FldLiteralN.
(refer_size): Tag with REFER macro.
(refer_size_dest): Likewise.
(refer_size_source): Likewise.
* genutil.h (get_integer_value): Delete declaration for odo_violation;
change comment for get_integer_value
(REFER_CHECK): Delete declaration.
(refer_check): Delete #define.
* lexio.cc (is_fixed_format): Changes for source format auto-detect.
(is_reference_format): Likewise.
(check_source_format_directive): Likewise.
(valid_sequence_area): Likewise.
(is_p): Likewise.
(is_program_id): Likewise.
(likely_nist_file): Likewise.
(infer_reference_format): Likewise.
(cdftext::free_form_reference_format): Likewise.
* parse.y: Token changes.
* parse_ante.h (class tokenset_t): Likewise.
(class current_tokens_t): Likewise.
(cmd_or_env_special_of): Likewise.
* scan.l: Likewise.
* scan_ante.h (bcomputable): Likewise.
(keyword_alias_add): Likewise.
(struct bint_t): Likewise.
(binary_integer_usage): Likewise.
(binary_integer_usage_of): Likewise.
* scan_post.h (start_condition_str): Likewise.
* symbols.cc (symbol_table_init): Formatting.
* symbols.h (struct cbl_field_data_t): Add "input" method to field_data_t.
(keyword_alias_add): Add forward declaration.
(binary_integer_usage_of): Likewise.
* token_names.h: Change list of tokens.
* util.cc (iso_cobol_word): Change list of COBOL reserved words.
Jan Hubicka [Sat, 10 May 2025 20:23:48 +0000 (22:23 +0200)]
i386: Fix some problems in stv cost model
this patch fixes some of problems with cosint in scalar to vector pass.
In particular
1) the pass uses optimize_insn_for_size which is intended to be used by
expanders and splitters and requires the optimization pass to use
set_rtl_profile (bb) for currently processed bb.
This is not done, so we get random stale info about hotness of insn.
2) register allocator move costs are all realtive to integer reg-reg move
which has cost of 2, so it is (except for size tables and i386)
a latency of instruction multiplied by 2.
These costs has been duplicated and are now used in combination with
rtx costs which are all based to COSTS_N_INSNS that multiplies latency
by 4.
Some of vectorizer costing contains COSTS_N_INSNS (move_cost) / 2
to compensate, but some new code does not. This patch adds compensatoin.
Perhaps we should update the cost tables to use COSTS_N_INSNS everywher
but I think we want to first fix inconsistencies. Also the tables will
get optically much longer, since we have many move costs and COSTS_N_INSNS
is a lot of characters.
3) variable m which decides how much to multiply integer variant (to account
that with -m32 all 64bit computations needs 2 instructions) is declared
unsigned which makes the signed computation of instruction gain to be
done in unsigned type and breaks i.e. for division.
4) I added integer_to_sse costs which are currently all duplicationof
sse_to_integer. AMD chips are asymetric and moving one direction is faster
than another. I will chance costs incremnetally once vectorizer part
is fixed up, too.
There are two failures gcc.target/i386/minmax-6.c and gcc.target/i386/minmax-7.c.
Both test stv on hasswell which no longer happens since SSE->INT and INT->SSE moves
are now more expensive.
There is only one instruction to convert:
Computing gain for chain #1...
Instruction gain 8 for 11: {r110:SI=smax(r116:SI,0);clobber flags:CC;}
Instruction conversion gain: 8
Registers conversion cost: 8 <- this is integer_to_sse and sse_to_integer
Total gain: 0
total gain used to be 4 since the patch doubles the conversion costs.
According to agner fog's tables the costs should be 1 cycle which is correct
here.
Instructions with latency info are those really different.
So the uncoverted code has sum of latencies 4 and real latency 3.
Converted code has sum of latencies 4 and real latency 3 (vmod+vpmaxsd+vmov).
So I do not quite see it should be a win.
There is also a bug in costing MIN/MAX
case ABS:
case SMAX:
case SMIN:
case UMAX:
case UMIN:
/* We do not have any conditional move cost, estimate it as a
reg-reg move. Comparisons are costed as adds. */
igain += m * (COSTS_N_INSNS (2) + ix86_cost->add);
/* Integer SSE ops are all costed the same. */
igain -= ix86_cost->sse_op;
break;
Now COSTS_N_INSNS (2) is not quite right since reg-reg move should be 1 or perhaps 0.
For Haswell cmov really is 2 cycles, but I guess we want to have that in cost vectors
like all other instructions.
I am not sure if this is really a win in this case (other minmax testcases seems to make
sense). I have xfailed it for now and will check if that affects specs on LNT testers.
I will proceed with similar fixes on vectorizer cost side. Sadly those introduces
quite some differences in the testuiste (partly triggered by other costing problems,
such as one of scatter/gather)
gcc/ChangeLog:
* config/i386/i386-features.cc
(general_scalar_chain::vector_const_cost): Add BB parameter; handle
size costs; use COSTS_N_INSNS to compute move costs.
(general_scalar_chain::compute_convert_gain): Use optimize_bb_for_size
instead of optimize_insn_for size; use COSTS_N_INSNS to compute move costs;
update calls of general_scalar_chain::vector_const_cost; use
ix86_cost->integer_to_sse.
(timode_immed_const_gain): Add bb parameter; use
optimize_bb_for_size_p.
(timode_scalar_chain::compute_convert_gain): Use optimize_bb_for_size_p.
* config/i386/i386-features.h (class general_scalar_chain): Update
prototype of vector_const_cost.
* config/i386/i386.h (struct processor_costs): Add integer_to_sse.
* config/i386/x86-tune-costs.h (struct processor_costs): Copy
sse_to_integer to integer_to_sse everywhere.
gcc/testsuite/ChangeLog:
* gcc.target/i386/minmax-6.c: xfail test that pmax is used.
* gcc.target/i386/minmax-7.c: xfall test that pmin is used.
Jakub Jelinek [Sat, 10 May 2025 19:20:09 +0000 (21:20 +0200)]
fortran: Fix debug info for unsigned(kind=1) and unsigned(kind=4) [PR120193]
As the following testcase shows, debug info for unsigned(kind=1)
and unsigned(kind=4) vars is wrong while unsigned(kind=2), unsigned(kind=8)
and unsigned(kind=16) look right.
Instead of objects having unsigned(kind=1) type they have character(kind=1)
and instead of unsigned(kind=4) they have character(kind=4).
This means in gdb e.g. unsigned(kind=1) :: a(2) variable initialized to
97 will print as 'aa' rather than (97, 97) etc.
While there can be just one unsigned_char_type_node and one
unsigned_type_node type, each can have arbitrary number of variants
(e.g. consider C
typedef unsigned char uc;
where uc is a variant type to unsigned char) or even distinct types
with different TYPE_MAIN_VARIANT.
The following patch uses a variant of the character(kind=4) type
for unsigned(kind=4) and a distinct type based on character(kind=1)
type for unsigned(kind=1). The reason for the latter is that
unsigned_char_type_node has TYPE_STRING_FLAG set on it, so it has
DW_AT_encoding DW_ATE_unsigned_char rather than DW_ATE_unsigned and
so the debugger then likes to print it as characters rather than numbers.
That is IMHO in Fortran desirable for character(kind=1) but not for
unsigned(kind=1). I've made sure TYPE_CANONICAL of the unsigned(kind=1)
type is still character(kind=1), so they are considered compatible by
the middle-end also e.g. for aliasing etc.
2025-05-10 Jakub Jelinek <jakub@redhat.com>
PR fortran/120193
* trans-types.cc (gfc_init_types): For flag_unsigned use
build_distinct_type_copy or build_variant_type_copy from
gfc_character_types[index_char] if index_char > -1 instead of
gfc_character_types[index_char] or
gfc_build_unsigned_type (&gfc_unsigned_kinds[index]).
Filip Kastl [Sat, 10 May 2025 16:30:23 +0000 (18:30 +0200)]
testsuite: Disable bit tests in aarch64/pr99988.c
My recent changes to bit-test switch lowering broke pr99988.c testcase.
The testcase assumes a switch will be lowered using jump tables. Make
the testcase run with -fno-bit-tests.
Filip Kastl [Sat, 10 May 2025 14:18:33 +0000 (16:18 +0200)]
gimple: Don't assert that switch has nondefault cases during lowering [PR120080]
I have mistakenly assumed that switch lowering cannot encounter a switch
with zero clusters. This patch removes the relevant assert and instead
gives up bit-test lowering when this happens.
PR tree-optimization/120080
gcc/ChangeLog:
* tree-switch-conversion.cc (bit_test_cluster::find_bit_tests):
Replace assert with return.
Shreya Munnangi [Sat, 10 May 2025 13:18:33 +0000 (07:18 -0600)]
[V2][RISC-V] Synthesize more efficient IOR/XOR sequences
So mvconst_internal's primary benefit is in constant synthesis not impacting
the combine budget in terms of the number of instructions it is willing to
combine together at any given time. The downside is mvconst_internal breaks
combine's toplevel costing model and as a result many other patterns have to be
implemented as define_insn_and_splits rather than the often more natural
define_splits.
This primarily impacts logical operations where we want to see the constant
operand and potentially simplify the logical with other nearby logicals or
shifts.
We can reduce our reliance on mvconst_internal and generate better code for
various cases by generating better initial code for logical operations.
So let's assume we have a inclusive-or of a register with a nontrivial
constant. Right now we will load the nontrivial constant into a new pseudo
(using multiple instructions), then emit a two register source ior operation.
For some cases we can just generate the code we want at expansion time.
Concretely let's take this testcase:
> unsigned long foo(unsigned long src) { return src | 0x8800000000000007; }
Right now we generate this code:
> li a5,-15
> slli a5,a5,59
> addi a5,a5,7
> or a0,a0,a5
The first three instructions are synthesizing the constant. The last
instruction performs the desired operation. But we can do better:
> ori a0,a0,7
> bseti a0,a0,59
> bseti a0,a0,63
Notice how we never even bother to synthesize the constant.
IOR/XOR are pretty simple and this patch focuses exclusively on those. We use
[x]ori to set whatever low 11 bits we need, then bset/binv for a small number
of higher bits. We use the cost of constant synthesis as our budget.
We also support a couple special cases. First, we might be able to rotate the
source value such that all the bits we want to manipulate are in the low 11
bits. So we rotate the source, manipulate the bits, then rotate things back to
where they belong. I didn't see this trigger in spec, but I did trivially find
a testcase where it was likely faster.
Second, we can have cases where we want to invert most of the bits, but a small
number are supposed to be preserved. We can pre-flip the bits we want to
preserve with binv, then invert the whole register with not (which puts the
bits to be preserved back in their original state).
I suspect there are likely a few more cases that could be improved, but the
patch should stand on its own now and getting it out of the way allows us to
focus on logical AND which is far tougher, but also more important in the task
of removing mvconst_internal.
As we're not removing mvconst_internal yet, this patch is mostly a nop. I did
look at spec before/after and didn't see anything particular interesting. I
also temporarily removed mvconst_internal and looked at spec before/after to
hopefully ensure we weren't missing anything obvious in the XOR/IOR cases.
Obviously that latter test showed all kinds of regressions with AND.
We're still working through implementation details on the AND case and
determining what bridge patterns we're going to need to ensure we don't
regress. But this XOR/IOR patch is in good enough shape that it can go
forward now.
Naturally this has been run through my tester (bootstrap & regression test is
in flight, but won't finish for many more hours). Obviously I'm quite
interested in anything spit out by the pre-commit CI system.
gcc/
* config/riscv/iterators.md (OPTAB): New iterator.
* config/riscv/predicates.md (arith_or_zbs_operand): Remove.
(reg_or_const_int_operand): New predicate.
* config/riscv/riscv-protos.h (synthesize_ior_xor): Prototype.
* config/riscv/riscv.cc (synthesize_ior_xor): New function.
* config/riscv/riscv.md (ior/xor expander): Use synthesize_ior_xor.
gcc/testsuite/
* gcc.target/riscv/ior-synthesis-1.c: New test.
* gcc.target/riscv/ior-synthesis-2.c: New test.
* gcc.target/riscv/xor-synthesis-1.c: New test.
* gcc.target/riscv/xor-synthesis-2.c: New test.
* gcc.target/riscv/xor-synthesis-3.c: New test.
which sets the default incoming stack boundary to this value, if it's not
overridden by other options or attributes.
Previously, GCC preferred 16-byte alignment like other platforms, unless
`-miamcu` was specified. However, the Microsoft x86 ABI only requires the
stack be aligned to 4-byte boundaries. Callback functions from MSVC code may
break this assumption by GCC (see reference below), causing local variables
to be misaligned.
For compatibility reasons, when the attribute `force_align_arg_pointer` is
attached to a function, it continues to ensure the stack is at least aligned
to a 16-byte boundary, as the documentation seems to suggest.
After this change, `STACK_REALIGN_DEFAULT` no longer has an effect on this
target, so it is removed.
Reference: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111107#c9 Signed-off-by: LIU Hao <lh_mouse@126.com> Signed-off-by: Jonathan Yong <10walls@gmail.com>
gcc/ChangeLog:
PR target/111107
* config/i386/cygming.h (PREFERRED_STACK_BOUNDARY_DEFAULT): Override
definition from i386.h.
(STACK_REALIGN_DEFAULT): Undefine, as it no longer has an effect.
* config/i386/i386.cc (ix86_update_stack_boundary): Force minimum
128-bit alignment if `force_align_arg_pointer`.
Alexandre Oliva [Thu, 8 May 2025 05:17:28 +0000 (02:17 -0300)]
[testsuite] [ppc] pr87600, pr89313: test for __PPC__ as well
gcc.dg/pr87600.h and gcc.dg/pr89313.c test for __powerpc__ and
__POWERPC__ to choose ppc register names, but ppc-elf defines neither;
it defines __PPC__, so test for that as well.
for gcc/testsuite/ChangeLog
* gcc.dg/pr87600.h (REG1, REG2): Test for __PPC__ as well.
* gcc.dg/pr89313.c (REG): Likewise.
Alexandre Oliva [Thu, 8 May 2025 05:17:38 +0000 (02:17 -0300)]
[testsuite] [ppc] block-cmp-8 should require powerpc64
gcc.target/powerpc/block-cmp-8.c is an execution test on ilp32. It
tests for support for the 64-bit ISA in the compiler, but not for the
ability to execute powerpc64 instructions, so the test fails on 32-bit
hardware. Require powerpc64 instead.
Alexandre Oliva [Sat, 10 May 2025 04:26:38 +0000 (01:26 -0300)]
vxworks: libstdc++: include ioLib.h for dup()
vxworks's dup function is not declared in unistd.h, but c++23/print.cc
expects to be able to call it if unistd.h is available. On vxworks,
the function is only declared in ioLib.h, so arrange to include it.
for libstdc++-v3/ChangeLog
* src/c++23/print.cc [__VXWORKS__]: Include ioLib.h.
Jason Merrill [Fri, 22 Nov 2024 15:05:51 +0000 (16:05 +0100)]
c++: visibility of instantiated template friends
In 20_util/variant/visit_member.cc, instantiation of the variant friend
declaration of __get for variant<test01()::X> was being marked as internal
because that variant specialization is itself internal. And therefore
check_module_override didn't try to merge it with the non-exported
namespace-scope declaration of __get.
But the template parms of variant are not part of the friend template's
identity, so they should not affect its visibility. If they are substituted
into the friend declaration, we'll handle that when looking at the
declaration itself.
This change no longer seems necessary to fix the testcase, but does still
seem correct. We definitely still get here during tsubst_friend_function.
gcc/cp/ChangeLog:
* decl2.cc (determine_visibility): Ignore args for friend templates.
but stretch_14 is a 8-bit boolean so the two forms are not equivalent, that
is to say dropping the "& 1" is wrong. It's another instance of the issue:
https://gcc.gnu.org/pipermail/gcc-patches/2020-November/558537.html
Here it's the reverse case: the bitwise NOT (~) is treated as logical by the
machinery in range-op.cc but the bitwise AND (&) is *not* treated as logical
by that of vr-values.cc, leading to the same problematic outcome.
gcc/
* vr-values.cc (simplify_using_ranges::simplify) <BIT_AND_EXPR>:
Do not call simplify_bit_ops_using_ranges for boolean types whose
precision is not 1.
gcc/testsuite/
* gnat.dg/opt106.adb: New test.
* gnat.dg/opt106_pkg1.ads, gnat.dg/opt106_pkg1.adb: New helper.
* gnat.dg/opt106_pkg2.ads, gnat.dg/opt106_pkg2.adb: Likewise.
projects / thirdparty / gcc.git / log
