Jack Chang [Thu, 4 Dec 2025 08:57:47 +0000 (16:57 +0800)]
drm/amd/display: DPCD for Selective Update
[Why&How]
Add flow to read selective update related info from DPCD,
and pass the info to DMUB.
Reviewed-by: Robin Chen <robin.chen@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Jack Chang <jack.chang@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
DP-HDMI dongles can execeed bandwidth requirements on high resolution
monitors. This can lead to pruning the high resolution modes.
HDMI 1.3 bumped the clock to 340MHz, but display code never matched it.
[How]
Set default to (DVI) 165MHz. Once HDMI display is identified update
to 340MHz.
Reported-by: Dianne Skoll <dianne@skoll.ca> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4780 Reviewed-by: Chris Park <chris.park@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Show link name in PSR status message
[Why]
The PSR message was moved in commit 4321742c394e ("drm/amd/display:
Move PSR support message into amdgpu_dm"). This message however shows
for every single link without showing which link is which. This can
send a confusing message to the user.
[How]
Add link name into the message.
Fixes: 4321742c394e ("drm/amd/display: Move PSR support message into amdgpu_dm") Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
Remove unused DMUB Replay set version command and related code.
Reviewed-by: Jack Chang <jack.chang@amd.com> Signed-off-by: Robin Chen <robin.chen@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
The update v3 path got refactored into new functions, which happened just
before the previous implementation was submitted, which resulted in the
optimizations not executing. This commit re-implements the same logic in
the new codepath.
Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Peichen Huang [Tue, 9 Dec 2025 02:47:06 +0000 (10:47 +0800)]
drm/amd/display: move panel replay out from edp
[WHY]
Panel Replay is not an eDP-specific function.
[HOW]
Create new Panel Replay source files and move the Panel Replay
functions from the eDP files to the new files. Additionally, create
a new link_service construct function to assign the related
function pointers.
Reviewed-by: Robin Chen <robin.chen@amd.com> Signed-off-by: Peichen Huang <PeiChen.Huang@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lang Yu [Fri, 19 Dec 2025 12:27:00 +0000 (20:27 +0800)]
drm/amdgpu/mes: Simplify hqd mask initialization
"adev->mes.compute_hqd_mask[i] = adev->gfx.disable_kq ? 0xF"
is actually incorrect for MEC with 8 queues per pipe.
Let's get rid of version check and hardcode, calculate hqd
mask with number of queues per pipe and number of gfx/compute
queues kernel used.
Currently, only MEC1 is used for both kernel/user compute queue.
To enable other MEC, we need to redistribute queues per pipe and
adjust queue resource shared with kfd that needs a separate patch.
Just skip other MEC for now to avoid potential issues.
v2: Force reserved queues to 0 if kernel queue is explicitly disabled.
Signed-off-by: Lang Yu <lang.yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Refactor amdgpu_gem_va_ioctl for Handling Last Fence Update and Timeline Management v7
When GPU memory mappings are updated, the driver returns a fence so
userspace knows when the update is finished.
The previous refactor could pick the wrong fence or rely on checks that
are not safe for GPU mappings that stay valid even when memory is
missing. In some cases this could return an invalid fence or cause fence
reference counting problems.
Fix this by (v5,v6, per Christian):
- Starting from the VM’s existing last update fence, so a valid and
meaningful fence is always returned even when no new work is required.
- Selecting the VM-level fence only for always-valid / PRT mappings using
the required combined bo_va + bo guard.
- Using the per-BO page table update fence for normal MAP and REPLACE
operations.
- For UNMAP and CLEAR, returning the fence provided by
amdgpu_vm_clear_freed(), which may remain unchanged when nothing needs
clearing.
- Keeping fence reference counting balanced.
v7: Drop the extra bo_va/bo NULL guard since
amdgpu_vm_is_bo_always_valid() handles NULL BOs correctly (including
PRT). (Christian)
This makes VM timeline fences correct and prevents crashes caused by
incorrect fence handling.
Fixes: bd8150a1b337 ("drm/amdgpu: Refactor amdgpu_gem_va_ioctl for Handling Last Fence Update and Timeline Management v4") Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Haoxiang Li [Thu, 8 Jan 2026 07:18:22 +0000 (15:18 +0800)]
drm/amdkfd: fix a memory leak in device_queue_manager_init()
If dqm->ops.initialize() fails, add deallocate_hiq_sdma_mqd()
to release the memory allocated by allocate_hiq_sdma_mqd().
Move deallocate_hiq_sdma_mqd() up to ensure proper function
visibility at the point of use.
Fixes: 11614c36bc8f ("drm/amdkfd: Allocate MQD trunk for HIQ and SDMA") Signed-off-by: Haoxiang Li <lihaoxiang@isrc.iscas.ac.cn> Signed-off-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 2 Dec 2025 15:12:41 +0000 (16:12 +0100)]
drm/amdgpu: Drop MMIO_REMAP domain bit and keep it Internal
"AMDGPU_GEM_DOMAIN_MMIO_REMAP" - Never activated as UAPI and it turned
out that this was to inflexible.
Allocate the MMIO_REMAP buffer object as a regular GEM BO and explicitly
move it into the fixed AMDGPU_PL_MMIO_REMAP placement at the TTM level.
This avoids relying on GEM domain bits for MMIO_REMAP, keeps the
placement purely internal, and makes the lifetime and pinning of the
global MMIO_REMAP BO explicit. The BO is pinned in TTM so it cannot be
migrated or evicted.
The corresponding free path relies on normal DRM teardown ordering,
where no further user ioctls can access the global BO once TTM teardown
begins.
v2 (Srini):
- Updated patch title.
- Drop use of AMDGPU_GEM_DOMAIN_MMIO_REMAP in amdgpu_ttm.c. The
MMIO_REMAP domain bit is removed from UAPI, so keep the MMIO_REMAP BO
allocation domain-less (bp.domain = 0) and rely on the TTM placement
(AMDGPU_PL_MMIO_REMAP) for backing/pinning.
- Keep fdinfo/mem-stats visibility for MMIO_REMAP by classifying BOs
based on bo->tbo.resource->mem_type == AMDGPU_PL_MMIO_REMAP, since the
domain bit is removed.
v3: Squash patches #1 & #3
Fixes: 056132483724 ("drm/amdgpu/uapi: Introduce AMDGPU_GEM_DOMAIN_MMIO_REMAP") Fixes: 2a7a794eb82c ("drm/amdgpu/ttm: Allocate/Free 4K MMIO_REMAP Singleton") Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Leo Liu <leo.liu@amd.com> Cc: Ruijing Dong <ruijing.dong@amd.com> Cc: David (Ming Qiang) Wu <David.Wu3@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Tue, 16 Dec 2025 05:50:54 +0000 (11:20 +0530)]
drm/amd/pm: Add smu message control block
Add message control block to abstract PMFW message protocol. Message
control block primarily carries message config which is set of register
addresses and message ops which abstracts the protocol of sending messages.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
YuBiao Wang [Wed, 12 Nov 2025 07:16:27 +0000 (15:16 +0800)]
drm/amdgpu: Skip loading SDMA_RS64 in VF
VFs use the PF SDMA ucode and are unable to load SDMA_RS64.
Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Signed-off-by: Victor Skvortsov <Victor.Skvortsov@amd.com> Reviewed-by: Gavin Wan <gavin.wan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Fixes: ce0478b02ed2 ("Merge tag 'v6.18-rc6' into drm-next") Signed-off-by: Peter Colberg <pcolberg@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
When an eGPU is unplugged the KFD topology should also be destroyed
for that GPU. This never happens because the fini_sw callbacks never
get to run. Run them manually before calling amdgpu_device_ip_fini_early()
when a device has already been disconnected.
This location is intentionally chosen to make sure that the kfd locking
refcount doesn't get incremented unintentionally.
Cc: kent.russell@amd.com Closes: https://community.frame.work/t/amd-egpu-on-linux/8691/33 Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mukesh Ogare [Sat, 20 Dec 2025 18:47:55 +0000 (02:47 +0800)]
drm/radeon: convert UVD v1.0 logging to drm_* helpers
Replace legacy DRM_ERROR()/DRM_INFO() logging in the UVD v1.0 code
with drm_err() and drm_info() helpers that take a struct drm_device.
Using drm_* logging provides proper device context in dmesg, which is
important for systems with multiple DRM devices, and aligns the radeon
driver with current DRM logging practices.
No functional change intended.
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Mukesh Ogare <mukeshogare871@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sun, 4 Jan 2026 14:37:56 +0000 (22:37 +0800)]
drm/amdgpu: Extend psp_skip_tmr for bare-metal and sriov
In SRIOV, guest drivers no longer setup/destory
VMR starting from mp0 v11_0_7.
In bare-metal, if boot-time TMR is enabled, some
generation (e.g., mp0 v13_0_x) don’t need runtime
TMR allocation but still require SETUP_TMR command
with tmr address 0 for backward compatibility.
some newer generations require neither SETUP_TMR nor
DESTROY_TMR and will return errors if they are sent.
Driver relies on boot_time_tmr and autoload_supported
to handle these cases correctly.
Philip Yang [Tue, 9 Dec 2025 23:15:23 +0000 (18:15 -0500)]
drm/amdgpu: Add helper to alloc GART entries
Add helper amdgpu_gtt_mgr_alloc/free_entries, define
GART_ENTRY_WITHOUT_BO_COLOR color for GART node not allocated with GTT
bo, then amdgpu_gtt_mgr_recover skip those mm_node.
Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Philip Yang [Thu, 4 Dec 2025 17:13:05 +0000 (12:13 -0500)]
drm/amdgpu: Fix gfx9 update PTE mtype flag
Fix copy&paste error, that should have been an assignment instead of an or,
otherwise MTYPE_UC 0x3 can not be updated to MTYPE_RW 0x1.
Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Tue, 2 Dec 2025 10:00:21 +0000 (15:30 +0530)]
drm/amd/pm: Use driver table for board temperature
GPU board and Baseboard temperatures come from system metrics table.
Driver keeps separate metrics table for both. Use the new driver table
structure to represent them.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Tue, 2 Dec 2025 15:05:51 +0000 (10:05 -0500)]
drm/amd/amdgpu: Port over some missing registers and bits from GC 10.1 to 10.3 (v2)
v2: Added SPI bits to sh_mask header
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lijo Lazar [Tue, 2 Dec 2025 07:07:32 +0000 (12:37 +0530)]
drm/amd/pm: Add smu driver table structure
For interfaces like gpu metrics, driver returns a formatted structure
based on IP version. Add a separate data structure for such tables which
also tracks the cache intervals.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Wang [Thu, 11 Dec 2025 04:46:52 +0000 (12:46 +0800)]
drm/amd/pm: fix pp_dpm_pcie wrong state issue for smu v13.0.0
put wrong value into incorrect data into following function,
which caused it to fail to match the correct item on smu v13.0.0:
smu_cmn_print_pcie_levels()
Fixes: a95f01edd80b ("drm/amd/pm: Use common helper for smuv13.0.0 dpm") Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Wang [Thu, 11 Dec 2025 04:49:35 +0000 (12:49 +0800)]
drm/amd/pm: fix pp_dpm_pcie wrong state issue for smu v13.0.7
put wrong value into incorrect data into following function,
which caused it to fail to match the correct item on smu v13.0.7:
smu_cmn_print_pcie_levels()
Fixes: b2debbbb60f1 ("drm/amd/pm: Use common helper for smuv13.0.7 dpm") Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Wang [Wed, 10 Dec 2025 12:33:43 +0000 (20:33 +0800)]
drm/amd/pm: fix pp_dpm_pcie wrong state issue for smu v14.0.2
put wrong value into incorrect data into following function,
which caused it to fail to match the correct item on smu v14.0.2:
smu_cmn_print_pcie_levels()
Fixes: 03d11f8564ca ("drm/amd/pm: Use common helper for smuv14.0.2 dpm") Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Julia Lawall [Tue, 30 Dec 2025 16:17:17 +0000 (17:17 +0100)]
drm/amdkfd: update outdated comment
The function acquire_packet_buffer() was renamed
kq_acquire_packet_buffer() by commit a5a4d68c9326 ("drm/amdkfd:
Eliminate unnecessary kernel queue function pointers"). Update
the comment accordingly.
Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Julia Lawall [Tue, 30 Dec 2025 17:53:53 +0000 (18:53 +0100)]
drm/amdgpu: update outdated comment
The function amdgpu_amdkfd_gpuvm_import_dmabuf() was split into
import_obj_create() and amdgpu_amdkfd_gpuvm_import_dmabuf_fd() in
commit 0188006d7c79 ("drm/amdkfd: Import DMABufs for interop
through DRM"). import_obj_create() now does the allocation for
the mem variable discussed in the comment.
Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Perry Yuan [Thu, 25 Dec 2025 08:43:49 +0000 (16:43 +0800)]
drm/amd/pm: Disable MMIO access during SMU Mode 1 reset
During Mode 1 reset, the ASIC undergoes a reset cycle and becomes
temporarily inaccessible via PCIe. Any attempt to access MMIO registers
during this window (e.g., from interrupt handlers or other driver threads)
can result in uncompleted PCIe transactions, leading to NMI panics or
system hangs.
To prevent this, set the `no_hw_access` flag to true immediately after
triggering the reset. This signals other driver components to skip
register accesses while the device is offline.
A memory barrier `smp_mb()` is added to ensure the flag update is
globally visible to all cores before the driver enters the sleep/wait
state.
Signed-off-by: Perry Yuan <perry.yuan@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Refactor amdgpu_gem_va_ioctl for Handling Last Fence Update and Timeline Management v4
This commit simplifies the amdgpu_gem_va_ioctl function, key updates
include:
- Moved the logic for managing the last update fence directly into
amdgpu_gem_va_update_vm.
- Introduced checks for the timeline point to enable conditional
replacement or addition of fences.
v2: Addressed review comments from Christian.
v3: Updated comments (Christian).
v4: The previous version selected the fence too early and did not manage its
reference correctly, which could lead to stale or freed fences being used.
This resulted in refcount underflows and could crash when updating GPU
timelines.
The fence is now chosen only after the VA mapping work is completed, and its
reference is taken safely. After exporting it to the VM timeline syncobj, the
driver always drops its local fence reference, ensuring balanced refcounting
and avoiding use-after-free on dma_fence.
Link: https://patchwork.freedesktop.org/patch/654669/ Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Sat, 6 Dec 2025 02:31:06 +0000 (03:31 +0100)]
drm/amd/display: Don't repeat DAC load detection
The analog link detection code path had already performed the
DAC load detection by the time the EDID read is attempted.
So there is no need to repeat the DAC load detection,
we can know that no display is connected if no EDID is read.
Fixes: ac1bb4952267 ("drm/amd/display: Use DAC load detection on analog connectors (v2)") Suggested-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Sat, 6 Dec 2025 02:31:04 +0000 (03:31 +0100)]
drm/amd/display: Add missing encoder setup to DACnEncoderControl
Apparently the DAC encoder needs to be set up before use.
The BIOS parser in DC did not support this so I assumed it was
not necessary, but the DAC doesn't work without it on some GPUs.
Fixes: 69b29b894660 ("drm/amd/display: Hook up DAC to bios_parser_encoder_control") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Sat, 6 Dec 2025 02:31:03 +0000 (03:31 +0100)]
drm/amd/display: Correct color depth for SelectCRTC_Source
Pass the correct enum values as expected by the VBIOS.
Previously the actual bit depth integer value was passed,
which was a mistake.
Fixes: 7fb4f254c8eb ("drm/amd/display: Add SelectCRTC_Source to BIOS parser") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Sat, 6 Dec 2025 02:31:02 +0000 (03:31 +0100)]
drm/amd/display: Pass proper DAC encoder ID to VBIOS
Similarly to the analog_engine field, add a new analog_id field
which contains the encoder ID of the analog encoder that
corresponds to the link encoder.
Previously, the default encoder ID of the link encoder was used,
which meant that we passed the wrong ID in case of DVI-I.
Fixes: 5834c33fd3f6 ("drm/amd/display: Add concept of analog encoders (v2)") Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 20 Aug 2025 14:07:38 +0000 (10:07 -0400)]
drm/amdgpu/gfx9: Implement KGQ ring reset
GFX ring resets work differently on pre-GFX10 hardware since
there is no MQD managed by the scheduler.
For ring reset, you need issue the reset via CP_VMID_RESET
via KIQ or MMIO and submit the following to the gfx ring to
complete the reset:
1. EOP packet with EXEC bit set
2. WAIT_REG_MEM to wait for the fence
3. Clear CP_VMID_RESET to 0
4. EVENT_WRITE ENABLE_LEGACY_PIPELINE
5. EOP packet with EXEC bit set
6. WAIT_REG_MEM to wait for the fence
Once those commands have completed the reset should
be complete and the ring can accept new packets.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Tested-by: Jiqian Chen <Jiqian.Chen@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Replace WAIT_REG_MEM with EVENT_WRITE flushes for all
shader types and ACQUIRE_MEM. That should accomplish
the same thing and avoid having to wait on a fence
preventing any issues with pipeline syncs during
queue resets.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 12 Dec 2025 16:46:48 +0000 (11:46 -0500)]
drm/amdgpu: avoid a warning in timedout job handler
Only set an error on the fence if the fence is not
signalled. We can end up with a warning if the
per queue reset path signals the fence and sets an error
as part of the reset, but fails to recover.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Pratap Nirujogi [Wed, 10 Dec 2025 01:22:15 +0000 (20:22 -0500)]
drm/amd/amdgpu: Fix SMU warning during isp suspend-resume
ISP mfd child devices are using genpd and the system suspend-resume
operations between genpd and amdgpu parent device which uses only
runtime suspend-resume are not in sync.
Linux power manager during suspend-resume resuming the genpd devices
earlier than the amdgpu parent device. This is resulting in the below
warning as SMU is in suspended state when genpd attempts to resume ISP.
WARNING: CPU: 13 PID: 5435 at drivers/gpu/drm/amd/amdgpu/../pm/swsmu/amdgpu_smu.c:398 smu_dpm_set_power_gate+0x36f/0x380 [amdgpu]
To fix this warning isp suspend-resume is handled as part of amdgpu
parent device suspend-resume instead of genpd sequence. Each ISP MFD
child device is marked as dev_pm_syscore_device to skip genpd
suspend-resume and use pm_runtime_force api's to suspend-resume
the devices when callbacks from amdgpu are received.
Co-developed-by: Gjorgji Rosikopulos <grosikop@amd.com> Signed-off-by: Gjorgji Rosikopulos <grosikop@amd.com> Signed-off-by: Bin Du <bin.du@amd.com> Signed-off-by: Pratap Nirujogi <pratap.nirujogi@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Taimur Hassan [Sat, 13 Dec 2025 02:32:55 +0000 (21:32 -0500)]
drm/amd/display: Promote DC to 3.2.364
This version brings along the following updates:
- Add frame skip feature support flag.
- Add sink EDID data null check.
- Update function name to link_detect_connection_type_analog.
- Fix mismatched unlock for DMUB HW lock in HWSS fast path.
- Fix P010, NV12, YUY2 scale down by four times failure.
- Fix and reenable UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL.
- Consolidate dmub fb info to a single struct.
- Add new fields to fams2 config.
- Update timing source enums.
- Add signal type check for dcn401 get_phyd32clk_src.
- Fix dsc eDP issue.
- Remove unnecessary divider update flag.
- Update dc_connection_dac_load to dc_connection_analog_load.
- Check NULL before calling dac_load_detection.
- Replace log macro for analog display detection.
Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Acked-by: Wayne Lin <Wayne.Lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Hung [Mon, 8 Dec 2025 19:18:02 +0000 (12:18 -0700)]
drm/amd/display: Replace log macro for analog display detection
link detection should use LINK_INFO() macro.
Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Hung [Mon, 8 Dec 2025 19:11:43 +0000 (12:11 -0700)]
drm/amd/display: Check NULL before calling dac_load_detection
dac_load_detection can be NULL in some scenario, so checking it before
calling.
Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Hung [Mon, 8 Dec 2025 19:09:08 +0000 (12:09 -0700)]
drm/amd/display: Update dc_connection_dac_load to dc_connection_analog_load
Update to a more accurate name dc_connection_analog_load.
Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cruise Hung [Fri, 5 Dec 2025 13:22:44 +0000 (21:22 +0800)]
drm/amd/display: Remove unnecessary divider update flag
[Why]
When transitioning from 640x480 at RBRx1 to HBR3x1,
both output pixel mode and pixel rate divider should update.
The needs_divider_update flag was only for 8b10b and 128b132b transition.
[How]
Remove needs_divider_update flag.
Reviewed-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Cruise Hung <Cruise.Hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Fix and reenable UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL
[Why]
Reenable new split implementation, previously partially reverted due
to issues with ODM on high-bandwidth displays 4k144Hz, resulting
in a corrupted gray screen.
Minimal flows require two separate commits, with extra intermediate
commit to enable seamless transitions, each followed by a swap. Since
new design requires commit to be run in execute and swap in cleanup
stage, an attempt was made to reorder them from CSCS (Commit-Swap-Commit-Swap)
to CCSS (Commit-Commit-Swap-Swap). Not only is this not viable, but
was implemented incorrectly as CCS, one swap missing.
[How]
* Change UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_NEW/CURRENT to execute
and cleanup one commit, then run UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS,
which closely matches old implementation where minimal flows fall back
to seamless.
* Fix uninitialized variable error.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kaier Hsueg [Thu, 4 Dec 2025 16:33:59 +0000 (00:33 +0800)]
drm/amd/display: Fix P010, NV12, YUY2 scale down by four times failure
[WHY]
When performing 4:1 downscaling with subsampled formats,
the SPL remainder distribution logic (+1) overrides the
upper layer’s aligned width, resulting in odd segment
widths and causing hang.
The upper layer alignment ensures the width is sufficient
and even, so SPL should not modify it further.
[HOW]
In dc_spl.c within calculate_mpc_slice_in_timing_active,
add an extra condition: Skip the remainder distribution
(+1) when use_recout_width_aligned is true.This change
respects the upper layer’s alignment decision, prevents
odd widths, and is a minimal, safe fix.
Reviewed-by: Joshua Aberback <joshua.aberback@amd.com> Signed-off-by: Kaier Hsueh <Kaier.Hsueh@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Fix mismatched unlock for DMUB HW lock in HWSS fast path
[Why]
The evaluation for whether we need to use the DMUB HW lock isn't the
same as whether we need to unlock which results in a hang when the
fast path is used for ASIC without FAMS support.
[How]
Store a flag that indicates whether we should use the lock and use
that same flag to specify whether unlocking is needed.
Reviewed-by: Swapnil Patel <swapnil.patel@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Hung [Tue, 2 Dec 2025 18:54:56 +0000 (11:54 -0700)]
drm/amd/display: Update function name to link_detect_connection_type_analog
[WHAT]
Update function "link_detect_analog" to a more accurate name
"link_detect_connection_type_analog".
Suggested-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
ChunTao Tso [Mon, 8 Dec 2025 09:36:57 +0000 (17:36 +0800)]
drm/amd/display: Add frame skip feature support flag
[WHY]
The set_replay_frame_skip_number() function should not execute when
the link does not support the Frame Skipping feature.
[HOW]
Add a new field `frame_skip_supported` to struct replay_config to
indicate whether the link supports frame skipping. Check this flag
at the beginning of set_replay_frame_skip_number() and return early
if the feature is not supported.
Reviewed-by: Robin Chen <robin.chen@amd.com> Signed-off-by: ChunTao Tso <chuntao.tso@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Wang [Mon, 15 Dec 2025 09:51:11 +0000 (17:51 +0800)]
drm/amd/pm: force send pcie parmater on navi1x
v1:
the PMFW didn't initialize the PCIe DPM parameters
and requires the KMD to actively provide these parameters.
v2:
clean & remove unused code logic (lijo)
Fixes: 1a18607c07bb ("drm/amd/pm: override pcie dpm parameters only if it is necessary") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4671 Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add documentation for the uma/carveout_options and uma/carveout
attributes in sysfs
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add UMA allocation interfaces to sysfs
Add a uma/ directory containing two sysfs files as interfaces to
inspect or change UMA carveout size. These files are:
- uma/carveout_options: a read-only file listing all the available
UMA allocation options and their index.
- uma/carveout: a file that is both readable and writable. On read,
it shows the index of the current setting. Writing a valid index
into this file allows users to change the UMA carveout size to that
option on the next boot.
Co-developed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
On some platforms, UMA allocation size can be set using the ATCS
methods. Add helper functions to interact with this functionality.
Co-developed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
projects / thirdparty / kernel / linux.git / log
