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3 weeks agodt-bindings: clock: qcom: document the Milos Video Clock Controller
Luca Weiss [Tue, 15 Jul 2025 07:19:10 +0000 (09:19 +0200)] 
dt-bindings: clock: qcom: document the Milos Video Clock Controller

Add bindings documentation for the Milos (e.g. SM7635) Video Clock
Controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-10-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: Add Graphics Clock controller (GPUCC) driver for Milos
Luca Weiss [Tue, 15 Jul 2025 07:19:09 +0000 (09:19 +0200)] 
clk: qcom: Add Graphics Clock controller (GPUCC) driver for Milos

Add support for the graphics clock controller found on Milos (e.g.
SM7635) based devices.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-9-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agodt-bindings: clock: qcom: document the Milos GPU Clock Controller
Luca Weiss [Tue, 15 Jul 2025 07:19:08 +0000 (09:19 +0200)] 
dt-bindings: clock: qcom: document the Milos GPU Clock Controller

Add bindings documentation for the Milos (e.g. SM7635) Graphics Clock
Controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-8-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: Add Display Clock controller (DISPCC) driver for Milos
Luca Weiss [Tue, 15 Jul 2025 07:19:07 +0000 (09:19 +0200)] 
clk: qcom: Add Display Clock controller (DISPCC) driver for Milos

Add support for the display clock controller found on Milos (e.g.
SM7635) based devices.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-7-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agodt-bindings: clock: qcom: document the Milos Display Clock Controller
Luca Weiss [Tue, 15 Jul 2025 07:19:06 +0000 (09:19 +0200)] 
dt-bindings: clock: qcom: document the Milos Display Clock Controller

Add bindings documentation for the Milos (e.g. SM7635) Display Clock
Controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-6-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: Add Camera Clock controller (CAMCC) driver for Milos
Luca Weiss [Tue, 15 Jul 2025 07:19:05 +0000 (09:19 +0200)] 
clk: qcom: Add Camera Clock controller (CAMCC) driver for Milos

Add support for the camera clock controller found on Milos (e.g. SM7635)
based devices.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-5-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agodt-bindings: clock: qcom: document the Milos Camera Clock Controller
Luca Weiss [Tue, 15 Jul 2025 07:19:04 +0000 (09:19 +0200)] 
dt-bindings: clock: qcom: document the Milos Camera Clock Controller

Add bindings documentation for the Milos (e.g. SM7635) Camera Clock Controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-4-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: Add Global Clock controller (GCC) driver for Milos
Luca Weiss [Tue, 15 Jul 2025 07:19:03 +0000 (09:19 +0200)] 
clk: qcom: Add Global Clock controller (GCC) driver for Milos

Add support for the global clock controller found on Milos (e.g. SM7635)
based devices.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-3-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agodt-bindings: clock: qcom: document the Milos Global Clock Controller
Luca Weiss [Tue, 15 Jul 2025 07:19:02 +0000 (09:19 +0200)] 
dt-bindings: clock: qcom: document the Milos Global Clock Controller

Add bindings documentation for the Milos (e.g. SM7635) Global Clock
Controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-2-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: common: Add support to register rcg dfs in qcom_cc_really_probe
Luca Weiss [Tue, 15 Jul 2025 07:19:01 +0000 (09:19 +0200)] 
clk: qcom: common: Add support to register rcg dfs in qcom_cc_really_probe

Add support to register the rcg dfs in qcom_cc_really_probe(). This
allows users to move the call from the probe function to static
properties.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-1-18f9faac4984@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: gcc-x1e80100: Add missing video resets
Stephan Gerhold [Wed, 9 Jul 2025 10:08:57 +0000 (12:08 +0200)] 
clk: qcom: gcc-x1e80100: Add missing video resets

Add the missing video resets that are needed for the iris video codec.
Copied from gcc-sm8550.c.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-5-ad1acf5674b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agodt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets
Stephan Gerhold [Wed, 9 Jul 2025 10:08:56 +0000 (12:08 +0200)] 
dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets

Add the missing video resets that are needed for the iris video codec.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-4-ad1acf5674b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: videocc-sm8550: Add separate frequency tables for X1E80100
Stephan Gerhold [Wed, 9 Jul 2025 10:08:55 +0000 (12:08 +0200)] 
clk: qcom: videocc-sm8550: Add separate frequency tables for X1E80100

X1E80100 videocc is identical to the one in SM8550, aside from slightly
different recommended PLL frequencies. Add the separate frequency tables
for that and apply them if the qcom,x1e80100-videocc compatible is used.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-3-ad1acf5674b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: videocc-sm8550: Allow building without SM8550/SM8560 GCC
Stephan Gerhold [Wed, 9 Jul 2025 10:08:54 +0000 (12:08 +0200)] 
clk: qcom: videocc-sm8550: Allow building without SM8550/SM8560 GCC

>From the build perspective, the videocc-sm8550 driver doesn't depend on
having one of the GCC drivers enabled. It builds just fine without the GCC
driver. In practice, it doesn't make much sense to have it enabled without
the GCC driver, but currently this extra dependency is inconsistent with
most of the other VIDEOCC entries in Kconfig. This can easily cause
confusion when you see the VIDEOCC options for some of the SoCs but not for
all of them.

Let's just drop the depends line to allow building the videocc driver
independent of the GCC selection. Compile testing with randconfig will also
benefit from keeping the dependencies minimal.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-2-ad1acf5674b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agodt-bindings: clock: qcom,sm8450-videocc: Document X1E80100 compatible
Stephan Gerhold [Wed, 9 Jul 2025 10:08:53 +0000 (12:08 +0200)] 
dt-bindings: clock: qcom,sm8450-videocc: Document X1E80100 compatible

X1E80100 videocc is largely identical to SM8550, but needs slightly
different PLL frequencies. Add a separate qcom,x1e80100-videocc compatible
to the existing schema used for SM8550.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-1-ad1acf5674b4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: tcsrcc-sm8650: Add support for Milos SoC
Luca Weiss [Mon, 7 Jul 2025 09:56:40 +0000 (11:56 +0200)] 
clk: qcom: tcsrcc-sm8650: Add support for Milos SoC

The Milos SoC has a very similar tcsrcc block, only TCSR_UFS_CLKREF_EN
uses different regs, and both TCSR_USB2_CLKREF_EN and
TCSR_USB3_CLKREF_EN are not present.

Modify these resources at probe if we're probing for Milos.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250707-sm7635-clocks-misc-v2-4-b49f19055768@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agodt-bindings: clock: qcom: document the Milos TCSR Clock Controller
Luca Weiss [Mon, 7 Jul 2025 09:56:39 +0000 (11:56 +0200)] 
dt-bindings: clock: qcom: document the Milos TCSR Clock Controller

Add bindings documentation for the Milos (e.g. SM7635) TCSR Clock
Controller.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250707-sm7635-clocks-misc-v2-3-b49f19055768@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: rpmh: Add support for RPMH clocks on Milos
Luca Weiss [Mon, 7 Jul 2025 09:56:38 +0000 (11:56 +0200)] 
clk: qcom: rpmh: Add support for RPMH clocks on Milos

Add support for RPMH clocks on Milos SoCs.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250707-sm7635-clocks-misc-v2-2-b49f19055768@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agodt-bindings: clock: qcom: Document the Milos RPMH Clock Controller
Luca Weiss [Mon, 7 Jul 2025 09:56:37 +0000 (11:56 +0200)] 
dt-bindings: clock: qcom: Document the Milos RPMH Clock Controller

Add bindings documentation for the Milos (e.g. SM7635) RPMH Clock
Controller.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250707-sm7635-clocks-misc-v2-1-b49f19055768@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: spmi-pmic-div: convert from round_rate() to determine_rate()
Brian Masney [Thu, 3 Jul 2025 23:22:30 +0000 (19:22 -0400)] 
clk: qcom: spmi-pmic-div: convert from round_rate() to determine_rate()

The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250703-clk-cocci-drop-round-rate-v1-6-3a8da898367e@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: smd-rpm: convert from round_rate() to determine_rate()
Brian Masney [Thu, 3 Jul 2025 23:22:29 +0000 (19:22 -0400)] 
clk: qcom: smd-rpm: convert from round_rate() to determine_rate()

The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250703-clk-cocci-drop-round-rate-v1-5-3a8da898367e@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: rpmh: convert from round_rate() to determine_rate()
Brian Masney [Thu, 3 Jul 2025 23:22:28 +0000 (19:22 -0400)] 
clk: qcom: rpmh: convert from round_rate() to determine_rate()

The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250703-clk-cocci-drop-round-rate-v1-4-3a8da898367e@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: rpm: convert from round_rate() to determine_rate()
Brian Masney [Thu, 3 Jul 2025 23:22:27 +0000 (19:22 -0400)] 
clk: qcom: rpm: convert from round_rate() to determine_rate()

The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250703-clk-cocci-drop-round-rate-v1-3-3a8da898367e@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: gcc-ipq4019: convert from round_rate() to determine_rate()
Brian Masney [Thu, 3 Jul 2025 23:22:26 +0000 (19:22 -0400)] 
clk: qcom: gcc-ipq4019: convert from round_rate() to determine_rate()

The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Link: https://lore.kernel.org/r/20250703-clk-cocci-drop-round-rate-v1-2-3a8da898367e@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: videocc-qcs615: Add QCS615 video clock controller driver
Taniya Das [Wed, 2 Jul 2025 09:04:29 +0000 (14:34 +0530)] 
clk: qcom: videocc-qcs615: Add QCS615 video clock controller driver

Add support for the video clock controller for video clients to
be able to request for the clocks on QCS615 platform.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-9-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agodt-bindings: clock: Add Qualcomm QCS615 Video clock controller
Taniya Das [Wed, 2 Jul 2025 09:04:28 +0000 (14:34 +0530)] 
dt-bindings: clock: Add Qualcomm QCS615 Video clock controller

Add DT bindings for the Video clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-8-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: gpucc-qcs615: Add QCS615 graphics clock controller driver
Taniya Das [Wed, 2 Jul 2025 09:04:27 +0000 (14:34 +0530)] 
clk: qcom: gpucc-qcs615: Add QCS615 graphics clock controller driver

Add support for the graphics clock controller for graphics clients to
be able to request for the clocks on QCS615 platform.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-7-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agodt-bindings: clock: Add Qualcomm QCS615 Graphics clock controller
Taniya Das [Wed, 2 Jul 2025 09:04:26 +0000 (14:34 +0530)] 
dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controller

Add DT bindings for the Graphics clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-6-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: dispcc-qcs615: Add QCS615 display clock controller driver
Taniya Das [Wed, 2 Jul 2025 09:04:25 +0000 (14:34 +0530)] 
clk: qcom: dispcc-qcs615: Add QCS615 display clock controller driver

Add support for the display clock controller for display clients to
be able to request for the clocks on QCS615 platform.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-5-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agodt-bindings: clock: Add Qualcomm QCS615 Display clock controller
Taniya Das [Wed, 2 Jul 2025 09:04:24 +0000 (14:34 +0530)] 
dt-bindings: clock: Add Qualcomm QCS615 Display clock controller

Add DT bindings for the Display clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-4-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: camcc-qcs615: Add QCS615 camera clock controller driver
Taniya Das [Wed, 2 Jul 2025 09:04:23 +0000 (14:34 +0530)] 
clk: qcom: camcc-qcs615: Add QCS615 camera clock controller driver

Add support for the camera clock controller for camera clients to
be able to request for camcc clocks on QCS615 platform.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-3-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agodt-bindings: clock: Add Qualcomm QCS615 Camera clock controller
Taniya Das [Wed, 2 Jul 2025 09:04:22 +0000 (14:34 +0530)] 
dt-bindings: clock: Add Qualcomm QCS615 Camera clock controller

Add DT bindings for the Camera clock on QCS615 platforms. Add the
relevant DT include definitions as well.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-2-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs
Taniya Das [Wed, 2 Jul 2025 09:04:21 +0000 (14:34 +0530)] 
clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLs

The alpha PLLs which slew to a new frequency at runtime would require
the PLL to calibrate at the mid point of the VCO. Add the new PLL ops
which can support the slewing of the PLL to a new frequency.

Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-1-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: gcc-ipq5018: fix GE PHY reset
George Moussalem [Mon, 30 Jun 2025 12:35:00 +0000 (16:35 +0400)] 
clk: qcom: gcc-ipq5018: fix GE PHY reset

The MISC reset is supposed to trigger a resets across the MDC, DSP, and
RX & TX clocks of the IPQ5018 internal GE PHY. So let's set the bitmask
of the reset definition accordingly in the GCC as per the downstream
driver.

Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/00743c3e82fa87cba4460e7a2ba32f473a9ce932
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-1-01be06378c15@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: gcc-qcm2290: Set HW_CTRL_TRIGGER for video GDSC
Loic Poulain [Fri, 13 Jun 2025 10:22:45 +0000 (12:22 +0200)] 
clk: qcom: gcc-qcm2290: Set HW_CTRL_TRIGGER for video GDSC

The venus video driver will uses dev_pm_genpd_set_hwmode() API to switch
the video GDSC to HW and SW control modes at runtime. This requires domain
to have the HW_CTRL_TRIGGER flag.

Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250613102245.782511-1-loic.poulain@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support
George Moussalem [Fri, 16 May 2025 12:36:10 +0000 (16:36 +0400)] 
clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support

The CMN PLL in IPQ5018 SoC supplies fixed clocks to XO, sleep, and the
ethernet block.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-3-389a6b30e504@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoclk: qcom: ipq5018: keep XO clock always on
George Moussalem [Fri, 16 May 2025 12:36:08 +0000 (16:36 +0400)] 
clk: qcom: ipq5018: keep XO clock always on

The XO clock must not be disabled to avoid the kernel trying to disable
the it. As such, keep the XO clock always on by flagging it as critical.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-1-389a6b30e504@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 weeks agoMerge branch '20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com' into clk-for...
Bjorn Andersson [Thu, 17 Jul 2025 04:04:22 +0000 (23:04 -0500)] 
Merge branch '20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com' into clk-for-6.17

Merge the IPQ5018 CMN PLL binding through a topic branch, to allow
merging the clock defines into DeviceTree branch as well.

3 weeks agodt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC
George Moussalem [Fri, 16 May 2025 12:36:09 +0000 (16:36 +0400)] 
dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC

The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference
input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and
ethernet (50Mhz) clocks.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 weeks agoclk: qcom: cmnpll: Add IPQ5424 SoC support
Luo Jie [Tue, 10 Jun 2025 10:35:19 +0000 (18:35 +0800)] 
clk: qcom: cmnpll: Add IPQ5424 SoC support

The CMN PLL in IPQ5424 SoC supplies the fixed clock to NSS at 300 MHZ
and to PPE at 375 MHZ. Other output clocks from CMN PLL on this SoC,
and their rates are same as IPQ9574.

Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-2-ceada8165645@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 weeks agoMerge branch '20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com' into clk...
Bjorn Andersson [Wed, 18 Jun 2025 22:16:38 +0000 (17:16 -0500)] 
Merge branch '20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com' into clk-for-6.17

Merge the IPQ5424 CMN PLL binding through a topic branch, to allow the
newly introduced clock constants to be made available to the DeviceTree
branch as well.

7 weeks agodt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC
Luo Jie [Tue, 10 Jun 2025 10:35:18 +0000 (18:35 +0800)] 
dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC

The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference
input clock. The output clocks are the same as IPQ9574 SoC, except
for the clock rate of output clocks to PPE and NSS.

Also, add the new header file to export the CMN PLL output clock
specifiers for IPQ5424 SoC.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: camcc-sc8180x: Add SC8180X camera clock controller driver
Satya Priya Kakitapalli [Mon, 12 May 2025 05:04:38 +0000 (10:34 +0530)] 
clk: qcom: camcc-sc8180x: Add SC8180X camera clock controller driver

Add support for the camera clock controller for camera clients to
be able to request for camcc clocks on SC8180X platform.

Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20250512-sc8180x-camcc-support-v4-3-8fb1d3265f52@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoMerge branch '20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com' into...
Bjorn Andersson [Wed, 11 Jun 2025 03:14:41 +0000 (22:14 -0500)] 
Merge branch '20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com' into clk-for-6.17

Merge topic branch with missing GCC clocks and the camera clock
controller for SC8180X through a topic branch, to make it available for
DeviceTree inclusion as well.

8 weeks agodt-bindings: clock: Add Qualcomm SC8180X Camera clock controller
Satya Priya Kakitapalli [Mon, 12 May 2025 05:04:37 +0000 (10:34 +0530)] 
dt-bindings: clock: Add Qualcomm SC8180X Camera clock controller

Add device tree bindings for the camera clock controller on
Qualcomm SC8180X platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agodt-bindings: clock: qcom: Add missing bindings on gcc-sc8180x
Satya Priya Kakitapalli [Mon, 12 May 2025 05:04:36 +0000 (10:34 +0530)] 
dt-bindings: clock: qcom: Add missing bindings on gcc-sc8180x

The multi-media AHB clocks are needed to create HW dependency in
the multimedia CC dt blocks and avoid any issues. They were not
defined in the initial bindings. Add all the missing clock bindings
for gcc-sc8180x.

Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250512-sc8180x-camcc-support-v4-1-8fb1d3265f52@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: dispcc-sm8750: Fix setting rate byte and pixel clocks
Krzysztof Kozlowski [Tue, 20 May 2025 09:07:42 +0000 (11:07 +0200)] 
clk: qcom: dispcc-sm8750: Fix setting rate byte and pixel clocks

On SM8750 the setting rate of pixel and byte clocks, while the parent
DSI PHY PLL, fails with:

  disp_cc_mdss_byte0_clk_src: rcg didn't update its configuration.

DSI PHY PLL has to be unprepared and its "PLL Power Down" bits in
CMN_CTRL_0 asserted.

Mark these clocks with CLK_OPS_PARENT_ENABLE to ensure the parent is
enabled during rate changes.

Cc: stable@vger.kernel.org
Fixes: f1080d8dab0f ("clk: qcom: dispcc-sm8750: Add SM8750 Display clock controller")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250520090741.45820-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: gcc-ipq8074: fix broken freq table for nss_port6_tx_clk_src
Christian Marangi [Thu, 22 May 2025 20:25:55 +0000 (22:25 +0200)] 
clk: qcom: gcc-ipq8074: fix broken freq table for nss_port6_tx_clk_src

With the conversion done by commit e88f03230dc0 ("clk: qcom: gcc-ipq8074:
rework nss_port5/6 clock to multiple conf") a Copy-Paste error was made
for the nss_port6_tx_clk_src frequency table.

This was caused by the wrong setting of the parent in
ftbl_nss_port6_tx_clk_src that was wrongly set to P_UNIPHY1_RX instead
of P_UNIPHY2_TX.

This cause the UNIPHY2 port to malfunction when it needs to be scaled to
higher clock. The malfunction was observed with the example scenario
with an Aquantia 10G PHY connected and a speed higher than 1G (example
2.5G)

Fix the broken frequency table to restore original functionality.

Cc: stable@vger.kernel.org
Fixes: e88f03230dc0 ("clk: qcom: gcc-ipq8074: rework nss_port5/6 clock to multiple conf")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20250522202600.4028-1-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: videocc: Use HW_CTRL_TRIGGER flag for video GDSC's
Taniya Das [Fri, 30 May 2025 10:31:59 +0000 (16:01 +0530)] 
clk: qcom: videocc: Use HW_CTRL_TRIGGER flag for video GDSC's

The video driver will be using the newly introduced
dev_pm_genpd_set_hwmode() API to switch the video GDSC to HW and SW
control modes at runtime.
Hence use HW_CTRL_TRIGGER flag instead of HW_CTRL for video GDSC's for
Qualcomm SoC SC7180, SDM845, SM7150, SM8150 and SM8450.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Vikash Garodia <quic_vgarodia@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Renjiang Han <quic_renjiang@quicinc.com>
Link: https://lore.kernel.org/r/20250530-switch_gdsc_mode-v5-1-657c56313351@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: Add video clock controller driver for SM6350
Konrad Dybcio [Mon, 24 Mar 2025 08:41:03 +0000 (09:41 +0100)] 
clk: qcom: Add video clock controller driver for SM6350

Add support for the video clock controller found on SM6350 based
devices.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konradybcio@kernel.org>
Co-developed-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250324-sm6350-videocc-v2-3-cc22386433f4@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: camcc-x1e80100: Move PLL & clk configuration to really probe
Jagadeesh Kona [Fri, 30 May 2025 13:20:57 +0000 (18:50 +0530)] 
clk: qcom: camcc-x1e80100: Move PLL & clk configuration to really probe

Camera PLLs on X1E80100 require both MMCX and MXC rails to be kept ON
to configure the PLLs properly. Hence move runtime power management,
PLL configuration and enabling critical clocks to qcom_cc_really_probe()
which ensures all required power domains are in enabled state before
configuring the PLLs or enabling the clocks.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> # Dell Inspiron
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-12-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: camcc-sm8650: Move PLL & clk configuration to really probe
Jagadeesh Kona [Fri, 30 May 2025 13:20:56 +0000 (18:50 +0530)] 
clk: qcom: camcc-sm8650: Move PLL & clk configuration to really probe

Camera PLLs on SM8650 require both MMCX and MXC rails to be kept ON
to configure the PLLs properly. Hence move runtime power management,
PLL configuration and enabling critical clocks to qcom_cc_really_probe()
which ensures all required power domains are in enabled state before
configuring the PLLs or enabling the clocks.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-11-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: camcc-sm8550: Move PLL & clk configuration to really probe
Jagadeesh Kona [Fri, 30 May 2025 13:20:55 +0000 (18:50 +0530)] 
clk: qcom: camcc-sm8550: Move PLL & clk configuration to really probe

Camera PLLs on SM8550 require both MMCX and MXC rails to be kept ON to
configure the PLLs properly. Hence move runtime power management, PLL
configuration and enabling critical clocks to qcom_cc_really_probe() which
ensures all required power domains are in enabled state before configuring
the PLLs or enabling the clocks.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-10-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: camcc-sm8450: Move PLL & clk configuration to really probe
Jagadeesh Kona [Fri, 30 May 2025 13:20:54 +0000 (18:50 +0530)] 
clk: qcom: camcc-sm8450: Move PLL & clk configuration to really probe

Camera PLLs on SM8450/SM8475 require both MMCX and MXC rails to be
kept ON to configure the PLLs properly. Hence move runtime power
management, PLL configuration and enable critical clocks to
qcom_cc_really_probe() which ensures all required power domains are in
enabled state before configuring the PLLs or enabling the clocks.

This change also removes the modelling for cam_cc_gdsc_clk and keeps it
always ON from probe since using CLK_IS_CRITICAL will prevent the clock
controller associated power domains from collapsing due to clock framework
invoking clk_pm_runtime_get() during prepare.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-9-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe
Jagadeesh Kona [Fri, 30 May 2025 13:20:53 +0000 (18:50 +0530)] 
clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe

Video PLLs on SM8550/SM8650 require both MMCX and MXC rails to be kept ON
to configure the PLLs properly. Hence move runtime power management, PLL
configuration and enable critical clocks to qcom_cc_really_probe() which
ensures all required power domains are in enabled state before configuring
the PLLs or enabling the clocks.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-8-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe
Jagadeesh Kona [Fri, 30 May 2025 13:20:52 +0000 (18:50 +0530)] 
clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe

Video PLLs on SM8450/SM8475 require both MMCX and MXC rails to be kept ON
to configure the PLLs properly. Hence move runtime power management, PLL
configuration and enable critical clocks to qcom_cc_really_probe() which
ensures all required power domains are in enabled state before configuring
the PLLs or enabling the clocks.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-7-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: common: Add support to configure clk regs in qcom_cc_really_probe
Jagadeesh Kona [Fri, 30 May 2025 13:20:51 +0000 (18:50 +0530)] 
clk: qcom: common: Add support to configure clk regs in qcom_cc_really_probe

Add support to configure PLLS and clk registers in qcom_cc_really_probe().
This ensures all required power domains are enabled and kept ON by runtime
PM code in qcom_cc_really_probe() before configuring the PLLS or clock
registers.

Add support for qcom_cc_driver_data struct to maintain the clock
controllers PLLs and CBCRs data, and a pointer of it can be stored in
clock descriptor structure. If any clock controller driver requires to
program some additional misc register settings, it can register the
clk_regs_configure() callback in the driver data.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-6-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: common: Handle runtime power management in qcom_cc_really_probe
Jagadeesh Kona [Fri, 30 May 2025 13:20:50 +0000 (18:50 +0530)] 
clk: qcom: common: Handle runtime power management in qcom_cc_really_probe

Add support for runtime power management in qcom_cc_really_probe() to
commonize it across all the clock controllers. The runtime power management
is not required for all clock controllers, hence handle the rpm based on
use_rpm flag in clock controller descriptor.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-5-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: clk-alpha-pll: Add support for common PLL configuration function
Taniya Das [Fri, 30 May 2025 13:20:49 +0000 (18:50 +0530)] 
clk: qcom: clk-alpha-pll: Add support for common PLL configuration function

To properly configure the PLLs on recent chipsets, it often requires more
than one power domain to be kept ON. The support to enable multiple power
domains is being added in qcom_cc_really_probe() and PLLs should be
configured post all the required power domains are enabled.

Hence integrate PLL configuration into clk_alpha_pll structure and add
support for qcom_clk_alpha_pll_configure() function which can be called
from qcom_cc_really_probe() to configure the clock controller PLLs after
all required power domains are enabled.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-4-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agodt-bindings: clock: qcom,sm8450-camcc: Move sc8280xp camcc to sa8775p camcc
Jagadeesh Kona [Fri, 30 May 2025 13:20:48 +0000 (18:50 +0530)] 
dt-bindings: clock: qcom,sm8450-camcc: Move sc8280xp camcc to sa8775p camcc

SC8280XP camcc only requires the MMCX power domain, unlike SM8450 camcc
which now supports both MMCX and MXC power domains. Hence move SC8280XP
camcc from SM8450 to SA8775P camcc, to have single power domain support.

SA8775P camcc doesn't support required-opps property currently but SC8280XP
camcc need that property,  so add required-opps based on SC8280XP camcc
conditional check in SA8775P camcc bindings.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-3-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agodt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains
Vladimir Zapolskiy [Fri, 30 May 2025 13:20:47 +0000 (18:50 +0530)] 
dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains

To configure the camera PLLs and enable the camera GDSCs on SM8450, SM8475,
SM8550 and SM8650 platforms, the MXC rail must be ON along with MMCX.
Therefore, update the camcc bindings to include the MXC power domain on
these platforms.

Fixes: 9cbc64745fc6 ("dt-bindings: clock: qcom: Add SM8550 camera clock controller")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-2-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agodt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain
Jagadeesh Kona [Fri, 30 May 2025 13:20:46 +0000 (18:50 +0530)] 
dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain

To configure the video PLLs and enable the video GDSCs on SM8450,
SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along
with MMCX. Therefore, update the videocc bindings to include
the MXC power domain on these platforms.

Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller")
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-1-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoLinux 6.16-rc1 v6.16-rc1
Linus Torvalds [Sun, 8 Jun 2025 20:44:43 +0000 (13:44 -0700)] 
Linux 6.16-rc1

2 months agoMerge tag 'turbostat-2025.06.08' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Sun, 8 Jun 2025 18:44:41 +0000 (11:44 -0700)] 
Merge tag 'turbostat-2025.06.08' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux

Pull turbostat updates from Len Brown:

 - Add initial DMR support, which required smarter RAPL probe

 - Fix AMD MSR RAPL energy reporting

 - Add RAPL power limit configuration output

 - Minor fixes

* tag 'turbostat-2025.06.08' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux:
  tools/power turbostat: version 2025.06.08
  tools/power turbostat: Add initial support for BartlettLake
  tools/power turbostat: Add initial support for DMR
  tools/power turbostat: Dump RAPL sysfs info
  tools/power turbostat: Avoid probing the same perf counters
  tools/power turbostat: Allow probing RAPL with platform_features->rapl_msrs cleared
  tools/power turbostat: Clean up add perf/msr counter logic
  tools/power turbostat: Introduce add_msr_counter()
  tools/power turbostat: Remove add_msr_perf_counter_()
  tools/power turbostat: Remove add_cstate_perf_counter_()
  tools/power turbostat: Remove add_rapl_perf_counter_()
  tools/power turbostat: Quit early for unsupported RAPL counters
  tools/power turbostat: Always check rapl_joules flag
  tools/power turbostat: Fix AMD package-energy reporting
  tools/power turbostat: Fix RAPL_GFX_ALL typo
  tools/power turbostat: Add Android support for MSR device handling
  tools/power turbostat.8: pm_domain wording fix
  tools/power turbostat.8: fix typo: idle_pct should be pct_idle

2 months agoMerge tag 'timers-cleanups-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sun, 8 Jun 2025 18:33:00 +0000 (11:33 -0700)] 
Merge tag 'timers-cleanups-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull timer cleanup from Thomas Gleixner:
 "The delayed from_timer() API cleanup:

  The renaming to the timer_*() namespace was delayed due massive
  conflicts against Linux-next. Now that everything is upstream finish
  the conversion"

* tag 'timers-cleanups-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  treewide, timers: Rename from_timer() to timer_container_of()

2 months agoMerge tag 'x86-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Sun, 8 Jun 2025 18:27:20 +0000 (11:27 -0700)] 
Merge tag 'x86-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 fixes from Thomas Gleixner:
 "A small set of x86 fixes:

   - Cure IO bitmap inconsistencies

     A failed fork cleans up all resources of the newly created thread
     via exit_thread(). exit_thread() invokes io_bitmap_exit() which
     does the IO bitmap cleanups, which unfortunately assume that the
     cleanup is related to the current task, which is obviously bogus.

     Make it work correctly

   - A lockdep fix in the resctrl code removed the clearing of the
     command buffer in two places, which keeps stale error messages
     around. Bring them back.

   - Remove unused trace events"

* tag 'x86-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  fs/resctrl: Restore the rdt_last_cmd_clear() calls after acquiring rdtgroup_mutex
  x86/iopl: Cure TIF_IO_BITMAP inconsistencies
  x86/fpu: Remove unused trace events

2 months agoMerge tag 'timers-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sun, 8 Jun 2025 18:25:13 +0000 (11:25 -0700)] 
Merge tag 'timers-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull timer fix from Thomas Gleixner:
 "Add the missing seq_file forward declaration in the timer namespace
  header"

* tag 'timers-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  timens: Add struct seq_file forward declaration

2 months agotools/power turbostat: version 2025.06.08
Len Brown [Sun, 8 Jun 2025 16:31:59 +0000 (12:31 -0400)] 
tools/power turbostat: version 2025.06.08

Add initial DMR support, which required smarter RAPL probe
Fix AMD MSR RAPL energy reporting
Add RAPL power limit configuration output
Minor fixes

Signed-off-by: Len Brown <len.brown@intel.com>
2 months agotools/power turbostat: Add initial support for BartlettLake
Zhang Rui [Fri, 18 Apr 2025 06:04:26 +0000 (14:04 +0800)] 
tools/power turbostat: Add initial support for BartlettLake

Add initial support for BartlettLake.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2 months agotools/power turbostat: Add initial support for DMR
Zhang Rui [Mon, 4 Mar 2024 06:54:40 +0000 (14:54 +0800)] 
tools/power turbostat: Add initial support for DMR

Add initial support for DMR.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2 months agotools/power turbostat: Dump RAPL sysfs info
Zhang Rui [Fri, 30 May 2025 06:01:31 +0000 (14:01 +0800)] 
tools/power turbostat: Dump RAPL sysfs info

for example:

intel-rapl:1: psys 28.0s:100W 976.0us:100W
intel-rapl:0: package-0 28.0s:57W,max:15W 2.4ms:57W
intel-rapl:0/intel-rapl:0:0: core disabled
intel-rapl:0/intel-rapl:0:1: uncore disabled
intel-rapl-mmio:0: package-0 28.0s:28W,max:15W 2.4ms:57W

[lenb: simplified format]

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
squish me

Signed-off-by: Len Brown <len.brown@intel.com>
2 months agotools/power turbostat: Avoid probing the same perf counters
Zhang Rui [Fri, 30 May 2025 00:09:28 +0000 (08:09 +0800)] 
tools/power turbostat: Avoid probing the same perf counters

For the RAPL package energy status counter, Intel and AMD share the same
perf_subsys and perf_name, but with different MSR addresses.

Both rapl_counter_arch_infos[0] and rapl_counter_arch_infos[1] are
introduced to describe this counter for different Vendors.

As a result, the perf counter is probed twice, and causes a failure in
in get_rapl_counters() because expected_read_size and actual_read_size
don't match.

Fix the problem by skipping the already probed counter.

Note, this is not a perfect fix. For example, if different
vendors/platforms use the same MSR value for different purpose, the code
can be fooled when it probes a rapl_counter_arch_infos[] entry that does
not belong to the running Vendor/Platform.

In a long run, better to put rapl_counter_arch_infos[] into the
platform_features so that this becomes Vendor/Platform specific.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2 months agotools/power turbostat: Allow probing RAPL with platform_features->rapl_msrs cleared
Zhang Rui [Sat, 17 May 2025 09:44:50 +0000 (17:44 +0800)] 
tools/power turbostat: Allow probing RAPL with platform_features->rapl_msrs cleared

platform_features->rapl_msrs describes the RAPL MSRs supported. While
RAPL Perf counters can be exposed from different kernel backend drivers,
e.g. RAPL MSR I/F driver, or RAPL TPMI I/F driver.

Thus, turbostat should first blindly probe all the available RAPL Perf
counters, and falls back to the RAPL MSR counters if they are listed in
platform_features->rapl_msrs.

With this, platforms that don't have RAPL MSRs can clear the
platform_features->rapl_msrs bits and use RAPL Perf counters only.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2 months agotools/power turbostat: Clean up add perf/msr counter logic
Zhang Rui [Sat, 17 May 2025 09:35:17 +0000 (17:35 +0800)] 
tools/power turbostat: Clean up add perf/msr counter logic

Increase the code readability by moving the no_perf/no_msr flag and the
cai->perf_name/cai->msr sanity checks into the counter probe functions.

No functional change.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2 months agotools/power turbostat: Introduce add_msr_counter()
Zhang Rui [Sat, 17 May 2025 07:58:51 +0000 (15:58 +0800)] 
tools/power turbostat: Introduce add_msr_counter()

probe_rapl_msr() is reused for probing RAPL MSR counters, cstate MSR
counters and MPERF/APERF/SMI MSR counters, thus its name is misleading.

Similar to add_perf_counter(), introduce add_msr_counter() to probe a
counter via MSR. Introduce wrapper function add_rapl_msr_counter() at
the same time to add extra check for Zero return value for specified
RAPL counters.

No functional change intended.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2 months agotools/power turbostat: Remove add_msr_perf_counter_()
Zhang Rui [Sat, 17 May 2025 09:40:08 +0000 (17:40 +0800)] 
tools/power turbostat: Remove add_msr_perf_counter_()

As the only caller of add_msr_perf_counter_(), add_msr_perf_counter()
just gives extra debug output on top. There is no need to keep both
functions.

Remove add_msr_perf_counter_() and move all the logic to
add_msr_perf_counter().

No functional change.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2 months agotools/power turbostat: Remove add_cstate_perf_counter_()
Zhang Rui [Sat, 17 May 2025 07:43:59 +0000 (15:43 +0800)] 
tools/power turbostat: Remove add_cstate_perf_counter_()

As the only caller of add_cstate_perf_counter_(),
add_cstate_perf_counter() just gives extra debug output on top. There is
no need to keep both functions.

Remove add_cstate_perf_counter_() and move all the logic to
add_cstate_perf_counter().

No functional change.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2 months agotools/power turbostat: Remove add_rapl_perf_counter_()
Zhang Rui [Sat, 17 May 2025 04:06:22 +0000 (12:06 +0800)] 
tools/power turbostat: Remove add_rapl_perf_counter_()

As the only caller of add_rapl_perf_counter_(), add_rapl_perf_counter()
just gives extra debug output on top. There is no need to keep both
functions.

Remove add_rapl_perf_counter_() and move all the logic to
add_rapl_perf_counter().

No functional change.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2 months agotools/power turbostat: Quit early for unsupported RAPL counters
Zhang Rui [Sat, 17 May 2025 02:26:14 +0000 (10:26 +0800)] 
tools/power turbostat: Quit early for unsupported RAPL counters

Quit early for unsupported RAPL counters.

No functional change.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2 months agotools/power turbostat: Always check rapl_joules flag
Zhang Rui [Fri, 30 May 2025 06:00:33 +0000 (14:00 +0800)] 
tools/power turbostat: Always check rapl_joules flag

rapl_joules bit should always be checked even if
platform_features->rapl_msrs is not set or no_msr flag is used.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2 months agotools/power turbostat: Fix AMD package-energy reporting
Gautham R. Shenoy [Thu, 29 May 2025 11:48:25 +0000 (17:18 +0530)] 
tools/power turbostat: Fix AMD package-energy reporting

commit 05a2f07db888 ("tools/power turbostat: read RAPL counters via
perf") that adds support to read RAPL counters via perf defines the
notion of a RAPL domain_id which is set to physical_core_id on
platforms which support per_core_rapl counters (Eg: AMD processors
Family 17h onwards) and is set to the physical_package_id on all the
other platforms.

However, the physical_core_id is only unique within a package and on
platforms with multiple packages more than one core can have the same
physical_core_id and thus the same domain_id. (For eg, the first cores
of each package have the physical_core_id = 0). This results in all
these cores with the same physical_core_id using the same entry in the
rapl_counter_info_perdomain[]. Since rapl_perf_init() skips the
perf-initialization for cores whose domain_ids have already been
visited, cores that have the same physical_core_id always read the
perf file corresponding to the physical_core_id of the first package
and thus the package-energy is incorrectly reported to be the same
value for different packages.

Note: This issue only arises when RAPL counters are read via perf and
not when they are read via MSRs since in the latter case the MSRs are
read separately on each core.

Fix this issue by associating each CPU with rapl_core_id which is
unique across all the packages in the system.

Fixes: 05a2f07db888 ("tools/power turbostat: read RAPL counters via perf")
Signed-off-by: Gautham R. Shenoy <gautham.shenoy@amd.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2 months agotools/power turbostat: Fix RAPL_GFX_ALL typo
Kaushlendra Kumar [Fri, 23 May 2025 08:06:59 +0000 (13:36 +0530)] 
tools/power turbostat: Fix RAPL_GFX_ALL typo

Fix typo in the currently unused RAPL_GFX_ALL macro definition.

Signed-off-by: Kaushlendra Kumar <kaushlendra.kumar@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2 months agotools/power turbostat: Add Android support for MSR device handling
Kaushlendra Kumar [Thu, 22 May 2025 08:49:46 +0000 (14:19 +0530)] 
tools/power turbostat: Add Android support for MSR device handling

It uses /dev/msrN device paths on Android instead of /dev/cpu/N/msr,
updates error messages and permission checks to reflect the Android
device path, and wraps platform-specific code with #if defined(ANDROID)
to ensure correct behavior on both Android and non-Android systems.
These changes improve compatibility and usability of turbostat on
Android devices.

Signed-off-by: Kaushlendra Kumar <kaushlendra.kumar@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
2 months agotools/power turbostat.8: pm_domain wording fix
Len Brown [Fri, 18 Apr 2025 21:54:39 +0000 (17:54 -0400)] 
tools/power turbostat.8: pm_domain wording fix

turbostat.8: clarify that uncore "domains" are Power Management domains,
aka pm_domains.

Signed-off-by: Len Brown <len.brown@intel.com>
2 months agotools/power turbostat.8: fix typo: idle_pct should be pct_idle
Len Brown [Wed, 9 Apr 2025 04:06:24 +0000 (00:06 -0400)] 
tools/power turbostat.8: fix typo: idle_pct should be pct_idle

idle_pct should be pct_idle

Signed-off-by: Len Brown <len.brown@intel.com>
2 months agoMerge tag 'perf-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Sun, 8 Jun 2025 18:07:33 +0000 (11:07 -0700)] 
Merge tag 'perf-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 perf fix from Thomas Gleixner:
 "A single fix for the x86 performance counters on Intel CPUs:

  The MSR offset calculations for fixed performance counters are stored
  at the wrong index in the configuration array causing the general
  purpose counter MSR offset to be overwritten, so both the general
  purpose and the fixed counters offsets are incorrect.

  Correct the array index calculation to fix that"

* tag 'perf-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/x86/intel: Fix incorrect MSR index calculations in intel_pmu_config_acr()

2 months agoMerge tag 'irq-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Sun, 8 Jun 2025 18:02:53 +0000 (11:02 -0700)] 
Merge tag 'irq-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq fix from Thomas Gleixner:
 "A single fix for the PCI/MSI code:

  The conversion to per device MSI domains created a MSI domain with
  size 1 instead of sizing it to the maximum possible number of MSI
  interrupts for the device. This "worked" as the subsequent allocations
  resized the domain, but the recent change to move the prepare() call
  into the domain creation path broke this works by chance mechanism.

  Size the domain properly at creation time"

* tag 'irq-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  PCI/MSI: Size device MSI domain with the maximum number of vectors

2 months agoMerge tag 'pull-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
Linus Torvalds [Sun, 8 Jun 2025 17:35:12 +0000 (10:35 -0700)] 
Merge tag 'pull-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs

Pull mount fixes from Al Viro:
 "Various mount-related bugfixes:

   - split the do_move_mount() checks in subtree-of-our-ns and
     entire-anon cases and adapt detached mount propagation selftest for
     mount_setattr

   - allow clone_private_mount() for a path on real rootfs

   - fix a race in call of has_locked_children()

   - fix move_mount propagation graph breakage by MOVE_MOUNT_SET_GROUP

   - make sure clone_private_mnt() caller has CAP_SYS_ADMIN in the right
     userns

   - avoid false negatives in path_overmount()

   - don't leak MNT_LOCKED from parent to child in finish_automount()

   - do_change_type(): refuse to operate on unmounted/not ours mounts"

* tag 'pull-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs:
  do_change_type(): refuse to operate on unmounted/not ours mounts
  clone_private_mnt(): make sure that caller has CAP_SYS_ADMIN in the right userns
  selftests/mount_setattr: adapt detached mount propagation test
  do_move_mount(): split the checks in subtree-of-our-ns and entire-anon cases
  fs: allow clone_private_mount() for a path on real rootfs
  fix propagation graph breakage by MOVE_MOUNT_SET_GROUP move_mount(2)
  finish_automount(): don't leak MNT_LOCKED from parent to child
  path_overmount(): avoid false negatives
  fs/fhandle.c: fix a race in call of has_locked_children()

2 months agoMerge tag '6.16-rc-part2-smb3-client-fixes' of git://git.samba.org/sfrench/cifs-2.6
Linus Torvalds [Sun, 8 Jun 2025 17:20:21 +0000 (10:20 -0700)] 
Merge tag '6.16-rc-part2-smb3-client-fixes' of git://git.samba.org/sfrench/cifs-2.6

Pull more smb client updates from Steve French:

 - multichannel/reconnect fixes

 - move smbdirect (smb over RDMA) defines to fs/smb/common so they will
   be able to be used in the future more broadly, and a documentation
   update explaining setting up smbdirect mounts

 - update email address for Paulo

* tag '6.16-rc-part2-smb3-client-fixes' of git://git.samba.org/sfrench/cifs-2.6:
  cifs: update internal version number
  MAINTAINERS, mailmap: Update Paulo Alcantara's email address
  cifs: add documentation for smbdirect setup
  cifs: do not disable interface polling on failure
  cifs: serialize other channels when query server interfaces is pending
  cifs: deal with the channel loading lag while picking channels
  smb: client: make use of common smbdirect_socket_parameters
  smb: smbdirect: introduce smbdirect_socket_parameters
  smb: client: make use of common smbdirect_socket
  smb: smbdirect: add smbdirect_socket.h
  smb: client: make use of common smbdirect.h
  smb: smbdirect: add smbdirect.h with public structures
  smb: client: make use of common smbdirect_pdu.h
  smb: smbdirect: add smbdirect_pdu.h with protocol definitions

2 months agoMerge tag 'trace-v6.16-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
Linus Torvalds [Sun, 8 Jun 2025 15:19:01 +0000 (08:19 -0700)] 
Merge tag 'trace-v6.16-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace

Pull more tracing fixes from Steven Rostedt:

 - Fix regression of waiting a long time on updating trace event filters

   When the faultable trace points were added, it needed task trace RCU
   synchronization.

   This was added to the tracepoint_synchronize_unregister() function.
   The filter logic always called this function whenever it updated the
   trace event filters before freeing the old filters. This increased
   the time of "trace-cmd record" from taking 13 seconds to running over
   2 minutes to complete.

   Move the freeing of the filters to call_rcu*() logic, which brings
   the time back down to 13 seconds.

 - Fix ring_buffer_subbuf_order_set() error path lock protection

   The error path of the ring_buffer_subbuf_order_set() released the
   mutex too early and allowed subsequent accesses to setting the
   subbuffer size to corrupt the data and cause a bug.

   By moving the mutex locking to the end of the error path, it prevents
   the reentrant access to the critical data and also allows the
   function to convert the taking of the mutex over to the guard()
   logic.

 - Remove unused power management clock events

   The clock events were added in 2010 for power management. In 2011 arm
   used them. In 2013 the code they were used in was removed. These
   events have been wasting memory since then.

 - Fix sparse warnings

   There was a few places that sparse warned about trace_events_filter.c
   where file->filter was referenced directly, but it is annotated with
   an __rcu tag. Use the helper functions and fix them up to use
   rcu_dereference() properly.

* tag 'trace-v6.16-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace:
  tracing: Add rcu annotation around file->filter accesses
  tracing: PM: Remove unused clock events
  ring-buffer: Fix buffer locking in ring_buffer_subbuf_order_set()
  tracing: Fix regression of filter waiting a long time on RCU synchronization

2 months agotreewide, timers: Rename from_timer() to timer_container_of()
Ingo Molnar [Fri, 9 May 2025 05:51:14 +0000 (07:51 +0200)] 
treewide, timers: Rename from_timer() to timer_container_of()

Move this API to the canonical timer_*() namespace.

[ tglx: Redone against pre rc1 ]

Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/aB2X0jCKQO56WdMt@gmail.com
2 months agoMerge tag 'kbuild-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy...
Linus Torvalds [Sat, 7 Jun 2025 17:05:35 +0000 (10:05 -0700)] 
Merge tag 'kbuild-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild

Pull Kbuild updates from Masahiro Yamada:

 - Add support for the EXPORT_SYMBOL_GPL_FOR_MODULES() macro, which
   exports a symbol only to specified modules

 - Improve ABI handling in gendwarfksyms

 - Forcibly link lib-y objects to vmlinux even if CONFIG_MODULES=n

 - Add checkers for redundant or missing <linux/export.h> inclusion

 - Deprecate the extra-y syntax

 - Fix a genksyms bug when including enum constants from *.symref files

* tag 'kbuild-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild: (28 commits)
  genksyms: Fix enum consts from a reference affecting new values
  arch: use always-$(KBUILD_BUILTIN) for vmlinux.lds
  kbuild: set y instead of 1 to KBUILD_{BUILTIN,MODULES}
  efi/libstub: use 'targets' instead of extra-y in Makefile
  module: make __mod_device_table__* symbols static
  scripts/misc-check: check unnecessary #include <linux/export.h> when W=1
  scripts/misc-check: check missing #include <linux/export.h> when W=1
  scripts/misc-check: add double-quotes to satisfy shellcheck
  kbuild: move W=1 check for scripts/misc-check to top-level Makefile
  scripts/tags.sh: allow to use alternative ctags implementation
  kconfig: introduce menu type enum
  docs: symbol-namespaces: fix reST warning with literal block
  kbuild: link lib-y objects to vmlinux forcibly even when CONFIG_MODULES=n
  tinyconfig: enable CONFIG_LD_DEAD_CODE_DATA_ELIMINATION
  docs/core-api/symbol-namespaces: drop table of contents and section numbering
  modpost: check forbidden MODULE_IMPORT_NS("module:") at compile time
  kbuild: move kbuild syntax processing to scripts/Makefile.build
  Makefile: remove dependency on archscripts for header installation
  Documentation/kbuild: Add new gendwarfksyms kABI rules
  Documentation/kbuild: Drop section numbers
  ...

2 months agoMerge tag 'sh-for-v6.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubi...
Linus Torvalds [Sat, 7 Jun 2025 17:00:03 +0000 (10:00 -0700)] 
Merge tag 'sh-for-v6.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux

Pull sh updates from John Paul Adrian Glaubitz:

 - replace the __ASSEMBLY__ with __ASSEMBLER__ macro in all headers
   since the latter is now defined automatically by both GCC and Clang
   when compiling assembly code (Thomas Huth)

 - set the default SPI mode for the ecovec24 board which became
   necessary after a new mode member as added to the sh_msiof_spi_info
   struct in cf9e4784f3bd ("spi: sh-msiof: Add slave mode support")
   (Geert Uytterhoeven)

 - remove unused variables in the kprobes code in
   kprobe_exceptions_notify() (Mike Rapoport)

* tag 'sh-for-v6.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux:
  sh: kprobes: Remove unused variables in kprobe_exceptions_notify()
  sh: ecovec24: Make SPI mode explicit
  sh: Replace __ASSEMBLY__ with __ASSEMBLER__ in all headers

2 months agoMerge tag 'loongarch-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuaca...
Linus Torvalds [Sat, 7 Jun 2025 16:56:18 +0000 (09:56 -0700)] 
Merge tag 'loongarch-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson

Pull LoongArch updates from Huacai Chen:

 - Adjust the 'make install' operation

 - Support SCHED_MC (Multi-core scheduler)

 - Enable ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS

 - Enable HAVE_ARCH_STACKLEAK

 - Increase max supported CPUs up to 2048

 - Introduce the numa_memblks conversion

 - Add PWM controller nodes in dts

 - Some bug fixes and other small changes

* tag 'loongarch-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson:
  platform/loongarch: laptop: Unregister generic_sub_drivers on exit
  platform/loongarch: laptop: Add backlight power control support
  platform/loongarch: laptop: Get brightness setting from EC on probe
  LoongArch: dts: Add PWM support to Loongson-2K2000
  LoongArch: dts: Add PWM support to Loongson-2K1000
  LoongArch: dts: Add PWM support to Loongson-2K0500
  LoongArch: vDSO: Correctly use asm parameters in syscall wrappers
  LoongArch: Fix panic caused by NULL-PMD in huge_pte_offset()
  LoongArch: Preserve firmware configuration when desired
  LoongArch: Avoid using $r0/$r1 as "mask" for csrxchg
  LoongArch: Introduce the numa_memblks conversion
  LoongArch: Increase max supported CPUs up to 2048
  LoongArch: Enable HAVE_ARCH_STACKLEAK
  LoongArch: Enable ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS
  LoongArch: Add SCHED_MC (Multi-core scheduler) support
  LoongArch: Add some annotations in archhelp
  LoongArch: Using generic scripts/install.sh in `make install`
  LoongArch: Add a default install.sh

2 months agoMerge tag 'sound-fix-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai...
Linus Torvalds [Sat, 7 Jun 2025 16:40:08 +0000 (09:40 -0700)] 
Merge tag 'sound-fix-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound

Pull sound fixes from Takashi Iwai:
 "A collection of fix patches for the 6.16-rc1 merge window.

  Most of changes are about ASoC, especially lots of AVS driver fixes.
  Larger LOCs are seen in TAS571x codec drivers, but the changes are
  trivial and safe. The rest are all device-specific small fixes"

* tag 'sound-fix-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (27 commits)
  ASoC: Intel: avs: boards: Fix rt5663 front end name
  ASoC: Intel: avs: Simplify verification of parse_int_array() result
  ALSA: usb-audio: Add implicit feedback quirk for RODE AI-1
  ALSA: hda: Ignore unsol events for cards being shut down
  ALSA: hda: Add new pci id for AMD GPU display HD audio controller
  ALSA: hda: cs35l41: Constify regmap_irq_chip
  ALSA: usb-audio: Add a quirk for Lenovo Thinkpad Thunderbolt 3 dock
  ASoC: ti: omap-hdmi: Re-add dai_link->platform to fix card init
  ASoC: pcm: Do not open FEs with no BEs connected
  ASoC: rt1320: fix speaker noise when volume bar is 100%
  ASoC: Intel: avs: Include missing string.h
  ASoC: Intel: avs: Verify content returned by parse_int_array()
  ASoC: Intel: avs: Verify kcalloc() status when setting constraints
  ASoC: Intel: avs: Fix paths in MODULE_FIRMWARE hints
  ASoC: Intel: avs: Fix possible null-ptr-deref when initing hw
  ASoC: Intel: avs: Fix PPLCxFMT calculation
  ASoC: Intel: avs: Fix deadlock when the failing IPC is SET_D0IX
  ASoC: codecs: hda: Fix RPM usage count underflow
  ASoC: amd: yc: Add support for Lenovo Yoga 7 16ARP8
  ASoC: tas571x: fix tas5733 num_controls
  ...

2 months agotracing: Add rcu annotation around file->filter accesses
Steven Rostedt [Sat, 7 Jun 2025 14:28:21 +0000 (10:28 -0400)] 
tracing: Add rcu annotation around file->filter accesses

Running sparse on trace_events_filter.c triggered several warnings about
file->filter being accessed directly even though it's annotated with __rcu.

Add rcu_dereference() around it and shuffle the logic slightly so that
it's always referenced via accessor functions.

Cc: Masami Hiramatsu <mhiramat@kernel.org>
Cc: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://lore.kernel.org/20250607102821.6c7effbf@gandalf.local.home
Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
2 months agoMerge tag 'ubifs-for-linus-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sat, 7 Jun 2025 14:24:07 +0000 (07:24 -0700)] 
Merge tag 'ubifs-for-linus-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs

Pull JFFS2 and UBIFS fixes from Richard Weinberger:
 "JFFS2:
   - Correctly check return code of jffs2_prealloc_raw_node_refs()

  UBIFS:
   - Spelling fixes"

* tag 'ubifs-for-linus-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs:
  jffs2: check jffs2_prealloc_raw_node_refs() result in few other places
  jffs2: check that raw node were preallocated before writing summary
  ubifs: Fix grammar in error message

2 months agosh: kprobes: Remove unused variables in kprobe_exceptions_notify()
Mike Rapoport [Sat, 17 May 2025 09:30:48 +0000 (12:30 +0300)] 
sh: kprobes: Remove unused variables in kprobe_exceptions_notify()

kbuild reports the following warning:

   arch/sh/kernel/kprobes.c: In function 'kprobe_exceptions_notify':
>> arch/sh/kernel/kprobes.c:412:24: warning: variable 'p' set but not used [-Wunused-but-set-variable]
     412 |         struct kprobe *p = NULL;
         |                        ^

The variable 'p' is indeed unused since the commit fa5a24b16f94
("sh/kprobes: Don't call the ->break_handler() in SH kprobes code")

Remove that variable along with 'kprobe_opcode_t *addr' which also
becomes unused after 'p' is removed.

Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202505151341.EuRFR22l-lkp@intel.com/
Fixes: fa5a24b16f94 ("sh/kprobes: Don't call the ->break_handler() in SH kprobes code")
Signed-off-by: Mike Rapoport (Microsoft) <rppt@kernel.org>
Reviewed-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
2 months agosh: ecovec24: Make SPI mode explicit
Geert Uytterhoeven [Fri, 2 May 2025 11:13:36 +0000 (13:13 +0200)] 
sh: ecovec24: Make SPI mode explicit

Commit cf9e4784f3bde3e4 ("spi: sh-msiof: Add slave mode support") added
a new mode member to the sh_msiof_spi_info structure, but did not update
any board files.  Hence all users in board files rely on the default
being host mode.

Make this unambiguous by configuring host mode explicitly.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Signed-off-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
2 months agosh: Replace __ASSEMBLY__ with __ASSEMBLER__ in all headers
Thomas Huth [Fri, 14 Mar 2025 07:10:03 +0000 (08:10 +0100)] 
sh: Replace __ASSEMBLY__ with __ASSEMBLER__ in all headers

While the GCC and Clang compilers already define __ASSEMBLER__
automatically when compiling assembly code, __ASSEMBLY__ is a
macro that only gets defined by the Makefiles in the kernel.
This can be very confusing when switching between userspace
and kernelspace coding, or when dealing with uapi headers that
rather should use __ASSEMBLER__ instead. So let's standardize on
the __ASSEMBLER__ macro that is provided by the compilers now.

This is a completely mechanical patch (done with a simple "sed -i"
statement).

Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: Rich Felker <dalias@libc.org>
Cc: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Cc: linux-sh@vger.kernel.org
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Signed-off-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>