Bob Duff [Tue, 28 May 2024 16:19:51 +0000 (12:19 -0400)]
ada: Rewrite generic formal/actual matching
...in preparation for implementing type inference for generic
parameters.
The main change is to do the "matching" computation early, and produce a
*constant* data structure (Gen_Assocs_Rec) to represent the matching
between each triple of unanalyzed formal, analyzed formal, and
corresponding actual. This will allow us to look at that data structure
more than once, which will be necessary for type inference.
Matching_Actual is removed; Match_Assocs is added.
Other changes include removal of global variables, splitting out
processing into subprograms, adding assertions, comment corrections,
and other general cleanups.
gcc/ada/
* expander.ads: Minor comment fixes.
* nlists.ads: Misc comment improvements.
* sem_aux.ads (First_Discriminant): Improve comment.
* sem_ch12.adb: Misc cleanups.
(Associations): New package containing type Gen_Assocs_Rec
to represent matchings, and function Match_Assocs to create the
Gen_Assocs_Rec constant.
(Analyze_Associations): Call Match_Assocs, and other major
changes related to that.
* sem_ch12.ads: Minor comment fixes.
* sem_ch3.adb: Minor comment fixes.
Steve Baird [Fri, 24 May 2024 21:14:03 +0000 (14:14 -0700)]
ada: Replace "All" argument to Extensions_Allowed pragma with "All_Extensions"
The argument to pragma Extensions_Allowed to enable all extensions is
no longer "All", but instead "All_Extensions".
gcc/ada/
* doc/gnat_rm/gnat_language_extensions.rst: Update documentation.
* doc/gnat_rm/implementation_defined_pragmas.rst: Update
documentation.
* errout.adb
(Error_Msg_GNAT_Extension): Update error message text.
* par-prag.adb: Update pragma parsing. This includes changing the
the name of the Check_Arg_Is_On_Or_Off formal parameter All_OK_Too
to All_Extensions_OK_Too.
* sem_prag.adb (Analyze_Pragma): In analyzing an
Extensions_Allowed pragma, replace uses of Name_All with
Name_All_Extensions; update a comment to reflect this.
* snames.ads-tmpl: Add Name_All_Extensions declaration.
* gnat_rm.texi: Regenerate.
Gary Dismukes [Thu, 23 May 2024 22:06:21 +0000 (22:06 +0000)]
ada: Crash on selected component of formal derived type in generic instance
The compiler crashes on an instantiation of a generic child unit G1.GC
that has a formal private extension P_Ext of a private type P declared
in the parent G1 whose full type has a component C, when analyzing a
selected component ACC.C whose prefix is of an access type coming from
an instantiation of another generic G2 where the designated type is
the formal type P_Ext (coming in from a formal type of G2).
gcc/ada/
* sem_ch4.adb (Try_Selected_Component_In_Instance): Reverse if_statement
clauses so that the testing for the special case of extensions of private
types in instance bodies is done first, followed by the testing for the case
of a parent type that's a generic actual type. In the extension case, apply
Base_Type to the type actual in the test of Used_As_Generic_Actual, and add
a test of Present (Parent_Subtype (Typ)).
Yannick Moy [Thu, 23 May 2024 12:39:19 +0000 (14:39 +0200)]
ada: Fix inlining of fixed-lower-bound array for GNATprove
Inlining in GNATprove may fail on a call to a subprogram with a formal
of an array type with fixed lower bound (a GNAT extension), because the
appropriate conversion is not used. Fix it.
Also fix the function that inserts an unchecked conversion, in cases where
it could skip sliding due to the target type having fixed lower bound.
gcc/ada/
* inline.adb (Establish_Actual_Mapping_For_Inlined_Call): In the
case of formal with a fixed lower bounds, insert appropriate
conversion like in the case of a constrained type.
* tbuild.adb (Unchecked_Convert_To): Do not skip the conversion
when it may involve sliding due to a type with fixed lower bound.
Eric Botcazou [Tue, 21 May 2024 06:40:06 +0000 (08:40 +0200)]
ada: Fix composition of primitive equality for untagged records with variant part
In Ada 2012, primitive equality operators of untagged record types compose
like those of tagged record types, but this has never been implemented for
untagged record types with a variant part.
gcc/ada/
* exp_ch4.adb (Expand_Composite_Equality): In the untagged record
case, always look for a user-defined equality operator in Ada 2012.
Doug Rupp [Sat, 3 Feb 2024 12:18:51 +0000 (04:18 -0800)]
ada: New pragma to default all interrupts to system.
New pragma Interrupts_System_By_Default defaults all interrupts/signals
to system (which will inhibit the installation of default signal handlers).
Note this changes the ALI format: it optionally adds an identifier to
the 'P' line (similar to pragma Unreserve_All_Interrupts). As per comment
in lib-writ spec regarding new modifiers, adding modifiers to the P line
is always safe. Also note this does not introduce a bootstrap problem
because the compiler and binder do not set the underlying _gl global nor
do they use this pragma.
gcc/ada/
* ali.ads (Interrupts_Default_To_System): New boolean.
(Interrupts_Default_To_System_Specified): New boolean.
* ali.adb (Interrupts_Default_To_System_Specified): Initialize.
(Interrupts_Default_To_System): Initialize.
(Scan_ALI): Processing for "ID".
* bindgen.adb: Coallesce comments on interrupt settings to ...
(Gen_Adainit): Import Interrupts_Default_To_System flag and set if
pragma specified.
(Gen_Output_File_Ada): Generate Local_Interrupt_States according
to pragma.
* init.c: ... here.
[vxworks] (__gnat_install_handler): Test for interrupt_state.
(__gl_interrupts_default_to_system): New global flag.
(__gnat_get_interrupt_State): return interrupt state according to
new global flag.
* lib-writ.ads: Document "ID".
* lib-writ.adb: Write out "ID".
* opt.ads (Interrupts_System_By_Default): New boolean, defaulted
to False.
* par-prag.adb (Pragma_Interrupts_System_By_Default): New.
* sem_prag.adb (Pragma_Interrupts_System_By_Default): Handle it.
(Pragma_Interrupts_System_By_Default): Default it.
* snames.ads-tmpl (Name_Interrupts_System_By_Default): New name.
(Pragma_Interrupts_System_By_Default): New
* libgnarl/s-intman__posix.adb (Initialize): Ensure the
Keep_Unmasked signal is sigset-able.
* doc/gnat_rm/implementation_defined_pragmas.rst: Document pragma
Interrupts_System_By_Default.
* doc/gnat_ugn/the_gnat_compilation_model.rst (Configuration
pragmas): Add Interrupts_System_By_Default. (Partition-Wide
Settings): Mention pragma Interrupts_System_By_Default.
* gnat_rm.texi: Regenerate.
* gnat_ugn.texi: Regenerate.
Eric Botcazou [Mon, 20 May 2024 16:08:07 +0000 (18:08 +0200)]
ada: Fix bogus error with "=" operator on array of private unchecked union
The code is legal and, therefore, must be accepted by the compiler, but it
must raise Program_Error at run time due to operands not having inferable
discriminants and a warning be given at compile time (RM B.3.3(22-23)).
gcc/ada/
* exp_ch4.adb (Expand_Array_Equality.Component_Equality): Copy the
Comes_From_Source flag from the original test to the new one, and
remove obsolete code dealing with unchecked unions.
* sem_util.adb (Has_Inferable_Discriminants): Return False for an
incomplete or private nominal subtype.
Eric Botcazou [Sun, 19 May 2024 13:45:34 +0000 (15:45 +0200)]
ada: Enforce strict alignment for array types with aliased component
This was initially implemented as part of AI12-001 but immediately disabled
because it breaks Florist on 32-bit platforms. However, it is possible to
reenable it in almost all cases without affecting Florist, and the -gnatd_l
switch can now be used to disable it again.
gcc/ada/
* debug.adb (d_l): Document new usage for the compiler.
* freeze.adb (Check_Strict_Alignment): Set the Strict_Alignment
flag on array types with aliased component, except if the
component size is equal to the storage unit or the -gnatd_l switch
is specified.
Eric Botcazou [Wed, 15 May 2024 21:56:44 +0000 (23:56 +0200)]
ada: Streamline propagation of controlled flags on types
The front-end maintains a set of 4 flags on (base) types that are used to
parameterize the implementation of controlled operations, and these flags
need to be propagated through composition and derivation. This is done
on a per-flag basis in the current implementation with a few loopholes.
This introduces a Propagate_Controlled_Flags routine to that effect, which
is modeled on the existing Propagate_Concurrent_Flags routine, and is used
in most cases to do the propagation. This also removes the handling of the
Finalize_Storage_Only flag from Inherit_Aspects_At_Freeze_Point, since the
associated aspect does not exist (only the pragma does).
gcc/ada/
* freeze.adb (Freeze_Array_Type): Call Propagate_Controlled_Flags
to propagate the controlled flags from the component to the array.
(Freeze_Record_Type): Propagate the Finalize_Storage_Only flag
from the components to the record.
* sem_ch3.adb (Analyze_Private_Extension_Declaration): Do not call
Propagate_Concurrent_Flags here but...
(Array_Type_Declaration): Tidy and call Propagate_Controlled_Flags
to propagate the controlled flags from the component to the array.
(Build_Derived_Private_Type): Do not propagate the controlled flags
manually here but...
(Build_Derived_Record_Type): ...call Propagate_Controlled_Flags to
propagate the controlled flags from parent to derived type.
(Build_Derived_Type): Likewise.
(Copy_Array_Base_Type_Attributes): Call Propagate_Controlled_Flags
to copy the controlled flags.
(Record_Type_Definition): Streamline the propagation of the
Finalize_Storage_Only flag from the components to the record.
* sem_ch7.adb (Preserve_Full_Attributes): Use Full_Base and call
Propagate_Controlled_Flags to copy the controlled flags.
* sem_ch9.adb (Analyze_Protected_Definition): Use canonical idiom
to compute Has_Controlled_Component.
(Analyze_Protected_Type_Declaration): Minor tweak.
* sem_ch13.adb (Inherit_Aspects_At_Freeze_Point): Do not deal with
Finalize_Storage_Only here.
* sem_util.ads (Propagate_Controlled_Flags): New declaration.
* sem_util.adb (Propagate_Controlled_Flags): New procedure.
Piotr Trojanek [Wed, 15 May 2024 08:58:33 +0000 (10:58 +0200)]
ada: Remove redundant conditions from freezing code
Code cleanup; behavior is unaffected.
gcc/ada/
* freeze.adb (Check_Current_Instance): This routine is only called
with parameter E being a type entity, so there is no need to check
for types just before the equality with E.
* sem_ch13.adb (Analyze_Aspect_Specifications): Regroup condition
to avoid unnecessary evaluation.
(Check_Aspect_At_End_Of_Declarations): If In_Instance is true,
then the routine exits early.
Eric Botcazou [Thu, 16 May 2024 13:24:11 +0000 (15:24 +0200)]
ada: Remove Max_Entry_Queue_Depth pragma/aspect
It was implemented apparently because a very early version of AI12-0164
that standardizes GNAT's Max_Queue_Length opted for the subtly different
moniker, but later versions of the AI use Max_Entry_Queue_Length instead.
gcc/ada/
* aspects.ads (Aspect_Id): Remove Aspect_Max_Entry_Queue_Depth.
(global arrays): Remove entry for it.
* exp_ch9.adb (Expand_N_Protected_Type_Declaration): Remove
reference to pragma Max_Entry_Queue_Depth in comment.
* par-prag.adb (Prag): Remove handling of
Pragma_Max_Entry_Queue_Depth.
* sem_ch13.adb (Analyze_Aspect_Specifications): Remove reference
to aspect Max_Entry_Queue_Depth in comment.
(Analyze_Aspect_Specifications): Remove processing of aspect
Max_Entry_Queue_Depth.
(Check_Aspect_At_Freeze_Point): Likewise.
* sem_prag.ads (Find_Related_Declaration_Or_Body): Remove
reference to pragma Max_Entry_Queue_Depth in comment.
* sem_prag.adb (Analyze_Pragma): Remove processing of pragma
Max_Entry_Queue_Depth.
(Sig_Flags): Remove entry for Pragma_Max_Entry_Queue_Depth.
* sem_util.adb (Get_Max_Queue_Length): Remove handling of pragma
Max_Entry_Queue_Depth.
(Has_Max_Queue_Length): Likewise.
* snames.ads-tmpl (Name_Max_Entry_Queue_Depth): Move back from
pragmas section to others section.
(Pragma_Id): Remove Pragma_Max_Entry_Queue_Depth.
The purpose of this patch is to make it possible to set up code
coverage for the GNAT front end in gnat1 using GNATcoverage. It is
not obvious how to have GNATcoverage instrument gnat1's main function,
and since the front end has a clear entry point (Gnat1drv), we add
manual instrumentation annotations there.
Eric Botcazou [Tue, 14 May 2024 20:06:17 +0000 (22:06 +0200)]
ada: Do not compute Has_Controlled_Component twice during freezing
The Has_Controlled_Component flag is computed twice during freezing when
expansion is enabled: in Freeze_Array_Type and Expand_Freeze_Array_Type
for array types, and in Freeze_Record_Type and Expand_Freeze_Record_Type
for record types.
This removes the latter computation in both cases, as well as moves the
computation of concurrent flags from the latter to the former places, which
happens to plug a loophole in the detection of errors when the No_Task_Parts
aspect is specified on peculiar types.
gcc/ada/
* exp_ch3.adb (Expand_Freeze_Array_Type): Do not propagate the
concurrent flags and the Has_Controlled_Component flag here.
(Expand_Freeze_Record_Type): Likewise.
* freeze.adb (Freeze_Array_Type): Propagate the concurrent flags.
(Freeze_Record_Type): Likewise.
* sem_util.adb (Has_Some_Controlled_Component): Adjust comment.
Viljar Indus [Mon, 13 May 2024 08:53:45 +0000 (11:53 +0300)]
ada: Change messages for -gnatw.v to warnings
Previously this switch was emitting only info messages
which was both confusing in terms of the name of the
switch that was used internally and externally.
gcc/ada/
* doc/gnat_ugn/building_executable_programs_with_gnat.rst: Update
documentation for -gnatw.v.
* sem_ch13.adb: Convert all -gnatw.v related messages to warnings.
* gnat_ugn.texi: Regenerate.
Viljar Indus [Fri, 10 May 2024 11:52:58 +0000 (14:52 +0300)]
ada: Convert -gnatw.n messages to warnings
Previously the messages produced by this warning switch
were info messages that were suppressed with the same
methods as regular warnings. Since info messages are now
separated as a completely different class of messages then
these messages should be converted back to warnings in order
for the previous pragma based suppression methods to work.
gcc/ada/
* doc/gnat_ugn/building_executable_programs_with_gnat.rst: Update
documentation for -gnatw.n switch.
* exp_util.adb: Convert info messages into warnings.
* gnat_ugn.texi: Regenerate.
Viljar Indus [Tue, 7 May 2024 13:35:30 +0000 (16:35 +0300)]
ada: Add switch for suppressing info messages
Add a separate switch -gnatis to suppress info messages
separately from warning messages that are controlled by
-gnatws.
gcc/ada/
* doc/gnat_ugn/building_executable_programs_with_gnat.rst: Add
entry for -gnatis.
* errout.adb (Error_Msg_Internal): Stop printing info messages if
-gnatis was used.
* opt.ads: Add Info_Suppressed flag to track whether info messages
should be suppressed.
* switch-c.adb: Add parsing for -gnatis.
* gnat_ugn.texi: Regenerate.
Viljar Indus [Mon, 6 May 2024 12:17:27 +0000 (15:17 +0300)]
ada: Treat Info-Warnings as Info messages
There was a general concept of info messages being a subset of
warnings. However that is no longer the case. Messages with an
info insertion character should be treated just as info messages.
gcc/ada/
* atree.ads: Remove Warning_Info_Messages.
* errout.adb: Remove various places where Warning_Info_Messages
was used.
* erroutc.adb: Remove various places where Warning_Info_Messages
was used. Create Error_Msg_Object objects with only an info
attribute if the message contained both info and warning insertion
characters. New method Has_Switch_Tag for detecting if a message
should have an error tag.
* errutil.adb: Create Error_Msg_Object objects with only an info
attribute if the message contained both info and warning insertion
characters.
Steve Baird [Fri, 10 May 2024 22:03:37 +0000 (15:03 -0700)]
ada: Improve preprocessor error handling.
In some cases, gnatprep would correctly emit an error message and then
incorrectly exit with a return code of zero, indicating success.
In some cases, a correct message about an error detected by the integrated
preprocessor would be accompanied by an incorrect message indicating that
a source file could not be found.
gcc/ada/
* gprep.adb (Process_Files.Process_One_File): When calling OS_Exit in an error
path, pass in a Status parameter of 1 instead of 0 (because 0
indicates success).
* lib-load.adb (Load_Main_Source): Do not emit a message about a missing source file
if other error messages were generated by calling Load_Source_File;
the file isn't missing - it failed preprocessing.
Piotr Trojanek [Thu, 1 Feb 2024 12:15:27 +0000 (13:15 +0100)]
ada: Fix list of attributes defined by Ada 2022
Recognize references to attributes Put_Image and Object_Size as
language-defined in Ada 2022 and implementation-defined in earlier
versions of Ada. Other attributes listed in Ada 2022 RM, K.2 and
currently implemented in GNAT are correctly categorized.
This change only affects code with restriction
No_Implementation_Attributes.
Hongyu Wang [Mon, 17 Jun 2024 02:34:01 +0000 (10:34 +0800)]
i386: Fix some ISA bit test in option_override
Adjust several new feature check in ix86_option_override_interal that
directly use TARGET_* instead of TARGET_*_P (opts->ix86_isa_flags)
to avoid cmdline option overrides target_attribute isa flag.
gcc/ChangeLog:
* config/i386/i386-options.cc (ix86_option_override_internal):
Use TARGET_*_P (opts->x_ix86_isa_flags*) instead of TARGET_*
for UINTR, LAM and APX_F.
gcc/testsuite/ChangeLog:
* gcc.target/i386/apx-ccmp-2.c: Remove -mno-apxf in option.
* gcc.target/i386/funcspec-56.inc: Drop uintr tests.
* gcc.target/i386/funcspec-6.c: Add uintr tests.
Paul Thomas [Thu, 20 Jun 2024 07:01:36 +0000 (08:01 +0100)]
Fortran: Auto array allocation with function dependencies [PR59104]
2024-06-20 Paul Thomas <pault@gcc.gnu.org>
gcc/fortran
PR fortran/59104
* dependency.cc (dependency_fcn, gfc_function_dependency): New
functions to detect dependency in array bounds and character
lengths on old style function results.
* dependency.h : Add prototype for gfc_function_dependency.
* error.cc (error_print): Remove trailing space.
* gfortran.h : Remove dummy_order and add fn_result_spec.
* symbol.cc : Remove declaration of next_dummy_order..
(gfc_set_sym_referenced): remove setting of symbol dummy order.
* trans-array.cc (gfc_trans_auto_array_allocation): Detect
non-dummy symbols with function dependencies and put the
allocation at the end of the initialization code.
* trans-decl.cc : Include dependency.h.
(decl_order): New function that determines uses the location
field of the symbol 'declared_at' to determine the order of two
declarations.
(gfc_defer_symbol_init): Call gfc_function_dependency to put
dependent symbols in the right part of the tlink chain. Use
the location field of the symbol declared_at to determine the
order of declarations.
(gfc_trans_auto_character_variable): Put character length
initialization of dependent symbols at the end of the chain.
* trans.cc (gfc_add_init_cleanup): Add boolean argument with
default false that determines whther an expression is placed at
the back or the front of the initialization chain.
* trans.h : Update the prototype for gfc_add_init_cleanup.
gcc/testsuite/
PR fortran/59104
* gfortran.dg/dependent_decls_2.f90: New test.
Richard Biener [Wed, 19 Jun 2024 10:57:27 +0000 (12:57 +0200)]
tree-optimization/114413 - SLP CSE after permute optimization
We currently fail to re-CSE SLP nodes after optimizing permutes
which results in off cost estimates. For gcc.dg/vect/bb-slp-32.c
this shows in not re-using the SLP node with the load and arithmetic
for both the store and the reduction. The following implements
CSE by re-bst-mapping nodes as finalization part of vect_optimize_slp.
I've tried to make the CSE part of permute materialization but it
isn't a very good fit there. I've not bothered to implement something
more complete, also handling external defs or defs without
SLP_TREE_SCALAR_STMTS.
I realize this might result in more BB SLP which in turn might slow
down code given costing for BB SLP is difficult (even that we now
vectorize gcc.dg/vect/bb-slp-32.c on x86_64 might be not a good idea).
This is nevertheless feeding more accurate info to costing which is
good.
PR tree-optimization/114413
* tree-vect-slp.cc (release_scalar_stmts_to_slp_tree_map):
New function, split out from ...
(vect_analyze_slp): ... here. Call it.
(vect_cse_slp_nodes): New function.
(vect_optimize_slp): Call it.
* gcc.dg/vect/bb-slp-32.c: Expect CSE and vectorization on x86.
Collin Funk [Wed, 19 Jun 2024 23:36:50 +0000 (16:36 -0700)]
build: Fix missing variable quotes and typo
When dlopen and pthread_create are in libc the variable is
set to "none required", therefore running configure will show
the following errors:
./configure: line 8997: test: too many arguments
./configure: line 8999: test: too many arguments
./configure: line 9003: test: too many arguments
./configure: line 9005: test: =: unary operator expected
ChangeLog:
PR bootstrap/115453
* configure.ac: Quote variable result of AC_SEARCH_LIBS. Fix
typo ac_cv_search_pthread_crate.
* configure: Regenerate.
Feng Xue [Sun, 16 Jun 2024 05:33:52 +0000 (13:33 +0800)]
vect: Tighten an assertion for lane-reducing in transform
According to logic of code nearby the assertion, all lane-reducing operations
should not appear, not just DOT_PROD_EXPR. Since "use_mask_by_cond_expr_p"
treats SAD_EXPR same as DOT_PROD_EXPR, and WIDEN_SUM_EXPR should not be allowed
by the following assertion "gcc_assert (commutative_binary_op_p (...))", so
tighten the assertion.
2024-06-16 Feng Xue <fxue@os.amperecomputing.com>
gcc/
* tree-vect-loop.cc (vect_transform_reduction): Change assertion to
cover all lane-reducing ops.
Feng Xue [Sun, 16 Jun 2024 05:21:13 +0000 (13:21 +0800)]
vect: Use an array to replace 3 relevant variables
It's better to place 3 relevant independent variables into array, since we
have requirement to access them via an index in the following patch. At the
same time, this change may get some duplicated code be more compact.
2024-06-16 Feng Xue <fxue@os.amperecomputing.com>
gcc/
* tree-vect-loop.cc (vect_transform_reduction): Replace vec_oprnds0/1/2
with one new array variable vec_oprnds[3].
Feng Xue [Sat, 15 Jun 2024 15:17:10 +0000 (23:17 +0800)]
vect: Add a function to check lane-reducing stmt
Add a utility function to check if a statement is lane-reducing operation,
which could simplify some existing code.
2024-06-16 Feng Xue <fxue@os.amperecomputing.com>
gcc/
* tree-vectorizer.h (lane_reducing_stmt_p): New function.
* tree-vect-slp.cc (vect_analyze_slp): Use new function
lane_reducing_stmt_p to check statement.
Patrick O'Neill [Tue, 18 Jun 2024 21:40:15 +0000 (14:40 -0700)]
RISC-V: Promote Zaamo/Zalrsc to a when using an old binutils
Binutils 2.42 and before don't support Zaamo/Zalrsc. When users specify
both Zaamo and Zalrsc, promote them to 'a' in the -march string.
This does not affect testsuite results for users with old versions of binutils.
Testcases that failed due to 'call'/isa string continue to fail after this PATCH
when using an old version of binutils.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add 'a' extension to
riscv_combine_info.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Jakub Jelinek [Wed, 19 Jun 2024 19:10:39 +0000 (21:10 +0200)]
bitint: Fix up lowering of COMPLEX_EXPR [PR115544]
We don't really support _Complex _BitInt(N), the only place we use
bitint complex types is for the .{ADD,SUB,MUL}_OVERFLOW internal function
results and COMPLEX_EXPR in the usual case should be either not present
yet because the ifns weren't folded and will be lowered, or optimized
into something simpler, because normally the complex bitint should be
used just for extracting the 2 subparts from it.
Still, with disabled optimizations it can occassionally happen that it
appears in the IL and that is why there is support for lowering those,
but it doesn't handle optimizing those too much, so if it uses SSA_NAME,
it relies on them having a backing VAR_DECL during the lowering.
This is normally achieves through the
&& ((is_gimple_assign (use_stmt)
&& (gimple_assign_rhs_code (use_stmt)
!= COMPLEX_EXPR))
|| gimple_code (use_stmt) == GIMPLE_COND)
hunk in gimple_lower_bitint, but as the following testcase shows, there
is one thing I've missed, the load optimization isn't guarded by the
above stuff. So, either we'd need to add support for loads to
lower_complexexpr_stmt, or because they should be really rare, this
patch just disables the load optimization if at least one load use is
a COMPLEX_EXPR (like we do already for PHIs, calls, asm).
2024-06-19 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/115544
* gimple-lower-bitint.cc (gimple_lower_bitint): Disable optimizing
loads used by COMPLEX_EXPR operands.
xtensa: Eliminate double MEMW insertions for volatile memory
This patch makes avoid inserting a MEMW instruction before a load/store
nstruction with volatile memory reference if there is already a MEMW
immediately before it.
gcc/ChangeLog:
* config/xtensa/xtensa.cc (print_operand):
When outputting MEMW before the instruction, check if the previous
instruction is already that.
Jonathan Wakely [Tue, 18 Jun 2024 19:59:25 +0000 (20:59 +0100)]
libstdc++: Add noexcept to some std::promise shared state internals
Making the state ready for a std::promise<void> only needs to move a
unique_ptr, which cannot throw. Make its call operator noexcept.
Similarly, making the state ready by storing an exception_ptr also can't
throw, so make that call operator noexcept too.
Jonathan Wakely [Tue, 18 Jun 2024 19:57:24 +0000 (20:57 +0100)]
libstdc++: Add conditional noexcept to std::pair default ctor
Most of std::pair constructors implemented using C++20 concepts have a
conditional noexcept-specifier, but the default constructor doesn't.
This fixes that.
Harald Anlauf [Tue, 18 Jun 2024 19:57:19 +0000 (21:57 +0200)]
Fortran: fix for CHARACTER(len=*) dummies with bind(C) [PR115390]
gcc/fortran/ChangeLog:
PR fortran/115390
* trans-decl.cc (gfc_conv_cfi_to_gfc): Move derivation of type sizes
for character via gfc_trans_vla_type_sizes to after character length
has been set.
gcc/testsuite/ChangeLog:
PR fortran/115390
* gfortran.dg/bind_c_char_11.f90: New test.
Andre Vieira [Wed, 19 Jun 2024 16:05:55 +0000 (17:05 +0100)]
arm: Add support for MVE Tail-Predicated Low Overhead Loops
This patch adds support for MVE Tail-Predicated Low Overhead Loops by using the
doloop funcitonality added to support predicated vectorized hardware loops.
gcc/ChangeLog:
* config/arm/arm-protos.h (arm_target_bb_ok_for_lob): Change
declaration to pass basic_block.
(arm_attempt_dlstp_transform): New declaration.
* config/arm/arm.cc (TARGET_LOOP_UNROLL_ADJUST): Define targethook.
(TARGET_PREDICT_DOLOOP_P): Likewise.
(arm_target_bb_ok_for_lob): Adapt condition.
(arm_mve_get_vctp_lanes): New function.
(arm_dl_usage_type): New internal enum.
(arm_get_required_vpr_reg): New function.
(arm_get_required_vpr_reg_param): New function.
(arm_get_required_vpr_reg_ret_val): New function.
(arm_mve_get_loop_vctp): New function.
(arm_mve_insn_predicated_by): New function.
(arm_mve_across_lane_insn_p): New function.
(arm_mve_load_store_insn_p): New function.
(arm_mve_impl_pred_on_outputs_p): New function.
(arm_mve_impl_pred_on_inputs_p): New function.
(arm_last_vect_def_insn): New function.
(arm_mve_impl_predicated_p): New function.
(arm_mve_check_reg_origin_is_num_elems): New function.
(arm_mve_dlstp_check_inc_counter): New function.
(arm_mve_dlstp_check_dec_counter): New function.
(arm_mve_loop_valid_for_dlstp): New function.
(arm_predict_doloop_p): New function.
(arm_loop_unroll_adjust): New function.
(arm_emit_mve_unpredicated_insn_to_seq): New function.
(arm_attempt_dlstp_transform): New function.
* config/arm/arm.opt (mdlstp): New option.
* config/arm/iterators.md (dlstp_elemsize, letp_num_lanes,
letp_num_lanes_neg, letp_num_lanes_minus_1): New attributes.
(DLSTP, LETP): New iterators.
* config/arm/mve.md (predicated_doloop_end_internal<letp_num_lanes>,
dlstp<dlstp_elemsize>_insn): New insn patterns.
* config/arm/thumb2.md (doloop_end): Adapt to support tail-predicated
loops.
(doloop_begin): Likewise.
* config/arm/types.md (mve_misc): New mve type to represent
predicated_loop_end insn sequences.
* config/arm/unspecs.md:
(DLSTP8, DLSTP16, DLSTP32, DSLTP64,
LETP8, LETP16, LETP32, LETP64): New unspecs for DLSTP and LETP.
gcc/testsuite/ChangeLog:
* gcc.target/arm/lob.h: Add new helpers.
* gcc.target/arm/lob1.c: Use new helpers.
* gcc.target/arm/lob6.c: Likewise.
* gcc.target/arm/mve/dlstp-compile-asm-1.c: New test.
* gcc.target/arm/mve/dlstp-compile-asm-2.c: New test.
* gcc.target/arm/mve/dlstp-compile-asm-3.c: New test.
* gcc.target/arm/mve/dlstp-int8x16.c: New test.
* gcc.target/arm/mve/dlstp-int8x16-run.c: New test.
* gcc.target/arm/mve/dlstp-int16x8.c: New test.
* gcc.target/arm/mve/dlstp-int16x8-run.c: New test.
* gcc.target/arm/mve/dlstp-int32x4.c: New test.
* gcc.target/arm/mve/dlstp-int32x4-run.c: New test.
* gcc.target/arm/mve/dlstp-int64x2.c: New test.
* gcc.target/arm/mve/dlstp-int64x2-run.c: New test.
* gcc.target/arm/mve/dlstp-invalid-asm.c: New test.
Andre Vieira [Wed, 19 Jun 2024 16:05:45 +0000 (17:05 +0100)]
doloop: Add support for predicated vectorized loops
This patch adds support in the target agnostic doloop pass for the detection of
predicated vectorized hardware loops. Arm is currently the only target that
will make use of this feature.
gcc/ChangeLog:
* df-core.cc (df_bb_regno_only_def_find): New helper function.
* df.h (df_bb_regno_only_def_find): Declare new function.
* loop-doloop.cc (doloop_condition_get): Add support for detecting
predicated vectorized hardware loops.
(doloop_modify): Add support for GTU condition checks.
(doloop_optimize): Update costing computation to support alterations to
desc->niter_expr by the backend.
Pan Li [Wed, 19 Jun 2024 13:14:31 +0000 (21:14 +0800)]
RISC-V: Add testcases for unsigned .SAT_SUB vector form 10
After the middle-end support the form 10 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 10:
#define DEF_VEC_SAT_U_SUB_FMT_10(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
out[i] = !overflow ? ret : 0; \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c: New test.
Pan Li [Wed, 19 Jun 2024 13:02:27 +0000 (21:02 +0800)]
RISC-V: Add testcases for unsigned .SAT_SUB vector form 9
After the middle-end support the form 9 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 9:
#define DEF_VEC_SAT_U_SUB_FMT_9(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
out[i] = overflow ? 0 : ret; \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c: New test.
Pan Li [Wed, 19 Jun 2024 12:38:43 +0000 (20:38 +0800)]
RISC-V: Add testcases for unsigned .SAT_SUB vector form 8
After the middle-end support the form 8 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 8:
#define DEF_VEC_SAT_U_SUB_FMT_8(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
out[i] = ret & (T)-(!overflow); \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c: New test.
Pan Li [Wed, 19 Jun 2024 12:28:11 +0000 (20:28 +0800)]
RISC-V: Add testcases for unsigned .SAT_SUB vector form 7
After the middle-end support the form 7 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 7:
#define DEF_VEC_SAT_U_SUB_FMT_7(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
out[i] = ret & (T)(overflow - 1); \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c: New test.
Pan Li [Wed, 19 Jun 2024 12:15:27 +0000 (20:15 +0800)]
RISC-V: Add testcases for unsigned .SAT_SUB vector form 6
After the middle-end support the form 6 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 6:
#define DEF_VEC_SAT_U_SUB_FMT_6(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x <= y ? 0 : x - y; \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c: New test.
Pan Li [Wed, 19 Jun 2024 11:44:52 +0000 (19:44 +0800)]
RISC-V: Add testcases for unsigned .SAT_SUB vector form 5
After the middle-end support the form 5 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 5:
#define DEF_VEC_SAT_U_SUB_FMT_5(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x < y ? 0 : x - y; \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c: New test.
Pan Li [Wed, 19 Jun 2024 11:19:23 +0000 (19:19 +0800)]
RISC-V: Add testcases for unsigned .SAT_SUB vector form 4
After the middle-end support the form 4 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 4:
#define DEF_VEC_SAT_U_SUB_FMT_4(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x >= y ? x - y : 0; \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c: New test.
Pan Li [Wed, 19 Jun 2024 10:56:51 +0000 (18:56 +0800)]
RISC-V: Add testcases for unsigned .SAT_SUB vector form 3
After the middle-end support the form 3 of unsigned SAT_SUB and
the RISC-V backend implement the .SAT_SUB for vector mode, thus
add more test case to cover that.
Form 3:
#define DEF_VEC_SAT_U_SUB_FMT_3(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x > y ? x - y : 0; \
} \
}
Passed the rv64gcv regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c: New test.
Jonathan Wakely [Tue, 18 Jun 2024 19:53:53 +0000 (20:53 +0100)]
libstdc++: Fix warning regressions in <bits/stl_tempbuf.h>
I caused some new warnings with -Wsystem-headers with my recent changes
to std::get_temporary_buffer and std::_Temporary_buffer. There's a
-Wsign-compare warning which can be avoided by casting the ptrdiff_t
argument to size_t (which also conveniently rejects negative values).
There's also a -Wdeprecated-declarations warning because I moved where
std::get_temporary_buffer is called, but didn't move the diagnostic
pragmas that suppress the warning for calling it.
libstdc++-v3/ChangeLog:
* include/bits/stl_tempbuf.h (__get_temporary_buffer): Cast
argument to size_t to handle negative values and suppress
-Wsign-compare warning.
(_Temporary_buffer): Move diagnostic pragmas to new location of
call to std::get_temporary_buffer.
Collin Funk [Fri, 14 Jun 2024 00:53:55 +0000 (17:53 -0700)]
build: Fix missing variable quotes
When dlopen and pthread_create are in libc the variable is
set to "none required", therefore running configure will show
the following errors:
./configure: line 8997: test: too many arguments
./configure: line 8999: test: too many arguments
./configure: line 9003: test: too many arguments
./configure: line 9005: test: =: unary operator expected
gcc/configure also has a similar problem on
gcc_cv_as_mips_explicit_relocs:
./gcc/configure: line 30242: test: =: unary operator expected
ChangeLog:
* configure.ac: Quote variable result of AC_SEARCH_LIBS.
* configure: Regenerate.
* trans-decl.cc (gfc_generate_function_code): Set vptr for
results to declared class type.
* trans-expr.cc (gfc_reset_vptr): Allow to provide the typespec
instead of the expression.
* trans.h (gfc_reset_vptr): Same.
gcc/testsuite/ChangeLog:
* gfortran.dg/class_76.f90: Add declared vtab occurrence.
* gfortran.dg/class_78.f90: New test.
xtensa: constantsynth: Reforge to fix some non-fatal issues
The previous constant synthesis logic had some issues that were non-fatal
but worth considering:
- It didn't work with DFmode literals, because those were cast to SImode
rather SFmode when splitting into two natural-width words by
split_double().
- It didn't work with large literals when TARGET_AUTO_LITPOOLS was enabled,
because those were relaxed MOVI immediates rather references to literal
pool entries,
- It didn't take into account that when literals with the same RTL
representation are pooled multiple times within a function, those entries
are shared (especially important when optimizing for size).
This patch addresses the above issues by making appropriate tweaks to the
constant synthesis logic.
gcc/ChangeLog:
* config/xtensa/xtensa-protos.h (xtensa_constantsynth):
Change the second argument from HOST_WIDE_INT to rtx.
* config/xtensa/xtensa.cc (#include):
Add "context.h" and "pass_manager.h".
(machine_function): Add a new hash_map field "litpool_usage".
(xtensa_constantsynth): Make "src" (the second operand) accept
RTX literal instead of its value, and treat both bare and pooled
SI/SFmode literals equally by bit-exact canonicalization into
CONST_INT RTX internally. And then, make avoid synthesis if
such multiple identical canonicalized literals are found in same
function when optimizing for size. Finally, for literals where
synthesis is not possible or has been avoided, re-emit "move"
RTXes with canonicalized ones to increase the chances of sharing
literal pool entries.
* config/xtensa/xtensa.md (split patterns for constant synthesis):
Change to simply invoke xtensa_constantsynth() as mentioned above,
and add new patterns for when TARGET_AUTO_LITPOOLS is enabled.
Pan Li [Mon, 17 Jun 2024 14:31:27 +0000 (22:31 +0800)]
RISC-V: Add testcases for unsigned .SAT_ADD vector form 8
After the middle-end support the form 8 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 8.
Form 8:
#define DEF_VEC_SAT_U_ADD_FMT_8(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x > (T)(x + y) ? -1 : (x + y); \
} \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-32.c: New test.
Pan Li [Mon, 17 Jun 2024 14:19:54 +0000 (22:19 +0800)]
RISC-V: Add testcases for unsigned .SAT_ADD vector form 7
After the middle-end support the form 7 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 7.
Form 7:
#define DEF_VEC_SAT_U_ADD_FMT_7(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = (T)(x + y) < x ? -1 : (x + y); \
} \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-25.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-26.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-27.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-28.c: New test.
Pan Li [Mon, 17 Jun 2024 14:10:31 +0000 (22:10 +0800)]
RISC-V: Add testcases for unsigned .SAT_ADD vector form 6
After the middle-end support the form 6 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 6.
Form 6:
#define DEF_VEC_SAT_U_ADD_FMT_6(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = x <= (T)(x + y) ? (x + y) : -1; \
} \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c: New test.
Pan Li [Mon, 17 Jun 2024 08:31:26 +0000 (16:31 +0800)]
RISC-V: Add testcases for unsigned .SAT_ADD vector form 5
After the middle-end support the form 5 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 5.
Form 5:
#define DEF_VEC_SAT_U_ADD_FMT_5(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
out[i] = __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1; \
} \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-17.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-18.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-19.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-20.c: New test.
Pan Li [Mon, 17 Jun 2024 08:09:13 +0000 (16:09 +0800)]
RISC-V: Add testcases for unsigned .SAT_ADD vector form 4
After the middle-end support the form 4 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 4.
Form 4:
#define DEF_VEC_SAT_U_ADD_FMT_4(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
out[i] = __builtin_add_overflow (x, y, &ret) ? -1 : ret; \
} \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c: New test.
Pan Li [Mon, 17 Jun 2024 06:53:12 +0000 (14:53 +0800)]
RISC-V: Add testcases for unsigned .SAT_ADD vector form 3
After the middle-end support the form 3 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 3.
Form 3:
#define DEF_VEC_SAT_U_ADD_FMT_3(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T ret; \
T overflow = __builtin_add_overflow (x, y, &ret); \
out[i] = (T)(-overflow) | ret; \
} \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c: New test.
Pan Li [Mon, 17 Jun 2024 06:39:10 +0000 (14:39 +0800)]
RISC-V: Add testcases for unsigned .SAT_ADD vector form 2
After the middle-end support the form 2 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 2.
Form 2:
#define DEF_VEC_SAT_U_ADD_FMT_2(T) \
void __attribute__((noinline)) \
vec_sat_u_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = (T)(x + y) >= x ? (x + y) : -1; \
} \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c: New test.
Pan Li [Tue, 18 Jun 2024 08:22:59 +0000 (16:22 +0800)]
RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12
After the middle-end support the form 12 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 12.
Form 12:
#define DEF_SAT_U_SUB_FMT_12(T) \
T __attribute__((noinline)) \
sat_u_sub_##T##_fmt_12 (T x, T y) \
{ \
T ret; \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
return !overflow ? ret : 0; \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for
testing.
* gcc.target/riscv/sat_u_sub-45.c: New test.
* gcc.target/riscv/sat_u_sub-46.c: New test.
* gcc.target/riscv/sat_u_sub-47.c: New test.
* gcc.target/riscv/sat_u_sub-48.c: New test.
* gcc.target/riscv/sat_u_sub-run-45.c: New test.
* gcc.target/riscv/sat_u_sub-run-46.c: New test.
* gcc.target/riscv/sat_u_sub-run-47.c: New test.
* gcc.target/riscv/sat_u_sub-run-48.c: New test.
Pan Li [Tue, 18 Jun 2024 08:14:23 +0000 (16:14 +0800)]
RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11
After the middle-end support the form 11 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 11.
Form 11:
#define DEF_SAT_U_SUB_FMT_11(T) \
T __attribute__((noinline)) \
sat_u_sub_##T##_fmt_11 (T x, T y) \
{ \
T ret; \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
return overflow ? 0 : ret; \
}
Passed the rv64gcv regression tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/sat_u_sub-41.c: New test.
* gcc.target/riscv/sat_u_sub-42.c: New test.
* gcc.target/riscv/sat_u_sub-43.c: New test.
* gcc.target/riscv/sat_u_sub-44.c: New test.
* gcc.target/riscv/sat_u_sub-run-41.c: New test.
* gcc.target/riscv/sat_u_sub-run-42.c: New test.
* gcc.target/riscv/sat_u_sub-run-43.c: New test.
* gcc.target/riscv/sat_u_sub-run-44.c: New test.
Edwin Lu [Fri, 14 Jun 2024 16:46:01 +0000 (09:46 -0700)]
RISC-V: Move mode assertion out of conditional branch in emit_insn
When emitting insns, we have an early assertion to ensure the input
operand's mode and the expanded operand's mode are the same; however, it
does not perform this check if the pattern does not have an explicit
machine mode specifying the operand. In this scenario, it will always
assume that mode = Pmode to correctly satisfy the
maybe_legitimize_operand check, however, there may be problems when
working in 32 bit environments.
Make the assert unconditional and replace it with an internal error for
more descriptive logging
gcc/ChangeLog:
* config/riscv/riscv-v.cc: Move assert out of conditional block
Signed-off-by: Edwin Lu <ewlu@rivosinc.com> Co-authored-by: Robin Dapp <rdapp@ventanamicro.com>
Edwin Lu [Tue, 11 Jun 2024 20:50:02 +0000 (13:50 -0700)]
RISC-V: Fix vwsll combine on rv32 targets
On rv32 targets, vwsll_zext1_scalar_<mode> would trigger an ice in
maybe_legitimize_instruction when zero extending a uint32 to uint64 due
to a mismatch between the input operand's mode (DI) and the expanded insn
operand's mode (Pmode == SI). Ensure that mode of the operands match
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Fix mode mismatch
Signed-off-by: Edwin Lu <ewlu@rivosinc.com> Co-authored-by: Robin Dapp <rdapp@ventanamicro.com>
Andrew Pinski [Mon, 17 Jun 2024 20:26:54 +0000 (13:26 -0700)]
aarch64: make thunderxt88p1 an alias of thunderxt88
Since r7-6575-g71aba51d6460ff, thunderxt88 has been the same as thunderxt88p1 so let's make
them a true alias and remove the odd variant handling and moves it below thunderxt88.
Bootstrapped and tested on aarch64-linux-gnu with no regressions.
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (thunderxt88p1): Make an alias of thunderxt88 and
move below thunderxt88.
* config/aarch64/aarch64-tune.md: Regenerate.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
gcc/c-family/ChangeLog:
* c-opts.cc: Replace include of "tree-diagnostic.h" with
"diagnostic-macro-unwinding.h".
gcc/ChangeLog:
* diagnostic-macro-unwinding.cc: New file, with material taken
from tree-diagnostic.cc.
* diagnostic-macro-unwinding.h: New file, with material taken
from tree-diagnostic.h.
* tree-diagnostic-path.cc: Repalce include of "tree-diagnostic.h"
with "diagnostic-macro-unwinding.h".
* tree-diagnostic.cc (struct loc_map_pair): Move to
diagnostic-macro-unwinding.cc.
(maybe_unwind_expanded_macro_loc): Likewise.
(virt_loc_aware_diagnostic_finalizer): Likewise.
* tree-diagnostic.h (virt_loc_aware_diagnostic_finalizer): Move
decl to diagnostic-macro-unwinding.h.
(maybe_unwind_expanded_macro_loc): Likewise.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
Now that the path-handling code for json_output_format no longer
needs "tree", and thus can be in OBJS-libcommon we can move it
from tree-diagnostic-path.cc to diagnostic-format-json.cc where it
should have been all along.
No functional change intended.
gcc/ChangeLog:
* diagnostic-format-json.cc: Include "diagnostic-path.h" and
"logical-location.h".
(make_json_for_path): Move tree-diagnostic-path.cc's
default_tree_make_json_for_path here, renaming it and making it
static.
(json_output_format::on_end_diagnostic): Replace call of
m_context's m_make_json_for_path callback with a direct call to
make_json_for_path.
* diagnostic.h (diagnostic_context::m_make_json_for_path): Drop
field.
* tree-diagnostic-path.cc: Drop include of "json.h".
(default_tree_make_json_for_path): Rename to make_json_for_path
and move to diagnostic-format-json.cc.
* tree-diagnostic.cc (tree_diagnostics_defaults): Drop
initialization of m_make_json_for_path.
* tree-diagnostic.h (default_tree_make_json_for): Delete decl.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
David Malcolm [Tue, 18 Jun 2024 14:59:55 +0000 (10:59 -0400)]
diagnostics: remove tree usage from tree-diagnostic-path.cc
No functional change intended.
gcc/ChangeLog:
* Makefile.in (OBJS): Add selftest-diagnostic-path.o and
selftest-logical-location.o.
* logical-location.h: Include "label-text.h".
(class logical_location): Update leading comment.
* selftest-diagnostic-path.cc: New file, adapted from
simple-diagnostic-path.cc and from material in
tree-diagnostic-path.cc.
* selftest-diagnostic-path.h: New file, adapted from
simple-diagnostic-path.h and from material in
tree-diagnostic-path.cc.
* selftest-logical-location.cc: New file.
* selftest-logical-location.h: New file.
* tree-diagnostic-path.cc: Remove includes of "tree-pretty-print.h",
"langhooks.h", and "simple-diagnostic-path.h". Add include of
"selftest-diagnostic-path.h".
(class test_diagnostic_path): Delete, in favor of new
implementation in selftest-diagnostic-path.{h,cc}, which is
directly derived from diagnostic_path, rather than from
simple_diagnostic_path.
(selftest::test_intraprocedural_path): Eliminate tree usage,
via change to test_diagnostic_path, using strings rather than
function_decls for identifying functions in the test.
(selftest::test_interprocedural_path_1): Likewise.
(selftest::test_interprocedural_path_2): Likewise.
(selftest::test_recursion): Likewise.
(selftest::test_control_flow_1): Likewise.
(selftest::test_control_flow_2): Likewise.
(selftest::test_control_flow_3): Likewise.
(selftest::assert_cfg_edge_path_streq): Likewise.
(selftest::test_control_flow_5): Likewise.
(selftest::test_control_flow_6): Likewise.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
David Malcolm [Tue, 18 Jun 2024 14:59:54 +0000 (10:59 -0400)]
diagnostics: eliminate "tree" from diagnostic_{event,path}
This patch eliminates the use of "tree" from diagnostic_{event,path} in
favor of const logical_location *.
No functional change intended.
gcc/analyzer/ChangeLog:
* checker-event.h (checker_event::fndecl): Drop "final" and
"override", converting from a vfunc implementation to a plain
accessor.
* checker-path.cc (checker_path::same_function_p): New.
* checker-path.h (checker_path::same_function_p): New decl.
gcc/ChangeLog:
* diagnostic.cc: Include "logical-location.h".
(diagnostic_path::get_first_event_in_a_function): Fix typo in
leading comment. Rewrite to use logical_location rather than
tree. Drop test on stack depth.
(diagnostic_path::interprocedural_p): Rewrite to use
logical_location rather than tree.
(logical_location::function_p): New.
* diagnostic-path.h (diagnostic_event::get_fndecl): Eliminate
vfunc.
(diagnostic_path::same_function_p): New pure virtual func.
* logical-location.h (logical_location::get_name_for_path_output):
New pure virtual func.
* simple-diagnostic-path.cc
(simple_diagnostic_path::same_function_p): New.
(simple_diagnostic_event::simple_diagnostic_event): Initialize
m_logical_loc.
* simple-diagnostic-path.h: Include "tree-logical-location.h".
(simple_diagnostic_event::get_fndecl): Convert from a vfunc
implementation to an accessor.
(simple_diagnostic_event::get_logical_location): Use
m_logical_loc.
(simple_diagnostic_event::m_logical_loc): New field.
(simple_diagnostic_path::same_function_p): New decl.
* tree-diagnostic-path.cc: Move pragma disabling -Wformat-diag to
cover the whole file.
(can_consolidate_events): Add params "path", "ev1_idx", and
"ev2_idx". Rewrite to use diagnostic_path::same_function_p rather
than tree.
(per_thread_summary::per_thread_summary): Add "path" param
(per_thread_summary::m_path): New field.
(event_range::event_range): Update for conversion of m_fndecl to
m_logical_loc.
(event_range::maybe_add_event): Rename param "idx" to
"new_ev_idx". Update call to can_consolidate_events to pass in
"m_path", "m_start_idx", and "new_ev_idx".
(event_range::m_fndecl): Replace with...
(event_range::m_logical_loc): ...this.
(path_summary::get_or_create_events_for_thread_id): Pass "path" to
per_thread_summary ctor.
(per_thread_summary::interprocedural_p): Rewrite to use
diagnostic_path::same_function_p rather than tree.
(print_fndecl): Delete.
(thread_event_printer::print_swimlane_for_event_range): Update for
conversion from tree to logical_location.
(default_tree_diagnostic_path_printer): Likewise.
(default_tree_make_json_for_path): Likewise.
* tree-logical-location.cc: Include "intl.h".
(compiler_logical_location::get_name_for_tree_for_path_output):
New.
(tree_logical_location::get_name_for_path_output): New.
(current_fndecl_logical_location::get_name_for_path_output): New.
* tree-logical-location.h
(compiler_logical_location::get_name_for_tree_for_path_output):
New decl.
(tree_logical_location::get_name_for_path_output): New decl.
(current_fndecl_logical_location::get_name_for_path_output): New
decl.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
Pan Li [Mon, 17 Jun 2024 01:31:33 +0000 (09:31 +0800)]
Match: Support forms 7 and 8 for the unsigned .SAT_ADD
When investigate the vectorization of .SAT_ADD, we notice there
are additional 2 forms, aka form 7 and 8 for .SAT_ADD.
Form 7:
#define DEF_SAT_U_ADD_FMT_7(T) \
T __attribute__((noinline)) \
sat_u_add_##T##_fmt_7 (T x, T y) \
{ \
return x > (T)(x + y) ? -1 : (x + y); \
}
Form 8:
#define DEF_SAT_U_ADD_FMT_8(T) \
T __attribute__((noinline)) \
sat_u_add_##T##_fmt_8 (T x, T y) \
{ \
return x <= (T)(x + y) ? (x + y) : -1; \
}
Thus, add above 2 forms to the match gimple_unsigned_integer_sat_add,
and then the vectorizer can try to recog the pattern like form 7 and
form 8.
The below test suites are passed for this patch:
1. The rv64gcv fully regression test with newlib.
2. The rv64gcv build with glibc.
3. The x86 bootstrap test.
4. The x86 fully regression test.
gcc/ChangeLog:
* match.pd: Add form 7 and 8 for the unsigned .SAT_ADD match.
Pan Li [Mon, 17 Jun 2024 06:56:42 +0000 (14:56 +0800)]
Match: Support form 11 for the unsigned scalar .SAT_SUB
We missed one match pattern for the unsigned scalar .SAT_SUB, aka
form 11.
Form 11:
#define SAT_SUB_U_11(T) \
T sat_sub_u_11_##T (T x, T y) \
{ \
T ret; \
bool overflow = __builtin_sub_overflow (x, y, &ret); \
return overflow ? 0 : ret; \
}
Thus, add above form 11 to the match pattern gimple_unsigned_integer_sat_sub.
The below test suites are passed for this patch:
1. The rv64gcv fully regression test with newlib.
2. The rv64gcv build with glibc.
3. The x86 bootstrap test.
4. The x86 fully regression test.
gcc/ChangeLog:
* match.pd: Add form 11 match pattern for .SAT_SUB.
PR tree-optimization/115537
* tree-vect-loop.cc (vectorizable_reduction): Also reject
SLP condition reductions of EXTRACT_LAST kind when multiple
statement copies are involved.
Jeff Law [Tue, 18 Jun 2024 12:40:40 +0000 (06:40 -0600)]
[to-be-committed,RISC-V] Improve bset generation when bit position is limited
So more work in the ongoing effort to make better use of the Zbs
extension. This time we're trying to exploit knowledge of the shift
count/bit position to allow us to use a bset instruction.
Consider this expression in SImode
(1 << (pos & 0xf)
None of the resulting values will have bit 31 set. So if there's an
explicit zero or sign extension to DI we can drop that explicit
extension and generate a simple bset with x0 as the input value.
Or another example (which I think came from spec at some point and IIRC
was the primary motivation for this patch):
(1 << (7-(pos) % 8))
Before this change they'd generate something like this respectively:
We achieve this with simple define_splits which target the bsetdi_2
pattern I recently added. Much better than the original implementation
I did a few months back :-) I've got a bclr/binv variant from a few
months back as well, but it needs to be updated to the simpler
implementation found here.
Just ran this through my tester. Will wait for the precommit CI to
render its verdict before moving forward.
gcc/
* config/riscv/bitmanip.md (bset splitters): New patterns for
generating bset when bit position is limited.
Jonathan Wakely [Tue, 18 Jun 2024 12:05:39 +0000 (13:05 +0100)]
libstdc++: Fix outdated comment about standard integer types
The long long and unsigned long long types have been standard since
C++11, so are not extensions. There are also the char8_t, char16_t and
char32_t types. Just refer to the standard integer types, without saying
how many there are.
libstdc++-v3/ChangeLog:
* include/bits/cpp_type_traits.h: Fix outdated comment about the
number of standard integer types.
Jonathan Wakely [Fri, 14 Jun 2024 12:57:10 +0000 (13:57 +0100)]
analyzer: Fix g++ 4.8 bootstrap without using std::move to return std::unique_ptr
Revert the changes in r15-1111-ge22b7f741ab54f and fix bootstrap with
GCC 4.8 a different way. The original problem is not related to C++17
guaranteed copy elision, it's related to Core DR 1579 [1], which was
part of C++14 but only implemented in G++ as a C++11 DR with r5-1576-gfb682f9458c6cf (so GCC 4.8 doesn't implement it).
The original fix causes -Wredundant-move warnings with GCC trunk.
This patch adds uses of force_highpart_subreg to places that
already use force_lowpart_subreg.
gcc/
* config/aarch64/aarch64.cc (aarch64_addti_scratch_regs): Use
force_highpart_subreg instead of gen_highpart and simplify_gen_subreg.
(aarch64_subvti_scratch_regs): Likewise.
This patch makes target-independent code use force_lowpart_subreg
instead of simplify_gen_subreg and lowpart_subreg in some places.
The criteria were:
(1) The code is obviously specific to expand (where new pseudos
can be created), or at least would be invalid to call when
!can_create_pseudo_p () and temporaries are needed.
(2) The value is obviously an rvalue rather than an lvalue.
Doing this should reduce the likelihood of bugs like PR115464
occuring in other situations.
gcc/
* builtins.cc (expand_builtin_issignaling): Use force_lowpart_subreg
instead of simplify_gen_subreg and lowpart_subreg.
* expr.cc (convert_mode_scalar, expand_expr_real_2): Likewise.
* optabs.cc (expand_doubleword_mod): Likewise.
optabs had a local function called lowpart_subreg_maybe_copy
that is very similar to the lowpart version of force_subreg.
This patch adds a force_lowpart_subreg wrapper around
force_subreg and uses it in optabs.cc.
The only difference between the old and new functions is that
the old one asserted success while the new one doesn't.
It's common not to assert elsewhere when taking subregs;
normally a null result is enough.
Later patches will make more use of the new function.
gcc/
* explow.h (force_lowpart_subreg): Declare.
* explow.cc (force_lowpart_subreg): New function.
* optabs.cc (lowpart_subreg_maybe_copy): Delete.
(expand_absneg_bit): Use force_lowpart_subreg instead of
lowpart_subreg_maybe_copy.
(expand_copysign_bit): Likewise.
projects / thirdparty / gcc.git / log
