Pan Li [Wed, 9 Oct 2024 14:37:00 +0000 (22:37 +0800)]
RISC-V: Add testcases for form 3 of scalar signed SAT_TRUNC
Form 3:
#define DEF_SAT_S_TRUNC_FMT_3(NT, WT, NT_MIN, NT_MAX) \
NT __attribute__((noinline)) \
sat_s_trunc_##WT##_to_##NT##_fmt_3 (WT x) \
{ \
NT trunc = (NT)x; \
return (WT)NT_MIN < x && x <= (WT)NT_MAX \
? trunc \
: x < 0 ? NT_MIN : NT_MAX; \
}
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_s_trunc-3-i16-to-i8.c: New test.
* gcc.target/riscv/sat_s_trunc-3-i32-to-i16.c: New test.
* gcc.target/riscv/sat_s_trunc-3-i32-to-i8.c: New test.
* gcc.target/riscv/sat_s_trunc-3-i64-to-i16.c: New test.
* gcc.target/riscv/sat_s_trunc-3-i64-to-i32.c: New test.
* gcc.target/riscv/sat_s_trunc-3-i64-to-i8.c: New test.
* gcc.target/riscv/sat_s_trunc-run-3-i16-to-i8.c: New test.
* gcc.target/riscv/sat_s_trunc-run-3-i32-to-i16.c: New test.
* gcc.target/riscv/sat_s_trunc-run-3-i32-to-i8.c: New test.
* gcc.target/riscv/sat_s_trunc-run-3-i64-to-i16.c: New test.
* gcc.target/riscv/sat_s_trunc-run-3-i64-to-i32.c: New test.
* gcc.target/riscv/sat_s_trunc-run-3-i64-to-i8.c: New test.
Pan Li [Wed, 9 Oct 2024 02:33:31 +0000 (10:33 +0800)]
RISC-V: Add testcases for form 2 of scalar signed SAT_TRUNC
Form 2:
#define DEF_SAT_S_TRUNC_FMT_2(NT, WT, NT_MIN, NT_MAX) \
NT __attribute__((noinline)) \
sat_s_trunc_##WT##_to_##NT##_fmt_2 (WT x) \
{ \
NT trunc = (NT)x; \
return (WT)NT_MIN < x && x < (WT)NT_MAX \
? trunc \
: x < 0 ? NT_MIN : NT_MAX; \
}
The below test are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_s_trunc-2-i16-to-i8.c: New test.
* gcc.target/riscv/sat_s_trunc-2-i32-to-i16.c: New test.
* gcc.target/riscv/sat_s_trunc-2-i32-to-i8.c: New test.
* gcc.target/riscv/sat_s_trunc-2-i64-to-i16.c: New test.
* gcc.target/riscv/sat_s_trunc-2-i64-to-i32.c: New test.
* gcc.target/riscv/sat_s_trunc-2-i64-to-i8.c: New test.
* gcc.target/riscv/sat_s_trunc-run-2-i16-to-i8.c: New test.
* gcc.target/riscv/sat_s_trunc-run-2-i32-to-i16.c: New test.
* gcc.target/riscv/sat_s_trunc-run-2-i32-to-i8.c: New test.
* gcc.target/riscv/sat_s_trunc-run-2-i64-to-i16.c: New test.
* gcc.target/riscv/sat_s_trunc-run-2-i64-to-i32.c: New test.
* gcc.target/riscv/sat_s_trunc-run-2-i64-to-i8.c: New test.
Jakub Jelinek [Fri, 11 Oct 2024 09:41:53 +0000 (11:41 +0200)]
i386: Fix up spaceship expanders for -mtune=i[45]86 [PR117053]
The adjusted and new spaceship expanders ICE with -mtune=i486 or
-mtune=i586.
The problem is that in that case TARGET_ZERO_EXTEND_WITH_AND is true
and zero_extendqisi2 isn't allowed in that case, and we can't use
the replacement AND, because that clobbers flags and we want to use them
again.
The following patch fixes that by using in those cases roughly what
we want to expand it to after peephole2 optimizations, i.e. xor
before the comparison, *setcc_qi_slp and sbbl $0 (or for signed
int case xoring of 2 regs, two *setcc_qi_slp, subl).
For *setcc_qi_slp, it uses the setcc_si_slp hacks with UNSPEC that
were in use for the floating point jp case (so such code is IMHO
undesirable for the !TARGET_ZERO_EXTEND_WITH_AND case as we want to
give combiner more liberty in that case).
Jonathan Wakely [Wed, 9 Oct 2024 13:24:19 +0000 (14:24 +0100)]
libstdc++: Fix some test failures with -fno-char8_t
libstdc++-v3/ChangeLog:
* testsuite/20_util/duration/io.cc [!__cpp_lib_char8_t]: Define
char8_t as a typedef for unsigned char.
* testsuite/std/format/parse_ctx_neg.cc: Skip for -fno-char8_t.
Richard Biener [Thu, 10 Oct 2024 12:00:11 +0000 (14:00 +0200)]
Fix possible wrong-code with masked store-lanes
When we're doing masked store-lanes one mask element applies to all
loads of one struct element. This requires uniform masks for all
of the SLP lanes, something we already compute into STMT_VINFO_SLP_VECT_ONLY
but fail to check when doing SLP store-lanes. The following corrects
this. The following also adjusts the store-lane heuristic to properly
check for masked or non-masked optab support.
* tree-vect-slp.cc (vect_slp_prefer_store_lanes_p): Allow
passing in of vectype, pass in whether the stores are masked
and query the correct optab.
(vect_build_slp_instance): Guard store-lanes query with
! STMT_VINFO_SLP_VECT_ONLY, guaranteeing an uniform mask.
Hu, Lin1 [Wed, 9 Oct 2024 02:20:05 +0000 (10:20 +0800)]
i386: Fix some patterns's mem attribute.
Hi, all
This is another patch to modify some pattern's type attr from ssemov to
ssemov2.
Some ssemov pattern's mem attr should be load when their 2 operand is a memory
operand.
Bootstrapped and regtested on x86-64-linux-pc, OK for trunk?
BRs,
Lin
gcc/ChangeLog:
* config/i386/sse.md
(sse_movhlps): Change type attr from ssemov to ssemov2.
(sse_loadhps): Ditto.
(*vec_concat<mode>): Ditto.
(vec_setv2df_0): Ditto.
(sse_loadlps): Change attr from ssemov to ssemov2 except for 2, 3.
(sse2_loadhps): Change attr from ssemov to ssemov2 except for 0, 1.
(sse2_loadlpd): Change attr from ssemov to ssemov2 except for 0, 1,
2.
(sse2_movsd_<mode>): Change attr from ssemov to ssemov2 except for 5.
(vec_concatv2df): Change attr from ssemov to ssemov2 except for 0, 1,
2.
(*vec_concat<mode>): Change attr from ssemov to ssemov2 for 3, 4.
(vec_concatv2di): Change attr from ssemov to ssemov2 except for 0, 1,
2, 3, 4, 5.
Richard Ball [Thu, 10 Oct 2024 18:16:39 +0000 (19:16 +0100)]
aarch64: Alter pr116258.c test to correct for big endian.
The test at pr116258.c fails on big endian targets,
this is because the test checks that the index of a floating
point multiply is 0, which is correct only for little endian.
gcc/testsuite/ChangeLog:
PR tree-optimization/116258
* gcc.target/aarch64/pr116258.c:
Alter test to add big-endian support.
Michael Matz [Thu, 10 Oct 2024 14:36:51 +0000 (16:36 +0200)]
Fix PR116650: check all regs in regrename targets
(this came up for m68k vs. LRA, but is a generic problem)
Regrename wants to use new registers for certain def-use chains.
For validity of replacements it needs to check that the selected
candidates are unused up to then. That's done in check_new_reg_p.
But if it so happens that the new register needs more hardregs
than the old register (which happens if the target allows inter-bank
moves and the mode is something like a DFmode that needs to be placed
into a SImode reg-pair), then check_new_reg_p only checks the
first of those registers for free-ness.
This is caused by that function looking up the number of necessary
hardregs only in terms of the old hardreg number. It of course needs
to do that in terms of the new candidate regnumber. The symptom is that
regrename sometimes clobbers the higher numbered registers of such a
regrename target pair. This patch fixes that problem.
(In the particular case of the bug report it was LRA that left over a
inter-bank move instruction that triggers regrename, ultimately causing
the mis-compile. Reload didn't do that, but in general we of course
can't rely on such moves not happening if the target allows them.)
This also shows a general confusion in that function and the target hook
interface here:
for (i = nregs - 1; i >= 0; --)
...
|| ! HARD_REGNO_RENAME_OK (reg + i, new_reg + i))
it uses nregs in a way that requires it to be the same between old and
new register. The problem is that the target hook only gets register
numbers, when it instead should get a mode and register numbers and
would be called only for the first but not for subsequent registers.
I've looked at a number of definitions of that target hook and I think
that this is currently harmless in the sense that it would merely rule
out some potential reg-renames that would in fact be okay to do. So I'm
not changing the target hook interface here and hence that problem
remains unfixed.
PR rtl-optimization/116650
* regrename.cc (check_new_reg_p): Calculate nregs in terms of
the new candidate register.
Li Xu [Thu, 10 Oct 2024 14:51:19 +0000 (08:51 -0600)]
RISC-V:Bugfix for C++ code compilation failure with rv32imafc_zve32f[pr116883]
From: xuli <xuli1@eswincomputing.com>
Example as follows:
int main()
{
unsigned long arraya[128], arrayb[128], arrayc[128];
for (int i = 0; i < 128; i++)
{
arraya[i] = arrayb[i] + arrayc[i];
}
return 0;
}
Compiled with -march=rv32imafc_zve32f -mabi=ilp32f, it will cause a compilation issue:
riscv_vector.h:40:25: error: ambiguating new declaration of 'vint64m4_t __riscv_vle64(vbool16_t, const long long int*, unsigned int)'
40 | #pragma riscv intrinsic "vector"
| ^~~~~~~~
riscv_vector.h:40:25: note: old declaration 'vint64m1_t __riscv_vle64(vbool64_t, const long long int*, unsigned int)'
With zvl=32b, vbool16_t is registered in init_builtins() with
type_common.precision=0x101 (nunits=2), mode_nunits[E_RVVMF16BI]=[2,2].
Normally, vbool64_t is only valid when TARGET_MIN_VLEN > 32, so vbool64_t
is not registered in init_builtins(), meaning vbool64_t=null.
In order to implement __attribute__((target("arch=+v"))), we must register
all vector types and all RVV intrinsics. Therefore, vbool64_t will be registered
by default with zvl=128b in reinit_builtins(), resulting in
type_common.precision=0x101 (nunits=2) and mode_nunits[E_RVVMF64BI]=[2,2].
We then get TYPE_VECTOR_SUBPARTS(vbool16_t) == TYPE_VECTOR_SUBPARTS(vbool64_t),
calculated using type_common.precision, resulting in 2. Since vbool16_t and
vbool64_t have the same element type (boolean_type), the compiler treats them
as the same type, leading to a re-declaration conflict.
After all types and intrinsics have been registered, processing
__attribute__((target("arch=+v"))) will update the parameters option and
init_adjust_machine_modes. Therefore, to avoid conflicts, we can choose
zvl=4096b for the null type reinit_builtins().
vect: Avoid divide by zero for permutes of extern VLA vectors
My recent VLA SLP patches caused a regression with cross compilers
in gcc.dg/torture/neon-sve-bridge.c. There we have a VEC_PERM_EXPR
created from two BIT_FIELD_REFs, with the child node being an
external VLA vector:
For this kind of external node, the SLP_TREE_LANES is normally
the total number of lanes in the vector, but it is zero if the
vector has variable length:
auto nunits = TYPE_VECTOR_SUBPARTS (SLP_TREE_VECTYPE (vnode));
unsigned HOST_WIDE_INT const_nunits;
if (nunits.is_constant (&const_nunits))
SLP_TREE_LANES (vnode) = const_nunits;
This led to division by zero in:
/* Check whether the output has N times as many lanes per vector. */
else if (constant_multiple_p (SLP_TREE_LANES (node) * op_nunits,
SLP_TREE_LANES (child) * nunits,
&this_unpack_factor)
&& (i == 0 || unpack_factor == this_unpack_factor))
unpack_factor = this_unpack_factor;
No repetition takes place for this kind of external node, so this
patch goes with Richard's suggestion to check for external nodes
that have no scalar statements.
This didn't show up for my native testing since division by zero
doesn't trap on AArch64.
gcc/
* tree-vect-slp.cc (vectorizable_slp_permutation_1): Set repeating_p
to false if we have an external node for a pre-existing vector.
match.pd: Check trunc_mod vector obtap before folding.
This patch guards the simplification x / y * y == x -> x % y == 0 in
match.pd by a check for:
1) Non-vector mode of x OR
2) Lack of support for vector division OR
3) Support of vector modulo
The patch was bootstrapped and tested with no regression on
aarch64-linux-gnu and x86_64-linux-gnu.
OK for mainline?
Signed-off-by: Jennifer Schmitz <jschmitz@nvidia.com>
gcc/
PR tree-optimization/116831
* match.pd: Guard simplification to trunc_mod with check for
mod optab support.
gcc/testsuite/
PR tree-optimization/116831
* gcc.dg/torture/pr116831.c: New test.
Richard Biener [Wed, 9 Oct 2024 13:31:59 +0000 (15:31 +0200)]
Allow SLP store of mixed external and constant
vect_build_slp_tree_1 rejected this during SLP discovery because it
ran into the rhs code comparison code for stores. The following
skips that completely for loads and stores as those are handled
later anyway.
This needs a heuristic adjustment in vect_get_and_check_slp_defs
to avoid fallout with regard to BB vectorization and splitting
of a store group vs. demoting one operand to external.
gcc.dg/Wstringop-overflow-47.c needs adjustment given we now have
vast improvements for code generation. gcc.dg/strlenopt-32.c
needs adjustment because the strlen pass doesn't handle
* tree-vect-slp.cc (vect_build_slp_tree_1): Do not compare
RHS codes for loads or stores.
(vect_get_and_check_slp_defs): Only demote operand to external
in case there is more than one operand.
According to Intel SOM[1], For Crestmont, most 256-bit Intel AVX2
instructions can be decomposed into two independent 128-bit
micro-operations, except for a subset of Intel AVX2 instructions,
known as cross-lane operations, can only compute the result for an
element by utilizing one or more sources belonging to other elements.
The 256-bit instructions listed below use more operand sources than
can be natively supported by a single reservation station within these
microarchitectures. They are decomposed into two μops, where the first
μop resolves a subset of operand dependencies across two cycles. The
dependent second μop executes the 256-bit operation by using a single
128-bit execution port for two consecutive cycles with a five-cycle
latency for a total latency of seven cycles.
Instead of setting tune avx128_optimal for SRF, the patch add a new
tune avx256_avoid_vec_perm for it. so by default, vectorizer still
uses 256-bit VF if cost is profitable, but lowers to 128-bit whenever
256-bit vec_perm is needed for auto-vectorization. w/o vec_perm,
performance of 256-bit vectorization should be similar as 128-bit
ones(some benchmark results show it's even better than 128-bit
vectorization since it enables more parallelism for convert cases.)
* config/i386/i386.cc (ix86_vector_costs::ix86_vector_costs):
Add new member m_num_avx256_vec_perm.
(ix86_vector_costs::add_stmt_cost): Record 256-bit vec_perm.
(ix86_vector_costs::finish_cost): Prevent vectorization for
TAREGT_AVX256_AVOID_VEC_PERM when there's 256-bit vec_perm
instruction.
* config/i386/i386.h (TARGET_AVX256_AVOID_VEC_PERM): New
Macro.
* config/i386/x86-tune.def (X86_TUNE_AVX256_SPLIT_REGS): Add
m_CORE_ATOM.
(X86_TUNE_AVX256_AVOID_VEC_PERM): New tune.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx256_avoid_vec_perm.c: New test.
For Crestmont, 4-operand vex blendv instructions come from MSROM and
is slower than 3-instructions sequence (op1 & mask) | (op2 & ~mask).
legacy blendv instruction can still be handled by the decoder.
The patch add a new tune which is enabled for all processors except
for SRF/CWF. It will use vpand + vpandn + vpor instead of
vpblendvb(similar for vblendvps/vblendvpd) for SRF/CWF.
gcc/ChangeLog:
* config/i386/i386-expand.cc (ix86_expand_sse_movcc): Guard
instruction blendv generation under new tune.
* config/i386/i386.h (TARGET_SSE_MOVCC_USE_BLENDV): New Macro.
* config/i386/x86-tune.def (X86_TUNE_SSE_MOVCC_USE_BLENDV):
New tune.
David Malcolm [Thu, 10 Oct 2024 01:26:09 +0000 (21:26 -0400)]
diagnostics: move text output member functions to correct file
No functional change intended.
gcc/ChangeLog:
* diagnostic-format-text.cc
(diagnostic_text_output_format::after_diagnostic): Replace call to
show_any_path with body, taken from diagnostic.cc.
(diagnostic_text_output_format::build_prefix): Move here from
diagnostic.cc, updating to use get_diagnostic_kind_text and
diagnostic_get_color_for_kind.
(diagnostic_text_output_format::file_name_as_prefix): Move here
from diagnostic.cc
(diagnostic_text_output_format::append_note): Likewise.
* diagnostic-format-text.h
(diagnostic_text_output_format::show_any_path): Drop decl.
* diagnostic.cc
(diagnostic_text_output_format::file_name_as_prefix): Move to
diagnostic-format-text.cc.
(diagnostic_text_output_format::build_prefix): Likewise.
(diagnostic_text_output_format::show_any_path): Move to body of
diagnostic_text_output_format::after_diagnostic.
(diagnostic_text_output_format::append_note): Move to
diagnostic-format-text.cc.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
David Malcolm [Thu, 10 Oct 2024 01:26:09 +0000 (21:26 -0400)]
diagnostics: mark the JSON output format as deprecated
The bulk of the documentation for -fdiagnostics-format= is taken up
by a description of the "json" format added in r9-4156-g478dd60ddcf177.
I don't plan to add any extra features to the "json" format; all my
future work on machine-readable GCC diagnostics is likely to be on the
SARIF output format (https://gcc.gnu.org/wiki/SARIF).
Hence users seeking machine-readable output from GCC should use SARIF.
This patch removes the long documentation of the format and describes it
as deprecated.
gcc/ChangeLog:
* doc/invoke.texi (fdiagnostics-format): Describe "json" et al as
deprecated, and remove the long description of the output format.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
David Malcolm [Thu, 10 Oct 2024 01:26:08 +0000 (21:26 -0400)]
lto: reimplement print_lto_docs_link [PR116613]
gcc/ChangeLog:
PR other/116613
* lto-wrapper.cc (print_lto_docs_link): Use a format string rather
than building the string manually. Fix memory leak of "url" by
using label_text.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
liuhongt [Tue, 26 Mar 2024 04:28:14 +0000 (21:28 -0700)]
Enable vectorization for unknown tripcount in very cheap cost model but disable epilog vectorization.
gcc/ChangeLog:
* tree-vect-loop.cc (vect_analyze_loop_costing): Enable
vectorization for LOOP_VINFO_PEELING_FOR_NITER in very cheap
cost model.
(vect_analyze_loop): Disable epilogue vectorization in very
cheap cost model.
* doc/invoke.texi: Adjust documents for very-cheap cost model.
Jovan Vukic [Wed, 9 Oct 2024 22:53:38 +0000 (16:53 -0600)]
RISC-V: Optimize branches with shifted immediate operands
After the valuable feedback I received, it’s clear to me that the
oversight was in the tests showing the benefits of the patch. In the
test file, I added functions f5 and f6, which now generate more
efficient code with fewer instructions.
Before the patch:
f5:
li a4,2097152
addi a4,a4,-2048
li a5,1167360
and a0,a0,a4
addi a5,a5,-2048
beq a0,a5,.L4
f6:
li a5,3407872
addi a5,a5,-2048
and a0,a0,a5
li a5,1114112
beq a0,a5,.L7
After the patch:
f5:
srli a5,a0,11
andi a5,a5,1023
li a4,569
beq a5,a4,.L5
f6:
srli a5,a0,11
andi a5,a5,1663
li a4,544
beq a5,a4,.L9
PR target/115921
gcc/ChangeLog:
* config/riscv/iterators.md (any_eq): New code iterator.
* config/riscv/riscv.h (COMMON_TRAILING_ZEROS): New macro.
(SMALL_AFTER_COMMON_TRAILING_SHIFT): Ditto.
* config/riscv/riscv.md (*branch<ANYI:mode>_shiftedarith_<optab>_shifted):
New pattern.
Eric Botcazou [Wed, 9 Oct 2024 19:31:13 +0000 (21:31 +0200)]
Fix LTO bootstrap failure with -Werror=lto-type-mismatch
In GNAT's implementation model, using convention C (or C_Pass_By_Copy) has
no effect on the internal representation of types since the representation
is identical to that of C by default. It's even counter-productive given
the implementation advice listed in B.3(63-71) so the interface between the
front-end and gigi does not use it and instead uses structurally identical
types on both sides.
gcc/ada
PR ada/117038
* fe.h (struct c_array): Add 'const' to declaration of pointer.
(C_Source_Buffer): Use consistent formatting.
* par-ch3.adb (P_Component_Items): Properly set Aliased_Present on
access definition.
* sinput.ads: Remove clause for Interfaces.C.
(C_Array): Change type of Length to Integer and make both components
aliased. Remove Convention aspect.
(C_Source_Buffer): Remove all aspects.
* sinput.adb (C_Source_Buffer): Adjust to above change.
Jason Merrill [Wed, 9 Oct 2024 16:28:46 +0000 (12:28 -0400)]
c++: more modules and -M
In r15-4119-gc877a27f04f648 I told preprocess_file to use the
directives-only scan with modules, but it seems that I also need to set the
cpp_option so that communication between _cpp_handle_directive and
scan_translation_unit_directives_only works properly in
c-c++-common/cpp/embed-6.c.
gcc/c-family/ChangeLog:
* c-ppoutput.cc (preprocess_file): Set directives_only flag.
Jonathan Wakely [Fri, 4 Oct 2024 11:40:47 +0000 (12:40 +0100)]
libstdc++: Test 17_intro/names.cc with -D_FORTIFY_SOURCE=2 [PR116210]
Add a new testcase that repeats 17_intro/names.cc but with
_FORTIFY_SOURCE defined, to find problems in Glibc fortify wrappers like
https://sourceware.org/bugzilla/show_bug.cgi?id=32052 (which is fixed
now).
libstdc++-v3/ChangeLog:
PR libstdc++/116210
* testsuite/17_intro/names.cc (sz): Undef for versions of Glibc
that use it in the fortify wrappers.
* testsuite/17_intro/names_fortify.cc: New test.
Jonathan Wakely [Fri, 4 Oct 2024 11:08:12 +0000 (12:08 +0100)]
libstdc++: Drop format attribute from snprintf wrapper [PR116969]
When __LONG_DOUBLE_IEEE128__ is defined we need to declare a wrapper for
Glibc's 'snprintf' symbol, so we can call the original definition that
works with the IBM128 format of long double. Because we were declaring
the wrapper using __typeof__(__builtin_snprintf) it inherited the
__attribute__((format(printf, 3, 4))) decoration, and then we got a
warning for calling that wrapper with an __ibm128 argument for a %Lf
conversion specifier. The warning is bogus, because the function we're
calling really does want __ibm128 for %Lf, but there's no "printf but
with a different long double format" archetype for the attribute.
In r15-4039-g28911f626864e7 I added a diagnostic pragma to suppress the
warning, but it would be better to just declare the wrapper without the
attribute, and not have to suppress a warning for code that we know is
actually correct.
libstdc++-v3/ChangeLog:
PR libstdc++/116969
* include/bits/locale_facets_nonio.tcc (money_put::__do_put):
Remove diagnostic pragmas.
(__glibcxx_snprintfibm128): Declare type manually, instead of
using __typeof__(__builtin_snprintf).
aarch64: Fix SVE ACLE gimple folds for C++ LTO [PR116629]
The SVE ACLE code has two ways of handling overloaded functions.
One, used by C, is to define a single dummy function for each unique
overloaded name, with resolve_overloaded_builtin then resolving calls
to real non-overloaded functions. The other, used by C++, is to
define a separate function for each individual overload.
The builtins harness assigns integer function codes programmatically.
However, LTO requires it to use the same assignment for every
translation unit, regardless of language. This means that C++ TUs
need to create (unused) slots for the C overloads and that C TUs
need to create (unused) slots for the C++ overloads.
In many ways, it doesn't matter whether the LTO frontend itself
uses the C approach or the C++ approach to defining overloaded
functions, since the LTO frontend never has to resolve source-level
overloading. However, the C++ approach of defining a separate
function for each overload means that C++ calls never need to
be redirected to a different function. Calls to an overload
can appear in the LTO dump and survive until expand. In contrast,
calls to C's dummy overload functions are resolved by the front
end and never survive to LTO (or expand).
Some optimisations work by moving between sibling functions, such as _m
to _x. If the source function is an overload, the expected destination
function is too. The LTO frontend needs to define C++ overloads if it
wants to do this optimisation properly for C++.
The PR is about a tree checking failure caused by trying to use a
stubbed-out C++ overload in LTO. Dealing with that by detecting the
stub (rather than changing which overloads are defined) would have
turned this from an ice-on-valid to a missed optimisation.
In future, it would probably make sense to redirect overloads to
non-overloaded functions during gimple folding, in case that exposes
more CSE opportunities. But it'd probably be of limited benefit, since
it should be rare for code to mix overloaded and non-overloaded uses of
the same operation. It also wouldn't be suitable for backports.
gcc/
PR target/116629
* config/aarch64/aarch64-sve-builtins.cc
(function_builder::function_builder): Use direct overloads for LTO.
gcc/testsuite/
PR target/116629
* gcc.target/aarch64/sve/acle/general/pr106326_2.c: New test.
testsuite: Make check-function-bodies work with LTO
This patch tries to make check-function-bodies automatically
choose between reading the regular assembly file and reading the
LTO assembly file. There should only ever be one right answer,
since check-function-bodies doesn't make sense on slim LTO output.
Maybe this will turn out to be impossible to get right, but I'd like
to try at least.
gcc/testsuite/
* lib/scanasm.exp (check-function-bodies): Look in ltrans0.ltrans.s
if the test appears to be using LTO.
Jonathan Wakely [Mon, 7 Oct 2024 09:22:24 +0000 (10:22 +0100)]
libstdc++: Ignore _GLIBCXX_USE_POSIX_SEMAPHORE if not supported [PR116992]
If _GLIBCXX_HAVE_POSIX_SEMAPHRE is undefined then users get an error
when defining _GLIBCXX_USE_POSIX_SEMAPHORE. We can just ignore it
instead (and warn them it's being ignored).
This fixes a testsuite failure on hppa64-hp-hpux11.11 (and probably some
other targets):
FAIL: 30_threads/semaphore/platform_try_acquire_for.cc -std=gnu++20 (test for excess errors)
Excess errors:
semaphore:49: error: '__semaphore_impl' has not been declared
libstdc++-v3/ChangeLog:
PR libstdc++/116992
* include/bits/semaphore_base.h (_GLIBCXX_USE_POSIX_SEMAPHORE):
Undefine and issue a warning if POSIX sem_t is not supported.
* testsuite/30_threads/semaphore/platform_try_acquire_for.cc:
Prune new warning.
Jonathan Wakely [Mon, 7 Oct 2024 09:19:29 +0000 (10:19 +0100)]
libstdc++: Fix -Wnarrowing in <complex> [PR116991]
When _GLIBCXX_USE_C99_COMPLEX_ARC is undefined we use the generic
__complex_acos function template for _Float32 etc. and that gives a
-Wnarrowing warning:
complex:2043: warning: ISO C++ does not allow converting to '_Float32' from 'long double' with greater conversion rank [-Wnarrowing]
Use a cast to do the conversion so that it doesn't warn.
libstdc++-v3/ChangeLog:
PR libstdc++/116991
* include/std/complex (__complex_acos): Cast literal to
destination type.
Jonathan Wakely [Thu, 26 Sep 2024 15:55:07 +0000 (16:55 +0100)]
libstdc++: Enable _GLIBCXX_ASSERTIONS by default for -O0 [PR112808]
Too many users don't know about -D_GLIBCXX_ASSERTIONS and so are missing
valuable checks for C++ standard library preconditions. This change
enables libstdc++ assertions by default when compiling with -O0 so that
we diagnose more bugs by default.
When users enable optimization we don't add the assertions by default
(because they have non-zero overhead) so they still need to enable them
manually.
For users who really don't want the assertions even in unoptimized
builds, defining _GLIBCXX_NO_ASSERTIONS will prevent them from being
enabled automatically.
Jonathan Wakely [Thu, 26 Sep 2024 15:42:27 +0000 (16:42 +0100)]
libstdc++: Simplify std::aligned_storage and fix for versioned namespace [PR61458]
This simplifies the implementation of std::aligned_storage. For the
unstable ABI it also fixes the bug where its size is too large when the
default alignment is used. We can't fix that for the stable ABI though,
so just add a comment about the bug.
libstdc++-v3/ChangeLog:
PR libstdc++/61458
* doc/doxygen/user.cfg.in (GENERATE_BUGLIST): Set to NO.
* include/std/type_traits (__aligned_storage_msa): Remove.
(__aligned_storage_max_align_t): New struct.
(__aligned_storage_default_alignment): New function.
(aligned_storage): Use __aligned_storage_default_alignment for
default alignment. Replace union with a struct containing an
aligned buffer. Improve Doxygen comment.
(aligned_storage_t): Use __aligned_storage_default_alignment for
default alignment.
Jonathan Wakely [Thu, 11 Jul 2024 19:38:05 +0000 (20:38 +0100)]
libstdc++: Do not cast away const-ness in std::construct_at (LWG 3870)
This change also requires implementing the proposed resolution of LWG
3216 so that std::make_shared and std::allocate_shared still work, and
the proposed resolution of LWG 3891 so that std::expected still works.
libstdc++-v3/ChangeLog:
* include/bits/shared_ptr_base.h: Remove cv-qualifiers from
type managed by _Sp_counted_ptr_inplace, as per LWG 3210.
* include/bits/stl_construct.h: Do not cast away cv-qualifiers
when passing pointer to placement new.
* include/std/expected: Use remove_cv_t for union member, as per
LWG 3891.
* testsuite/20_util/allocator/void.cc: Do not test construction
via const pointer.
Jonathan Wakely [Mon, 18 Mar 2024 16:59:50 +0000 (16:59 +0000)]
libstdc++: Make std::construct_at support arrays (LWG 3436)
The issue was approved at the recent St. Louis meeting, requiring
support for bounded arrays, but only without arguments to initialize the
array elements.
libstdc++-v3/ChangeLog:
* include/bits/stl_construct.h (construct_at): Support array
types (LWG 3436).
* testsuite/20_util/specialized_algorithms/construct_at/array.cc:
New test.
* testsuite/20_util/specialized_algorithms/construct_at/array_neg.cc:
New test.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/initlist-opt1.C: Adjust for different diagnostics
from std::construct_at by adding -fconcepts-diagnostics-depth=2.
Jonathan Wakely [Fri, 27 Sep 2024 15:54:31 +0000 (16:54 +0100)]
libstdc++: Tweak %c formatting for chrono types
libstdc++-v3/ChangeLog:
* include/bits/chrono_io.h (__formatter_chrono::_M_c): Add
[[unlikely]] attribute to condition for missing %c format in
locale. Use %T instead of %H:%M:%S in fallback.
Jonathan Wakely [Wed, 18 Sep 2024 16:20:29 +0000 (17:20 +0100)]
libstdc++: Fix formatting of chrono::duration with character rep [PR116755]
Implement Peter Dimov's suggestion for resolving LWG 4118, which is to
use +d.count() so that character types are promoted to an integer type
before formatting them. This didn't have unanimous consensus in the
committee as Howard Hinnant proposed that we should format the rep
consistently with std::format("{}", d.count()) instead. That ends up
being more complicated, because it makes std::formattable a precondition
of operator<< which was not previously the case, and it means that
ios_base::fmtflags from the stream would be ignored because std::format
doesn't use them.
libstdc++-v3/ChangeLog:
PR libstdc++/116755
* include/bits/chrono_io.h (operator<<): Use +d.count() for
duration inserter.
(__formatter_chrono::_M_format): Likewise for %Q format.
* testsuite/20_util/duration/io.cc: Test durations with
character types as reps.
Richard Biener [Wed, 9 Oct 2024 09:47:08 +0000 (11:47 +0200)]
Clear DR_GROUP_NEXT_ELEMENT upon group dissolving
I've tried to sanitize DR_GROUP_NEXT_ELEMENT accesses but there are too
many so the following instead makes sure DR_GROUP_NEXT_ELEMENT is never
non-NULL for !STMT_VINFO_GROUPED_ACCESS.
* tree-vect-data-refs.cc (vect_analyze_data_ref_access): When
cancelling a DR group also clear DR_GROUP_NEXT_ELEMENT.
Richard Biener [Wed, 9 Oct 2024 09:42:59 +0000 (11:42 +0200)]
tree-optimization/117041 - fix load classification of former grouped load
When we first detect a grouped load but later dis-associate it we
only set DR_GROUP_FIRST_ELEMENT to NULL, indicating it is not a
STMT_VINFO_GROUPED_ACCESS but leave DR_GROUP_NEXT_ELEMENT set. This
causes a stray DR_GROUP_NEXT_ELEMENT access in get_group_load_store_type
to go wrong, indicating a load isn't single_element_p when it actually
is, leading to wrong classification and an ICE.
PR tree-optimization/117041
* tree-vect-stmts.cc (get_group_load_store_type): Only
check DR_GROUP_NEXT_ELEMENT for STMT_VINFO_GROUPED_ACCESS.
Richard Biener [Wed, 13 Mar 2024 13:59:27 +0000 (14:59 +0100)]
tree-optimization/116974 - Handle single-lane SLP for OMP scan store
The following massages the GIMPLE matching way of handling scan
stores to work with single-lane SLP. I do not fully understand all
the cases that can happen and the stmt matching at vectorizable_store
time is less than ideal - but the following gets me all the testcases
to pass with and without forced SLP.
Long term we want to perform the matching at SLP discovery time,
properly chaining the various SLP instances the current state ends
up with.
PR tree-optimization/116974
* tree-vect-stmts.cc (check_scan_store): Pass in the SLP node
instead of just a flag. Allow single-lane scan stores.
(vectorizable_store): Adjust.
* tree-vect-loop.cc (vect_analyze_loop_2): Empty scan_map
before re-trying.
Richard Biener [Tue, 8 Oct 2024 12:28:16 +0000 (14:28 +0200)]
tree-optimization/116575 - handle SLP of permuted masked loads
The following handles SLP discovery of permuted masked loads which
was prohibited (because wrongly handled) for PR114375. In particular
with single-lane SLP at the moment all masked group loads appear
permuted and we fail to use masked load lanes as well. The following
addresses parts of the issues, starting with doing correct basic
discovery - namely discover an unpermuted mask load followed by
a permute node. In particular groups with gaps do not support masking
yet (and didn't before w/o SLP IIRC). There's still issues with
how we represent masked load/store-lanes I think, but I first have to
get my hands on a good testcase.
PR tree-optimization/116575
PR tree-optimization/114375
* tree-vect-slp.cc (vect_build_slp_tree_2): Do not reject
permuted mask loads without gaps but instead discover a
node for the full unpermuted load and permute that with
a VEC_PERM node.
* gcc.dg/vect/vect-pr114375.c: Expect vectorization now with avx2.
Richard Biener [Tue, 8 Oct 2024 07:01:01 +0000 (09:01 +0200)]
tree-optimization/117000 - elide .REDUC_IOR with compare against zero
The following adds a pattern to elide a .REDUC_IOR operation when
the result is compared against zero with a cbranch. I've resorted
to using can_compare_p since that's what RTL expansion eventually
checks - while GIMPLE allowed whole vector equality compares for long
I'll notice vector lowering won't lower unsupported ones and RTL
expansion doesn't seem to try using [u]cmp<vector-mode> optabs
(and neither x86 nor aarch64 implements those). There's cstore
but no target implements that for vector modes either.
PR tree-optimization/117000
* match.pd (.REDUC_IOR !=/== 0): New pattern.
* gimple-match-head.cc: Include memmodel.h and optabs.h.
* generic-match-head.cc: Likewise.
Ken Matsui [Sat, 2 Mar 2024 06:10:55 +0000 (22:10 -0800)]
gcc, libcpp: Add warning switch for "#pragma once in main file" [PR89808]
This patch adds a warning switch for "#pragma once in main file". The
warning option name is Wpragma-once-outside-header, which is the same
as Clang provides.
PR preprocessor/89808
gcc/c-family/ChangeLog:
* c.opt (Wpragma_once_outside_header): Define new option.
* c.opt.urls: Regenerate.
Artemiy Volkov [Wed, 9 Oct 2024 00:06:23 +0000 (18:06 -0600)]
tree-optimization/116024 - simplify some cases of X +- C1 cmp C2
Whenever C1 and C2 are integer constants, X is of a wrapping type, and
cmp is a relational operator, the expression X +- C1 cmp C2 can be
simplified in the following cases:
(a) If cmp is <= and C2 -+ C1 == +INF(1), we can transform the initial
comparison in the following way:
X +- C1 <= C2
-INF <= X +- C1 <= C2 (add left hand side which holds for any X, C1)
-INF -+ C1 <= X <= C2 -+ C1 (add -+C1 to all 3 expressions)
-INF -+ C1 <= X <= +INF (due to (1))
-INF -+ C1 <= X (eliminate the right hand side since it holds for any X)
(b) By analogy, if cmp if >= and C2 -+ C1 == -INF(1), use the following
sequence of transformations:
X +- C1 >= C2
+INF >= X +- C1 >= C2 (add left hand side which holds for any X, C1)
+INF -+ C1 >= X >= C2 -+ C1 (add -+C1 to all 3 expressions)
+INF -+ C1 >= X >= -INF (due to (1))
+INF -+ C1 >= X (eliminate the right hand side since it holds for any X)
(c) The > and < cases are negations of (a) and (b), respectively.
This transformation allows to occasionally save add / sub instructions,
for instance the expression
3 + (uint32_t)f() < 2
compiles to
cmn w0, #4
cset w0, ls
instead of
add w0, w0, 3
cmp w0, 2
cset w0, ls
on aarch64.
Testcases that go together with this patch have been split into two
separate files, one containing testcases for unsigned variables and the
other for wrapping signed ones (and thus compiled with -fwrapv).
Additionally, one aarch64 test has been adjusted since the patch has
caused the generated code to change from
cmn w0, #2
csinc w0, w1, wzr, cc (x < -2)
to
cmn w0, #3
csinc w0, w1, wzr, cs (x <= -3)
This patch has been bootstrapped and regtested on aarch64, x86_64, and
i386, and additionally regtested on riscv32.
gcc/ChangeLog:
PR tree-optimization/116024
* match.pd: New transformation around integer comparison.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/pr116024-2.c: New test.
* gcc.dg/tree-ssa/pr116024-2-fwrapv.c: Ditto.
* gcc.target/aarch64/gtu_to_ltu_cmp_1.c: Adjust.
Artemiy Volkov [Wed, 9 Oct 2024 00:04:13 +0000 (18:04 -0600)]
tree-optimization/116024 - simplify C1-X cmp C2 for wrapping signed types
Implement a match.pd transformation inverting the sign of X in
C1 - X cmp C2, where C1 and C2 are integer constants and X is
of a wrapping signed type, by observing that:
(a) If cmp is == or !=, simply move X and C2 to opposite sides of
the comparison to arrive at X cmp C1 - C2.
(b) If cmp is <:
- C1 - X < C2 means that C1 - X spans the values of -INF,
-INF + 1, ..., C2 - 1;
- Therefore, X is one of C1 - -INF, C1 - (-INF + 1), ...,
C1 - C2 + 1;
- Subtracting (C1 + 1), X - (C1 + 1) is one of - (-INF) - 1,
- (-INF) - 2, ..., -C2;
- Using the fact that - (-INF) - 1 is +INF, derive that
X - (C1 + 1) spans the values +INF, +INF - 1, ..., -C2;
- Thus, the original expression can be simplified to
X - (C1 + 1) > -C2 - 1.
(c) Similarly, C1 - X <= C2 is equivalent to X - (C1 + 1) >= -C2 - 1.
(d) The >= and > cases are negations of (b) and (c), respectively.
(e) In all cases, the expression -C2 - 1 can be shortened to
bit_not (C2).
This transformation allows to occasionally save load-immediate /
subtraction instructions, e.g. the following statement:
10 - (int)f() >= 20;
now compiles to
addi a0,a0,-11
slti a0,a0,-20
instead of
li a5,10
sub a0,a5,a0
slti t0,a0,20
xori a0,t0,1
on 32-bit RISC-V when compiled with -fwrapv.
Additional examples can be found in the newly added test file. This
patch has been bootstrapped and regtested on aarch64, x86_64, and i386,
and additionally regtested on riscv32.
gcc/ChangeLog:
PR tree-optimization/116024
* match.pd: New transformation around integer comparison.
Artemiy Volkov [Tue, 8 Oct 2024 23:54:55 +0000 (17:54 -0600)]
tree-optimization/116024 - simplify C1-X cmp C2 for unsigned types
Implement a match.pd transformation inverting the sign of X in
C1 - X cmp C2, where C1 and C2 are integer constants and X is
of an unsigned type, by observing that:
(a) If cmp is == or !=, simply move X and C2 to opposite sides of the
comparison to arrive at X cmp C1 - C2.
(b) If cmp is <:
- C1 - X < C2 means that C1 - X spans the range of 0, 1, ..., C2 - 1;
- This means that X spans the range of C1 - (C2 - 1),
C1 - (C2 - 2), ..., C1;
- Subtracting C1 - (C2 - 1), X - (C1 - (C2 - 1)) is one of 0, 1,
..., C1 - (C1 - (C2 - 1));
- Simplifying the above, X - (C1 - C2 + 1) is one of 0, 1, ...,
C2 - 1;
- Summarizing, the expression C1 - X < C2 can be transformed
into X - (C1 - C2 + 1) < C2.
(c) Similarly, if cmp is <=:
- C1 - X <= C2 means that C1 - X is one of 0, 1, ..., C2;
- It follows that X is one of C1 - C2, C1 - (C2 - 1), ..., C1;
- Subtracting C1 - C2, X - (C1 - C2) has range 0, 1, ..., C2;
- Thus, the expression C1 - X <= C2 can be transformed into
X - (C1 - C2) <= C2.
(d) The >= and > cases are negations of (b) and (c), respectively.
This transformation allows to occasionally save load-immediate /
subtraction instructions, e.g. the following statement:
300 - (unsigned int)f() < 100;
now compiles to
addi a0,a0,-201
sltiu a0,a0,100
instead of
li a5,300
sub a0,a5,a0
sltiu a0,a0,100
on 32-bit RISC-V.
Additional examples can be found in the newly added test file. This
patch has been bootstrapped and regtested on aarch64, x86_64, and i386,
and additionally regtested on riscv32.
gcc/ChangeLog:
PR tree-optimization/116024
* match.pd: New transformation around integer comparison.
Artemiy Volkov [Tue, 8 Oct 2024 23:51:08 +0000 (17:51 -0600)]
tree-optimization/116024 - simplify C1-X cmp C2 for UB-on-overflow types
Implement a match.pd pattern for C1 - X cmp C2, where C1 and C2 are
integer constants and X is of a UB-on-overflow type. The pattern is
simplified to X rcmp C1 - C2 by moving X and C2 to the other side of the
comparison (with opposite signs). If C1 - C2 happens to overflow,
replace the whole expression with either a constant 0 or a constant 1
node, depending on the comparison operator and the sign of the overflow.
This transformation allows to occasionally save load-immediate /
subtraction instructions, e.g. the following statement:
10 - (int) x <= 9;
now compiles to
sgt a0,a0,zero
instead of
li a5,10
sub a0,a5,a0
slti a0,a0,10
on 32-bit RISC-V.
Additional examples can be found in the newly added test file. This
patch has been bootstrapped and regtested on aarch64, x86_64, and
i386, and additionally regtested on riscv32. Existing tests were
adjusted where necessary.
gcc/ChangeLog:
PR tree-optimization/116024
* match.pd: New transformation around integer comparison.
gcc/testsuite/ChangeLog:
* gcc.dg/tree-ssa/pr116024.c: New test.
* gcc.dg/pr67089-6.c: Adjust.
Yangyu Chen [Tue, 8 Oct 2024 17:08:44 +0000 (11:08 -0600)]
RISC-V: Implement TARGET_CAN_INLINE_P
Currently, we lack support for TARGET_CAN_INLINE_P on the RISC-V
ISA. As a result, certain functions cannot be optimized with inlining
when specific options, such as __attribute__((target("arch=+v"))) .
This can lead to potential performance issues when building
retargetable binaries for RISC-V.
To address this, I have implemented the riscv_can_inline_p function.
This addition enables inlining when the callee either has no special
options or when the some options match, and also ensuring that the
callee's ISA is a subset of the caller's. I also check some other
options when there is no always_inline set.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (cl_opt_var_ref_t): Add
cl_opt_var_ref_t pointer to member of cl_target_option.
(struct riscv_ext_flag_table_t): Add new cl_opt_var_ref_t field.
(RISCV_EXT_FLAG_ENTRY): New macro to simplify the definition of
riscv_ext_flag_table.
(riscv_ext_is_subset): New function to check if the callee's ISA
is a subset of the caller's.
(riscv_x_target_flags_isa_mask): New function to get the mask of
ISA extension in x_target_flags of gcc_options.
* config/riscv/riscv-subset.h (riscv_ext_is_subset): Declare
riscv_ext_is_subset function.
(riscv_x_target_flags_isa_mask): Declare
riscv_x_target_flags_isa_mask function.
* config/riscv/riscv.cc (riscv_can_inline_p): New function.
(TARGET_CAN_INLINE_P): Implement TARGET_CAN_INLINE_P.
Pan Li [Tue, 8 Oct 2024 03:28:44 +0000 (11:28 +0800)]
RISC-V: Add testcases for form 1 of scalar signed SAT_TRUNC
Form 1:
#define DEF_SAT_S_TRUNC_FMT_1(WT, NT, NT_MIN, NT_MAX) \
NT __attribute__((noinline)) \
sat_s_trunc_##WT##_to_##NT##_fmt_1 (WT x) \
{ \
NT trunc = (NT)x; \
return (WT)NT_MIN <= x && x <= (WT)NT_MAX \
? trunc \
: x < 0 ? NT_MIN : NT_MAX; \
}
The below test are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_arith_data.h: Add test data for SAT_TRUNC.
* gcc.target/riscv/sat_s_trunc-1-i16-to-i8.c: New test.
* gcc.target/riscv/sat_s_trunc-1-i32-to-i16.c: New test.
* gcc.target/riscv/sat_s_trunc-1-i32-to-i8.c: New test.
* gcc.target/riscv/sat_s_trunc-1-i64-to-i16.c: New test.
* gcc.target/riscv/sat_s_trunc-1-i64-to-i32.c: New test.
* gcc.target/riscv/sat_s_trunc-1-i64-to-i8.c: New test.
* gcc.target/riscv/sat_s_trunc-run-1-i16-to-i8.c: New test.
* gcc.target/riscv/sat_s_trunc-run-1-i32-to-i16.c: New test.
* gcc.target/riscv/sat_s_trunc-run-1-i32-to-i8.c: New test.
* gcc.target/riscv/sat_s_trunc-run-1-i64-to-i16.c: New test.
* gcc.target/riscv/sat_s_trunc-run-1-i64-to-i32.c: New test.
* gcc.target/riscv/sat_s_trunc-run-1-i64-to-i8.c: New test.
Before this patch:
10 │ sat_s_trunc_int64_t_to_int32_t_fmt_1:
11 │ li a5,1
12 │ slli a5,a5,31
13 │ li a4,-1
14 │ add a5,a0,a5
15 │ srli a4,a4,32
16 │ bgtu a5,a4,.L2
17 │ sext.w a0,a0
18 │ ret
19 │ .L2:
20 │ srai a5,a0,63
21 │ li a0,-2147483648
22 │ xor a0,a0,a5
23 │ not a0,a0
24 │ ret
After this patch:
10 │ sat_s_trunc_int64_t_to_int32_t_fmt_1:
11 │ li a5,-2147483648
12 │ xori a3,a5,-1
13 │ slt a4,a0,a3
14 │ slt a5,a5,a0
15 │ and a5,a4,a5
16 │ srai a4,a0,63
17 │ xor a4,a4,a3
18 │ addi a3,a5,-1
19 │ neg a5,a5
20 │ and a4,a4,a3
21 │ and a0,a0,a5
22 │ or a0,a0,a4
23 │ sext.w a0,a0
24 │ ret
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_expand_sstrunc): Add new
func decl to expand SAT_TRUNC.
* config/riscv/riscv.cc (riscv_expand_sstrunc): Add new func
impl to expand SAT_TRUNC.
* config/riscv/riscv.md (sstrunc<mode><anyi_double_truncated>2):
Add new pattern for double truncation.
(sstrunc<mode><anyi_quad_truncated>2): Ditto but for quad.
(sstrunc<mode><anyi_oct_truncated>2): Ditto but for oct.
Pan Li [Tue, 8 Oct 2024 03:06:23 +0000 (11:06 +0800)]
Widening-Mul: Fix one bug of consume after phi node released
When try to matching saturation related pattern on PHI node, we may have
to try each pattern for all phi node of bb. Aka:
for each PHI node in bb:
gphi *phi = xxx;
try_match_sat_add (, phi);
try_match_sat_sub (, phi);
try_match_sat_trunc (, phi);
The PHI node will be removed if one of the above 3 sat patterns are
matched. There will be a problem that, for example, sat_add is
matched and then the phi is removed(freed), and the next 2 sat_sub and
sat_trunc will depend on the removed(freed) phi node.
This patch would like to fix this consume after phi node released issue.
To ensure at most one pattern of the above will be matched.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
* The x86 bootstrap test.
* The x86 fully regression test.
gcc/ChangeLog:
* tree-ssa-math-opts.cc (build_saturation_binary_arith_call): Rename
to...
(build_saturation_binary_arith_call_and_replace): ...this.
(build_saturation_binary_arith_call_and_insert): ...this.
(match_unsigned_saturation_add): Leverage renamed func.
(match_unsigned_saturation_sub): Ditto.
(match_saturation_add): Return bool on matched and leverage
renamed func.
(match_saturation_sub): Ditto.
(match_saturation_trunc): Ditto.
(math_opts_dom_walker::after_dom_children): Ensure at most one
pattern will be matched for each phi node.
The below test suites are passed for this patch.
* The rv64gcv fully regression test with pr116861-1.c failed.
* The x86 bootstrap test.
* The x86 fully regression test.
The failed pr116861-1.c ice will be fixed in underlying patch, as it
just trigger one existing bug.
gcc/ChangeLog:
* match.pd: Add case 1 matching pattern for signed SAT_TRUNC.
* tree-ssa-math-opts.cc (gimple_signed_integer_sat_trunc): Add
new decl for signed SAT_TRUNC.
(match_saturation_trunc): Add new func impl to try SAT_TRUNC
pattern on phi node.
(math_opts_dom_walker::after_dom_children): Add
match_saturation_trunc for phi node iteration.
Jan Beulich [Tue, 8 Oct 2024 14:05:33 +0000 (16:05 +0200)]
x86/{,V}AES: adjust when to force EVEX encoding
Commit a79d13a01f8c ("i386: Fix aes/vaes patterns [PR114576]") correctly
said "..., but we need to emit {evex} prefix in the assembly if AES ISA
is not enabled". Yet it did so only for the TARGET_AES insns. Going from
the alternative chosen in the TARGET_VAES insns isn't quite right: If
AES is (also) enabled, EVEX encoding would needlessly be forced.
Palmer Dabbelt [Tue, 8 Oct 2024 13:28:32 +0000 (07:28 -0600)]
[RISC-V][PR target/116615] RISC-V: Use default LOGICAL_OP_NON_SHORT_CIRCUIT
> We have cheap logical ops, so let's just move this back to the default
> to take advantage of the standard branch/op hueristics.
>
> gcc/ChangeLog:
>
> PR target/116615
> * config/riscv/riscv.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Remove.
> ---
> There's a bunch more discussion in the bug, but it's starting to smell
> like this was just a holdover from MIPS (where maybe it also shouldn't
> be set). I haven't tested this, but I figured I'd send the patch to get
> a little more visibility.
>
> I guess we should also kick off something like a SPEC run to make sure
> there's no regressions?
So as I noted earlier, this appears to be a nice win on the BPI. Testsuite
fallout is minimal -- just the one SFB related test tripping at -Os that was
also hit by Andrew P's work.
After looking at it more closely, the SFB codegen and the codegen after
Andrew's work should be equivalent assuming two independent ops can dispatch
together.
The test actually generates sensible code at -Os. It's the -Os in combination
with the -fno-ssa-phiopt that causes problems. I think the best thing to do
here is just skip at -Os. That still keeps a degree of testing the SFB path.
Tested successfully in my tester. But will wait for the pre-commit tester to
render a verdict before moving forward.
Fix parsing of substring refs in coarrays. [PR51815]
The parser was greadily taking the substring ref as an array ref because
an array_spec was present. Fix this by only parsing the coarray (pseudo)
ref when no regular array is present.
gcc/fortran/ChangeLog:
PR fortran/51815
* array.cc (gfc_match_array_ref): Only parse coarray part of
ref.
* match.h (gfc_match_array_ref): Add flag.
* primary.cc (gfc_match_varspec): Request only coarray ref
parsing when no regular array is present. Report error on
unexpected additional ref.
gcc/testsuite/ChangeLog:
* gfortran.dg/pr102532.f90: Fix dg-errors: Add new error.
* gfortran.dg/coarray/substring_1.f90: New test.
Pan Li [Thu, 3 Oct 2024 08:47:52 +0000 (16:47 +0800)]
RISC-V: Add testcases for form 4 of scalar signed SAT_SUB
Form 4:
#define DEF_SAT_S_SUB_FMT_4(T, UT, MIN, MAX) \
T __attribute__((noinline)) \
sat_s_sub_##T##_fmt_4 (T x, T y) \
{ \
T minus; \
bool overflow = __builtin_sub_overflow (x, y, &minus); \
return !overflow ? minus : x < 0 ? MIN : MAX; \
}
The below test are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_s_sub-4-i16.c: New test.
* gcc.target/riscv/sat_s_sub-4-i32.c: New test.
* gcc.target/riscv/sat_s_sub-4-i64.c: New test.
* gcc.target/riscv/sat_s_sub-4-i8.c: New test.
* gcc.target/riscv/sat_s_sub-run-4-i16.c: New test.
* gcc.target/riscv/sat_s_sub-run-4-i32.c: New test.
* gcc.target/riscv/sat_s_sub-run-4-i64.c: New test.
* gcc.target/riscv/sat_s_sub-run-4-i8.c: New test.
Pan Li [Thu, 3 Oct 2024 08:15:56 +0000 (16:15 +0800)]
RISC-V: Add testcases for form 3 of scalar signed SAT_SUB
Form 3:
#define DEF_SAT_S_SUB_FMT_3(T, UT, MIN, MAX) \
T __attribute__((noinline)) \
sat_s_sub_##T##_fmt_3 (T x, T y) \
{ \
T minus; \
bool overflow = __builtin_sub_overflow (x, y, &minus); \
return overflow ? x < 0 ? MIN : MAX : minus; \
}
The below test are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add test helper macros.
* gcc.target/riscv/sat_s_sub-3-i16.c: New test.
* gcc.target/riscv/sat_s_sub-3-i32.c: New test.
* gcc.target/riscv/sat_s_sub-3-i64.c: New test.
* gcc.target/riscv/sat_s_sub-3-i8.c: New test.
* gcc.target/riscv/sat_s_sub-run-3-i16.c: New test.
* gcc.target/riscv/sat_s_sub-run-3-i32.c: New test.
* gcc.target/riscv/sat_s_sub-run-3-i64.c: New test.
* gcc.target/riscv/sat_s_sub-run-3-i8.c: New test.
Jakub Jelinek [Tue, 8 Oct 2024 08:40:29 +0000 (10:40 +0200)]
ssa-math-opts, i386: Handle most unordered values rather than just 2 [PR116896]
On Mon, Oct 07, 2024 at 10:32:57AM +0200, Richard Biener wrote:
> > They are implementation defined, -1, 0, 1, 2 is defined by libstdc++:
> > using type = signed char;
> > enum class _Ord : type { equivalent = 0, less = -1, greater = 1 };
> > enum class _Ncmp : type { _Unordered = 2 };
> > https://eel.is/c++draft/cmp#categories.pre-1 documents them as
> > enum class ord { equal = 0, equivalent = equal, less = -1, greater = 1 }; // exposition only
> > enum class ncmp { unordered = -127 }; // exposition only
> > and now looking at it, LLVM's libc++ takes that literally and uses
> > -1, 0, 1, -127. One can't use <=> operator without including <compare>
> > which provides the enums, so I think if all we care about is libstdc++,
> > then just hardcoding -1, 0, 1, 2 is fine, if we want to also optimize
> > libc++ when used with gcc, we could support -1, 0, 1, -127 as another
> > option.
> > Supporting arbitrary 4 values doesn't make sense, at least on x86 the
> > only reason to do the conversion to int in an optab is a good sequence
> > to turn the flag comparisons to -1, 0, 1. So, either we do nothing
> > more than the patch, or add handle both 2 and -127 for unordered,
> > or add support for arbitrary value for the unordered case except
> > -1, 0, 1 (then -1 could mean signed int, 1 unsigned int, 0 do the jumps
> > and any other value what should be returned for unordered.
Here is an incremental patch which adds support for (almost) arbitrary
unordered constant value. It changes the .SPACESHIP and spaceship<mode>4
optab conventions, so 0 means use branches, floating point, -1, 0, 1, 2
results consumed by tree-ssa-math-opts.cc emitted comparisons, -1
means signed int comparisons, -1, 0, 1 results, 1 means unsigned int
comparisons, -1, 0, 1 results, and for constant other than -1, 0, 1
which fit into [-128, 127] converted to the PHI type are otherwise
specified as the last argument (then it is -1, 0, 1, C results).
2024-10-08 Jakub Jelinek <jakub@redhat.com>
PR middle-end/116896
* tree-ssa-math-opts.cc (optimize_spaceship): Handle unordered values
other than 2, but they still need to be signed char range possibly
converted to the PHI result and can't be in [-1, 1] range. Use
last .SPACESHIP argument of 1 for unsigned int comparisons, -1 for
signed int, 0 for floating point branches and any other for floating
point with that value as unordered.
* config/i386/i386-expand.cc (ix86_expand_fp_spaceship): Use op2 rather
const2_rtx if op2 is not const0_rtx for unordered result.
(ix86_expand_int_spaceship): Change INTVAL (op2) == 1 tests to
INTVAL (op2) != -1.
* doc/md.texi (spaceship@var{m}4): Document the above changes.
Eric Botcazou [Wed, 11 Sep 2024 18:15:32 +0000 (20:15 +0200)]
ada: Fix infinite loop on MSP430 with -mlarge flag
This removes the loop trying to find a pointer mode among the integer modes,
which is obsolete and does not work on platforms where pointers have unusual
size like MSP430 or special semantics like Morello.
gcc/ada/ChangeLog:
PR ada/116498
* gcc-interface/decl.cc (validate_size): Use the size of the default
pointer mode as the minimum size for access types and fat pointers.
Eric Botcazou [Tue, 10 Sep 2024 13:02:19 +0000 (15:02 +0200)]
ada: Remove -gnateE information message for noncontiguous enumeration type
It is very confusing for the user because it does not make any reference
to the source code but only to details of the underlying implementation.
gcc/ada/ChangeLog:
* gcc-interface/trans.cc (Raise_Error_to_gnu) <CE_Invalid_Data>:
Do not the generate range information if the value is a call to a
Rep_To_Pos function.
The initial signal handling code introduced for aarch64-android
overlooked details of the tasking runtime, not in the initial testing
perimeter.
Specifically, a reference to __gnat_sigtramp from __gnat_error_handler,
initially introduced for the arm port, was prevented if !arm on the
grounds that other ports would rely on kernel CFI. aarch64-android
does provide kernel CFI and __gnat_sigtramp was not provided for this
configuration.
But there is a similar reference from s-intman__android, which kicks in
as soon as the tasking runtime gets activated, triggering link failures.
Testing for more precise target specific parameters from Ada
code is inconvenient and replicating the logic is not attractive in
any case, so this change addresses the problem in the following
fashion:
- Always provide a __gnat_sigtramp entry point, common to the
tasking and non-tasking signal handling code for all the Android
configurations,
- There (C code), from target definition macros, select a path
that either routes directly to the actual signal handler or goes
through the intermediate layer providing hand crafted CFI
information which allows unwinding up to the interrupted code.
- Similarily to what was done for VxWorks, move the arm specific
definitions to a separate header file to make the general structure
of the common C code easier to grasp,
- Adjust the comments in the common sigtramp.h header to
account for such an organisation possibility.
gcc/ada/ChangeLog:
* sigtramp-armdroid.c: Refactor into ...
* sigtramp-android.c, sigtramp-android-asm.h: New files.
* Makefile.rtl (arm/aarch64-android section): Add
sigtramp-android.o to EXTRA_LIBGNAT_OBJS unconditionally. Add
sigtramp.h and sigtramp-android-asm.h to EXTRA_LIBGNAT_SRCS.
* init.c (android section, __gnat_error_handler): Defer to
__gnat_sigramp unconditionally again.
* sigtramp.h: Adjust comments to allow neutral signal handling
relays, merely forwarding to the underlying handler without any
intermediate CFI magic.
Eric Botcazou [Thu, 12 Sep 2024 10:45:27 +0000 (12:45 +0200)]
ada: Fix bogus Constraint_Error for 'Wide_Wide_Value on wide enumeration literal
The problem is that 'Wide_Wide_Value is piggybacked on 'Value and the latter
invokes System.Val_Util.Normalize_String, which incorrectly normalizes the
input string in the presence of enumeration literals with wide characters.
gcc/ada/ChangeLog:
PR ada/115507
* exp_imgv.adb (Expand_Valid_Value_Attribute): Add actual parameter
for Is_Wide formal in the call to Valid_Value_Enumeration_NN.
(Expand_Value_Attribute): Likewise.
* libgnat/s-vaen16.ads (Value_Enumeration_16): Add Is_Wide formal.
(Valid_Value_Enumeration_16): Likewise.
* libgnat/s-vaen32.ads (Value_Enumeration_32): Likewise.
(Valid_Value_Enumeration_32): Likewise.
* libgnat/s-vaenu8.ads (Value_Enumeration_8): Likewise.
(Valid_Value_Enumeration_8): Likewise.
* libgnat/s-valboo.adb (Value_Boolean): Pass True for To_Upper_Case
formal parameter in call to Normalize_String.
* libgnat/s-valcha.adb (Value_Character): Likewise.
* libgnat/s-valuen.ads (Value_Enumeration): Add Is_Wide formal.
(Valid_Value_Enumeration): Likewise.
* libgnat/s-valuen.adb (Value_Enumeration_Pos): Likewise and pass
its negation for To_Upper_Case formal in call to Normalize_String.
(Valid_Value_Enumeration): Add Is_Wide formal and forward it in
call to Value_Enumeration_Pos.
(Value_Enumeration): Likewise.
* libgnat/s-valuti.ads (Normalize_String): Add To_Upper_Case formal
parameter and adjust post-condition accordingly.
* libgnat/s-valuti.adb (Normalize_String): Add To_Upper_Case formal
parameter and adjust implementation accordingly.
* libgnat/s-valwch.adb (Value_Wide_Wide_Character): Pass False for
To_Upper_Case formal parameter in call to Normalize_String.
Eric Botcazou [Wed, 11 Sep 2024 17:42:03 +0000 (19:42 +0200)]
ada: Fix bogus error in instantiation with formal package
The compiler reports that an actual does not match the formal when there
is a defaulted formal discrete type because Check_Formal_Package_Instance
fails to skip the implicit base type generated by the compiler.
gcc/ada/ChangeLog:
PR ada/114636
* sem_ch12.adb (Check_Formal_Package_Instance): For a defaulted
formal discrete type, skip the generated implicit base type.
Eric Botcazou [Wed, 11 Sep 2024 17:37:08 +0000 (19:37 +0200)]
ada: Fix negative value returned by 'Image for array with nonnegative component
The problem is that Exp_Put_Image.Build_Elementary_Put_Image_Call uses the
signedness of the base type but the size of the first subtype, hence the
discrepancy between them.
gcc/ada/ChangeLog:
PR ada/115535
* exp_put_image.adb (Build_Elementary_Put_Image_Call): Use the size
of the underlying type to find the support type.
Eric Botcazou [Wed, 11 Sep 2024 17:26:18 +0000 (19:26 +0200)]
ada: Fix internal error on elsif part of if-statement containing if-expression
The problem occurs when the compiler is trying to find a context to which
it can hoist finalization actions coming from the if-expression, because
Find_Hook_Context incorrectly returns the N_Elsif_Part node.
gcc/ada/ChangeLog:
PR ada/114640
* exp_util.adb (Find_Hook_Context): For a node present within a
conditional expression, do not return an N_Elsif_Part node.
A container aggregate can either be empty, contain only
positional elements or named element associations. Reject the
scenario where the latter two are both used.
gcc/ada/ChangeLog:
* diagnostics-constructors.adb
(Make_Mixed_Container_Aggregate_Error): New function for the error
message
(Record_Mixed_Container_Aggregate_Error): New function for the
error message.
* diagnostics-constructors.ads: Likewise.
* diagnostics-repository.ads: register new diagnostics id
* diagnostics.ads: add new diagnostics id
* errout.adb (First_And_Last_Node): Detect the span for component
associations.
* sem_aggr.adb (Resolve_Container_Aggregate): reject container
aggregates that have both named and positional elements.
ada: Add mechanism to test internal error machinery
This patch adds a pragma that triggers an internal compiler error when
analyzed. It is not externally documented and makes it possible to test
the code that runs when the compiler encounters an internal error.
gcc/ada/ChangeLog:
* snames.ads-tmpl: Add new pragma definition.
* par-prag.adb (Prag): Handle new pragma.
* sem_prag.adb (Analyze_Pragma): Implement new pragma.
This patch puts a comment explaining the absence of Storage_Size in an
alphabetically sorted list at the spot where Storage_Size would be in
that list.
gcc/ada/ChangeLog:
* snames.ads-tmpl: Tweak position of comment.
gcc/ada/ChangeLog:
* doc/gnat_rm/gnat_language_extensions.rst: replace
references to RFC's with appropriate text from the rfc
* gnat_rm.texi: Regenerate.
* gnat_ugn.texi: Regenerate.
ada: Add dependency lines for External_Initialization
When a file included through External_Initialization has been modified,
the unit including it must be recompiled. This patch adds the
generation of dependency lines to the handling of the
External_Initialization aspect, to signal that fact to gnatmake and
other tools that invoke GNAT.
projects / thirdparty / gcc.git / log
