This patch adds a helper routine that constructs rtxes
for constant shift amounts, given the mode of the value
being shifted. As well as helping with the SVE patches, this
is one step towards allowing CONST_INTs to have a real mode.
One long-standing problem has been to decide what the mode
of a shift count should be for arbitrary rtxes (as opposed to those
directly tied to a target pattern). Realistic choices would be
the mode of the shifted elements, word_mode, QImode, a 64-bit mode,
or the same mode as the shift optabs (in which case what should the
mode be when the target doesn't have a pattern?)
For now the patch picks a 64-bit mode, but with a ??? comment.
2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
Fix a stupid inversion. This function is very rarely used and was
mostly to help split patches up, which is why it didn't get picked
up during initial testing.
2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* poly-int.h (multiple_p): Fix handling of two non-poly_ints.
gcc/testsuite/
* gcc.dg/plugin/poly-int-tests.h (test_nonpoly_multiple_p): New
function.
(test_nonpoly_type): Call it.
Richard Earnshaw [Wed, 20 Dec 2017 10:30:00 +0000 (10:30 +0000)]
[arm] PR target/83105: Minor change of default CPU for arm-linux-gnueabi
When GCC for ARM/linux is configured with --with-float=hard, or
--with-float=softfp the compiler will now die when trying to build the
support libraries because the baseline architecture is too old to
support VFP (older versions of GCC just emitted the VFP instructions
anyway, even though they wouldn't run on that version of the
architecture; but we're now more prickly about it).
This patch fixed the problem by raising the default architecture
(actually the default CPU) to ARMv5te (ARM10e) when we need to generate
HW floating-point code.
PR target/83105
* config.gcc (arm*-*-linux*): When configured with --with-float=hard
or --with-float=softfp, set the default CPU to arm10e.
Kyrylo Tkachov [Wed, 20 Dec 2017 10:28:13 +0000 (10:28 +0000)]
[aarch64][libstdc++] Use __ARM_BIG_ENDIAN instead of __AARCH64EB__ in opt_random.h
As has been spotted at https://gcc.gnu.org/ml/gcc-patches/2017-12/msg01289.html
we check the __AARCH64EB__ macro for aarch64 big-endian
detection in config/cpu/aarch64/opt/ext/opt_random.h.
That works just fine with GCC but the standardised ACLE[1] macro
for that purpose is __ARM_BIG_ENDIAN so there is a possibility
that non-GCC compilers that include this header are not aware
of this predefine.
So this patch changes the use of __AARCH64EB__ to
the more portable __ARM_BIG_ENDIAN.
Tested on aarch64-none-elf and aarch64_be-none-elf.
Preapproved by Jeff at https://gcc.gnu.org/ml/gcc-patches/2017-12/msg01326.html
* config/cpu/aarch64/opt/ext/opt_random.h (__VEXT): Check
__ARM_BIG_ENDIAN instead of __AARCH64EB__.
Marek Polacek [Tue, 19 Dec 2017 20:44:19 +0000 (20:44 +0000)]
re PR c++/82231 (ICE when deducing non-type template parameter value whose type depends on a non-type `auto` template parameter from function arguments)
PR c++/82231
* g++.dg/cpp1z/nontype-auto14.C: New test.
Jakub Jelinek [Tue, 19 Dec 2017 18:10:04 +0000 (19:10 +0100)]
re PR tree-optimization/83444 (missing strlen optimization on a member array of a local struct)
PR tree-optimization/83444
* tree-ssa-strlen.c (strlen_check_and_optimize_stmt): For the
character load case, if get_stridx on MEM_REF's operand doesn't
look usable, retry with get_addr_stridx.
Alexandre Oliva [Tue, 19 Dec 2017 17:50:31 +0000 (17:50 +0000)]
[SFN] start rtl block with label, then markers
Emitting markers before labels turned out to not be worth the trouble.
The markers outside BBs confuse the ebb scheduler, and they don't add
any useful information. I'll arrange for markers to be moved past
labels, even in gimple, but for now this will fix the two remaining
known problems on ia64.
for gcc/ChangeLog
PR bootstrap/83396
* cfgexpand.c (expand_gimple_basic_block): Expand label first,
even if there are markers before it.
* cfgrtl.c (rtl_verify_bb_layout): Reject DEBUG_INSNs outside BBs.
Kyrylo Tkachov [Tue, 19 Dec 2017 16:58:22 +0000 (16:58 +0000)]
[arm] PR target/82975: Guard against reg_renumber being NULL in arm.h
In this bug we ICE when checking REGNO_OK_FOR_INDEX_P on arm during pre-IRA scheduling.
This is because REGNO_OK_FOR_INDEX_P ends up checking the reg_renumber array.
Before IRA reg_renumber is NULL and thus we segfault.
The fix is to guard the use of reg_renumber in the logic in TEST_REGNO in arm.h.
On aarch64, for example, we also guard against the reg_renumber == NULL case.
This fixes the ICE. I also remove the part of the comment that muses on when reg_renumber
is available as with this patch it should now be safe to use at any point.
Bootstrapped and tested on arm-none-linux-gnueabihf.
PR target/82975
* config/arm/arm.h (TEST_REGNO): Check reg_renumber is set before
accessing it. Adjust comment.
Jakub Jelinek [Tue, 19 Dec 2017 16:43:04 +0000 (17:43 +0100)]
re PR middle-end/81914 (gcc 7.1 generates branch for code which was branchless in earlier gcc version)
PR middle-end/81914
* predict.c (zero_one_minusone): New function.
(apply_return_prediction): Avoid return prediction for functions
returning only -1, 0 and 1 values, unless they only return -1 and 0
or 0 and 1.
Martin Liska [Tue, 19 Dec 2017 13:21:07 +0000 (14:21 +0100)]
Fix another failing test-case.
2017-12-19 Martin Liska <mliska@suse.cz>
* gcc.dg/tree-prof/switch-case-1.c: Scan IPA profile dump
file instead of expand in order to not mix it with expanded
tree decision tree for the switch statement.
Daniel Cederman [Tue, 19 Dec 2017 08:04:52 +0000 (08:04 +0000)]
SPARC: Make sure that jump is to a label in errata workaround
In some cases the jump could be to a return instruction and in those cases the
next_active_insn() function tries to follow an invalid pointer which leads to a
crash. This error did not manifest when using a 32-bit version of GCC which is
why I did not detect it before.
gcc/
* config/sparc/sparc.c (sparc_do_work_around_errata): Make sure
the jump is to a label.
Jakub Jelinek [Tue, 19 Dec 2017 07:41:30 +0000 (08:41 +0100)]
re PR ipa/82801 (Internal compiler error with Eigen and __attribute__((always_inline, flatten)))
PR ipa/82801
PR ipa/83346
* ipa-inline.c (flatten_remove_node_hook): New function.
(ipa_inline): Keep only nodes with flatten attribute at the end of
the array in the order from ipa_reverse_postorder, only walk that
portion of array for flattening, if there is more than one such
node, temporarily register a removal hook and ignore removed nodes.
Jakub Jelinek [Tue, 19 Dec 2017 07:39:24 +0000 (08:39 +0100)]
re PR tree-optimization/80631 (Compiling with -O3 -mavx2 gives wrong code)
PR tree-optimization/80631
* tree-vect-loop.c (vect_create_epilog_for_reduction): Compare
induc_code against MAX_EXPR or MIN_EXPR instead of reduc_fn against
IFN_REDUC_MAX or IFN_REDUC_MIN.
Martin Sebor [Mon, 18 Dec 2017 22:49:57 +0000 (22:49 +0000)]
PR middle-end/83373 - False positive reported by -Wstringop-overflow
PR middle-end/83373 - False positive reported by -Wstringop-overflow
PR tree-optimization/78450 - strlen(s) return value can be assumed to be less than the size of s
gcc/ChangeLog:
PR middle-end/83373
PR tree-optimization/78450
* tree-ssa-strlen.c (maybe_set_strlen_range): New function.
(handle_builtin_strlen): Call it.
gcc/testsuite/ChangeLog:
PR middle-end/83373
PR tree-optimization/78450
* gcc.dg/pr83373.c: New test.
* gcc.dg/strlenopt-36.c: New test.
* gcc.dg/strlenopt-37.c: New test.
rtlanal: dead_or_set_regno_p should handle CLOBBER (PR83424)
In PR83424 combine's move_deaths puts a REG_DEAD note in the wrong place
because dead_or_set_regno_p does not account for CLOBBER insns. This
fixes it.
PR rtl-optimization/83424
* rtlanal.c (dead_or_set_regno_p): Handle CLOBBER just like SET.
gcc/testsuite/
PR rtl-optimization/83424
* gcc.dg/pr83424.c: New testsuite.
David Malcolm [Mon, 18 Dec 2017 19:23:30 +0000 (19:23 +0000)]
testsuite: add coverage for diagnostics relating to inlining (PR tree-optimization/83336)
In theory, the diagnostics subsystem can print context information on
code inlining when diagnostics are emitted by the middle-end, describing
the chain of inlined callsites that led to a particular warning,
but PR tree-optimization/83336 describes various issues with this.
An underlying issue is that we have very little automated testing for
this code: gcc.dg/tm/pr52141.c has a test, but in general, prune.exp
filters out the various "inlined from" lines.
The following patch adds test coverage for it for C and C++ via a new
testsuite plugin, which emits a warning from the middle-end; the test
cases use dg-regexp to verify that the "inlined from" lines are
emitted correctly, with the correct function names and source locations.
Doing so requires a change to prune.exp: the dg-regexp lines have to
be handled *before* the "inlined from" lines are stripped.
gcc/testsuite/ChangeLog:
PR tree-optimization/83336
* g++.dg/cpp0x/missing-initializer_list-include.C: Update for
changes to prune.exp's handling of dg-regexp.
* g++.dg/plugin/diagnostic-test-inlining-1.C: New test case.
* g++.dg/plugin/plugin.exp (plugin_test_list): Add it, via
gcc.dg's plugin/diagnostic_plugin_test_inlining.c.
* gcc.dg/plugin/diagnostic-test-inlining-1.c: New test case.
* gcc.dg/plugin/diagnostic-test-inlining-2.c: Likewise.
* gcc.dg/plugin/diagnostic-test-inlining-3.c: Likewise.
* gcc.dg/plugin/diagnostic-test-inlining-4.c: Likewise.
* gcc.dg/plugin/diagnostic_plugin_test_inlining.c: New test
plugin.
* gcc.dg/plugin/plugin.exp (plugin_test_list): Add them.
* lib/prune.exp (prune_gcc_output): Move call to handle-dg-regexps
to before the various text stripping regsup invocations,
in particular, to before the stripping of "inlined from".
Jakub Jelinek [Mon, 18 Dec 2017 17:52:13 +0000 (18:52 +0100)]
re PR c++/83300 (Segmentation fault with template and __attribute__((vector_size (sizeof(int) * N)));)
PR c++/83300
* decl2.c (save_template_attributes): Add flags argument, if
not ATTR_FLAG_TYPE_IN_PLACE, *decl_p is a type and we want to
modify TYPE_ATTRIBUTES, add them on type attribute variant.
Marek Polacek [Mon, 18 Dec 2017 16:44:35 +0000 (16:44 +0000)]
re PR middle-end/83463 (ICE: tree check: expected integer_type or enumeral_type or boolean_type or real_type or fixed_point_type, have pointer_type in builtin_memr ef, at gimple-ssa-warn-restrict.c:297)
PR middle-end/83463
* gimple-ssa-warn-restrict.c (builtin_memref::builtin_memref):
Check if TYPE is INTEGRAL_TYPE_P before accessing its min/max
values.
The accumulator registers are freely used by the compiler. However,
there are a number of instructions which are having an intrinsic use
of these registers. Update patterns to inform the compiler which ones.
Richard Biener [Mon, 18 Dec 2017 08:33:26 +0000 (08:33 +0000)]
re PR tree-optimization/77291 (False positive for -Warray-bounds)
2017-12-18 Richard Biener <rguenther@suse.de>
PR middle-end/77291
* tree.c (array_at_struct_end_p): Return true if the underlying
object has space for at least one element in excess of what
the array domain specifies.
gcc/
* doc/invoke.texi (Option Summary): Add -mverbose-cost-dump
to AArch64 and ARM lists, plus missing -mflip-thumb for ARM.
(AArch64 Options): Document -mverbose-cost-dump.
(ARM Options): Likewise, plus -mflip-thumb.
Janne Blomqvist [Sun, 17 Dec 2017 16:28:08 +0000 (18:28 +0200)]
Support -std=f2018
The Fortran committee has decided to rename the upcoming Fortran 2015
standard to Fortran 2018. This is not a reflection of a three year
delay in the process, but rather they are following other standards in
adopting the year of publication for the name. For more details see
N2144.
This patch renames GFC_STD_F2015 to GFC_STD_F2018, and makes it a
separate flag rather than an alias for GFC_STD_GNU. Also, it adds a
-std=f2018 argument, and documents it.
Regtested on x86_64-pc-linux-gnu.
gcc/fortran/ChangeLog:
2017-12-17 Janne Blomqvist <jb@gcc.gnu.org>
* decl.c (gfc_match_implicit_none): Use GFC_STD_F2018 instead of
GFC_STD_F2015.
* error.c (gfc_notify_std): Add GFC_STD_F2018{_DEL,_OBS} to
switch.
* gfortran.texi: Document -std=f2018.
* interface.c (compare_parameter): Fix comment.
* invoke.texi: Document -std=f2018.
* lang.opt: Add -std=f2018 argumnet.
* libgfortran.h (GFC_STD_F2015): Rename to GFC_STD_F0218, use
separate flag bit.
(GFC_STD_F2018_DEL): New macro.
(GFC_STD_F2018_OBS): Likewise.
* match.c (gfc_match_stopcode): Use GFC_STD_F2018.
* options.c (set_default_std_flags): Add F2018 flags to defaults.
(gfc_handle_option): Set options for -std=f2018.
Jerry DeLisle [Sat, 16 Dec 2017 19:50:42 +0000 (19:50 +0000)]
re PR libfortran/81937 (stack-buffer-overflow on memcpy in libgfortran/io/unix.c on character(kind=4))
2017-12-16 Jerry DeLisle <jvdelisle@gcc.gnu.org>
PR libgfortran/81937
* io/list_read.c (next_char_internal): Don't attempt to read
from the internal unit stream if no bytes are left. Decrement
bytes_left in the right place.
This patch changes the bit size and vector count arguments to the
machmode.h functions from unsigned int to poly_uint64.
2017-12-16 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* machmode.h (mode_for_size, int_mode_for_size, float_mode_for_size)
(smallest_mode_for_size, smallest_int_mode_for_size): Take the mode
size as a poly_uint64.
(mode_for_vector, mode_for_int_vector): Take the number of vector
elements as a poly_uint64.
* stor-layout.c (mode_for_size, smallest_mode_for_size): Take the mode
size as a poly_uint64.
(mode_for_vector, mode_for_int_vector): Take the number of vector
elements as a poly_uint64.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255747
This patch adds a helper routine that constructs rtxes
for constant shift amounts, given the mode of the value
being shifted. As well as helping with the SVE patches, this
is one step towards allowing CONST_INTs to have a real mode.
One long-standing problem has been to decide what the mode
of a shift count should be for arbitrary rtxes (as opposed to those
directly tied to a target pattern). Realistic choices would be
the mode of the shifted elements, word_mode, QImode, or the same
mode as the shift optabs (in which case what should the mode
be when the target doesn't have a pattern?)
For now the patch picks the mode of the shifted elements,
but with a ??? comment.
2017-11-06 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
This patch uses a MACRO_MODE wrapper for the target macro invocations
in targhooks.c and address.h, so that macros for non-AArch64 targets
can continue to treat modes as fixed-size.
It didn't seem worth converting the address macros to hooks since
(a) they're heavily used, (b) they should be probably be replaced
with a different interface rather than converted to hooks as-is,
and most importantly (c) addresses.h already localises the problem.
2017-12-16 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* machmode.h (MACRO_MODE): New macro.
* addresses.h (base_reg_class, ok_for_base_p_1): Use it.
* targhooks.c (default_libcall_value, default_secondary_reload)
(default_memory_move_cost, default_register_move_cost)
(default_class_max_nregs): Likewise.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255744
The repeated checks for MEM_REF made this code hard to convert to
poly_ints as-is. Hopefully the new structure also makes it clearer
at a glance what the two cases are.
2017-12-16 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree-ssa-sccvn.c (vn_reference_lookup_3): Avoid repeated
checks for MEM_REF.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255742
SVE needs a way of broadcasting a scalar to a variable-length vector.
This patch adds VEC_DUPLICATE_EXPR for when CONSTRUCTOR would be used
for fixed-length vectors; this is the tree equivalent of the existing
rtl code VEC_DUPLICATE.
The patch also adds a vec_duplicate_optab to go with VEC_DUPLICATE_EXPR.
2017-12-16 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hawyard@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* doc/generic.texi (VEC_DUPLICATE_EXPR): Document.
(VEC_COND_EXPR): Add missing @tindex.
* doc/md.texi (vec_duplicate@var{m}): Document.
* tree.def (VEC_DUPLICATE_EXPR): New tree codes.
* tree.c (build_vector_from_val): Add stubbed-out handling of
variable-length vectors, using VEC_DUPLICATE_EXPR.
(uniform_vector_p): Handle VEC_DUPLICATE_EXPR.
* cfgexpand.c (expand_debug_expr): Likewise.
* tree-cfg.c (verify_gimple_assign_unary): Likewise.
* tree-inline.c (estimate_operator_cost): Likewise.
* tree-pretty-print.c (dump_generic_node): Likewise.
* tree-vect-generic.c (ssa_uniform_vector_p): Likewise.
* fold-const.c (const_unop): Fold VEC_DUPLICATE_EXPRs of a constant.
(test_vec_duplicate_folding): New function.
(fold_const_c_tests): Call it.
* optabs.def (vec_duplicate_optab): New optab.
* optabs-tree.c (optab_for_tree_code): Handle VEC_DUPLICATE_EXPR.
* optabs.h (expand_vector_broadcast): Declare.
* optabs.c (expand_vector_broadcast): Make non-static. Try using
vec_duplicate_optab.
* expr.c (store_constructor): Try using vec_duplicate_optab for
uniform vectors.
(expand_expr_real_2): Handle VEC_DUPLICATE_EXPR.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r255740
Jeff Law [Fri, 15 Dec 2017 22:35:51 +0000 (15:35 -0700)]
re PR middle-end/36550 (Wrong "may be used uninitialized" warning (conditional PHIs))
PR tree-optimization/36550
* tree-ssa-threadupdate.c (count_stmts_and_phis_in_block): New.
(mark_threaded_blocks): Rewrite code to avoid block copying when
optimizing for size. Don't pessimize blocks which will be
copied, but all the statements will be dead.
PR tree-optimization/36550
* gcc.dg/tree-ssa/pr36550.c: New test.
projects / thirdparty / gcc.git / log
