Fedor Ross [Tue, 6 Jan 2026 19:00:40 +0000 (20:00 +0100)]
arm64: dts: imx8mn: Add ifm VHIP4 EvalBoard v1 and v2
Add support for ifm i.MX8MN VHIP4 EvalBoard v1 and v2 reference design.
This system exists in two generations, v1 and v2, which share a lot of
commonality. The boards come with either single gigabit ethernet or an
KSZ8794 fast-ethernet switch, boot from eMMC, and offer CAN interfaces
via Microchip MCP25xx SPI CAN controllers, UART, and USB host. The GPU
is not available in the SoC populated on these devices.
Signed-off-by: Fedor Ross <fedor.ross@ifm.com> Signed-off-by: Marek Vasut <marex@nabladev.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arm64: dts: imx8mq-librem5: Limit uSDHC2 frequency to 50MHz
SparkLAN card has stability issues at 100MHz. It still appears to be
able to max out its throughput this way, so limit the frequency to
ensure stable operation.
Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
It has been disabled because it was being used for system clock instead
of the discrete RTC. However, SNVS has some features that the discrete
RTC does not, such as being able to turn the device on. Solve that issue
with aliases instead and reenable SNVS RTC.
Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
i2c-imx can perform bus recovery by temporarily switching I2C pins
into GPIO mode. To do so, it needs GPIO and pinctrl handles to be
provided in the device tree.
Suggested-by: Denis Sergeevich <galilley@gmail.com> Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marek Vasut [Sat, 29 Nov 2025 14:31:30 +0000 (15:31 +0100)]
arm64: dts: imx95: Use GPU_CGC as core clock for GPU
The i.MX95 imx-sm introduced new GPU_CGC clock since imx-sm commit ca5e078833fa ("SM-128: Add clock management via CCM LPCG direct control")
which are downstream clock of GPU clock. These new GPU_CGC clock
gate the existing GPU clock. Currently, without clk_ignore_unused
on kernel command line, those new GPU_CGC clock are unused and the
kernel will disable them. This has no impact on i.MX95 A0/A1, but
does prevent GPU register access from working at all on i.MX95 B0.
The GPU_CGC clock are present on both i.MX95 A0/A1/B0, therefore
update the DT such, that the GPU core clock are the GPU_CGC clock.
When the panthor driver enables the GPU core clock, it enables both
the GPU_CGC as well as its parent GPU clock.
Fixes: 67934f248e64 ("arm64: dts: imx95: Describe Mali G310 GPU") Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Joseph Guo [Tue, 30 Dec 2025 07:58:54 +0000 (16:58 +0900)]
arm64: dts: freescale: Add FRDM-IMX91 basic support
The FRDM i.MX 91 development board is a low-cost and
compact developmentboard featuring the i.MX 91 applications processor:
https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-IMX91
Add FRDM-IMX91 board dts support.
- Enable ADC1.
- Enable lpuart1 and lpuart5.
- Enable network eqos and fec.
- Enable I2C bus and children nodes under I2C bus.
- Enable USB and related nodes.
- Enable uSDHC1, uSDHC2 and uSDHC3.
- Enable MU1 and MU2.
- Enable Watchdog3.
- Enable MQS
Co-developed-by: Tom Zheng <haidong.zheng@nxp.com> Signed-off-by: Tom Zheng <haidong.zheng@nxp.com> Co-developed-by: Steven Yang <steven.yang@nxp.com> Signed-off-by: Steven Yang <steven.yang@nxp.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Francesco Valla <francesco@valla.it> Tested-by: Francesco Valla <francesco@valla.it> Signed-off-by: Joseph Guo <qijian.guo@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Marek Vasut [Tue, 30 Dec 2025 01:40:35 +0000 (02:40 +0100)]
arm64: dts: imx8mp: Update Data Modul i.MX8M Plus eDM SBC DT to rev.903
Update the DT to match newest Data Modul i.MX8M Plus eDM SBC rev.903
board which implements significant changes. Keep some of the rev.900
and rev.902 nodes in the DT so that a DTO can be used to support old
rev.900 and rev.902 boards easily.
The changes from rev.900 to rev.902 are:
- Both ethernet PHYs replaced from AR8031 to BCM54213PE
- Both ethernet PHYs MDIO address changed
- PCIe WiFi now comes with dedicated regulator
- I2C TPM chip address
- Additional GPIO expander for LVDS panel control added
- Current EEPROM I2C address changed
- Another optional EEPROM added onto another I2C bus
The changes from rev.902 to rev.903 are:
- Additional GPIO expander for WiFi and LVDS panel control added
- Multiple GPIOs are reassigned
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add CMA in device tree and set its size to 416MiB for all
Colibri iMX8X.
The size is tuned to be enough to play full HD video using gst-play
and to fit in the SKU with the lowest amount of RAM (1GB).
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Max Krummenacher [Fri, 31 Oct 2025 12:49:42 +0000 (13:49 +0100)]
arm64: dts: colibri-imx8x: Add wi-fi 32kHz clock
The Wi-Fi module requires a 32kHz clock to support Wi-Fi/BT low power
operation.
Setting the pinmuxing option on the connected pin to 32kHz is all
needed to generated the signal.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add support for the Apalis iMX8QP SoM mated with Apalis Ixora and Apalis
Evaluation board.
Apalis iMX8QP is a variant of the Apalis iMX8QM, using an NXP i.MX8QP
SoC instead of the i.MX8QM. The two SoCs are pin to pin compatible, with
the i.MX8QP being a lower end variant, with a slower GPU and one Cortex
A72 core instead of two.
The two Apalis SoMs variants share the same schematics and PCB, and the
iMX8QP variant exists only on revision V1.1 of board.
Add labels to the cpu cluster nodes to prepare for the addition of the
i.MX8QP SoC in which these nodes would need to be adjusted from another
DT file.
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Haibo Chen [Tue, 23 Dec 2025 09:05:57 +0000 (17:05 +0800)]
arm64: dts: imx94: add mt35xu512aba spi nor support
Add mt35xu512aba spi nor support on imx943-evk board.
This nor chip support OCT DTR mode.
For the reset pin, since the nor chip side need 1.8v IO
voltage for reset pin, but the IO expander side use 3.3v
IO voltage, so to make circuit safe, need to config the
pad as OPEN DRAIN.
Peng Fan [Mon, 22 Dec 2025 01:42:15 +0000 (09:42 +0800)]
arm64: dts: freescale: Add initial device tree for i.MX952
i.MX952 is designed for AI-powered sensor fusion and vision sensing
applications, it features 4 Corte-A55, 1 Cortex-M33, 1 Cortex-M7 and
NXP eIQ NPU and advanced graphics, video and advanced security with
edgelock. Product info could be found at:
https://www.nxp.com/products/i.MX-952
The basic device tree includes:
- clock, pin, power header files
- device nodes: CPU[0-3], SCMI firmware, Interrupt Controller, Sys counter,
eDMA, MU, SPI, UART, I2C, USB and etc
Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Fabian Pflug [Thu, 18 Dec 2025 11:39:22 +0000 (12:39 +0100)]
arm64: dts: freescale: add support for NXP i.MX93 FRDM
The FRDM i.MX 93 development board is a low-cost and compact development
board featuring the i.MX93 applications processor.
It features:
- Dual Cortex-A55
- 2 GB LPDDR4X / LPDDR4
- 32 GB eMMC5.1
- MicroSD slot
- GbE RJ45 x 2
- USB2.0 1x Type C, 1x Type A
This file is based upon the one provided by nxp in their own kernel and
yocto meta layer for the device, but adapted for mainline.
Signed-off-by: Haidong Zheng <haidong.zheng@nxp.com> Signed-off-by: Danwei Luo <danwei.luo@nxp.com> Signed-off-by: Lei Xu <lei.xu@nxp.com> Signed-off-by: Fabian Pflug <f.pflug@pengutronix.de> Reviewed-by: Francesco Valla <francesco@valla.it> Tested-by: Francesco Valla <francesco@valla.it> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Markus Niebel [Tue, 16 Dec 2025 13:39:25 +0000 (14:39 +0100)]
arm64: dts: imx8mn-tqma8mqnl: fix LDO5 power off
Fix SD card removal caused by automatic LDO5 power off after boot
To prevent this, add vqmmc regulator for USDHC, using a GPIO-controlled
regulator that is supplied by LDO5. Since this is implemented on SoM but
used on baseboards with SD-card interface, implement the functionality
on SoM part and optionally enable it on baseboards if needed.
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Markus Niebel [Tue, 16 Dec 2025 13:31:07 +0000 (14:31 +0100)]
arm64: dts: imx8mm-tqma8mqml: fix LDO5 power off
Fix SD card removal caused by automatic LDO5 power off after boot.
To prevent this, add vqmmc regulator for USDHC, using a GPIO-controlled
regulator that is supplied by LDO5. Since this is implemented on SoM but
used on baseboards with SD-card interface, implement the functionality
on SoM part and optionally enable it on baseboards if needed.
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Stefano Radaelli [Sun, 14 Dec 2025 21:52:53 +0000 (22:52 +0100)]
arm64: dts: imx8mp-var-som: Add support for TSC2046 touchscreen
The VAR-SOM-MX8MP integrates a TSC2046 resistive touchscreen controller.
The controller is physically located on the SOM, and its signals are
routed to the SOM pins, allowing carrier boards to make use of it.
This patch adds the TSC2046 node and the appropriate SPI controller.
Stefano Radaelli [Sun, 14 Dec 2025 21:52:52 +0000 (22:52 +0100)]
arm64: dts: imx8mp-var-som: Add support for WM8904 audio codec
The VAR-SOM-MX8MP can integrate the WM8904, a high-performance
ultra-low-power stereo codec optimized for portable audio applications.
This patch adds the WM8904 device to the appropriate I2C bus, enables
the SAI peripheral, and introduces the sound node to expose the
sound card to the system.
Stefano Radaelli [Sun, 14 Dec 2025 21:52:51 +0000 (22:52 +0100)]
arm64: dts: imx8mp-var-som: Add WiFi and Bluetooth support
Add device tree nodes for the WiFi and Bluetooth module mounted on the
VAR-SOM-MX8MP. The module can be based on either the NXP IW612 or IW611
chipset, depending on the configuration chosen by the customer.
Regardless of the chipset used, WiFi communicates over SDIO and Bluetooth
over UART.
Stefano Radaelli [Sun, 14 Dec 2025 21:52:50 +0000 (22:52 +0100)]
arm64: dts: imx8mp-var-som: Move UART2 description to Symphony carrier
The VAR-SOM-MX8MP module does not provide an onboard debug console.
UART2 is routed and exposed only on the Symphony carrier board, while
custom carrier designs may choose to expose a different UART.
Move the UART2 node from the SOM device tree to the
imx8mp-var-som-symphony.dts, keeping the SOM dtsi limited to hardware
present on the module itself.
Stefano Radaelli [Sun, 14 Dec 2025 21:52:49 +0000 (22:52 +0100)]
arm64: dts: imx8mp-var-som: Move PCA9534 GPIO expander to Symphony carrier
The VAR-SOM-MX8MP module does not include the PCA9534 GPIO expander nor
the LED connected to it. These components are present only on the
Symphony carrier board and may vary across custom carrier designs.
Move the PCA9534 GPIO expander node and the associated LED definition
from the SOM device tree to the Symphony carrier DTS, ensuring the SOM
dtsi describes only hardware present on the module.
Stefano Radaelli [Sun, 14 Dec 2025 21:52:48 +0000 (22:52 +0100)]
arm64: dts: imx8mp-var-som: Move USDHC2 support to Symphony carrier
The VAR-SOM-MX8MP module does not include a microSD slot connected to
USDHC2. The USDHC2 interface is routed only on the Symphony carrier
board, and it may optionally be used or omitted depending on the
customer's carrier design.
Move the USDHC2 node, its regulators, pinctrl groups and related GPIOs
from the SOM device tree to the Symphony carrier DTS, keeping the SOM
description limited to hardware populated on the module.
Peng Fan [Fri, 12 Dec 2025 09:57:21 +0000 (17:57 +0800)]
arm64: dts: imx93-11x11-evk: Use phys to replace xceiver-supply
The TJA1057 used on i.MX93 EVK is actually high-speed CAN
transceiver, not a regulator supply. So use phys to reflect the truth.
Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Fri, 12 Dec 2025 09:57:20 +0000 (17:57 +0800)]
arm64: dts: imx8mp-evk: Use phys to replace xceiver-supply
The TJA1048 used on i.MX8MP-EVK is actually high-speed CAN transceiver,
not a regulator supply. So use phys to reflect the truth.
Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Peng Fan [Fri, 12 Dec 2025 09:57:19 +0000 (17:57 +0800)]
arm64: dts: imx95-15x15-evk: Use phys to replace xceiver-supply
The TJA1051T/3 used on i.MX95-15x15-EVK is actually high-speed CAN
transceiver, not a regulator supply. So use phys to reflect the truth.
Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arm64: dts: freescale: imx8-apalis: Add ethernet alias
Add alias for the apalis first ethernet interface, this ensures
consistent interface naming (e.g. `end0`) and this is used by the
firmware to correctly set the MAC address.
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arm64: dts: imx93-var-som-symphony: Add USB support
The Symphony carrier board includes a USB Type-C connector on the USB1
port through an NXP PTN5150 Type-C controller connected on the I2C bus.
The PTN5150 provides cable orientation detection and role switching
information to the USB controller.
This patch adds the PTN5150 node, its interrupt line, the required pin
muxing, and wires the controller to the USB1 OTG dual-role device using
the USB role-switch framework.
This patch adds also USB2 support, that remains in host-only mode,
matching the hardware capabilities of the Symphony board.
arm64: dts: imx93-var-som-symphony: Add support for ft5x06 touch controller
The Symphony carrier board exposes a capacitive touch interface through an
FFC/FPC connector. This interface is wired to an FT5x06 touch controller
on the I2C bus when using Variscite’s 7-inch capacitive touch display.
This patch adds the FT5x06 device node to describe the actual hardware
connection and enables touch functionality on the Symphony board
PEB-WLBT-05 is an expansion board that provides WIFI and Bluetooth
functionality. It features the Ezurio Sterling LWB module [1].
Add missing regulator to baseboard dts.
Haibo Chen [Tue, 2 Dec 2025 06:04:33 +0000 (14:04 +0800)]
arm64: dts: imx93-9x9-qsb: add CAN support overlay file
CAN1 and Micfil share pins on imx93-9x9-qsb board, use TMUX1574RSVR
to control the connection: put sel to high, select CAN1, put sel to
low, select Micfil. In default, sel keep low.
To support CAN1, need to put the sel to high. Besides, CAN1 use phy
TJA1057GT/3.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Alexander Stein [Mon, 1 Dec 2025 07:03:33 +0000 (08:03 +0100)]
arm64: dts: tqmls1046a: Move BMAN/QMAN buffers to DRAM1 area
DRAM1 is only 2GiB in size (0x00_8000_0000 - 0x01_0000_0000) which is
already used by Linux kernel, etc. Move the allocation area of BMAN and
QMAN to DRAM1 region. This frees the complete DRAM2 area for e.g. CMA.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Rogerio Pimentel [Sun, 23 Nov 2025 18:14:44 +0000 (13:14 -0500)]
arm64: dts: add support for NXP i.MX8MP FRDM board
The FRDM-i.MX8MP is an NXP development platform based on the i.MX8M Plus
SoC, featuring a quad Cortex-A53, Cortex-M7 co-processor, 4GB LPDDR4,
32GB eMMC, Wi-Fi 6/Bluetooth 5.4/802.15.4 tri-radio, Ethernet, HDMI/MIPI
display interfaces, camera connectors, and standard expansion headers.
Based on the device tree found in the NXP repository at github
https://github.com/nxp-imx-support/meta-imx-frdm and on imx8mp-evk
board kernel mainline device tree.
This is a basic device tree supporting:
- Quad Cortex-A53
- 4GB LPDDR4 DRAM
- PCA9450C PMIC with regulators
- Two NXP PCAL6416 GPIO expanders
- RGB LEDs via GPIO expander
- I2C1, I2C2, I2C3 controllers
- UART2 (console) and UART3 (with RTS/CTS)
- USDHC3 (8-bit eMMC)
- SNVS power key (onboard power button)
Alexander Stein [Fri, 21 Nov 2025 07:31:41 +0000 (08:31 +0100)]
arm64: dts: tqma8xxs-mb-smarc-2: replace 0 with IMX_LPCG_CLK_0 for lpcg indices
Replace the 0 with IMX_LPCG_CLK_0 for LPCG clock indices. Although the
numerical value is identical, the LPCG input is defined as
IMX_LPCG_CLK_<n>, so using the symbolic constant improves clarity and
consistency with the LPCG clock naming convention.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Alexander Stein [Fri, 21 Nov 2025 07:31:40 +0000 (08:31 +0100)]
arm64: dts: tqma8xxs: replace 0 with IMX_LPCG_CLK_0 for lpcg indices
Replace the 0 with IMX_LPCG_CLK_0 for LPCG clock indices. Although the
numerical value is identical, the LPCG input is defined as
IMX_LPCG_CLK_<n>, so using the symbolic constant improves clarity and
consistency with the LPCG clock naming convention.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Frank Li [Thu, 20 Nov 2025 21:43:18 +0000 (16:43 -0500)]
arm64: dts: mba8xx: replace 0 with IMX_LPCG_CLK_0 for lpcg indices
Replace the 0 with IMX_LPCG_CLK_0 for LPCG clock indices. Although the
numerical value is identical, the LPCG input is defined as
IMX_LPCG_CLK_<n>, so using the symbolic constant improves clarity and
consistency with the LPCG clock naming convention.
Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add an overlay of expansion board (PEB-AV-10) that supports multimedia
interfaces, 3.5mm headphone jack, a USB-A port and LVDS, backlight
connectors can be connected to the imx8mp libra. Audio works when no
display is connected to expansion board.
A separate overlay for Powertip display, based on peb-av-10.dtsi and
intended for use with PEB-AV-10 expansion board, will be added
later as display support is not yet available.
arm64: dts: imx8mp libra: add and update display overlays
Add imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtso
devicetree display overlay for the i.MX8MP Libra RDK platform.
The overlay enable LVDS display configuration.
To keep the consistent style of panel and backlight nodes and labels.
They are updated in imx8mp-libra base board devicetree and
etml1010g3dra display overlay.
Wei Fang [Sun, 16 Nov 2025 01:35:58 +0000 (09:35 +0800)]
arm64: dts: imx943-evk: add ENETC, EMDIO and PTP Timer support
Add ENETC instance 1~3, EMDIO and PTP Timer 0~1 support.
The EMDIO provides MDIO bus for ENETCs to access their external PHYs.
The PTP Timer provides current time with nanosecond resolution, precise
periodic pulse, pulse on timeout, and time capture on external pulse
support. It also provides PTP clock for ENETCs to implement time
synchronization as required for IEEE 1588 and IEEE 802.1AS-2020.
Wei Fang [Sun, 16 Nov 2025 01:35:57 +0000 (09:35 +0800)]
arm64: dts: imx94: add basic NETC related nodes
The NETC related nodes for i.MX94, this NETC has two PCIe buses, the bus
0 has 1 ENETC instance, one PTP timer, one RCEC and a switch, currently,
the switch is not added due to the DT binding and the driver is not
ready at the moment. The bus 1 has three ENETC instances, 2 PTP timers,
1 RCEC and one EMDIO.
Frank Li [Mon, 3 Nov 2025 21:48:32 +0000 (16:48 -0500)]
arm64: dts: imx8qm: add ddr perf device node
Add ddr perf monitor device node for i.MX8QM. Change imx8-ss-ddr.dtsi's
compatible string to fsl,imx8qxp-ddr-pmu. i.MX8QM overwrite to
fsl,imx8qm-ddr-pmu. All fallback to fsl,imx8-ddr-pmu.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
projects / thirdparty / kernel / linux.git / log
