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3 weeks agoMerge tag 'reset-for-v6.19' of https://git.pengutronix.de/git/pza/linux into soc...
Arnd Bergmann [Tue, 25 Nov 2025 13:11:21 +0000 (14:11 +0100)] 
Merge tag 'reset-for-v6.19' of https://git.pengutronix.de/git/pza/linux into soc/drivers

Reset controller updates for v6.19

* Add support for LAN969x, eic770 and RZ/G3S reset controllers,
  for the RZ/G3S USB-PHY reset controller, and for the remaining
  TH1520 reset controllers.
* Drop legacy reset control lookup code.
* Include linux/bits.h from linux/reset.h to make it self-contained.

* tag 'reset-for-v6.19' of https://git.pengutronix.de/git/pza/linux:
  Documentation: reset: Remove reset_controller_add_lookup()
  reset: fix BIT macro reference
  reset: rzg2l-usbphy-ctrl: Fix a NULL vs IS_ERR() bug in probe
  reset: th1520: Support reset controllers in more subsystems
  reset: th1520: Prepare for supporting multiple controllers
  dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys
  dt-bindings: reset: thead,th1520-reset: Remove non-VO-subsystem resets
  reset: remove legacy reset lookup code
  clk: davinci: psc: drop unused reset lookup
  reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC
  reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY
  dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support
  reset: eswin: Add eic7700 reset driver
  dt-bindings: reset: eswin: Documentation for eic7700 SoC
  reset: sparx5: add LAN969x support
  dt-bindings: reset: microchip: Add LAN969x support

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 weeks agoMerge tag 'stm32-bus-firewall-for-v6.19-1' of git://git.kernel.org/pub/scm/linux...
Arnd Bergmann [Tue, 25 Nov 2025 13:04:50 +0000 (14:04 +0100)] 
Merge tag 'stm32-bus-firewall-for-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/drivers

STM32 Firewall bus for v6.19, round 1

Highlights:
----------

The STM32MP21x platforms have a slightly different RIFSC. Add support
for these platforms.

Also, the RIF is a complex firewall framework which can be tricky
to debug. To facilitate the latter, add a debugfs entry that can
be used to display the whole RIFSC firewall configuration at runtime.

* tag 'stm32-bus-firewall-for-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
  bus: rifsc: add debugfs entry to dump the firewall configuration
  dt-bindings: bus: add stm32mp21 RIFSC compatible

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 weeks agoMerge tag 'v6.19-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel...
Arnd Bergmann [Tue, 25 Nov 2025 13:02:26 +0000 (14:02 +0100)] 
Merge tag 'v6.19-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/drivers

Some additional sane defaults for the oldish rk3368 soc.

* tag 'v6.19-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  soc: rockchip: grf: Add select correct PWM implementation on RK3368
  soc: rockchip: grf: Set pwm2/xin32k pad default to xin32k for rk3368

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 weeks agoMerge tag 'qcom-drivers-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel...
Arnd Bergmann [Tue, 25 Nov 2025 13:00:48 +0000 (14:00 +0100)] 
Merge tag 'qcom-drivers-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers

Qualcomm driver updates for v6.19

Support for hardware-keymanager v1 support for wrapped keys is introduce
in the ICE driver.

Support for the new Kaanapali mobile platform is added to last-level
cache controller, pd-mapper, and UBWC drivers.

UBWC driver gains support for the Monaco and Glymur platforms.

The PMIC GLINK driver is extended to handle the differences found in
targets where the related firmware runs on the SoCCP.

Support for running on targets without initialized SMEM is provided, by
reworking the SMEM driver to differentiate between "not yet probed" and
"probed but there was no SMEM". An unwanted WARN_ON() that triggered if
clients asked for a SMEM item beyond the currently running system's
limit, was removed, to allow new use cases to gracefully fail on old
targets.

The Qualcomm socinfo driver is extended with support for version 20
through 23 and support for providing version information about more than
32 remote processors. Identifiers for QCS6490 and SM8850 are also added.

Additionally, a number of smaller bug fixes and cleanups in PBS, OCMEM,
GSBI, TZMEM, and MDT-loader are included.

* tag 'qcom-drivers-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (31 commits)
  soc: qcom: mdt_loader: rename 'firmware' parameter of qcom_mdt_load()
  soc: qcom: mdt_loader: merge __qcom_mdt_load() and qcom_mdt_load_no_init()
  soc: qcom: socinfo: Add reserve field to support future extension
  soc: qcom: socinfo: Add support for new fields in revision 20
  dt-bindings: firmware: qcom,scm: Document SCM on Kaanapali SOC
  soc: qcom: socinfo: add support to extract more than 32 image versions
  soc: qcom: smem: drop the WARN_ON() on SMEM item validation
  soc: qcom: ubwc: Add config for Kaanapali
  soc: qcom: socinfo: Add SoC ID for QCS6490
  dt-bindings: arm: qcom,ids: Add SoC ID for QCS6490
  soc: qcom: ice: Add HWKM v1 support for wrapped keys
  soc: qcom: smem: better track SMEM uninitialized state
  err.h: add INIT_ERR_PTR() macro
  soc: qcom: smem: fix hwspinlock resource leak in probe error paths
  dt-bindings: soc: qcom,aoss-qmp: Document the Glymur AOSS side channel
  dt-bindings: soc: qcom,aoss-qmp: Document the Kaanapali AOSS channel
  soc: qcom: ubwc: Add QCS8300 UBWC cfg
  dt-bindings: firmware: qcom,scm: Document Glymur scm
  soc: qcom: socinfo: Add SM8850 SoC ID
  dt-bindings: arm: qcom,ids: Add SoC ID for SM8850
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 weeks agoMerge tag 'omap-for-v6.19/drivers-signed' of git://git.kernel.org/pub/scm/linux/kerne...
Arnd Bergmann [Tue, 25 Nov 2025 12:59:03 +0000 (13:59 +0100)] 
Merge tag 'omap-for-v6.19/drivers-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/drivers

ti-sysc: allow OMAP2 and OMAP4 timers to be reserved on AM33xx

* tag 'omap-for-v6.19/drivers-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap:
  ti-sysc: allow OMAP2 and OMAP4 timers to be reserved on AM33xx

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 weeks agoMerge tag 'ti-driver-soc-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel...
Arnd Bergmann [Tue, 25 Nov 2025 10:33:10 +0000 (11:33 +0100)] 
Merge tag 'ti-driver-soc-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/drivers

TI SoC driver updates for v6.19

- ti_sci: Add Partial-IO poweroff support and sys_off handler integration
- ti_sci: Gate IO isolation programming on firmware capability flag
- ti_sci: cleanup by replacing ifdeffery in PM ops with pm_sleep_ptr() macro

* tag 'ti-driver-soc-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
  firmware: ti_sci: Partial-IO support
  firmware: ti_sci: Support transfers without response
  firmware: ti_sci: Set IO Isolation only if the firmware is capable
  firmware: ti_sci: Replace ifdeffery by pm_sleep_ptr() macro

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 weeks agoMerge tag 'imx-drivers-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/shawn...
Arnd Bergmann [Tue, 25 Nov 2025 10:32:26 +0000 (11:32 +0100)] 
Merge tag 'imx-drivers-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/drivers

i.MX drivers update for 6.19:

- A series from Peng Fan to to improve i.MX SCU firmware drivers

* tag 'imx-drivers-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  firmware: imx: scu: Use devm_mutex_init
  firmware: imx: scu: Suppress bind attrs
  firmware: imx: scu: Update error code
  firmware: imx: scu-irq: Remove unused export of imx_scu_enable_general_irq_channel
  firmware: imx: scu-irq: Set mu_resource_id before get handle
  firmware: imx: scu-irq: Init workqueue before request mbox channel
  firmware: imx: scu-irq: Free mailbox client on failure at imx_scu_enable_general_irq_channel()
  firmware: imx: scu-irq: fix OF node leak in

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 weeks agoMerge tag 'sunxi-drivers-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel...
Arnd Bergmann [Tue, 25 Nov 2025 10:25:49 +0000 (11:25 +0100)] 
Merge tag 'sunxi-drivers-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/drivers

Allwinner driver changes for 6.19

Just one cleanup change that is part of tree wide cleanup of redundant
pm_runtime_mark_last_busy() calls.

* tag 'sunxi-drivers-for-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  bus: sunxi-rsb: Remove redundant pm_runtime_mark_last_busy() calls

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 weeks agoMerge tag 'tegra-for-6.19-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra...
Arnd Bergmann [Tue, 25 Nov 2025 09:49:03 +0000 (10:49 +0100)] 
Merge tag 'tegra-for-6.19-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers

soc/tegra: Changes for v6.19-rc1

A couple of small fixes across the board: ACPI support on FUSE no longer
exposes duplicate SoC information, speedo IDs for Tegra210 are updated,
some comments see typo fixes or kerneldoc additions. Finally, support
for USB wake events is added on Tegra234, which allow these systems to
resume from suspend on USB activity.

* tag 'tegra-for-6.19-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: pmc: Add USB wake events for Tegra234
  soc/tegra: pmc: Document tegra_pmc.syscore field
  soc/tegra: pmc: Don't fail if "aotag" is not present
  soc/tegra: fuse: speedo-tegra210: Add SoC speedo 2
  soc/tegra: fuse: speedo-tegra210: Update speedo IDs
  soc/tegra: Resolve a spelling error in the tegra194-cbb.c
  soc/tegra: fuse: Do not register SoC device on ACPI boot

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 weeks agoMerge tag 'tegra-for-6.19-syscore' of git://git.kernel.org/pub/scm/linux/kernel/git...
Arnd Bergmann [Tue, 25 Nov 2025 09:25:55 +0000 (10:25 +0100)] 
Merge tag 'tegra-for-6.19-syscore' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers

syscore: Changes for v6.19-rc1

Add a parameter to syscore operations to allow passing contextual data,
which in turn enables refactoring of drivers to make them independent of
global data. This initially only contains the API changes along with the
updates for existing drivers. Subsequent work will make use of this to
improve drivers.

* tag 'tegra-for-6.19-syscore' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  syscore: Pass context data to callbacks

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 weeks agoMerge tag 'tegra-for-6.19-core' of git://git.kernel.org/pub/scm/linux/kernel/git...
Arnd Bergmann [Tue, 25 Nov 2025 09:24:21 +0000 (10:24 +0100)] 
Merge tag 'tegra-for-6.19-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers

amba: Fixes for v6.19-rc1

Fix a device leak. Could go into v6.18 as a fix, but since this problem
has existed for a long time and nobody has reported it before it doesn't
seem critical enough and sufficient to get it into 6.19 and then
backported.

* tag 'tegra-for-6.19-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  amba: tegra-ahb: Fix device leak on SMMU enable

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 weeks agoMerge tag 'renesas-drivers-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux...
Arnd Bergmann [Tue, 25 Nov 2025 09:23:26 +0000 (10:23 +0100)] 
Merge tag 'renesas-drivers-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers

Renesas driver updates for v6.19 (take two)

  - Fix accessing forbidden registers from regmap debugfs on RZ/G3E,
    RZ/G3S, RZ/V2H, and RZ/V2N.

* tag 'renesas-drivers-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: rz-sysc: Populate readable_reg/writeable_reg in regmap config
  soc: renesas: r9a09g056-sys: Populate max_register

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 weeks agoMerge tag 'samsung-drivers-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git...
Arnd Bergmann [Tue, 25 Nov 2025 09:21:51 +0000 (10:21 +0100)] 
Merge tag 'samsung-drivers-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers

Samsung SoC drivers for v6.19

1. ChipID driver: Add support for identifying Exynos8890 and Exynos9610.

2. PMU driver: Allow specifying list of valid registers for the custom
   regmap used on Google GS101 SoC.  The PMU (Power Management Unit) on
   that SoC uses more complex access to registers than simple MMIO and
   invalid registers trigger aborts halting the system.

3. Few minor cleanups.

4. Several new bindings for compatible devices.

* tag 'samsung-drivers-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  dt-bindings: soc: samsung: exynos-pmu: allow mipi-phy subnode for Exynos7870 PMU
  soc: samsung: exynos-chipid: use a local dev variable
  dt-bindings: soc: samsung: exynos-sysreg: add gs101 hsi0 and misc compatibles
  dt-bindings: soc: samsung: exynos-sysreg: add power-domains
  soc: samsung: gs101-pmu: implement access tables for read and write
  soc: samsung: exynos-pmu: move some gs101 related code into new file
  soc: samsung: exynos-pmu: allow specifying read & write access tables for secure regmap
  dt-bindings: samsung: exynos-sysreg: add exynos7870 sysregs
  soc: samsung: exynos-chipid: add exynos8890 SoC support
  dt-bindings: hwinfo: samsung,exynos-chipid: add exynos8890-chipid compatible
  dt-bindings: soc: samsung: exynos-pmu: add exynos8890 compatible
  soc: samsung: exynos-pmu: Annotate online/offline functions with __must_hold
  soc: samsung: exynos-chipid: Add exynos9610 SoC support
  dt-bindings: hwinfo: samsung,exynos-chipid: add exynos9610 compatible
  dt-bindings: soc: samsung: exynos-sysreg: Add Exynos990 PERIC0/1 compatibles

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 weeks agoMerge tag 'memory-controller-drv-6.19-2' of https://git.kernel.org/pub/scm/linux...
Arnd Bergmann [Tue, 25 Nov 2025 08:24:27 +0000 (09:24 +0100)] 
Merge tag 'memory-controller-drv-6.19-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers

Memory controller drivers for v6.19

1. Tegra drivers: Several cleanups (dev_err_probe(), error messages).
2. Renesas RPC IF: Add system suspend support.

* tag 'memory-controller-drv-6.19-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: tegra186-emc: Fix missing put_bpmp
  memory: renesas-rpc-if: Add suspend/resume support
  memory: tegra30-emc: Add the SoC model prefix to functions
  memory: tegra20-emc: Add the SoC model prefix to functions
  memory: tegra186-emc: Add the SoC model prefix to functions
  memory: tegra124-emc: Add the SoC model prefix to functions
  memory: tegra124-emc: Simplify and handle deferred probe with dev_err_probe()
  memory: tegra186-emc: Simplify and handle deferred probe with dev_err_probe()
  memory: tegra20-emc: Simplify and handle deferred probe with dev_err_probe()
  memory: tegra30-emc: Simplify and handle deferred probe with dev_err_probe()
  memory: tegra30-emc: Do not print error on icc_node_create() failure
  memory: tegra20-emc: Do not print error on icc_node_create() failure
  memory: tegra186-emc: Do not print error on icc_node_create() failure
  memory: tegra124-emc: Do not print error on icc_node_create() failure
  memory: tegra124-emc: Simplify return of emc_init()

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
3 weeks agoMerge tag 'renesas-drivers-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux...
Arnd Bergmann [Tue, 25 Nov 2025 08:23:02 +0000 (09:23 +0100)] 
Merge tag 'renesas-drivers-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers

Renesas driver updates for v6.19

  - Keep the WDTRSTCR.RESBAR2S bit in the default state on R-Car Gen4.

* tag 'renesas-drivers-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  soc: renesas: rcar-rst: Keep RESBAR2S in default state

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
4 weeks agomemory: tegra186-emc: Fix missing put_bpmp
Jon Hunter [Thu, 6 Nov 2025 19:05:50 +0000 (19:05 +0000)] 
memory: tegra186-emc: Fix missing put_bpmp

Commit a52ddb98a674 ("memory: tegra186-emc: Simplify and handle deferred
probe with dev_err_probe()") accidently dropped a call to 'put_bpmp' to
release a handle to the BPMP when getting the EMC clock fails. Fix this
by restoring the 'goto put_bpmp' if devm_clk_get() fails.

Fixes: a52ddb98a674 ("memory: tegra186-emc: Simplify and handle deferred probe with dev_err_probe()")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20251106190550.1776974-1-jonathanh@nvidia.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
4 weeks agoDocumentation: reset: Remove reset_controller_add_lookup()
Yue Haibing [Fri, 14 Nov 2025 02:05:31 +0000 (10:05 +0800)] 
Documentation: reset: Remove reset_controller_add_lookup()

Commit 205b261463ff ("reset: remove legacy reset lookup code") removed this
api, so update the document.

Signed-off-by: Yue Haibing <yuehaibing@huawei.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
4 weeks agoreset: fix BIT macro reference
Encrow Thorne [Mon, 10 Nov 2025 06:10:37 +0000 (14:10 +0800)] 
reset: fix BIT macro reference

RESET_CONTROL_FLAGS_BIT_* macros use BIT(), but reset.h does not
include bits.h. This causes compilation errors when including
reset.h standalone.

Include bits.h to make reset.h self-contained.

Suggested-by: Troy Mitchell <troy.mitchell@linux.dev>
Reviewed-by: Troy Mitchell <troy.mitchell@linux.dev>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Encrow Thorne <jyc0019@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
4 weeks agoreset: rzg2l-usbphy-ctrl: Fix a NULL vs IS_ERR() bug in probe
Dan Carpenter [Sat, 1 Nov 2025 13:27:07 +0000 (16:27 +0300)] 
reset: rzg2l-usbphy-ctrl: Fix a NULL vs IS_ERR() bug in probe

The devm_regmap_field_alloc() function never returns NULL, it returns
error pointers.  Update the error checking to match.

Fixes: 58128aa88867 ("reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
4 weeks agoreset: th1520: Support reset controllers in more subsystems
Yao Zi [Tue, 14 Oct 2025 13:10:31 +0000 (13:10 +0000)] 
reset: th1520: Support reset controllers in more subsystems

Introduce reset controllers for AP, MISC, VI, VP and DSP subsystems and
add their reset signal mappings.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
4 weeks agoreset: th1520: Prepare for supporting multiple controllers
Yao Zi [Tue, 14 Oct 2025 13:10:30 +0000 (13:10 +0000)] 
reset: th1520: Prepare for supporting multiple controllers

TH1520 SoC is divided into several subsystems, shipping distinct reset
controllers with similar control logic. Let's make reset signal mapping
a data structure specific to one compatible to prepare for introduction
of more reset controllers in the future.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
4 weeks agodt-bindings: reset: thead,th1520-reset: Add controllers for more subsys
Yao Zi [Tue, 14 Oct 2025 13:10:29 +0000 (13:10 +0000)] 
dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys

TH1520 SoC is divided into several subsystems, most of them have
distinct reset controllers. Let's document reset controllers other than
the one for VO subsystem and IDs for their reset signals.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
4 weeks agodt-bindings: reset: thead,th1520-reset: Remove non-VO-subsystem resets
Yao Zi [Tue, 14 Oct 2025 13:10:28 +0000 (13:10 +0000)] 
dt-bindings: reset: thead,th1520-reset: Remove non-VO-subsystem resets

Registers in control of TH1520_RESET_ID_{NPU,WDT0,WDT1} belong to AP
reset controller, not the VO one which is documented as
"thead,th1520-reset" and is the only reset controller supported for
TH1520 for now.

Let's remove the IDs, leaving them to be implemented by AP-subsystem
reset controller in the future.

Fixes: 30e7573babdc ("dt-bindings: reset: Add T-HEAD TH1520 SoC Reset Controller")
Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
4 weeks agoreset: remove legacy reset lookup code
Bartosz Golaszewski [Wed, 22 Oct 2025 13:51:32 +0000 (15:51 +0200)] 
reset: remove legacy reset lookup code

There are no more users of this code. Let's remove the exported symbols
and the implementation from reset core.

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
[p.zabel@pengutronix.de: folded in 8e6ec20e-8965-4b42-99fc-0462269ff2f1@paulmck-laptop]
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
4 weeks agoclk: davinci: psc: drop unused reset lookup
Bartosz Golaszewski [Wed, 22 Oct 2025 13:51:31 +0000 (15:51 +0200)] 
clk: davinci: psc: drop unused reset lookup

We no longer support any non-DT DaVinci boards so there are no more
users of legacy reset lookup.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: David Lechner <david@lechnology.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
4 weeks agoreset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC
Claudiu Beznea [Thu, 23 Oct 2025 13:58:08 +0000 (16:58 +0300)] 
reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC

The Renesas RZ/G3S SoC USB PHY HW block receives as input the USB PWRRDY
signal from the system controller. Add support for the Renesas RZ/G3S SoC.

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
4 weeks agoreset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY
Claudiu Beznea [Thu, 23 Oct 2025 13:58:07 +0000 (16:58 +0300)] 
reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY

On the Renesas RZ/G3S SoC, the USB PHY block has an input signal called
PWRRDY. This signal is managed by the system controller and must be
de-asserted after powering on the area where USB PHY resides and asserted
before powering it off.

On power-on/resume the USB PWRRDY signal need to be de-asserted before
enabling clock and switching the module to normal state (through MSTOP
support). The power-on/resume configuration sequence must be:

1/ PWRRDY=0
2/ CLK_ON=1
3/ MSTOP=0

On power-off/suspend the configuration sequence should be:

1/ MSTOP=1
2/ CLK_ON=0
3/ PWRRDY=1

The CLK_ON and MSTOP functionalities are controlled by clock drivers.
The suspend/resume support will be handled by different patches.

After long discussions with the internal HW team, it has been confirmed
that the HW connection b/w USB PHY block, the USB channels, the system
controller, clock, MSTOP, PWRRDY signal is as follows:

                               ┌──────────────────────────────┐
                               │                              │◄── CPG_CLKON_USB.CLK0_ON
                               │     USB CH0                  │
┌──────────────────────────┐   │┌───────────────────────────┐ │◄── CPG_CLKON_USB.CLK2_ON
│                 ┌────────┐   ││host controller registers  │ │
│                 │        │   ││function controller registers│
│                 │ PHY0   │◄──┤└───────────────────────────┘ │
│     USB PHY     │        │   └────────────▲─────────────────┘
│                 └────────┘                │
│                          │    CPG_BUS_PERI_COM_MSTOP.MSTOP{6, 5}_ON
│┌──────────────┐ ┌────────┐
││USHPHY control│ │        │
││  registers   │ │ PHY1   │   ┌──────────────────────────────┐
│└──────────────┘ │        │◄──┤     USB CH1                  │
│                 └────────┘   │┌───────────────────────────┐ │◄── CPG_CLKON_USB.CLK1_ON
└─▲───────▲─────────▲──────┘   ││ host controller registers │ │
  │       │         │          │└───────────────────────────┘ │
  │       │         │          └────────────▲─────────────────┘
  │       │         │                       │
  │       │         │           CPG_BUS_PERI_COM_MSTOP.MSTOP7_ON
  │PWRRDY │         │
  │       │   CPG_CLK_ON_USB.CLK3_ON
  │       │
  │  CPG_BUS_PERI_COM_MSTOP.MSTOP4_ON
  │
┌────┐
│SYSC│
└────┘

where:
- CPG_CLKON_USB.CLK.CLKX_ON is the register bit controlling the clock X
  of different USB blocks, X in {0, 1, 2, 3}
- CPG_BUS_PERI_COM_MSTOP.MSTOPX_ON is the register bit controlling the
  MSTOP of different USB blocks, X in {4, 5, 6, 7}
- USB PHY is the USB PHY block exposing 2 ports, port0 and port1, used
  by the USB CH0, USB CH1
- SYSC is the system controller block controlling the PWRRDY signal
- USB CHx are individual USB block with host and function capabilities
  (USB CH0 have both host and function capabilities, USB CH1 has only
  host capabilities)

The USBPHY control registers are controlled though the
reset-rzg2l-usbphy-ctrl driver. The USB PHY ports are controlled by
phy_rcar_gen3_usb2 (drivers/phy/renesas/phy-rcar-gen3-usb2.c file). The
USB PHY ports request resets from the reset-rzg2l-usbphy-ctrl driver.

The connection b/w the system controller and the USB PHY CTRL driver is
implemented through the renesas,sysc-pwrrdy device tree property
proposed in this patch. This property specifies the register offset and the
bitmask required to control the PWRRDY signal.

Since the USB PHY CTRL driver needs to be probed before any other
USB-specific driver on RZ/G3S, control of PWRRDY is passed exclusively
to it. This guarantees the correct configuration sequence between clocks,
MSTOP bits, and the PWRRDY bit on probe/resume and remove/suspend. At the
same time, changes are kept minimal by avoiding modifications to the USB
PHY driver to also handle the PWRRDY itself.

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
4 weeks agodt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support
Claudiu Beznea [Thu, 23 Oct 2025 13:58:06 +0000 (16:58 +0300)] 
dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support

The Renesas USB PHY hardware block needs to have the PWRRDY bit in the
system controller set before applying any other settings. The PWRRDY bit
must be controlled during power-on, power-off, and system suspend/resume
sequences as follows:
- during power-on/resume, it must be set to zero before enabling clocks and
  modules
- during power-off/suspend, it must be set to one after disabling clocks
  and modules

Add the renesas,sysc-pwrrdy device tree property, which allows the
reset-rzg2l-usbphy-ctrl driver to parse, map, and control the system
controller PWRRDY bit at the appropriate time. Along with it add a new
compatible for the RZ/G3S SoC.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
4 weeks agoreset: eswin: Add eic7700 reset driver
Xuyang Dong [Tue, 30 Sep 2025 09:32:38 +0000 (17:32 +0800)] 
reset: eswin: Add eic7700 reset driver

Add support for reset controller in eic7700 series chips.
Provide functionality for asserting and deasserting resets
on the chip.

Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com>
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
4 weeks agodt-bindings: reset: eswin: Documentation for eic7700 SoC
Xuyang Dong [Tue, 30 Sep 2025 09:32:18 +0000 (17:32 +0800)] 
dt-bindings: reset: eswin: Documentation for eic7700 SoC

Add device tree binding documentation and header file for the ESWIN
eic7700 reset controller module.

Signed-off-by: Yifeng Huang <huangyifeng@eswincomputing.com>
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
4 weeks agoreset: sparx5: add LAN969x support
Robert Marko [Mon, 22 Sep 2025 14:27:29 +0000 (16:27 +0200)] 
reset: sparx5: add LAN969x support

LAN969x uses the same reset configuration as LAN966x, but we need to
allow compiling it when ARCH_LAN969X is selected.

A fallback compatible to LAN966x will be used.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
4 weeks agodt-bindings: reset: microchip: Add LAN969x support
Robert Marko [Mon, 22 Sep 2025 14:27:28 +0000 (16:27 +0200)] 
dt-bindings: reset: microchip: Add LAN969x support

LAN969x also uses the Microchip reset driver, it reuses the LAN966x
support so use a fallback compatible.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
4 weeks agosoc: rockchip: grf: Add select correct PWM implementation on RK3368
Heiko Stuebner [Tue, 21 Oct 2025 07:42:48 +0000 (09:42 +0200)] 
soc: rockchip: grf: Add select correct PWM implementation on RK3368

Similar to the RK3288, the RK3368 has two different implementations of
the PWM block inside the SoC - the newer ones that we have a driver for
and that is used on every SoC and a previous variant that was likely
left as a fallback if the new one creates problems.

The devicetree is already set up for the new variant, so make sure
we actually use it - similar to the RK3288.

Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Link: https://patch.msgid.link/20251021074254.87065-4-heiko@sntech.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 weeks agosoc/tegra: pmc: Add USB wake events for Tegra234
Haotien Hsu [Mon, 11 Aug 2025 07:45:57 +0000 (15:45 +0800)] 
soc/tegra: pmc: Add USB wake events for Tegra234

Add USB wake events for Tegra234 so that system can be woken up from
suspend when USB devices hot-plug/unplug event is detected.

Signed-off-by: Haotien Hsu <haotienh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
5 weeks agoamba: tegra-ahb: Fix device leak on SMMU enable
Johan Hovold [Thu, 25 Sep 2025 15:00:07 +0000 (17:00 +0200)] 
amba: tegra-ahb: Fix device leak on SMMU enable

Make sure to drop the reference taken to the AHB platform device when
looking up its driver data while enabling the SMMU.

Note that holding a reference to a device does not prevent its driver
data from going away.

Fixes: 89c788bab1f0 ("ARM: tegra: Add SMMU enabler in AHB")
Cc: stable@vger.kernel.org # 3.5
Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
5 weeks agosoc/tegra: pmc: Document tegra_pmc.syscore field
Thierry Reding [Wed, 29 Oct 2025 15:10:33 +0000 (16:10 +0100)] 
soc/tegra: pmc: Document tegra_pmc.syscore field

This eliminates a warning from the documentation build targets.

Signed-off-by: Thierry Reding <treding@nvidia.com>
5 weeks agosoc/tegra: pmc: Don't fail if "aotag" is not present
Prathamesh Shete [Fri, 14 Nov 2025 16:17:11 +0000 (16:17 +0000)] 
soc/tegra: pmc: Don't fail if "aotag" is not present

The "aotog" is an optional aperture, so if that aperture is not defined
for a given device, then initialise the 'aotag' pointer to NULL instead
of returning an error. Note that the PMC driver will not use 'aotag'
pointer if initialised to NULL.

Co-developed-by: Shardar Mohammed <smohammed@nvidia.com>
Signed-off-by: Shardar Mohammed <smohammed@nvidia.com>
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
5 weeks agosoc/tegra: fuse: speedo-tegra210: Add SoC speedo 2
Aaron Kling [Wed, 22 Oct 2025 03:11:15 +0000 (22:11 -0500)] 
soc/tegra: fuse: speedo-tegra210: Add SoC speedo 2

The Jetson Nano series of modules only have 2 EMC table entries,
different from other SoC SKUs. As the EMC driver uses the SoC speedo ID
to populate the EMC OPP tables, add a new speedo ID to uniquely identify
this.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
5 weeks agosoc/tegra: fuse: speedo-tegra210: Update speedo IDs
Aaron Kling [Tue, 23 Sep 2025 16:58:05 +0000 (11:58 -0500)] 
soc/tegra: fuse: speedo-tegra210: Update speedo IDs

Existing code only sets CPU and GPU speedo IDs 0 and 1. The CPU DVFS
code supports 11 IDs and nouveau supports 5. This aligns with what the
downstream vendor kernel supports. Align SKUs with the downstream list.

The Tegra210 CVB tables were added in the first referenced fixes commit.
Since then, all Tegra210 SoCs have tried to scale to 1.9 GHz, when the
supported devkits are only supposed to scale to 1.5 or 1.7 GHZ.
Overclocking should not be the default state.

Fixes: 2b2dbc2f94e5 ("clk: tegra: dfll: add CVB tables for Tegra210")
Fixes: 579db6e5d9b8 ("arm64: tegra: Enable DFLL support on Jetson Nano")
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
5 weeks agosoc/tegra: Resolve a spelling error in the tegra194-cbb.c
Bruno Sobreira França [Fri, 24 Oct 2025 01:35:14 +0000 (01:35 +0000)] 
soc/tegra: Resolve a spelling error in the tegra194-cbb.c

Fix a typo spotted during code reading.

Signed-off-by: Bruno Sobreira França <brunofrancadevsec@gmail.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Reviewed-by: Herve Codina <herve.codina@bootlin.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
5 weeks agosoc/tegra: fuse: Do not register SoC device on ACPI boot
Kartik Rajput [Wed, 8 Oct 2025 11:16:18 +0000 (16:46 +0530)] 
soc/tegra: fuse: Do not register SoC device on ACPI boot

On Tegra platforms using ACPI, the SMCCC driver already registers the
SoC device. This makes the registration performed by the Tegra fuse
driver redundant.

When booted via ACPI, skip registering the SoC device and suppress
printing SKU information from the Tegra fuse driver, as this information
is already provided by the SMCCC driver.

Fixes: 972167c69080 ("soc/tegra: fuse: Add ACPI support for Tegra194 and Tegra234")
Cc: stable@vger.kernel.org
Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
5 weeks agosyscore: Pass context data to callbacks
Thierry Reding [Wed, 29 Oct 2025 16:33:30 +0000 (17:33 +0100)] 
syscore: Pass context data to callbacks

Several drivers can benefit from registering per-instance data along
with the syscore operations. To achieve this, move the modifiable fields
out of the syscore_ops structure and into a separate struct syscore that
can be registered with the framework. Add a void * driver data field for
drivers to store contextual data that will be passed to the syscore ops.

Acked-by: Rafael J. Wysocki (Intel) <rafael@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
5 weeks agobus: rifsc: add debugfs entry to dump the firewall configuration
Gatien Chevallier [Thu, 6 Nov 2025 09:31:50 +0000 (10:31 +0100)] 
bus: rifsc: add debugfs entry to dump the firewall configuration

RIFSC configuration can be difficult to debug. Add a debugfs entry
that dumps the configuration of the RISUPs, the RISALs and the RIMUs.
This will allow to display the whole RIFSC firewall configuration at
runtime.

While there, fix a bug on the computation of firewall entries in the
probe function.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Link: https://lore.kernel.org/r/20251106-rifsc_debugfs-v2-3-f90e94ae756d@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
5 weeks agodt-bindings: bus: add stm32mp21 RIFSC compatible
Gatien Chevallier [Thu, 6 Nov 2025 09:31:48 +0000 (10:31 +0100)] 
dt-bindings: bus: add stm32mp21 RIFSC compatible

The STM32MP21x platforms have a slightly different RIFSC. While its
core functionalities are similar, the wiring is not the same. Hence,
declare a new compatible.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20251106-rifsc_debugfs-v2-1-f90e94ae756d@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
5 weeks agosoc: renesas: rz-sysc: Populate readable_reg/writeable_reg in regmap config
Claudiu Beznea [Wed, 5 Nov 2025 07:05:26 +0000 (09:05 +0200)] 
soc: renesas: rz-sysc: Populate readable_reg/writeable_reg in regmap config

Not all system controller registers are accessible from Linux. Accessing
such registers generates synchronous external abort. Populate the
readable_reg and writeable_reg members of the regmap config to inform the
regmap core which registers can be accessed. The list will need to be
updated whenever new system controller functionality is exported through
regmap.

Fixes: 2da2740fb9c8 ("soc: renesas: rz-sysc: Add syscon/regmap support")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251105070526.264445-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
5 weeks agosoc: renesas: r9a09g056-sys: Populate max_register
Claudiu Beznea [Wed, 5 Nov 2025 07:05:25 +0000 (09:05 +0200)] 
soc: renesas: r9a09g056-sys: Populate max_register

Populate max_register to avoid external aborts.

Fixes: 2da2740fb9c8 ("soc: renesas: rz-sysc: Add syscon/regmap support")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251105070526.264445-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
5 weeks agofirmware: ti_sci: Partial-IO support
Markus Schneider-Pargmann (TI.com) [Mon, 3 Nov 2025 12:42:20 +0000 (13:42 +0100)] 
firmware: ti_sci: Partial-IO support

Add support for Partial-IO poweroff. In Partial-IO pins of a few
hardware units can generate system wakeups while DDR memory is not
powered resulting in a fresh boot of the system. These hardware units in
the SoC are always powered so that some logic can detect pin activity.

If the system supports Partial-IO as described in the fw capabilities, a
sys_off handler is added. This sys_off handler decides if the poweroff
is executed by entering normal poweroff or Partial-IO instead. The
decision is made by checking if wakeup is enabled on all devices that
may wake up the SoC from Partial-IO.

The possible wakeup devices are found by checking which devices
reference a "Partial-IO" system state in the list of wakeup-source
system states. Only devices that are actually enabled by the user will
be considered as an active wakeup source. If none of the wakeup sources
is enabled the system will do a normal poweroff. If at least one wakeup
source is enabled it will instead send a TI_SCI_MSG_PREPARE_SLEEP
message from the sys_off handler. Sending this message will result in an
immediate shutdown of the system. No execution is expected after this
point. The code will wait for 5s and do an emergency_restart afterwards
if Partial-IO wasn't entered at that point.

A short documentation about Partial-IO can be found in section 6.2.4.5
of the TRM at
  https://www.ti.com/lit/pdf/spruiv7

Signed-off-by: Markus Schneider-Pargmann (TI.com) <msp@baylibre.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Kendall Willis <k-willis@ti.com>
Reviewed-by: Sebin Francis <sebin.francis@ti.com>
Link: https://patch.msgid.link/20251103-topic-am62-partialio-v6-12-b4-v10-2-0557e858d747@baylibre.com
Signed-off-by: Nishanth Menon <nm@ti.com>
5 weeks agofirmware: ti_sci: Support transfers without response
Markus Schneider-Pargmann (TI.com) [Mon, 3 Nov 2025 12:42:19 +0000 (13:42 +0100)] 
firmware: ti_sci: Support transfers without response

Check the header flags if an response is expected or not. If it is not
expected skip the receive part of ti_sci_do_xfer(). This prepares the
driver for one-way messages as prepare_sleep for Partial-IO.

Reviewed-by: Kendall Willis <k-willis@ti.com>
Signed-off-by: Markus Schneider-Pargmann (TI.com) <msp@baylibre.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Sebin Francis <sebin.francis@ti.com>
Link: https://patch.msgid.link/20251103-topic-am62-partialio-v6-12-b4-v10-1-0557e858d747@baylibre.com
Signed-off-by: Nishanth Menon <nm@ti.com>
5 weeks agosoc: qcom: mdt_loader: rename 'firmware' parameter of qcom_mdt_load()
Gabor Juhos [Tue, 11 Nov 2025 07:40:11 +0000 (08:40 +0100)] 
soc: qcom: mdt_loader: rename 'firmware' parameter of qcom_mdt_load()

In the 'mdt_loader.h' header, both the prototype and the inline
version of the qcom_mdt_load() function uses 'fw_name' as name for
the firmware name parameter. Additionally, the other qcom_mdt_*
functions are using that as well.

For consistency, rename the 'firmware' parameter in the implementation
of the qcom_mdt_load() to 'fw_name' and update the function accordingly.

No functional changes.

Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251111-mdt-loader-cleanup-v1-2-71afee094dce@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
5 weeks agosoc: qcom: mdt_loader: merge __qcom_mdt_load() and qcom_mdt_load_no_init()
Gabor Juhos [Tue, 11 Nov 2025 07:40:10 +0000 (08:40 +0100)] 
soc: qcom: mdt_loader: merge __qcom_mdt_load() and qcom_mdt_load_no_init()

The qcom_mdt_load_no_init() function is just a simple wrapper around
of __qcom_mdt_load(). Since commit 0daf35da397b ("soc: qcom: mdt_loader:
Remove pas id parameter") both functions are using the same type of
parameters and providing the same functionality.

Keeping two functions for the same purpose is superfluous, so rename
the __qcom_mdt_load() function to qcom_mdt_load_no_init() and remove
the wrapper.

No functional changes.

Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251111-mdt-loader-cleanup-v1-1-71afee094dce@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 weeks agosoc: qcom: socinfo: Add reserve field to support future extension
Mukesh Ojha [Tue, 4 Nov 2025 13:09:06 +0000 (18:39 +0530)] 
soc: qcom: socinfo: Add reserve field to support future extension

Some of the new field added to socinfo structure with version 21, 22
and 23 which is only used by boot firmware and it is of no use for
Linux.Add reserve field in socinfo so that the structure remain
updated and prepared if we get any new field in future which could
be used by Linux. While at it, also updates switch case for backward
compatibility if the SoC runs with boot firmware which has these
new version added.

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251104130906.167666-2-mukesh.ojha@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 weeks agosoc: qcom: socinfo: Add support for new fields in revision 20
Mukesh Ojha [Tue, 4 Nov 2025 13:09:05 +0000 (18:39 +0530)] 
soc: qcom: socinfo: Add support for new fields in revision 20

Add support for socinfo version 20. Version 20 adds a new field
package id and its zeroth bit contain information that can be
can be used to tune temperature thresholds on devices which might
be able to withstand higher temperatures. Zeroth bit value 1 means
that its heat dissipation is better and more relaxed thermal
scheme can be put in place and 0 means a more aggressive scheme
may be needed.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251104130906.167666-1-mukesh.ojha@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 weeks agodt-bindings: soc: samsung: exynos-pmu: allow mipi-phy subnode for Exynos7870 PMU
Kaustabh Chakraborty [Thu, 30 Oct 2025 19:20:15 +0000 (00:50 +0530)] 
dt-bindings: soc: samsung: exynos-pmu: allow mipi-phy subnode for Exynos7870 PMU

Exynos7870 PMU is already documented in schema. Add Exynos7870's PMU
compatible to the list of nodes which allow a MIPI PHY driver.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251031-exynos7870-drm-dts-v4-1-c1f77fb16b87@disroot.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
6 weeks agoti-sysc: allow OMAP2 and OMAP4 timers to be reserved on AM33xx
Matthias Schiffer [Mon, 25 Aug 2025 13:11:13 +0000 (15:11 +0200)] 
ti-sysc: allow OMAP2 and OMAP4 timers to be reserved on AM33xx

am33xx.dtsi has the same clock setup as am35xx.dtsi, setting
ti,no-reset-on-init and ti,no-idle on timer1_target and timer2_target,
so AM33 needs the same workaround as AM35 to avoid ti-sysc probe
failing on certain target modules.

Signed-off-by: Matthias Schiffer <matthias.schiffer@tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Link: https://lore.kernel.org/r/20250825131114.2206804-1-alexander.stein@ew.tq-group.com
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
6 weeks agodt-bindings: firmware: qcom,scm: Document SCM on Kaanapali SOC
Jingyi Wang [Mon, 3 Nov 2025 07:25:07 +0000 (23:25 -0800)] 
dt-bindings: firmware: qcom,scm: Document SCM on Kaanapali SOC

Document SCM compatible for the Qualcomm Kaanapali SoC.

Reviewed-by: Eugen Hristev <eugen.hristev@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251102-knp-soc-binding-v3-2-11255ec4a535@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 weeks agosoc: qcom: socinfo: add support to extract more than 32 image versions
Kathiravan Thirumoorthy [Fri, 31 Oct 2025 05:51:02 +0000 (11:21 +0530)] 
soc: qcom: socinfo: add support to extract more than 32 image versions

SMEM_IMAGE_VERSION_TABLE contains the version of the first 32 images.
Add images beyond that and read these from SMEM_IMAGE_VERSION_TABLE_2.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251031-image-crm-part2-v2-2-c224c45c381a@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 weeks agosoc: qcom: smem: drop the WARN_ON() on SMEM item validation
Kathiravan Thirumoorthy [Fri, 31 Oct 2025 05:51:01 +0000 (11:21 +0530)] 
soc: qcom: smem: drop the WARN_ON() on SMEM item validation

When a SMEM item is allocated or retrieved, sanity check on the SMEM item
is performed and backtrace is printed if it is invalid. But there is no
benefit in dumping that information in the logs. Lets drop it.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251031-image-crm-part2-v2-1-c224c45c381a@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 weeks agosoc: qcom: ubwc: Add config for Kaanapali
Akhil P Oommen [Tue, 30 Sep 2025 05:48:06 +0000 (11:18 +0530)] 
soc: qcom: ubwc: Add config for Kaanapali

Add the ubwc configuration for Kaanapali chipset. This chipset brings
support for UBWC v6 version. The rest of the configurations remains
as usual.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250930-kaana-gpu-support-v1-1-73530b0700ed@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 weeks agosoc: qcom: socinfo: Add SoC ID for QCS6490
Komal Bajaj [Mon, 3 Nov 2025 11:23:11 +0000 (16:53 +0530)] 
soc: qcom: socinfo: Add SoC ID for QCS6490

Add SoC ID table entry for Qualcomm QCS6490.

Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251103-qcs6490_soc_id-v1-2-c139dd1e32c8@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 weeks agodt-bindings: arm: qcom,ids: Add SoC ID for QCS6490
Komal Bajaj [Mon, 3 Nov 2025 11:23:10 +0000 (16:53 +0530)] 
dt-bindings: arm: qcom,ids: Add SoC ID for QCS6490

Add unique ID for Qualcomm QCS6490 SoC.

Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251103-qcs6490_soc_id-v1-1-c139dd1e32c8@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 weeks agosoc: qcom: ice: Add HWKM v1 support for wrapped keys
Neeraj Soni [Thu, 30 Oct 2025 16:10:12 +0000 (21:40 +0530)] 
soc: qcom: ice: Add HWKM v1 support for wrapped keys

HWKM v1 and v2 differ slightly in wrapped key size and the bit fields for
certain status registers and operating mode (legacy or standard).

Add support to select HWKM version based on the major and minor revisions.
Use this HWKM version to select wrapped key size and to configure the bit
fields in registers for operating modes and hardware status.

Support for SCM calls for wrapped keys is being added in the TrustZone for
few SoCs with HWKM v1. Existing check of qcom_scm_has_wrapped_key_support()
API ensures that HWKM is used only if these SCM calls are supported in
TrustZone for that SoC.

Signed-off-by: Neeraj Soni <neeraj.soni@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251030161012.3391239-1-neeraj.soni@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
6 weeks agofirmware: ti_sci: Set IO Isolation only if the firmware is capable
Thomas Richard (TI.com) [Fri, 31 Oct 2025 12:44:56 +0000 (13:44 +0100)] 
firmware: ti_sci: Set IO Isolation only if the firmware is capable

Prevent calling ti_sci_cmd_set_io_isolation() on firmware
that does not support the IO_ISOLATION capability. Add the
MSG_FLAG_CAPS_IO_ISOLATION capability flag and check it before
attempting to set IO isolation during suspend/resume operations.

Without this check, systems with older firmware may experience
undefined behavior or errors when entering/exiting suspend states.

Fixes: ec24643bdd62 ("firmware: ti_sci: Add system suspend and resume call")
Signed-off-by: Thomas Richard (TI.com) <thomas.richard@bootlin.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Link: https://patch.msgid.link/20251031-ti-sci-io-isolation-v2-1-60d826b65949@bootlin.com
Signed-off-by: Nishanth Menon <nm@ti.com>
6 weeks agofirmware: ti_sci: Replace ifdeffery by pm_sleep_ptr() macro
Thomas Richard (TI.com) [Tue, 14 Oct 2025 08:35:23 +0000 (10:35 +0200)] 
firmware: ti_sci: Replace ifdeffery by pm_sleep_ptr() macro

Using pm_sleep_ptr() macro allows to remove ifdeffery and
'__maybe_unused' annotations.

Signed-off-by: Thomas Richard (TI.com) <thomas.richard@bootlin.com>
Link: https://patch.msgid.link/20251014-ti-sci-pm-ops-cleanup-v1-1-70b50b73ac85@bootlin.com
Signed-off-by: Nishanth Menon <nm@ti.com>
6 weeks agosoc: samsung: exynos-chipid: use a local dev variable
Tudor Ambarus [Fri, 31 Oct 2025 12:56:01 +0000 (12:56 +0000)] 
soc: samsung: exynos-chipid: use a local dev variable

Use a local variable for struct device to avoid dereferencing.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://patch.msgid.link/20251031-gs101-chipid-v1-2-d78d1076b210@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
7 weeks agosoc: qcom: smem: better track SMEM uninitialized state
Christian Marangi [Fri, 31 Oct 2025 13:08:33 +0000 (14:08 +0100)] 
soc: qcom: smem: better track SMEM uninitialized state

There is currently a problem where, in the specific case of SMEM not
initialized by SBL, any SMEM API wrongly returns PROBE_DEFER
communicating wrong info to any user of this API.

A better way to handle this would be to track the SMEM state and return
a different kind of error than PROBE_DEFER.

Rework the __smem handle to always init it to the error pointer
-EPROBE_DEFER following what is already done by the SMEM API.
If we detect that the SBL didn't initialized SMEM, set the __smem handle
to the error pointer -ENODEV.
Also rework the SMEM API to handle the __smem handle to be an error
pointer and return it appropriately.

This way user of the API can react and return a proper error or use
fallback way for the failing API.

While at it, change the return error when SMEM is not initialized by SBL
also to -ENODEV to make it consistent with the __smem handle and use
dev_err_probe() helper to return the message.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20251031130835.7953-3-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 weeks agoerr.h: add INIT_ERR_PTR() macro
Christian Marangi [Fri, 31 Oct 2025 13:08:32 +0000 (14:08 +0100)] 
err.h: add INIT_ERR_PTR() macro

Add INIT_ERR_PTR() macro to initialize static variables with error
pointers. This might be useful for specific case where there is a static
variable initialized to an error condition and then later set to the
real handle once probe finish/completes.

This is to handle compilation problems like:

error: initializer element is not constant

where ERR_PTR() can't be used.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20251031130835.7953-2-ansuelsmth@gmail.com
[bjorn: Added () suffix on macro references]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 weeks agosoc: qcom: smem: fix hwspinlock resource leak in probe error paths
Haotian Zhang [Wed, 29 Oct 2025 02:27:33 +0000 (10:27 +0800)] 
soc: qcom: smem: fix hwspinlock resource leak in probe error paths

The hwspinlock acquired via hwspin_lock_request_specific() is not
released on several error paths. This results in resource leakage
when probe fails.

Switch to devm_hwspin_lock_request_specific() to automatically
handle cleanup on probe failure. Remove the manual hwspin_lock_free()
in qcom_smem_remove() as devm handles it automatically.

Fixes: 20bb6c9de1b7 ("soc: qcom: smem: map only partitions used by local HOST")
Signed-off-by: Haotian Zhang <vulab@iscas.ac.cn>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251029022733.255-1-vulab@iscas.ac.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 weeks agodt-bindings: soc: qcom,aoss-qmp: Document the Glymur AOSS side channel
Sibi Sankar [Wed, 22 Oct 2025 07:28:44 +0000 (00:28 -0700)] 
dt-bindings: soc: qcom,aoss-qmp: Document the Glymur AOSS side channel

Document the Always-on Subsystem side channel on the Glymur SoC.

Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20251022-knp-soc-binding-v2-4-3cd3f390f3e2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 weeks agodt-bindings: soc: qcom,aoss-qmp: Document the Kaanapali AOSS channel
Jingyi Wang [Wed, 22 Oct 2025 07:28:42 +0000 (00:28 -0700)] 
dt-bindings: soc: qcom,aoss-qmp: Document the Kaanapali AOSS channel

Document the Always-On Subsystem side channel on the Qualcomm Kaanapali
platform for communication with client found on the SoC such as
remoteprocs.

Reviewed-by: Eugen Hristev <eugen.hristev@linaro.org>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20251022-knp-soc-binding-v2-2-3cd3f390f3e2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 weeks agosoc: qcom: ubwc: Add QCS8300 UBWC cfg
Yongxing Mou [Wed, 29 Oct 2025 08:51:37 +0000 (16:51 +0800)] 
soc: qcom: ubwc: Add QCS8300 UBWC cfg

The QCS8300 supports UBWC 4.0 and 4 channels LP5 memory interface. Use
the SC8280XP data structure for QCS8300 according to the specification.

Acked-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251029-qcs8300_mdss-v13-4-e8c8c4f82da2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 weeks agobus: sunxi-rsb: Remove redundant pm_runtime_mark_last_busy() calls
Sakari Ailus [Mon, 27 Oct 2025 13:33:59 +0000 (15:33 +0200)] 
bus: sunxi-rsb: Remove redundant pm_runtime_mark_last_busy() calls

pm_runtime_put_autosuspend(), pm_runtime_put_sync_autosuspend(),
pm_runtime_autosuspend() and pm_request_autosuspend() now include a call
to pm_runtime_mark_last_busy(). Remove the now-reduntant explicit call to
pm_runtime_mark_last_busy().

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20251027133359.392984-1-sakari.ailus@linux.intel.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
7 weeks agodt-bindings: firmware: qcom,scm: Document Glymur scm
Pankaj Patil [Thu, 18 Sep 2025 14:17:38 +0000 (19:47 +0530)] 
dt-bindings: firmware: qcom,scm: Document Glymur scm

Document the SCM compatible for Qualcomm Glymur SoC.
Secure Channel Manager(SCM) is used to communicate
with secure firmware.

Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250918141738.2524269-1-pankaj.patil@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 weeks agosoc: qcom: socinfo: Add SM8850 SoC ID
Jingyi Wang [Thu, 23 Oct 2025 04:57:37 +0000 (21:57 -0700)] 
soc: qcom: socinfo: Add SM8850 SoC ID

Add SoC ID for Qualcomm SM8850 which represents the Kaanapali platform.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251022-knp-socid-v2-2-d147eadd09ee@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 weeks agodt-bindings: arm: qcom,ids: Add SoC ID for SM8850
Jingyi Wang [Thu, 23 Oct 2025 04:57:36 +0000 (21:57 -0700)] 
dt-bindings: arm: qcom,ids: Add SoC ID for SM8850

Add the ID for the Qualcomm SM8850 SoC which represents the Kaanapali
platform.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20251022-knp-socid-v2-1-d147eadd09ee@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 weeks agosoc: qcom: ubwc: Add configuration Glymur platform
Abel Vesa [Tue, 14 Oct 2025 12:38:32 +0000 (15:38 +0300)] 
soc: qcom: ubwc: Add configuration Glymur platform

Describe the Universal Bandwidth Compression (UBWC) configuration
for the new Glymur platform.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251014-glymur-display-v2-7-ff935e2f88c5@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 weeks agofirmware: imx: scu: Use devm_mutex_init
Peng Fan [Fri, 17 Oct 2025 01:56:31 +0000 (09:56 +0800)] 
firmware: imx: scu: Use devm_mutex_init

In normal case, there is no need to invoke mutex_destroy in error path,
but it is useful when CONFIG_DEBUG_MUTEXES, so use devm_mutex_init().

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
7 weeks agofirmware: imx: scu: Suppress bind attrs
Peng Fan [Fri, 17 Oct 2025 01:56:30 +0000 (09:56 +0800)] 
firmware: imx: scu: Suppress bind attrs

The SCU driver is critical for system working properly, it should
never be removed and binded again. So suppress the bind attrs

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
7 weeks agofirmware: imx: scu: Update error code
Peng Fan [Fri, 17 Oct 2025 01:56:29 +0000 (09:56 +0800)] 
firmware: imx: scu: Update error code

IMX_SC_ERR_NOTFOUND should map with -ENOENT, not -EEXIST. -ENODEV makes
more sense for IMX_SC_ERR_NOPOWER, and -ECOMM makes more sense for
IMX_SC_ERR_IPC.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
7 weeks agofirmware: imx: scu-irq: Remove unused export of imx_scu_enable_general_irq_channel
Peng Fan [Fri, 17 Oct 2025 01:56:28 +0000 (09:56 +0800)] 
firmware: imx: scu-irq: Remove unused export of imx_scu_enable_general_irq_channel

Since its introduction, this symbol has not been used by any loadable
modules. It remains only referenced within imx-scu.c, which is always built
together with imx-scu-irq.c

As such, exporting imx_scu_enable_general_irq_channel is unnecessary, so
remove the export.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
7 weeks agofirmware: imx: scu-irq: Set mu_resource_id before get handle
Peng Fan [Fri, 17 Oct 2025 01:56:27 +0000 (09:56 +0800)] 
firmware: imx: scu-irq: Set mu_resource_id before get handle

mu_resource_id is referenced in imx_scu_irq_get_status() and
imx_scu_irq_group_enable() which could be used by other modules, so
need to set correct value before using imx_sc_irq_ipc_handle in
SCU API call.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
7 weeks agofirmware: imx: scu-irq: Init workqueue before request mbox channel
Peng Fan [Fri, 17 Oct 2025 01:56:26 +0000 (09:56 +0800)] 
firmware: imx: scu-irq: Init workqueue before request mbox channel

With mailbox channel requested, there is possibility that interrupts may
come in, so need to make sure the workqueue is initialized before
the queue is scheduled by mailbox rx callback.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
7 weeks agofirmware: imx: scu-irq: Free mailbox client on failure at imx_scu_enable_general_irq_...
Peng Fan [Fri, 17 Oct 2025 01:56:25 +0000 (09:56 +0800)] 
firmware: imx: scu-irq: Free mailbox client on failure at imx_scu_enable_general_irq_channel()

The IRQ mailbox is an optional channel and does not need to be kept until
driver removal when an error occurs. Free the allocated memory in the
error path.

Add 'goto free_cl' when mbox_request_channel_byname() fails, to keep free
at one place.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
7 weeks agofirmware: imx: scu-irq: fix OF node leak in
Peng Fan [Fri, 17 Oct 2025 01:56:24 +0000 (09:56 +0800)] 
firmware: imx: scu-irq: fix OF node leak in

imx_scu_enable_general_irq_channel() calls of_parse_phandle_with_args(),
but does not release the OF node reference. Add a of_node_put() call
to release the reference.

Fixes: 851826c7566e ("firmware: imx: enable imx scu general irq function")
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
8 weeks agosoc: renesas: rcar-rst: Keep RESBAR2S in default state
Wolfram Sang [Fri, 17 Oct 2025 11:42:34 +0000 (13:42 +0200)] 
soc: renesas: rcar-rst: Keep RESBAR2S in default state

Unlike Gen2, Gen4 has bit 15 of WDTRSTCR register also used. Keep it in
the default state for the V3U firmware workaround.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251017114234.2968-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
8 weeks agomemory: renesas-rpc-if: Add suspend/resume support
Biju Das [Sun, 19 Oct 2025 18:09:38 +0000 (19:09 +0100)] 
memory: renesas-rpc-if: Add suspend/resume support

On RZ/G3E using PSCI, s2ram powers down the SoC. Add suspend/resume
callbacks to control spi/spix2 clocks.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20251019180940.157088-1-biju.das.jz@bp.renesas.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
8 weeks agosoc: qcom: gsbi: fix double disable caused by devm
Haotian Zhang [Mon, 20 Oct 2025 16:02:15 +0000 (00:02 +0800)] 
soc: qcom: gsbi: fix double disable caused by devm

In the commit referenced by the Fixes tag, devm_clk_get_enabled() was
introduced to replace devm_clk_get() and clk_prepare_enable(). While
the clk_disable_unprepare() call in the error path was correctly
removed, the one in the remove function was overlooked, leading to a
double disable issue.

Remove the redundant clk_disable_unprepare() call from gsbi_remove()
to fix this issue. Since all resources are now managed by devres
and will be automatically released, the remove function serves no purpose
and can be deleted entirely.

Fixes: 489d7a8cc286 ("soc: qcom: use devm_clk_get_enabled() in gsbi_probe()")
Signed-off-by: Haotian Zhang <vulab@iscas.ac.cn>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/stable/20251020160215.523-1-vulab%40iscas.ac.cn
Link: https://lore.kernel.org/r/20251020160215.523-1-vulab@iscas.ac.cn
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agosoc: qcom: socinfo: add the missing entries to the smem image table
Kathiravan Thirumoorthy [Mon, 29 Sep 2025 14:17:08 +0000 (19:47 +0530)] 
soc: qcom: socinfo: add the missing entries to the smem image table

Add the missing entries to the SMEM image table to ensure completeness,
rather than adding support for one image at a time.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250929-image_crm-v1-2-e06530c42357@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agosoc: qcom: socinfo: arrange the socinfo_image_names array in alphabetical order
Kathiravan Thirumoorthy [Mon, 29 Sep 2025 14:17:07 +0000 (19:47 +0530)] 
soc: qcom: socinfo: arrange the socinfo_image_names array in alphabetical order

The socinfo_image_names array is currently neither arranged alphabetically
nor by image index values, making it harder to maintain. Reorder the array
alphabetically to improve readability and simplify the addition of new
entries.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250929-image_crm-v1-1-e06530c42357@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agosoc: qcom: pbs: fix device leak on lookup
Johan Hovold [Fri, 26 Sep 2025 14:35:11 +0000 (16:35 +0200)] 
soc: qcom: pbs: fix device leak on lookup

Make sure to drop the reference taken to the pbs platform device when
looking up its driver data.

Note that holding a reference to a device does not prevent its driver
data from going away so there is no point in keeping the reference.

Fixes: 5b2dd77be1d8 ("soc: qcom: add QCOM PBS driver")
Cc: stable@vger.kernel.org # 6.9
Cc: Anjelique Melendez <quic_amelende@quicinc.com>
Signed-off-by: Johan Hovold <johan@kernel.org>
Link: https://lore.kernel.org/r/20250926143511.6715-3-johan@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agosoc: qcom: ocmem: fix device leak on lookup
Johan Hovold [Fri, 26 Sep 2025 14:35:10 +0000 (16:35 +0200)] 
soc: qcom: ocmem: fix device leak on lookup

Make sure to drop the reference taken to the ocmem platform device when
looking up its driver data.

Note that holding a reference to a device does not prevent its driver
data from going away so there is no point in keeping the reference.

Also note that commit 0ff027027e05 ("soc: qcom: ocmem: Fix missing
put_device() call in of_get_ocmem") fixed the leak in a lookup error
path, but the reference is still leaking on success.

Fixes: 88c1e9404f1d ("soc: qcom: add OCMEM driver")
Cc: stable@vger.kernel.org # 5.5: 0ff027027e05
Cc: Brian Masney <bmasney@redhat.com>
Cc: Miaoqian Lin <linmq006@gmail.com>
Signed-off-by: Johan Hovold <johan@kernel.org>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Link: https://lore.kernel.org/r/20250926143511.6715-2-johan@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agosoc: qcom: llcc-qcom: Add support for Kaanapali
Jingyi Wang [Wed, 24 Sep 2025 23:24:55 +0000 (16:24 -0700)] 
soc: qcom: llcc-qcom: Add support for Kaanapali

Add system cache table and configs for Kaanapali SoC.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250924-knp-llcc-v1-2-ae6a016e5138@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agodt-bindings: cache: qcom,llcc: Document the Kaanapali LLCC
Jingyi Wang [Wed, 24 Sep 2025 23:24:54 +0000 (16:24 -0700)] 
dt-bindings: cache: qcom,llcc: Document the Kaanapali LLCC

Document the Last Level Cache Controller on Kaanapali platform.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250924-knp-llcc-v1-1-ae6a016e5138@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agosoc: qcom: pmic_glink: Add support for SOCCP remoteproc channels
Anjelique Melendez [Fri, 19 Sep 2025 17:50:25 +0000 (10:50 -0700)] 
soc: qcom: pmic_glink: Add support for SOCCP remoteproc channels

System On Chip Control Processor (SOCCP) is a subsystem that can have
battery management firmware running on it to support Type-C/PD and
battery charging. SOCCP does not have multiple PDs and hence PDR is not
supported. So, if the subsystem comes up/down, rpmsg driver would be
probed or removed. Use that for notifying clients of pmic_glink for
PDR events.

Add support for battery management FW running on SOCCP by adding the
"PMIC_RTR_SOCCP_APPS" channel name to the rpmsg_match list and
updating notify_clients logic.

Signed-off-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250919175025.2988948-1-anjelique.melendez@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agodt-bindings: soc: samsung: exynos-sysreg: add gs101 hsi0 and misc compatibles
Peter Griffin [Mon, 13 Oct 2025 20:51:30 +0000 (21:51 +0100)] 
dt-bindings: soc: samsung: exynos-sysreg: add gs101 hsi0 and misc compatibles

Add dedicated compatibles for gs101 hsi0 and misc sysreg controllers to the
documentation.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251013-automatic-clocks-v1-1-72851ee00300@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
8 weeks agodt-bindings: soc: samsung: exynos-sysreg: add power-domains
André Draszik [Fri, 10 Oct 2025 06:29:01 +0000 (07:29 +0100)] 
dt-bindings: soc: samsung: exynos-sysreg: add power-domains

On gs101 only, sysreg can be part of a power domain, so we need to
allow the relevant property 'power-domains' for the relevant
compatibles google,gs101-*-sysreg.

Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20251010-power-domains-dt-bindings-soc-samsung-exynos-sysreg-v2-1-552f5787a3f3@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2 months agosoc: rockchip: grf: Set pwm2/xin32k pad default to xin32k for rk3368
WeiHao Li [Sat, 6 Sep 2025 14:21:25 +0000 (22:21 +0800)] 
soc: rockchip: grf: Set pwm2/xin32k pad default to xin32k for rk3368

PWM2 and xin32k share the same pad, but some peripheral need the xin32k
clock to run properly, such as tsadc. I have observed that this pad is
used as xin32k by default on some existing board [1], so it maybe more
appropriate to set it to xin32k by default.

I also tested it on another rk3368 based board [2], without this adjust,
tsadc does not work properly.

[1] https://rockchip.fr/geekbox/Geekbox_V1.23.pdf
[2] https://ieiao.github.io/wiki/embedded-dev/rockchip/rk3368

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
Link: https://patch.msgid.link/20250906142125.7602-1-cn.liweihao@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2 months agofirmware: qcom: tzmem: fix qcom_tzmem_policy kernel-doc
Randy Dunlap [Fri, 17 Oct 2025 19:13:23 +0000 (12:13 -0700)] 
firmware: qcom: tzmem: fix qcom_tzmem_policy kernel-doc

Fix kernel-doc warnings by using correct kernel-doc syntax and
formatting to prevent warnings:

Warning: include/linux/firmware/qcom/qcom_tzmem.h:25 Enum value
 'QCOM_TZMEM_POLICY_STATIC' not described in enum 'qcom_tzmem_policy'
Warning: ../include/linux/firmware/qcom/qcom_tzmem.h:25 Enum value
 'QCOM_TZMEM_POLICY_MULTIPLIER' not described in enum 'qcom_tzmem_policy'
Warning: ../include/linux/firmware/qcom/qcom_tzmem.h:25 Enum value
 'QCOM_TZMEM_POLICY_ON_DEMAND' not described in enum 'qcom_tzmem_policy'

Fixes: 84f5a7b67b61 ("firmware: qcom: add a dedicated TrustZone buffer allocator")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Link: https://lore.kernel.org/r/20251017191323.1820167-1-rdunlap@infradead.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agosoc: samsung: gs101-pmu: implement access tables for read and write
André Draszik [Thu, 9 Oct 2025 09:31:27 +0000 (10:31 +0100)] 
soc: samsung: gs101-pmu: implement access tables for read and write

Accessing non-existent PMU registers causes an SError, halting the
system.

Implement read and write access tables for the gs101-PMU to specify
which registers are read- and/or writable to avoid that SError.

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://patch.msgid.link/20251009-gs101-pmu-regmap-tables-v2-3-2d64f5261952@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2 months agosoc: samsung: exynos-pmu: move some gs101 related code into new file
André Draszik [Thu, 9 Oct 2025 09:31:26 +0000 (10:31 +0100)] 
soc: samsung: exynos-pmu: move some gs101 related code into new file

To avoid cluttering common code, move most of the gs101 code into a new
file, gs101-pmu.c

More code is going to be added for gs101 - having it all in one file
helps keeping the common code (file) more readable. While at it, rename
variables 'ctx' to 'context' for consistency.

No functional change.

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://patch.msgid.link/20251009-gs101-pmu-regmap-tables-v2-2-2d64f5261952@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2 months agosoc: samsung: exynos-pmu: allow specifying read & write access tables for secure...
André Draszik [Thu, 9 Oct 2025 09:31:25 +0000 (10:31 +0100)] 
soc: samsung: exynos-pmu: allow specifying read & write access tables for secure regmap

Accessing non-existent PMU registers causes an SError, halting the
system.

regmap can help us with that by allowing to pass the list of valid
registers as part of the config during creation. When this driver
creates a new regmap itself rather than relying on
syscon_node_to_regmap(), it's therefore easily possible to hook in
custom access tables for valid read and write registers.

Specifying access tables avoids SErrors for invalid registers and
instead the regmap core can just return an error. Outside drivers, this
is also helpful when using debugfs to access the regmap.

Make it possible for drivers to specify read and write tables to be
used on creation of the secure regmap by adding respective fields to
struct exynos_pmu_data. Also add kerneldoc to same struct while
updating it.

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://patch.msgid.link/20251009-gs101-pmu-regmap-tables-v2-1-2d64f5261952@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>