Tom Rini [Tue, 18 Nov 2025 18:51:22 +0000 (12:51 -0600)]
Merge patch series "'part name' subcommand and some robustification"
Rasmus Villemoes <ravi@prevas.dk> says:
Implement a "part name" subcommand, mirroring the existing "part
number" subcommand.
In the discussion for v1 of that, it came up that there's a bit of
inconsistency in how much and what one can assume to be initialized in
'struct disk_partition' after a successful call of one of the
get_info* family of functions. Patch 1/2 tries to consolidate
that by making sure all ->get_info invocations go through a common
helper that at least always initializes the string members.
Quentin, I've taken the liberty of including your Acks, as the
incremental diff in patch 1 is quite minor, but do speak up if I
should not have done that.
Rasmus Villemoes [Mon, 10 Nov 2025 20:54:10 +0000 (21:54 +0100)]
disk/part.c: ensure strings in struct disk_partition are valid after successful get_info
Not all ->get_info implementations necessarily populate all the string
members of struct disk_partition.
Currently, only part_get_info_by_type() (and thereby part_get_info)
ensure that the uuid strings are initialized; part_get_info_by_type()
and part_get_info_by_uuid() do not. In fact, the latter could lead to
a false positive match - if the ->get_info backend does not populate
info->uuid, stale contents in info could cause the strncasecmp() to
succeed.
None of the functions currently ensure that the ->name and ->type
strings are initialized.
Instead of forcing all callers of any of these functions to
pre-initialize info, or all implementations of the ->get_info method
to ensure there are valid C strings in all four fields, create a small
helper function and factor all invocations of ->get_info through that.
This also consolidates the -ENOSYS check and standardizes on using
log_debug() for reporting absence, instead of the current mix of
PRINTF and log_debug(). It does mean we have to special-case -ENOSYS
in the error cases inside the loops in the _by_uuid() and _by_name()
functions, but it's still a net win in #LOC.
Tom Rini [Tue, 18 Nov 2025 18:50:38 +0000 (12:50 -0600)]
Merge patch series "remoteproc: k3-r5: Build fixes and security improvements"
Philippe Schenker <philippe.schenker@impulsing.ch> says:
This series fixes compilation errors when building for R5 cores and
addresses a security issue where authenticated images were not being
used correctly.
Patch 1: Cosmetic removal of duplicate code
Patches 2-3: Fix build errors caused by type mismatches between
function signatures and the types used in R5 builds.
Patches 4-5: fix a bug where ti_secure_image_post_process() relocates
images during authentication, but callers were still using the original
unverified addresses.
Add is_running callback to query the R5F core halt status via the
TI-SCI processor control API. This allows the remoteproc framework
to determine whether the R5F core is currently runnin.
The core is considered running when the PROC_BOOT_CTRL_FLAG_R5_CORE_HALT
bit is not set in the control flags.
Signed-off-by: Philippe Schenker <philippe.schenker@impulsing.ch> Reviewed-by: Andrew Davis <afd@ti.com>
After ti_secure_image_post_process() authenticates the image, it may
relocate it to a different memory location and update image_addr to
point to the verified image.
However, rproc_elf_load_image() and rproc_elf_get_boot_addr() were
still using the original "addr" parameter, potentially operating on
the unverified or stale image location instead of the authenticated
image.
Use image_addr (cast to ulong to match function signatures) after
authentication to ensure all operations work with the verified image.
Signed-off-by: Philippe Schenker <philippe.schenker@impulsing.ch>
The ti_secure_image_check() function may relocate the image during
authentication, updating image_addr to point to the verified location.
The caller was not updated with this new address, causing it to
reference the original unverified location.
Update p_image with the verified image address after authentication
to ensure subsequent operations use the correct location.
Signed-off-by: Philippe Schenker <philippe.schenker@impulsing.ch>
When compiling for R5 with CONFIG_TI_PRUSS enabled, the
pruss_probe() function passed a u64* to ofnode_get_addr_size_index(),
which expects an fdt_size_t*. This caused a compiler error
about incompatible pointer types.
Cast the size pointer to fdt_size_t* to match the function
signature.
Signed-off-by: Philippe Schenker <philippe.schenker@impulsing.ch>
When compiling for R5 core with CONFIG_REMOTEPROC_TI_K3_R5F,
passing 'size' (ulong) to ti_secure_image_post_process() caused
a type mismatch compiler error.
On platforms where ulong and size_t differ in size, directly
casting could lead to out-of-bounds memory access. Fix by
introducing a size_t temporary variable, passing it to the
function, and writing back the potentially modified value for
use in subsequent calls.
Signed-off-by: Philippe Schenker <philippe.schenker@impulsing.ch> Acked-by: Andrew Davis <afd@ti.com>
The device tree contained a duplicate DT node 'main_mmc1_pins_default',
which was already defined a few lines below. This patch removes the
redundant entry.
Signed-off-by: Philippe Schenker <philippe.schenker@impulsing.ch> Reviewed-by: Anshul Dalal <anshuld@ti.com>
Tom Rini [Wed, 12 Nov 2025 15:42:50 +0000 (09:42 -0600)]
Merge patch series "ti: add speed grades support for AM62a"
Anshul Dalal <anshuld@ti.com> says:
TI offers SoCs in various speed grades, each speed grade specifies a
certain maximum operating frequency of the clocks for each core.
In K3's boot flow, the R5 SPL starts the A53 or A72 core and configures
the correct clocks and power using the K3 ARM64 rproc driver
(compatible: ti,am654-rproc). However, the driver expects the dt node
for the ARM64 core to be set with a correct "assigned-clock-rates"
value.
Currently the dt has a value of 1.2GHz for the A53 core on AM62a, this
is incorrect for lower speed grades. Therefore this patch set adds
support for fixing this value at runtime based on the detected speed
grade from the efuse MMR.
For the speed grade table, refer to Table 6-1 of the AM62a datasheet.
Anshul Dalal [Thu, 30 Oct 2025 13:03:22 +0000 (18:33 +0530)]
mach-k3: am62a: add support for speed grades
Speed grades indicate the maximum operating frequency of any core on the
SoC. This patch adds support for the same to AM62a, this allows the A53
core to be started with the correct frequency by the R5 SPL.
The K3 ARM64 rproc driver uses the "assigned-clock-rates" value in the
respective "/a53@0" node to properly configure the clocks for the A53
core.
Although the clock value in the DT node might need to be fixed based on
SoC's speed grade at runtime. Certain SoCs such as AM62p and AM62x
already had this implemented, this patch moves the common code to
common.c to avoid duplication and simplify speed grade handling.
The logic to detect the correct entry in the "assigned-clock-rates"
property has also changed. Where we earlier relied on per SoC specific
device and clock IDs for the A53 core, we now use the "clock-names"
property which is device agnostic.
fdt_fixup_cpu_freq_nodes_am62p is used to delete unsupported opp table
entries at runtime based on the SoC's speed grade.
However, the ti-cpufreq driver in kernel already has support for
rejecting unsupported entries. Therefore this fdt fixup is not necessary
and can be dropped.
Fixes: 8d05cbef73ae ("arm: mach-k3: am62p: Fixup a53 max cpu frequency by speed-grade") Signed-off-by: Anshul Dalal <anshuld@ti.com>
Tom Rini [Tue, 11 Nov 2025 20:53:47 +0000 (14:53 -0600)]
Merge patch series "reenable dm_gpio tests, add support for gpio-line-names lookup"
Rasmus Villemoes <ravi@prevas.dk> says:
Hopefully third time's the charm.
I merely wanted to add support (mostly for use by the 'gpio' shell
command) for looking up a gpio via the gpio-line-names DT property. We
already have a "gpio_request_by_line_name()", but cmd/gpio.c does a
separate "lookup + request", so it felt more natural to teach the
lookup machinery this as well. That ran into
OF_CONTROL-but-not-OF_LIBFDT being a thing for SPL, so here's yet
another attempt.
Now, when trying to do my civic duty and add tests for this, I found
that test/dm/gpio.c has been defunct for a couple of years, and
reinstating it is not entirely trivial.
After a couple of rounds CI is now happy with this:
https://github.com/u-boot/u-boot/pull/828
gpio: search gpio-line-names property in dm_gpio_lookup_name
In scripts as well as interactively, it's much nicer to be able to
refer to GPIOs via their names defined in the device tree property
"gpio-line-names", instead of the rather opaque names derived from the
bank name with a _xx suffix. E.g.
gpio read factory_reset FACTORY_RESET
if test $factory_reset = 1 ; then ...
versus
gpio read factory_reset gpio@481ac000_16
if test $factory_reset = 1 ; then ...
This is also consistent with the move on the linux/userspace side towards
using line names instead of legacy chip+offset or the even more legacy
global gpio numbering in sysfs.
As dev_read_stringlist_search() depends on both OF_CONTROL and
OF_LIBFDT (which matters for the SPL case), we need some .config
conditional. However, it only adds about ~50 bytes of code to U-Boot
proper, and dm_gpio_lookup_name() most often ends up being GC'ed for
SPL, thus adds no overhead there, so for now make it a hidden symbol
which is merely a convenient shorthand for
CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(OF_LIBFDT).
Commit ebaa3d053e5 ("test: fix CONFIG_ACPIGEN dependencies"), which
got into v2022.10-rc1, accidentally left out a $
before (CONFIG_DM_GPIO), with the effect that test/dm/gpio.c has not
been built for three years.
Unsurprisingly, the code in there has bit-rotted.
- There's a missing ; causing plain build fail.
That code was added in 9bf87e256c2 ("test: dm: update test for
open-drain/open-source emulation in gpio-uclass"), which was part of
v2020.07-rc3, i.e. long before the commit causing gpio.c to not be
built at all. It did build at that time, but also, the missing
semicolon wasn't found when fa847bb409d ("test: Wrap assert macros
in ({ ... }) and fix missing semicolons") happened in 2023.
- Commit 592b6f394ae ("led: add function naming option from linux")
bumped sandbox,gpio-count for bank gpio_a in test.dts to 25, but
didn't update the expected global gpio numbers accordingly.
- The "lookup by label" test likely worked when it was added, but then I
inadvertently broke it when I noticed that dm_gpio_lookup_label()
seemed to be broken in commit 10e66449d7e ("gpio-uclass: fix gpio
lookup by label") - which landed in v2023.01-rc1, so after gpio.c
was no longer being built.
The "label" (which is a u-boot concept) that a "hogged gpio" gets is
<gpio hog node name>.gpio-hog, which is why it used to work with the
strncmp() but doesn't with strcmp().
We can either revert 10e66449d7e or append the ".gpio-hog" suffix as
done below. I don't really have a dog in that race; when I did 10e66449d7e, it was because I thought the "lookup by label" was
actually about the standardized gpio-line-names property, but then I
learnt it was not, so is not at all useful to me.
And it fails with the same differences (160/176) even if I
remove the three lines that actually exercise any of the gpio code,
i.e. make the whole function amount to
So I suspect that the leak is somewhere in the test framework
setup/teardown code - dm_leack_check_end() isn't really used
anywhere else except in a dm/core test. Bisecting to figure out
where that was introduced is somewhat of a hassle because of the
other bitrot, and because of the SWIG failure that makes it very
hard to build older U-Boots.
So since it's better to have most of the gpio tests actually
working instead of leaving all of gpio.c as dead code, #if 0 that
part out and leave it as an archeological exercise.
Tom Rini [Tue, 11 Nov 2025 20:53:33 +0000 (14:53 -0600)]
Merge patch series "rsa: fix dependency, rename and relocate RSASSA PSS symbols"
Quentin Schulz <foss+uboot@0leil.net> says:
While historically signature verification is mostly done for FIT such
FIT_SIGNATURE dependency for signature algorithm makes sense, it isn't
the only kind of file we can verify signatures of. It can also be done
manually with rsa_verify_hash() with an embedded public key.
Considering the impacted code is guarded by RSA_VERIFY, let's make the
symbol depend on that otherwise selecting it without RSA_VERIFY won't do
anything. The FIT_SIGNATURE dependency wasn't also enough before as it
only implied RSA_VERIFY.
Then, simply relocate the RSA SSA PSS padding with the other RSA symbols
in lib/rsa instead of in boot/ and rename it to remove the mention to
FIT.
Finally, add the PSS padding wherever PKCS1.5 padding is specified as
one or the other can be used.
Quentin Schulz [Fri, 31 Oct 2025 17:08:24 +0000 (18:08 +0100)]
rsa: update doxygen doc for RSA signature verification to mention PSS
While the verification step originally only supported PKCS1.5 as padding
algorithm for the signature, it was later extended to add support for
PSS but the doxygen doc wasn't updated to reflect that so let's fix
that oversight.
Fixes: 061daa0b61f0 ("rsa: add support of padding pss") Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Quentin Schulz [Fri, 31 Oct 2025 17:08:23 +0000 (18:08 +0100)]
rsa: rename FIT_RSASSA_PSS to RSASSA_PSS and move symbols under lib/rsa
This renames FIT_RSASSA_PSS symbols to drop the FIT_ prefix to avoid
potential confusion since there's nothing FIT specific to those symbols.
It also isn't really related to booting, so boot/Kconfig is an odd place
for them to live. Since they make sense only in relation with RSA,
simply move them to lib/rsa where it makes more sense for them to
reside.
Quentin Schulz [Fri, 31 Oct 2025 17:08:20 +0000 (18:08 +0100)]
boot: fix incorrect dependency of FIT_RSASSA_PSS
This padding has nothing to do with FIT except that we can make use of
it when verifying the FIT signatures.
This padding can also be used to verify the signature "manually" e.g. by
calling rsa_verify_hash() directly with an embedded public key.
Additionally, this padding is only useful if RSA (and specifically
RSA_VERIFY) is enabled otherwise it's not used.
The only other place it's used is in rsa-sign.c which is only built for
the host tools and handled by TOOLS_FIT_RSASSA_PSS symbol instead, so no
need to care for that one.
Finally, the FIT_SIGNATURE dependency also wasn't enough because it only
implies RSA_VERIFY, meaning it can be disabled and still have
FIT_RSASSA_PSS enabled.
So add a dependency on RSA_VERIFY and reword the input prompt.
Tom Rini [Sat, 1 Nov 2025 15:32:01 +0000 (09:32 -0600)]
CI: Move to Ubuntu 24.04 'Noble' as the base
The changes here are that we need to ensure python setuptools are
in our build virtual environments as they will no longer come in via
python even in a virtual environment. As part of this ensure setuptools
is in our cache and also include pytest-azurepipelines as we should have
been doing. Next, we move away from using apt-key directly and move that
stanza towards the rest of the apt work. This also lets us drop
directly installing gnupg2. These steps are not strictly required for
24.04 but will be for later releases and are valid now. Finally, we drop
the unused PTYHONPATH ENV line.
In order to use these containers however, we need to stop running the
event_dump test as the 'addr2line' tool provided by binutils no longer
is able to decode those specific events in most cases. As this is a
problem with binutils and present for some time now, disabling the test
until someone has time to work with upstream this seems reasonable.
Tom Rini [Sun, 2 Nov 2025 20:08:12 +0000 (14:08 -0600)]
dm: Remove pre-schema tag support
Support for using "u-boot,dm-..." rather than "bootph-..." has been
deprecated since February 2023. Any platforms using this have had a
console message saying to migrate by 2023.07. Go and remove all support
here now, for the v2026.01 release.
The results of this change that aren't clear from the above are that we
still have a checkpatch.pl error message, and document in
doc/develop/spl.rst that they have been migrated since 2023. We also
change the key2dtsi.py tool to use the correct bootph phase rather than
the legacy phase.
Tom Rini [Fri, 7 Nov 2025 22:10:49 +0000 (16:10 -0600)]
Merge patch series "Add support for TI AM6254atl SiP"
Anshul Dalal <anshuld@ti.com> says:
This patch series adds support for AM6254atl SiP (or AM62x SiP for
short) to U-Boot.
The OPN (Orderable Part Number) 'AM6254atl' expands as follows[1]:
AM6254atl
||||
|||+-- Feature Lookup (L indicates 512MiB of integrated LPDDR4)
||+--- Device Speed Grade (T indicates 1.25GHz on A53 cores)
|+---- Silicon PG Revision (A indicates SR 1.0)
+----- Core configuration (4 indicates A53's in Quad core config)
AM62x SiP provides the existing AM62x SoC with 512MiB of DDR
integrated in a single packages. The first 4 patches in the series
are cherry-picked from the devicetree-rebasing repository at
'v6.18-rc2-dts'.
Tom Rini [Fri, 7 Nov 2025 22:09:39 +0000 (16:09 -0600)]
Merge patch series "Add PCIe Endpoint controller support for TI J784S4 SoC"
Hrushikesh Salunke <h-salunke@ti.com> says:
This series enables PCIe Endpoint mode on TI's J784S4 SoC. The J784S4
SoC features two Cadence PCIe controller instances (PCIe0 and PCIe1)
that can operate in endpoint mode. This series adds support for
configuring these controllers with up to 4 lanes.
Key changes include:
- Adding a stabilization delay after power domain reset to prevent
timing-related initialization issues
- SERDES mux configuration support for proper lane routing, which is
essential for SoCs where SERDES lanes are shared between multiple
controllers (PCIe, USB, etc.) with different configurations across
boot phases
- J784S4 SoC endpoint configuration with 4-lane support
- Disabling unconfigured endpoint functions to prevent enumeration
issues on the Root Complex side
This series has been tested on J784S4 EVM with PCIe endpoint boot
configuration. Following are the corresponding test logs.
Tom Rini [Fri, 7 Nov 2025 22:08:37 +0000 (16:08 -0600)]
Merge patch series "board: ti: am62x: Add EEPROM support and refactor board detection"
Guillaume La Roque (TI.com) <glaroque@baylibre.com> says:
This series adds EEPROM board detection support for AM62x and refactors
the board detection code across AM6x family boards to eliminate code
duplication.
The series introduces two new generic functions for AM6x boards:
- do_board_detect_am6(): Reads the on-board EEPROM with fallback logic
to alternate I2C addresses
- setup_serial_am6(): Sets up the serial number environment variable
from EEPROM data
This patch series adds basic support for the boards based on Airoha
EN7523/EN7529/EN7562 SoCs. Due to ATF restrictions these boards are
able to run 32-bit OS only.
This patch series adds support for the following hardware:
* console UART
* ethernet controller/switch
* spinand flash (in non-dma mode)
The following issues may be expected:
* Extra slow UBI attaching in U-Boot (up to 20 sec with fastmap enabled).
This is caused by the lack of DMA support in the U-Boot airoha-snfi driver.
* Linux airoha-snfi driver in some cases might damage you flash data
(see: https://lore.kernel.org/lkml/20251012121707.2296160-15-mikhail.kshevetskiy@iopsys.eu/)
* Latest linux kernel is recommended to properly support flashes
with more than one plane per lun
(see: https://lore.kernel.org/lkml/20251012121707.2296160-7-mikhail.kshevetskiy@iopsys.eu/)
* It's NOT recommended to use flashes working in continuous mode because
U-Boot airoha-snfi driver does not support such flashes properly.
The patches was tested on the board:
- SoC: Airoha EN7562
- RAM: 512 MB
- SPI NAND: 4 Gbit, made by Toshiba
- Linux boot: was NOT tested
The U-Boot was chain-loaded from the running U-Boot. Airoha ATF-2.3 does
not allow easily chain-loading of U-Boot from U-Boot, so a special FIT
image (mimic linux kernel) was created
1) Create u-boot.its file with the following contents:
Anshul Dalal [Sat, 25 Oct 2025 02:48:11 +0000 (08:18 +0530)]
ti: add support for AM6254atl SiP
TI's AM6254atl (or AM62x SiP for short) provides the existing AM62x SoC
with 512MiB of DDR integrated in a single package.
This patch adds the necessary U-Boot devie tree files, the required
defconfigs along with the documentation for the AM62x SiP EVM.
AM62x SiP differs from the already supported AM62x in following ways:
- OP-TEE for the AM62x resides from 0x9e800000 to 0xa0000000 which needs
to be moved to 0x80080000 to free up space at end of DDR in AM62x SiP
with 512MiB of memory. This is required to allow U-Boot to relocate to
end of DDR before booting to the kernel.
- Changes to the env:
1. splashimage address updated from 0x80200000 to 0x81a00000
2. DFU addresses updated to match updated TEXT_BASE for SPL and U-Boot
Anshul Dalal [Sat, 25 Oct 2025 02:48:10 +0000 (08:18 +0530)]
arm64: dts: ti: Add support for AM6254atl SiP SK
This patch adds the dt for SK-AM62-SIP, which uses the existing
SK-AM62 board design with the new AM6254atl SiP. This changes the
location of memory node from the board dts to SoC level dtsi
(k3-am6254atl in our case).
Therefore this patch introduces the new 'k3-am625-sk-common.dtsi'
which represents the common hardware used for both 'am625-sk' and
'am6254atl-sk' boards with the inheritance hierarchy modified to:
Anshul Dalal [Sat, 25 Oct 2025 02:48:08 +0000 (08:18 +0530)]
arm64: dts: ti: k3-am62*: remove SoC dtsi from common dtsi
The k3-am62x-sk-common dtsi represents the common hardware used across
am62x EVMs which can be configured with various DDR sizes or none (with
DDR integrated in the package) based on the specific am62x SoC used.
Therefore this patch moves the memory node and the SoC specific k3-am625
dtsi out of sk-common and into the board dts files. No functional change
is intended from this patch. The device-tree inheritance is changed as
follows:
Beleswar Padhi [Sat, 25 Oct 2025 02:48:07 +0000 (08:18 +0530)]
arm64: dts: ti: k3-am6*-boards: Add label to reserved-memory node
Add the label name 'reserved_memory' to the reserved-memory node in all
K3 AM6* board level dts files. This is done so that the node can be
referenced and extended to add more carveout entries as needed in future
refactoring patches.
configs: j784s4_evm_a72_defconfig: Enable configs for PCI Endpoint mode
TI's J784S4 SoC has two instances of PCIe Controller namely PCIe0 and
PCIe1 which are Cadence PCIe Controllers. Enable corresponding configs
to support PCIe Endpoint mode of operation on these instances.
pci_endpoint: pci_cdns_ti_ep: Enable PCIe Endpoint mode in J784S4 SoC
TI's J784S4 SoC has two instances of PCIe Controller namely PCIe0 and
PCIe1 which are Cadence PCIe Controllers. Add support to configure PCIe
instances in Endpoint mode of operation.
While at it disable all endpoint functions except function 0 during
probe to prevent the Root Complex from enumerating unconfigured
functions. This ensures only properly configured endpoint functions
are visible to the host and avoids enumeration issues with
multi-function devices.
pci_endpoint: pci_cdns_ti_ep: Add SERDES mux configuration support
Probe the mux device early in the SERDES configuration flow to ensure
proper lane routing before PHY initialization. This is required for SoCs
where SERDES lanes can be muxed between different controllers
(PCIe, USB, etc), and different mux configurations are required between
different boot phases.
pci_endpoint: pci_cdns_ti_ep: Add delay after power domain reset
Add a 1ms delay after powering on the PCIe power domain to ensure
the controller stabilizes before subsequent operations. This prevents
potential timing issues during PCIe endpoint initialization.
The delay allows sufficient time for the power domain to fully come
up and the hardware to be in a stable state before configuration
begins.
board: am65x: Use generic AM6x board detection function
Replace the board-specific implementation of do_board_detect()
with a call to the generic do_board_detect_am6() function to
avoid code duplication across AM6x family boards.
The generic function provides the same functionality with
additional fallback logic to try alternate EEPROM addresses.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Guillaume La Roque (TI.com) <glaroque@baylibre.com>
board: am64x: Use generic AM6x board detection functions
Replace the board-specific implementation of do_board_detect() and
setup_serial() with calls to the generic do_board_detect_am6() and
setup_serial_am6() functions.
The generic function provides the same functionality with
additional fallback logic to try alternate EEPROM addresses.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Guillaume La Roque (TI.com) <glaroque@baylibre.com>
I2C EEPROM data contains the board name and its revision.
Add support for:
- Reading EEPROM data and store a copy at end of SRAM
- Updating env variable with relevant board info
- Printing board info during boot
Use the generic do_board_detect_am6() and setup_serial_am6()
functions to avoid code duplication across AM6x family boards.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Guillaume La Roque (TI.com) <glaroque@baylibre.com>
Add two new generic functions for AM6x family boards to simplify
board-specific implementations:
- do_board_detect_am6(): Generic board detection function that reads
the on-board EEPROM. It first attempts to read at the configured
address, and if that fails, tries the alternate address
(CONFIG_EEPROM_CHIP_ADDRESS + 1). This provides a common
implementation that can be used across different AM6x boards.
- setup_serial_am6(): Sets up the serial number environment variable
from the EEPROM data. The serial number is converted from
hexadecimal string format to a 16-character hexadecimal
representation and stored in the "serial#" environment variable.
Both functions are protected by CONFIG_IS_ENABLED(TI_I2C_BOARD_DETECT)
and are designed to be used by AM62x, AM64x, AM65x, and other AM6x
family boards.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Guillaume La Roque (TI.com) <glaroque@baylibre.com>
In preparation for support for Airoha AN7583, convert the driver to
regmap API. This is needed as Airoha AN7583 will use syscon to access
reset registers.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
arm: airoha: introduce EN7523 helpers to get SCU and CHIP_SCU regmaps
We need access SCU and CHIP_SCU regmaps in several places (clk-airoha,
reset-airoha, airoha_eth). Unfortunately these regmaps can't be easily
retrieved with a common code, because of different Airoha SoCs uses
a different dts structure.
To make life easy we can write a commonly named SoC specific helpers
for these tasks. This patch implements helpers for Airoha EN7523 SoC.
arm: airoha: introduce AN7581 helpers to get SCU and CHIP_SCU regmaps
We need access SCU and CHIP_SCU regmaps in several places (clk-airoha,
reset-airoha, airoha_eth). Unfortunately these regmaps can't be easily
retrieved with a common code, because of different Airoha SoCs uses
a different dts structure.
To make life easy we can write a commonly named SoC specific helpers
for these tasks. This patch implements helpers for Airoha AN7581 SoC.
airoha/an7581: add CONFIG_TARGET_AN7581=y to the defconfig
This is required because airoha/en7523 will be added with the following
patches. Without this line config for en7523 will be created instead of
an7581.
Vitor Soares [Tue, 28 Oct 2025 15:10:11 +0000 (15:10 +0000)]
toradex: verdin-am62: sync rm-cfg with SDK 11.01.05.03 baseline
Update the resource management configuration (rm-cfg.yaml) to align
with the default configuration provided in TI's AM62xx Processor SDK
Linux version 11.01.05.03, generated using the K3 Resource Partitioning
Tool.
This matches the configuration from board/ti/am62x/rm-cfg.yaml and the
notable change is the sharing of MCU GPIO interrupts between DM R5 and
A53 cores, and reservation of an additional virtual interrupt and event
for TIFS usage.
Quentin Schulz [Tue, 28 Oct 2025 14:02:19 +0000 (15:02 +0100)]
ext4: include missing blk.h
If missing, lbaint_t typedef will not be found in some cases.
[The proper fix for the commit above at the time would have been to
include ide.h as only since commit 1a73661bc7a7 ("dm: Add a new header
for block devices") is the typedef in blk.h]
Tom Rini [Fri, 24 Oct 2025 17:26:42 +0000 (11:26 -0600)]
test/py: multiplexed_log.py: Clean up and correct RunAndLog()
The general python documentation for the subprocess class recommends
that run() be used in all cases that it can handle. What we do in
RunAndLog is simple enough that run() is easy to switch to. In fact,
looking at this exposed a problem we have today, which is that we had
combined stdout and stderr but then looked at both stdout and stderr as
if they were separate. Stop combining them.
Tom Rini [Fri, 7 Nov 2025 19:02:07 +0000 (13:02 -0600)]
Merge patch series "pwm: put symbols into a menu + use if DM_PWM block instead of depends on"
Quentin Schulz <foss+uboot@0leil.net> says:
This improves readability in menuconfig by putting PWM symbols under a
Kconfig menu.
It also groups PWM symbols that depend on DM_PWM together under an if
DM_PWM block so that we don't need to always list the dependency in the
depends on of the symbol.
No intended change in behavior except how it shows in menuconfig.
Quentin Schulz [Thu, 30 Oct 2025 10:03:57 +0000 (11:03 +0100)]
pwm: put all PWM DM drivers under an if condition on DM_PWM
This simplifies the "depends on" since we don't need DM_PWM listed
explicitly there as it already is made explicit via the surrounding
"if". No intended change in behavior.
Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Marek Vasut [Mon, 27 Oct 2025 16:38:38 +0000 (17:38 +0100)]
mailbox: Allow operation without .recv callback
Some shared memory mailboxes may have empty receive operation,
because the data are polled by upper layers directly from the
shared memory region, and there is no completion interrupt or
bit of any sort. Allow empty .recv callback, and if the .recv
callback is empty, exit from mbox_recv() right away, because
any polling for completion here would be meaningless.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Alice Guo <alice.guo@nxp.com>
Marek Vasut [Mon, 27 Oct 2025 16:33:29 +0000 (17:33 +0100)]
clk: renesas: Isolate R-Car Gen3 driver to Gen3, Gen4 and RZ/G2L
Isolate Renesas R-Car Gen3 clock driver to R-Car Gen3 and Gen4 and RZ/G2L.
The Renesas R-Car Gen5 uses SCMI clock protocol driver instead. This is
a preparatory change for R-Car Gen5. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
* bootstd: Describe environment variable extension_overlay_addr
environment and remove extension support from TODO list
EFI:
* Correct the detection of the video mode in the EFI payload app:
- Use struct efi_gop_mode_info in the definition of struct
efi_entry_gopmode.
- In function get_mode_from_entry() use the correct type for the video
mode structure.
* Use a valid error code as return value in efi_store_memory_map().
* Avoid a memory leak for the variable name in efi_bl_create_block_device().
* Correct the code indentation in efi_uc_stop().
* Correct the description of struct efi_priv.
* Fix typos in code comments.
Other:
* qfw: Add more fields and a heading to qfw list
* Fix the support for ACPI pass-through on ARM and RISC-V:
Avoid zeroing out the XSDT address
* test: provide unit test for 'acpi list' command
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# =OGcS
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 07 Nov 2025 12:21:45 AM CST
# gpg: using RSA key 6DC4F9C71F29A6FA06B76D33C481DBBC2C051AC4
# gpg: Good signature from "Heinrich Schuchardt <xypron.glpk@gmx.de>" [unknown]
# gpg: aka "[jpeg image of size 1389]" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6DC4 F9C7 1F29 A6FA 06B7 6D33 C481 DBBC 2C05 1AC4
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sam Protsenko [Sun, 26 Oct 2025 01:06:58 +0000 (20:06 -0500)]
mmc: exynos_dw_mmc: Disable FMP for Exynos850 chip
Add DWMCI_QUIRK_DISABLE_FMP flag to Exynos850 driver data to make the
driver disable FMP in case of Exynos850 chip. That makes eMMC on
Exynos850 functional when U-Boot is executed during USB boot.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sam Protsenko [Sun, 26 Oct 2025 01:06:57 +0000 (20:06 -0500)]
mmc: exynos_dw_mmc: Add exynos850 compatible
Up until now "samsung,exynos7-dw-mshc-smu" compatible was used for
Exynos850 SoC, as it's present in its device tree. But Exynos850 device
tree also supports "samsung,exynos850-dw-mshc-smu" compatible string.
Add it in compatible ID list in the driver so that it can be matched
against this string for Exynos850 device tree.
No functional change, as the driver data is just a copy of
"samsung,exynos7-dw-mshc-smu" data for now.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sam Protsenko [Sun, 26 Oct 2025 01:06:56 +0000 (20:06 -0500)]
mmc: exynos_dw_mmc: Add quirk for disabling FMP
Add DWMCI_QUIRK_DISABLE_FMP which disables Flash Memory Protector (FMP)
during driver's init. It's usually done by early bootloaders, but in
some cases (like USB boot) the FMP may be left unconfigured. The issue
was observed on Exynos850 SoC (the E850-96 board). Enabling this quirk
makes eMMC functional even in such cases.
No functional change, as this feature is only added here but not enabled
for any chips yet.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sam Protsenko [Sun, 26 Oct 2025 01:06:54 +0000 (20:06 -0500)]
mmc: dw_mmc: Do not export dwmci_send_cmd() and dwmci_set_ios()
Do not over-expose the private dw_mmc API. The glue layer drivers at
this point shouldn't be aware and shouldn't use the generic
dwmci_send_cmd() and dwmci_set_ios() functions. Making those functions
public causes a "leaky abstraction" issue. It clutters the public
interface of generic dw_mmc driver and possibly leads to improper usage
of those functions, so it's a bad design.
If struct dm_dwmci_ops has to be extended, do so by copying it first
(like it's done for example in snps_dw_mmc driver). That also makes sure
the future changes to struct dm_dwmci_ops in dw_mmc driver will be
automatically reflected in all extended copies, and avoid code
duplication.
This effectively reverts commit ef3b16bb8e73 ("mmc: dw_mmc: export
dwmci_send_cmd() and dwmci_set_ios()").
No functional change.
Fixes: ef3b16bb8e73 ("mmc: dw_mmc: export dwmci_send_cmd() and dwmci_set_ios()") Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Sam Protsenko [Sun, 26 Oct 2025 01:06:53 +0000 (20:06 -0500)]
mmc: exynos_dw_mmc: Extend dm_dwmci_ops without code duplication
Instead of extending dm_dwmci_ops by copy-pasting the structure code
first, copy the actual structure data with memcpy() and then set the
.execute_tuning field. Now if struct dm_dwmci_ops gets modified in
future, these changes will be automatically reflected in struct
exynos_dwmmc_ops, which prevents possible issues in future. It also
avoids code duplication.
No functional change, but it can prevent possible isssues in future.
Fixes: eda4bd29929c ("mmc: exynos_dw_mmc: add support for MMC HS200 and HS400 modes") Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Anshul Dalal [Fri, 31 Oct 2025 07:46:26 +0000 (13:16 +0530)]
spl: remove redundant prints in boot_from_devices
The null check for loader in boot_from_devices was moved earlier in the
code path by the commit ae409a84e7bff ("spl: NULL check variable before
dereference"), therefore the subsequent null checks for loader are not
necessary.
This patch removes those checks and refactors the prints to be more
useful in case of errors.
U-Boot's falcon mode expects the jump from SPL to kernel to happen on the same
core which is not directly applicable for our heterogeneous platforms since
ATF, OPTEE and other non SPL binaries from tispl.bin should be loaded before the
kernel by the R5 SPL.
So we have to use a different flow to bypass A53 SPL and U-Boot, we first load
the newly added tispl_falcon.bin instead of tispl.bin which lacks u-boot-spl.bin
(A53's SPL) and the corresponding fdt. This sets up dm, tifs, optee and
atf. Once loaded, we load the kernel and the dtb (with fixups) at ATF's
PRELOADED_BL33_BASE and K3_HW_CONFIG_BASE.
NOTE:
Since we're now using the SPL to load the kernel and kernel expects a 2MiB
aligned load address, the existing PRELOADED_BL33_BASE has to be changed for ATF
to 0x82000000 with K3_HW_CONFIG_BASE set to 0x88000000 for the DTB.
Anshul Dalal [Fri, 31 Oct 2025 07:37:57 +0000 (13:07 +0530)]
doc: ti: document R5 falcon mode for AM62 platforms
This patch adds user documentation for R5 falcon mode for AM62
platforms. The main section is added to am62x_sk.rst and other documents
just include the relevant sections. Steps to build falcon support, usage
and the modified R5 memory map have been documented.
Two svg images have also been added for reference, one for the modified
tifalcon.bin and other for the fitImage format specific to R5 falcon
mode.
Anshul Dalal [Fri, 31 Oct 2025 07:37:56 +0000 (13:07 +0530)]
mach-k3: r5: common: add bootargs to kernel's dtb
The bootargs are passed to the kernel in the chosen node, this patch
adds support for populating bootargs in the dtb if missing.
The values for kernel boot params is taken from the env, with 'boot' and
'bootpart' specifying the rootfs for the kernel similar to the
non-falcon boot flow.
Anshul Dalal [Fri, 31 Oct 2025 07:37:54 +0000 (13:07 +0530)]
mach-k3: common: support only MMC in R5 falcon mode
To simplify the boot process and prevent the R5 SPL size from growing,
this patch restricts the boot media to load the next stage payload
(tifalcon.bin and kernel FIT) to MMC only.
We select between eMMC/SD by checking "mmcdev" in env to conform with
how U-Boot proper handles loading binaries from MMC1 or MMC2.
Note that tiboot3.bin (the initial bootloader) can be loaded from any
boot mode supported by the ROM since the restriction only applies to
tifalcon.bin and fitImage.
projects / thirdparty / u-boot.git / log
