This patch removes the target macro LIBGCC2_LONG_DOUBLE_TYPE_SIZE.
After recent changes, this macro was used in two ways in libgcc: to
determine the mode of long double in dfp-bit.h, and to determine
whether a particular mode has excess precision for use in complex
multiplication.
The former is concerned specifically with long double: it relates to
use of strtold for converting between decimal and binary floating
point. This is replaced by comparing __LDBL_MANT_DIG__ with the
appropriate __LIBGCC_*_MANT_DIG__ macro. The latter is replaced
__LIBGCC_*_EXCESS_PRECISION__ predefined macros.
Remarks:
* Comparing (__LDBL_MANT_DIG__ == __LIBGCC_XF_MANT_DIG__) is more
fragile than it looks; it's possible for XFmode to have 53-bit
mantissa (TARGET_96_ROUND_53_LONG_DOUBLE, on FreeBSD and
DragonFlyBSD 32-bit), in which case such a comparison would not
distinguish XFmode and DFmode as possible modes for long double.
Fortunately, no target supporting that form of XFmode also supports
long double = double (but if some target did, we'd need e.g. an
additional macro giving the exponent range of each mode).
Furthermore, this code doesn't actually get used for x86 (or any
other target with XFmode support), because x86 uses BID not DPD and
BID has its own conversion code (which handles conversions for both
XFmode and TFmode without needing to go via strtold). And FreeBSD
and DragonFlyBSD aren't among the targets with DFP support. So
while in principle this code is fragile and it's a deficiency that
it can't support both XFmode and TFmode at once (something that
can't be solved with the string conversion approach without libc
having TS 18661 functions such as strtof128), all these issues
should not be a problem in practice.
* If other cases of excess precision are supported in future, the code
for defining __LIBGCC_*_EXCESS_PRECISION__ may need updating.
Although the most likely such cases might not actually involve
excess precision for any mode used in libgcc - FLT_EVAL_METHOD being
32 to do _Float16 arithmetic on _Float32 should have the effect of
_Complex _Float16 arithmetic using __mulsc3 and __divsc3, rather
than currently nonexistent __mulhc3 and __divhc3 as in bug 63250 for
ARM.
* As has been noted in the context of simultaneous support for
__float128 and __ibm128 on Power, the semantics of macros such as
LONG_DOUBLE_TYPE_SIZE are problematic because they rely on a
poorly-defined precision value for floating-point modes (which seems
to be intended as the number of significant bits in the
representation, e.g. 80 for XFmode which may be either 12 or 16
bytes) uniquely identifying a mode (although defining an arbitrarily
different value for one of the modes you wish to distinguish may
work as a hack). It would be cleaner to have a target hook that
gives a machine mode directly for float, double and long double,
rather than going via these precision values. By eliminating all
use of these macros (FLOAT_TYPE_SIZE, DOUBLE_TYPE_SIZE,
LONG_DOUBLE_TYPE_SIZE) from code built for the target, this patch
facilitates such a conversion to a hook (which I suppose would take
some suitable enum as an argument to identify which of the three
types to return a mode for).
(The issue of multiple type support for DFP conversions would apply
in that Power case.
<https://gcc.gnu.org/ml/gcc-patches/2014-07/msg01084.html> doesn't
seem to touch on it, but it would seem reasonable to punt on it
initially as hard to fix. There would also be the issue of getting
functions such as __powikf2, __mulkc3, __divkc3 defined, but that's
rather easier to address.)
Bootstrapped with no regressions on x86_64-unknown-linux-gnu.
libgcc:
* dfp-bit.h (LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Remove.
(__LIBGCC_XF_MANT_DIG__): Define if not already defined.
(LONG_DOUBLE_HAS_XF_MODE): Define in terms of
__LIBGCC_XF_MANT_DIG__.
(__LIBGCC_TF_MANT_DIG__): Define if not already defined.
(LONG_DOUBLE_HAS_TF_MODE): Define in terms of
__LIBGCC_TF_MANT_DIG__.
* libgcc2.c (NOTRUNC): Define in terms of
__LIBGCC_*_EXCESS_PRECISION__, not LIBGCC2_LONG_DOUBLE_TYPE_SIZE.
* libgcc2.h (LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Remove.
ian [Mon, 22 Sep 2014 21:14:43 +0000 (21:14 +0000)]
runtime: Mark runtime_goexit function as noinline.
If the compiler inlines this function into kickoff, it may reuse
the TLS block address to load g. However, this is not necessarily
correct, as the call to g->entry in kickoff may cause the TLS
address to change. If the wrong value is loaded for g->status in
runtime_goexit, it may cause a runtime panic.
By marking the function as noinline we prevent the compiler from
reusing the TLS address.
* charset.c (conversion): Rename to ...
(cpp_conversion): ... this one; update.
* files.c (file_hash_entry): Rename to ...
(cpp_file_hash_entry): ... this one ; update.
* gimplify.c (gimplify_init_constructor): Do not leave
non-GIMPLE vector constructors around.
* tree-cfg.c (verify_gimple_assign_single): Verify that
CONSTRUCTORs have gimple elements.
jakub [Mon, 22 Sep 2014 10:32:09 +0000 (10:32 +0000)]
PR debug/63328
* omp-low.c (ipa_simd_modify_stmt_ops): For debug stmts
insert a debug source bind stmt setting DEBUG_EXPR_DECL
instead of a normal gimple assignment stmt.
gcc/
* hard-reg-set.h: Include hash-table.h.
(target_hard_regs): Add a finalize method and a x_simplifiable_subregs
field.
* target-globals.c (target_globals::~target_globals): Call
hard_regs->finalize.
* rtl.h (subreg_shape): New structure.
(shape_of_subreg): New function.
(simplifiable_subregs): Declare.
* reginfo.c (simplifiable_subreg): New structure.
(simplifiable_subregs_hasher): Likewise.
(simplifiable_subregs): New function.
(invalid_mode_changes): Delete.
(alid_mode_changes, valid_mode_changes_obstack): New variables.
(record_subregs_of_mode): Remove subregs_of_mode parameter.
Record valid mode changes in valid_mode_changes.
(find_subregs_of_mode): Remove subregs_of_mode parameter.
Update calls to record_subregs_of_mode.
(init_subregs_of_mode): Remove invalid_mode_changes and bitmap
handling. Initialize new variables. Update call to
find_subregs_of_mode.
(invalid_mode_change_p): Check new variables instead of
invalid_mode_changes.
(finish_subregs_of_mode): Finalize new variables instead of
invalid_mode_changes.
(target_hard_regs::finalize): New function.
* ira-costs.c (print_allocno_costs): Call invalid_mode_change_p
even when CLASS_CANNOT_CHANGE_MODE is undefined.
gcc/
* hard-reg-set.h (COPY_HARD_REG_SET, COMPL_HARD_REG_SET)
(AND_HARD_REG_SET, AND_COMPL_HARD_REG_SET, IOR_HARD_REG_SET)
(IOR_COMPL_HARD_REG_SET): Allow the "from" set to be constant.
hp [Sun, 21 Sep 2014 23:38:05 +0000 (23:38 +0000)]
* configure.ac (target_header_dir): Move block defining
this to before the block setting inhibit_libc.
(inhibit_libc): When considering $with_headers, just
check it it's explicitly "no". If not, also check if
$target_header_dir/stdio.h is present. If not, set
inhibit_libc=true.
* configure: Regenerate.
* config/rs6000/rs6000.md (div<mode>3): Fix comment. Use a different
insn for divides by integer powers of two.
(div<mode>3_sra, *div<mode>3_sra_dot, *div<mode>3_sra_dot2): New.
(mod<mode>3): Fix formatting.
(three anonymous define_insn and two define_split): Delete.
* config/rs6000/rs6000.md (strlensi): Don't use subsi3 with a
constant, use addsi3 directly.
(three anonymous define_insn, two define_split): Delete.
(sub<mode>3): Move. Do not allow constant second operand.
Generate different insn for constant first operand.
(*subf<mode>3, *subf<mode>3_dot, *subf<mode>3_dot2): New.
(subf<mode>3_imm): New.
(ctz<mode>2, ffs<mode>2): Clobber CA_REGNO where required.
(*plus_ltu<mode>): Only handle registers.
(*plus_ltu<mode>_1): New. Handle integer third operand.
(*plus_gtu<mode>): Only handle registers.
(*plus_gtu<mode>_1): New. Handle integer third operand.
* config/rs6000/predicates.md (ca_operand): Allow subregs.
(input_operand): Do not allow ca_operand.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): For the
carry bit, allow SImode and Pmode.
(rs6000_init_hard_regno_mode_ok): Make the carry bit class NO_REGS.
PR c++/61825
* c-family/c-common.c (handle_alias_ifunc_attribute): Check
that visibility change is possible
(handle_weakref_attribute): Likewise.
* cgraph.h (symtab_node): Add method get_create and
field refuse_visibility_changes.
(symtab_node::get_create): New method.
* fold-const.c (tree_single_nonzero_warnv_p): Use get_create.
* varasm.c (mark_weak): Verify that visibility change is
possible.
* gcc.dg/tree-ssa/nonzero-1.c: Require error to be output.
2014-09-19 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/predicates.md (fusion_gpr_mem_load): Move testing
for base_reg_operand to be common between LO_SUM and PLUS.
(fusion_gpr_mem_combo): New predicate to match a fused address
that combines the addis and memory offset address.
* config/rs6000/rs6000.c (fusion_gpr_load_p): Change calling
signature to pass each argument separately, rather than
using an operands array. Rewrite the insns found by peephole2 to
be a single insn, rather than hoping the insns will still be
together when the peephole pass is done. Drop being called via a
normal peephole.
(emit_fusion_gpr_load): Change calling signature to be called from
the fusion_gpr_load_<mode> insns with a combined memory address
instead of the peephole pass passing the addis and offset
separately.
* config/rs6000/rs6000.md (UNSPEC_FUSION_GPR): New unspec for GPR
fusion.
(power8 fusion peephole): Drop support for doing power8 via a
normal peephole that was created by the peephole2 pass.
(power8 fusion peephole2): Create a new insn with the fused
address, so that the fused operation is kept together after
register allocation is done.
(fusion_gpr_load_<mode>): Likewise.
ak [Fri, 19 Sep 2014 17:09:10 +0000 (17:09 +0000)]
Fix mcount test cases to only run on supported targets
* gcc.dg/pg-override.c: Only run on x86 Linux.
* gcc.dg/pg.c: Dito.
* gcc.target/i386/fentry-override.c: Exclude for PIC.
* gcc.target/i386/fentry.c: Dito.
* config/rs6000/rs6000.c (rs6000_special_adjust_field_align_p):
Update GCC version name to GCC 5.
(rs6000_function_arg_boundary): Likewise.
(rs6000_function_arg): Likewise.
ian [Fri, 19 Sep 2014 15:24:56 +0000 (15:24 +0000)]
* simple-object-elf.c (simple_object_elf_write_ehdr): Correctly
handle objects with more than SHN_LORESERVE sections.
(simple_object_elf_write_shdr): Add sh_link parameter.
(simple_object_elf_write_to_file): Correctly handle objects with
more than SHN_LORESERVE sections.
[Patch] Teach genrecog/genoutput that scratch registers require write constraint modifiers
gcc/
* doc/md.texi (Modifiers): Consistently use "read/write"
nomenclature rather than "input/output".
* genrecog.c (constraints_supported_in_insn_p): New.
(validate_pattern): If needed, also check constraints on
MATCH_SCRATCH operands.
* genoutput.c (validate_insn_alternatives): Catch earlyclobber
operands with no '=' or '+' modifier.
2014-09-19 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
PR target/62662
* config/s390/s390.c (s390_emit_epilogue): When doing the return
address load optimization force s390_optimize_prologue to leave it
that way. Only do the optimization if we already decided to push
r14 into a stack slot.
This patch removes the (undocumented) LIBGCC2_TF_CEXT target macro,
replacing it by -fbuilding-libgcc predefines (and thereby gets rid of
another LIBGCC2_LONG_DOUBLE_TYPE_SIZE conditional, though some more
patches are needed before that target macro can be eliminated). This
macro indicated the suffix used on __builtin_huge_val,
__builtin_copysign, __builtin_fabs built-in function names to produce
the names for a given floating-point mode.
Predefines are added for all floating-point modes supported for
libgcc, not just TFmode. These are fully accurate for modes
corresponding to float, double and long double. For other modes, the
suffix for *constants* is determined by the targetm.c.mode_for_suffix
hook (the limit to two possible suffixes 'w' and 'q' being hardcoded
in various places). This is in fact the suffix for built-in functions
as well where such functions exist.
* For i386, the *q functions always exist (whether or not TFmode is
used for long double). The *w functions never exist (but this
doesn't matter for libgcc, since no i386 configuration treats XFmode
as a supported scalar mode if long double is TFmode; if __float80
were to be supported for 64-bit Android, properly such functions
ought to be added).
* For ia64, the *q functions exist for non-HP-UX (under HP-UX, long
double is TFmode, so they aren't needed). The *w functions never
exist. This is an issue for this libgcc code for the XFmode complex
functions in libgcc on HP-UX; as I understand it, right now those
will accidentally be using TFmode versions of those three functions,
so involving unnecessary conversions, while the sanity check on CEXT
accidentally passes because all it tests is the sizes of the types.
Because of the lack of 'w' functions, the patch uses 'l' when the
constant suffix is 'w', matching what the existing libgcc code would
do for IA64 HP-UX in that case.
Ideally there would be generic code to create such built-in functions
for all supported floating-point types. That may be something to
consider if support for TS 18661-3 (standard bindings for IEEE
754-2008, defining names such as _Float128, and function names such as
copysignf128) is added in future.
Bootstrapped with no regressions on x86_64-unknown-linux-gnu.
jakub [Thu, 18 Sep 2014 16:43:28 +0000 (16:43 +0000)]
PR c++/63248
* semantics.c (finish_omp_clauses): Don't call cp_omp_mappable_type
on type of type dependent expressions, and don't call it if
handle_omp_array_sections has kept TREE_LIST because something
was type dependent.
* pt.c (tsubst_expr) <case OMP_TARGET, case OMP_TARGET_DATA>:
Use keep_next_level, begin_omp_structured_block and
finish_omp_structured_block instead of push_stmt_list and
pop_stmt_list.
libgomp/
* testsuite/libgomp.c++/pr63248.C: New test.
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