Haochen Jiang [Mon, 9 Oct 2023 08:09:49 +0000 (16:09 +0800)]
Disable zmm register and 512 bit libmvec call when !TARGET_EVEX512
gcc/ChangeLog:
* config/i386/i386-expand.cc (ix86_broadcast_from_constant):
Disable zmm broadcast for !TARGET_EVEX512.
* config/i386/i386-options.cc (ix86_option_override_internal):
Do not use PVW_512 when no-evex512.
(ix86_simd_clone_adjust): Add evex512 target into string.
* config/i386/i386.cc (type_natural_mode): Report ABI warning
when using zmm register w/o evex512.
(ix86_return_in_memory): Do not allow zmm when !TARGET_EVEX512.
(ix86_hard_regno_mode_ok): Ditto.
(ix86_set_reg_reg_cost): Ditto.
(ix86_rtx_costs): Ditto.
(ix86_vector_mode_supported_p): Ditto.
(ix86_preferred_simd_mode): Ditto.
(ix86_get_mask_mode): Ditto.
(ix86_simd_clone_compute_vecsize_and_simdlen): Disable 512 bit
libmvec call when !TARGET_EVEX512.
(ix86_simd_clone_usable): Ditto.
* config/i386/i386.h (BIGGEST_ALIGNMENT): Disable 512 alignment
when !TARGET_EVEX512
(MOVE_MAX): Do not use PVW_512 when !TARGET_EVEX512.
(STORE_MAX_PIECES): Ditto.
Haochen Jiang [Mon, 9 Oct 2023 08:09:23 +0000 (16:09 +0800)]
Initial support for -mevex512
gcc/ChangeLog:
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_EVEX512_SET): New.
(OPTION_MASK_ISA2_EVEX512_UNSET): Ditto.
(ix86_handle_option): Handle EVEX512.
* config/i386/i386-c.cc
(ix86_target_macros_internal): Handle EVEX512. Add __EVEX256__
when AVX512VL is set.
* config/i386/i386-options.cc: (isa2_opts): Handle EVEX512.
(ix86_valid_target_attribute_inner_p): Ditto.
(ix86_option_override_internal): Set EVEX512 target if it is not
explicitly set when AVX512 is enabled. Disable
AVX512{PF,ER,4VNNIW,4FAMPS} for -mno-evex512.
* config/i386/i386.opt: Add mevex512. Temporaily RejectNegative.
Juzhe-Zhong [Sun, 8 Oct 2023 08:20:05 +0000 (16:20 +0800)]
TEST: Fix dump FAIL for RVV (RISCV-V vector)
As this showed: https://godbolt.org/z/3K9oK7fx3
ARM SVE 2 times for FOLD_EXTRACT_LAST wheras RVV 4 times.
This is because RISC-V doesn't enable vec_pack_trunc so we will failed conversion and fold_extract_last at the first time analysis.
Then we succeed at the second time.
So RVV has 4 times of showing "FOLD_EXTRACT_LAST:.
Haochen Gui [Mon, 9 Oct 2023 06:33:23 +0000 (14:33 +0800)]
rs6000: enable SImode in FP register on P7
gcc/
PR target/88558
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
Enable SImode on FP registers for P7.
* config/rs6000/rs6000.md (*movsi_internal1): Add fmr for SImode
move between FP registers. Set attribute isa of stfiwx to "*"
and attribute of stxsiwx to "p7".
Hongyu Wang [Mon, 9 Oct 2023 01:53:14 +0000 (09:53 +0800)]
[i386] APX EGPR: fix missing patterns that prohibit egpr
For some pattern m/Bm constraint in alternative 0 and 1 could result in
egpr allocated on memory operand under -mapxf. Should use jm/ja instead.
gcc/ChangeLog:
* config/i386/sse.md (vec_concatv2di): Replace constraint "m"
with "jm" for alternative 0 and 1 of operand 2.
(sse4_1_<code><mode>3<mask_name>): Replace constraint "Bm" with
"ja" for alternative 0 and 1 of operand2.
gcc/analyzer/ChangeLog:
PR analyzer/111155
* access-diagram.cc (boundaries::boundaries): Add logger param
(boundaries::add): Add logging.
(boundaries::get_hard_boundaries_in_range): New.
(boundaries::m_logger): New field.
(boundaries::get_table_x_for_offset): Make public.
(class svalue_spatial_item): New.
(class compound_svalue_spatial_item): New.
(add_ellipsis_to_gaps): New.
(valid_region_spatial_item::valid_region_spatial_item): Add theme
param. Initialize m_boundaries, m_existing_sval, and
m_existing_sval_spatial_item.
(valid_region_spatial_item::add_boundaries): Set m_boundaries.
Add boundaries for any m_existing_sval_spatial_item.
(valid_region_spatial_item::add_array_elements_to_table): Rewrite
creation of min/max index in terms of
maybe_add_array_index_to_table. Rewrite ellipsis code using
add_ellipsis_to_gaps. Add index values for any hard boundaries
within the valid region.
(valid_region_spatial_item::maybe_add_array_index_to_table): New,
based on code formerly in add_array_elements_to_table.
(valid_region_spatial_item::make_table): Make use of
m_existing_sval_spatial_item, if any.
(valid_region_spatial_item::m_boundaries): New field.
(valid_region_spatial_item::m_existing_sval): New field.
(valid_region_spatial_item::m_existing_sval_spatial_item): New
field.
(class svalue_spatial_item): Rename to...
(class written_svalue_spatial_item): ...this.
(class string_region_spatial_item): Rename to..
(class string_literal_spatial_item): ...this. Add "kind".
(string_literal_spatial_item::add_boundaries): Use m_kind to
determine kind of boundary. Update for renaming of m_actual_bits
to m_bits.
(string_literal_spatial_item::make_table): Likewise. Support not
displaying a row for byte indexes, and not displaying a row for
the type.
(string_literal_spatial_item::add_column_for_byte): Make byte index
row optional.
(svalue_spatial_item::make): Convert to...
(make_written_svalue_spatial_item): ...this.
(make_existing_svalue_spatial_item): New.
(access_diagram_impl::access_diagram_impl): Pass theme to
m_valid_region_spatial_item ctor. Update for renaming of
m_svalue_spatial_item.
(access_diagram_impl::find_boundaries): Pass logger to boundaries.
Update for renaming of...
(access_diagram_impl::m_svalue_spatial_item): Rename to...
(access_diagram_impl::m_written_svalue_spatial_item): ...this.
gcc/testsuite/ChangeLog:
PR analyzer/111155
* c-c++-common/analyzer/out-of-bounds-diagram-strcat-2.c: New test.
* c-c++-common/analyzer/out-of-bounds-diagram-strcat.c: New test.
* gcc.dg/analyzer/out-of-bounds-diagram-17.c: Update expected
result to show the existing content of "buf" and the index at
which the write starts.
* gcc.dg/analyzer/out-of-bounds-diagram-18.c: Likewise.
* gcc.dg/analyzer/out-of-bounds-diagram-19.c: Likewise.
* gcc.dg/analyzer/out-of-bounds-diagram-6.c: Update expected
output.
gcc/ChangeLog:
PR analyzer/111155
* text-art/table.cc (table::maybe_set_cell_span): New.
(table::add_other_table): New.
* text-art/table.h (class table::cell_placement): Add class table
as a friend.
(table::add_rows): New.
(table::add_row): Reimplement in terms of add_rows.
(table::maybe_set_cell_span): New decl.
(table::add_other_table): New decl.
* text-art/types.h (operator+): New operator for rect + coord.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
David Malcolm [Sun, 8 Oct 2023 22:43:16 +0000 (18:43 -0400)]
libcpp: eliminate COMBINE_LOCATION_DATA
This patch eliminates the function "COMBINE_LOCATION_DATA" (which hasn't
been a macro since r6-739-g0501dbd932a7e9) and the function
"get_combined_adhoc_loc" in favor of a new
line_maps::get_or_create_combined_loc member function.
No functional change intended.
gcc/cp/ChangeLog:
* module.cc (module_state::read_location): Update for renaming of
get_combined_adhoc_loc.
gcc/ChangeLog:
* genmatch.cc (main): Update for "m_" prefix of some fields of
line_maps.
* input.cc (make_location): Update for removal of
COMBINE_LOCATION_DATA.
(dump_line_table_statistics): Update for "m_" prefix of some
fields of line_maps.
(location_with_discriminator): Update for removal of
COMBINE_LOCATION_DATA.
(line_table_test::line_table_test): Update for "m_" prefix of some
fields of line_maps.
* toplev.cc (general_init): Likewise.
* tree.cc (set_block): Update for removal of
COMBINE_LOCATION_DATA.
(set_source_range): Likewise.
libcpp/ChangeLog:
* include/line-map.h (line_maps::reallocator): Rename to...
(line_maps::m_reallocator): ...this.
(line_maps::round_alloc_size): Rename to...
(line_maps::m_round_alloc_size): ...this.
(line_maps::location_adhoc_data_map): Rename to...
(line_maps::m_location_adhoc_data_map): ...this.
(line_maps::num_optimized_ranges): Rename to...
(line_maps::m_num_optimized_ranges): ..this.
(line_maps::num_unoptimized_ranges): Rename to...
(line_maps::m_num_unoptimized_ranges): ...this.
(get_combined_adhoc_loc): Delete decl.
(COMBINE_LOCATION_DATA): Delete.
* lex.cc (get_location_for_byte_range_in_cur_line): Update for
removal of COMBINE_LOCATION_DATA.
(warn_about_normalization): Likewise.
(_cpp_lex_direct): Likewise.
* line-map.cc (line_maps::~line_maps): Update for "m_" prefix of
some fields of line_maps.
(rebuild_location_adhoc_htab): Likewise.
(can_be_stored_compactly_p): Convert to...
(line_maps::can_be_stored_compactly_p): ...this private member
function.
(get_combined_adhoc_loc): Convert to...
(line_maps::get_or_create_combined_loc): ...this public member
function.
(line_maps::make_location): Update for removal of
COMBINE_LOCATION_DATA.
(get_data_from_adhoc_loc): Update for "m_" prefix of some fields
of line_maps.
(get_discriminator_from_adhoc_loc): Likewise.
(get_location_from_adhoc_loc): Likewise.
(get_range_from_adhoc_loc): Convert to...
(line_maps::get_range_from_adhoc_loc): ...this private member
function.
(line_maps::get_range_from_loc): Update for conversion of
get_range_from_adhoc_loc to a member function.
(linemap_init): Update for "m_" prefix of some fields of
line_maps.
(line_map_new_raw): Likewise.
(linemap_enter_macro): Likewise.
(linemap_get_statistics): Likewise.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
David Malcolm [Sun, 8 Oct 2023 22:43:15 +0000 (18:43 -0400)]
diagnostics: fix ICE on sarif output when source file is unreadable [PR111700]
gcc/ChangeLog:
PR driver/111700
* input.cc (file_cache::add_file): Update leading comment to
clarify that it can fail.
(file_cache::lookup_or_add_file): Likewise.
(file_cache::get_source_file_content): Gracefully handle
lookup_or_add_file failing.
gcc/testsuite/ChangeLog:
PR driver/111700
* c-c++-common/diagnostic-format-sarif-file-pr111700.c: New test.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
Support signbit/xorsign/copysign/abs/neg/and/xor/ior/andn for V2HF/V4HF.
gcc/ChangeLog:
* config/i386/i386.cc (ix86_build_const_vector): Handle V2HF
and V4HFmode.
(ix86_build_signbit_mask): Ditto.
* config/i386/mmx.md (mmxintvecmode): Ditto.
(<code><mode>2): New define_expand.
(*mmx_<code><mode>): New define_insn_and_split.
(*mmx_nabs<mode>2): Ditto.
(*mmx_andnot<mode>3): New define_insn.
(<code><mode>3): Ditto.
(copysign<mode>3): New define_expand.
(xorsign<mode>3): Ditto.
(signbit<mode>2): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/part-vect-absneghf.c: New test.
* gcc.target/i386/part-vect-copysignhf.c: New test.
* gcc.target/i386/part-vect-xorsignhf.c: New test.
* config/i386/mmx.md (VHF_32_64): New mode iterator.
(<insn><mode>3): New define_expand, merged from ..
(<insn>v4hf3): .. this and
(<insn>v2hf3): .. this.
(movd_v2hf_to_sse_reg): New define_expand, splitted from ..
(movd_v2hf_to_sse): .. this.
(<code><mode>3): New define_expand.
gcc/testsuite/ChangeLog:
* gcc.target/i386/part-vect-vminmaxph-1.c: New test.
* gcc.target/i386/avx512fp16-64-32-vecop-1.c: Scan-assembler
only for { target { ! ia32 } }.
Tobias Burnus [Sun, 8 Oct 2023 09:54:07 +0000 (11:54 +0200)]
Fortran/OpenMP: Fix handling of strictly structured blocks
For strictly structured blocks, a BLOCK was created but the code
was placed after the block the outer structured block. Additionally,
labelled blocks were mishandled. As the code is now properly in a
BLOCK, it solves additional issues.
gcc/fortran/ChangeLog:
* parse.cc (parse_omp_structured_block): Make the user code end
up inside of BLOCK construct for strictly structured blocks;
fix fallout for 'section' and 'teams'.
* openmp.cc (resolve_omp_target): Fix changed BLOCK handling
for teams in target checking.
libgomp/ChangeLog:
* testsuite/libgomp.fortran/strictly-structured-block-1.f90: New test.
gcc/testsuite/ChangeLog:
* gfortran.dg/block_17.f90: New test.
* gfortran.dg/gomp/strictly-structured-block-5.f90: New test.
Jiufu Guo [Tue, 10 Jan 2023 13:40:48 +0000 (21:40 +0800)]
rs6000: build constant via li/lis;rldic
This patch checks if a constant is possible to be built by "li;rldic".
Only need to take care of "negative li", other forms do not need to check.
For example, "negative lis" is just a "negative li" with an additional shift.
gcc/ChangeLog:
* config/rs6000/rs6000.cc (can_be_built_by_li_and_rldic): New function.
(rs6000_emit_set_long_const): Call can_be_built_by_li_and_rldic.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/const-build.c: Add more tests.
Jiufu Guo [Tue, 10 Jan 2023 12:52:33 +0000 (20:52 +0800)]
rs6000: build constant via li/lis;rldicl/rldicr
If a constant is possible left/right cleaned on a rotated value from
a negative value of "li/lis". Then, using "li/lis ; rldicl/rldicr"
to build the constant.
gcc/ChangeLog:
* config/rs6000/rs6000.cc (can_be_built_by_li_lis_and_rldicl): New
function.
(can_be_built_by_li_lis_and_rldicr): New function.
(rs6000_emit_set_long_const): Call can_be_built_by_li_lis_and_rldicr and
can_be_built_by_li_lis_and_rldicl.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/const-build.c: Add more tests.
Jiufu Guo [Thu, 15 Jun 2023 13:11:53 +0000 (21:11 +0800)]
rs6000: build constant via lis;rotldi
If a constant is possible to be rotated to/from a negative value from
"lis", then using "lis;rotldi" to build the constant.
The positive value of "lis" does not need to be analyzed. Because if a
constant can be rotated from the positive value of "lis", it also can be
rotated from a positive value of "li".
gcc/ChangeLog:
* config/rs6000/rs6000.cc (can_be_rotated_to_negative_lis): New
function.
(can_be_built_by_li_and_rotldi): Rename to ...
(can_be_built_by_li_lis_and_rotldi): ... this function.
(rs6000_emit_set_long_const): Call can_be_built_by_li_lis_and_rotldi.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/const-build.c: Add more tests.
Jiufu Guo [Thu, 24 Aug 2023 01:08:34 +0000 (09:08 +0800)]
rs6000: build constant via li;rotldi
If a constant is possible to be rotated to/from a positive or negative
value which "li" can generated, then "li;rotldi" can be used to build
the constant.
gcc/ChangeLog:
* config/rs6000/rs6000.cc (can_be_built_by_li_and_rotldi): New function.
(rs6000_emit_set_long_const): Call can_be_built_by_li_and_rotldi.
Yanzhang Wang [Sat, 7 Oct 2023 11:32:25 +0000 (19:32 +0800)]
RISC-V: add static-pie support
We only need to pass options to the linker when static-pie is passed.
There's another patch to enable static-pie in glibc. And we need to
enable in GCC first.
gcc/ChangeLog:
* config/riscv/linux.h: Pass the static-pie specific options to
the linker.
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Kong Lingling [Wed, 29 Mar 2023 08:22:54 +0000 (16:22 +0800)]
[APX EGPR] Handle vex insns that only support GPR16 (5/5)
These vex insn may have legacy counterpart that could support EGPR,
but they do not have evex counterpart. Split out its vex part from
patterns and set the vex part to non-EGPR supported by adjusting
constraints and attr_gpr32.
* config/i386/constraints.md (jb): New constraint for vsib memory
that does not allow gpr32.
* config/i386/i386.md: (setcc_<mode>_sse): Replace m to jm for avx
alternative and set attr_gpr32 to 0.
(movmsk_df): Split avx/noavx alternatives and replace "r" to "jr" for
avx alternative.
(<sse>_rcp<mode>2): Split avx/noavx alternatives and replace
"m/Bm" to "jm/ja" for avx alternative, set its gpr32 attr to 0.
(*rsqrtsf2_sse): Likewise.
* config/i386/mmx.md (mmx_pmovmskb): Split alternative 1 to
avx/noavx and assign jr/r constraint to dest.
* config/i386/sse.md (<sse>_movmsk<ssemodesuffix><avxsizesuffix>):
Split avx/noavx alternatives and replace "r" to "jr" for avx alternative.
(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): Likewise.
(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_lt): Likewise.
(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_lt): Likewise.
(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_shift): Likewise.
(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_shift): Likewise.
(<sse2_avx2>_pmovmskb): Likewise.
(*<sse2_avx2>_pmovmskb_zext): Likewise.
(*sse2_pmovmskb_ext): Likewise.
(*<sse2_avx2>_pmovmskb_lt): Likewise.
(*<sse2_avx2>_pmovmskb_zext_lt): Likewise.
(*sse2_pmovmskb_ext_lt): Likewise.
(<sse>_rcp<mode>2): Split avx/noavx alternatives and replace
"m/Bm" to "jm/ja" for avx alternative, set its attr_gpr32 to 0.
(sse_vmrcpv4sf2): Likewise.
(*sse_vmrcpv4sf2): Likewise.
(rsqrt<mode>2): Likewise.
(sse_vmrsqrtv4sf2): Likewise.
(*sse_vmrsqrtv4sf2): Likewise.
(avx_h<insn>v4df3): Likewise.
(sse3_hsubv2df3): Likewise.
(avx_h<insn>v8sf3): Likewise.
(sse3_h<insn>v4sf3): Likewise.
(<sse3>_lddqu<avxsizesuffix>): Likewise.
(avx_cmp<mode>3): Likewise.
(avx_vmcmp<mode>3): Likewise.
(*sse2_gt<mode>3): Likewise.
(sse_ldmxcsr): Likewise.
(sse_stmxcsr): Likewise.
(avx_vtest<ssemodesuffix><avxsizesuffix>): Replace m to jm for
avx alternative and set attr_gpr32 to 0.
(avx2_permv2ti): Likewise.
(*avx_vperm2f128<mode>_full): Likewise.
(*avx_vperm2f128<mode>_nozero): Likewise.
(vec_set_lo_v32qi): Likewise.
(<avx_avx2>_maskload<ssemodesuffix><avxsizesuffix>): Likewise.
(<avx_avx2>_maskstore<ssemodesuffix><avxsi)zesuffix>: Likewise.
(avx_cmp<mode>3): Likewise.
(avx_vmcmp<mode>3): Likewise.
(*<sse>_maskcmp<mode>3_comm): Likewise.
(*avx2_gathersi<VEC_GATHER_MODE:mode>): Replace Tv to jb and set
attr_gpr32 to 0.
(*avx2_gathersi<VEC_GATHER_MODE:mode>_2): Likewise.
(*avx2_gatherdi<VEC_GATHER_MODE:mode>): Likewise.
(*avx2_gatherdi<VEC_GATHER_MODE:mode>_2): Likewise.
(*avx2_gatherdi<VI4F_256:mode>_3): Likewise.
(*avx2_gatherdi<VI4F_256:mode>_4): Likewise.
(avx_vbroadcastf128_<mode>): Restrict non-egpr alternative to
noavx512vl, set its constraint to jm and set attr_gpr32 to 0.
(vec_set_lo_<mode><mask_name>): Likewise.
(vec_set_lo_<mode><mask_name>): Likewise for SF/SI modes.
(vec_set_hi_<mode><mask_name>): Likewise.
(vec_set_hi_<mode><mask_name>): Likewise for SF/SI modes.
(vec_set_hi_<mode>): Likewise.
(vec_set_lo_<mode>): Likewise.
(avx2_set_hi_v32qi): Likewise.
Co-authored-by: Hongyu Wang <hongyu.wang@intel.com> Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
Kong Lingling [Wed, 29 Mar 2023 02:05:16 +0000 (10:05 +0800)]
[APX_EGPR] Handle legacy insns that only support GPR16 (4/5)
The APX enabled hardware should also be AVX10 enabled, thus for map2/3 insns
with evex counterpart, we assume auto promotion to EGPR under APX_F if the
insn uses GPR32. So for below insns, we disabled EGPR usage for their sse
mnenomics, while allowing egpr generation of their v prefixed mnemonics.
* config/i386/i386-protos.h (x86_evex_reg_mentioned_p): New
prototype.
* config/i386/i386.cc (x86_evex_reg_mentioned_p): New
function.
* config/i386/i386.md (sse4_1_round<mode>2): Set attr gpr32 0
and constraint jm to all non-evex alternatives, adjust
alternative outputs if evex reg is mentioned.
* config/i386/sse.md (<sse4_1>_ptest<mode>): Set attr gpr32 0
and constraint jm/ja to all non-evex alternatives.
(ptesttf2): Likewise.
(<sse4_1>_round<ssemodesuffix><avxsizesuffix): Likewise.
(sse4_1_round<ssescalarmodesuffix>): Likewise.
(sse4_2_pcmpestri): Likewise.
(sse4_2_pcmpestrm): Likewise.
(sse4_2_pcmpestr_cconly): Likewise.
(sse4_2_pcmpistr): Likewise.
(sse4_2_pcmpistri): Likewise.
(sse4_2_pcmpistrm): Likewise.
(sse4_2_pcmpistr_cconly): Likewise.
(aesimc): Likewise.
(aeskeygenassist): Likewise.
Kong Lingling [Fri, 24 Mar 2023 01:54:46 +0000 (09:54 +0800)]
[APX EGPR] Handle legacy insn that only support GPR16 (1/5)
These legacy insn in opcode map0/1 only support GPR16,
and do not have vex/evex counterpart, directly adjust constraints and
add gpr32 attr to patterns.
Hongyu Wang [Thu, 17 Aug 2023 00:30:04 +0000 (08:30 +0800)]
[APX EGPR] Handle GPR16 only vector move insns
For vector move insns like vmovdqa/vmovdqu, their evex counterparts
requrire explicit suffix 64/32/16/8. The usage of these instruction
are prohibited under AVX10_1 or AVX512F, so for we select
vmovaps/vmovups for vector load/store insns that contains EGPR if
ther is no AVX512VL, and keep the original move insn selection
otherwise.
gcc/ChangeLog:
* config/i386/i386.cc (ix86_get_ssemov): Check if egpr is used,
adjust mnemonic for vmovduq/vmovdqa.
* config/i386/sse.md (*<extract_type>_vinsert<shuffletype><extract_suf>_0):
Check if egpr is used, adjust mnemonic for vmovdqu/vmovdqa.
(avx_vec_concat<mode>): Likewise, and separate alternative 0 to
avx_noavx512f.
Co-authored-by: Kong Lingling <lingling.kong@intel.com> Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
Kong Lingling [Thu, 23 Mar 2023 06:25:50 +0000 (14:25 +0800)]
[APX EGPR] Map reg/mem constraints in inline asm to non-EGPR constraint.
In inline asm, we do not know if the insn can use EGPR, so disable EGPR
usage by default via mapping the common reg/mem constraint to non-EGPR
constraints.
For memory constraints, we add an option -mapx-inline-asm-use-gpr32
to allow/disallow gpr32 usage in any memory related constraints, as
base_reg_class/index_reg_class cannot aware whether the asm insn
support gpr32 or not.
gcc/ChangeLog:
* config/i386/i386.cc (map_egpr_constraints): New funciton to
map common constraints to EGPR prohibited constraints.
(ix86_md_asm_adjust): Calls map_egpr_constraints.
* config/i386/i386.opt: Add option mapx-inline-asm-use-gpr32.
gcc/testsuite/ChangeLog:
* gcc.target/i386/apx-inline-gpr-norex2.c: New test.
Co-authored-by: Hongyu Wang <hongyu.wang@intel.com> Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
Kong Lingling [Thu, 23 Mar 2023 06:44:18 +0000 (14:44 +0800)]
[APX EGPR] Add backend hook for base_reg_class/index_reg_class.
Add backend helper functions to verify if a rtx_insn can adopt EGPR to
its base/index reg of memory operand. The verification rule goes like
1. For asm insn, enable/disable EGPR by ix86_apx_inline_asm_use_gpr32.
2. Disable EGPR for unrecognized insn.
3. If which_alternative is not decided, loop through enabled alternatives
and check its attr_gpr32. Only enable EGPR when all enabled
alternatives has attr_gpr32 = 1.
4. If which_alternative is decided, enable/disable EGPR by its corresponding
attr_gpr32.
gcc/ChangeLog:
* config/i386/i386-protos.h (ix86_insn_base_reg_class): New
prototype.
(ix86_regno_ok_for_insn_base_p): Likewise.
(ix86_insn_index_reg_class): Likewise.
* config/i386/i386.cc (ix86_memory_address_use_extended_reg_class_p):
New helper function to scan the insn.
(ix86_insn_base_reg_class): New function to choose BASE_REG_CLASS.
(ix86_regno_ok_for_insn_base_p): Likewise for base regno.
(ix86_insn_index_reg_class): Likewise for INDEX_REG_CLASS.
* config/i386/i386.h (INSN_BASE_REG_CLASS): Define.
(REGNO_OK_FOR_INSN_BASE_P): Likewise.
(INSN_INDEX_REG_CLASS): Likewise.
(enum reg_class): Add INDEX_GPR16.
(GENERAL_GPR16_REGNO_P): Define.
* config/i386/i386.md (gpr32): New attribute.
Co-authored-by: Hongyu Wang <hongyu.wang@intel.com> Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
Kong Lingling [Thu, 23 Mar 2023 06:21:33 +0000 (14:21 +0800)]
[APX EGPR] Add register and memory constraints that disallow EGPR
For APX, as we extended the GENERAL_REG_CLASS, new constraints are
needed to restrict insns that cannot adopt EGPR either in its reg or
memory operands. We added a series of constraints for general/backend
ones that related to GPR usage. All of them are prefixed with "j" to
indicate the constraints does not allow EGPR.
gcc/ChangeLog:
* config/i386/constraints.md (jr): New register constraint
that prohibits EGPR.
(jR): Constraint that force usage of EGPR.
(jm): New memory constraint that prohibits EGPR.
(ja): Likewise for Bm constraint.
(jb): Likewise for Tv constraint.
(j<): New auto-dec memory constraint that prohibits EGPR.
(j>): Likewise for ">" constraint.
(jo): Likewise for "o" constraint.
(jv): Likewise for "V" constraint.
(jp): Likewise for "p" constraint.
* config/i386/i386.h (enum reg_class): Add new reg class
GENERAL_GPR16.
Co-authored-by: Hongyu Wang <hongyu.wang@intel.com> Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
Kong Lingling [Fri, 11 Nov 2022 08:16:27 +0000 (16:16 +0800)]
[APX_EGPR] Initial support for APX_F
Add -mapx-features= enumeration to separate subfeatures of APX_F.
-mapxf is treated same as previous ISA flag, while it sets
-mapx-features=apx_all that enables all subfeatures.
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (XSTATE_APX_F): New macro.
(XCR_APX_F_ENABLED_MASK): Likewise.
(get_available_features): Detect APX_F under
* common/config/i386/i386-common.cc (OPTION_MASK_ISA2_APX_F_SET): New.
(OPTION_MASK_ISA2_APX_F_UNSET): Likewise.
(ix86_handle_option): Handle -mapxf.
* common/config/i386/i386-cpuinfo.h (FEATURE_APX_F): New.
* common/config/i386/i386-isas.h: Add entry for APX_F.
* config/i386/cpuid.h (bit_APX_F): New.
* config/i386/i386.h (bit_APX_F): (TARGET_APX_EGPR,
TARGET_APX_PUSH2POP2, TARGET_APX_NDD): New define.
* config/i386/i386-opts.h (enum apx_features): New enum.
* config/i386/i386-isa.def (APX_F): New DEF_PTA.
* config/i386/i386-options.cc (ix86_function_specific_save):
Save ix86_apx_features.
(ix86_function_specific_restore): Restore it.
(ix86_valid_target_attribute_inner_p): Add mapxf.
(ix86_option_override_internal): Set ix86_apx_features for PTA
and TARGET_APX_F. Also reports error when APX_F is set but not
having TARGET_64BIT.
* config/i386/i386.opt: (-mapxf): New ISA flag option.
(-mapx=): New enumeration option.
(apx_features): New enum type.
(apx_none): New enum value.
(apx_egpr): Likewise.
(apx_push2pop2): Likewise.
(apx_ndd): Likewise.
(apx_all): Likewise.
* doc/invoke.texi: Document mapxf.
gcc/testsuite/ChangeLog:
* gcc.target/i386/apx-1.c: New test.
Co-authored-by: Hongyu Wang <hongyu.wang@intel.com> Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
Hongyu Wang [Fri, 14 Jul 2023 08:33:32 +0000 (16:33 +0800)]
[APX EGPR] middle-end: Add index_reg_class with insn argument.
Like base_reg_class, INDEX_REG_CLASS also does not support backend insn.
Add index_reg_class with insn argument for lra/reload usage.
gcc/ChangeLog:
* addresses.h (index_reg_class): New wrapper function like
base_reg_class.
* doc/tm.texi: Document INSN_INDEX_REG_CLASS.
* doc/tm.texi.in: Ditto.
* lra-constraints.cc (index_part_to_reg): Pass index_class.
(process_address_1): Calls index_reg_class with curr_insn and
replace INDEX_REG_CLASS with its return value index_cl.
* reload.cc (find_reloads_address): Likewise.
(find_reloads_address_1): Likewise.
Co-authored-by: Kong Lingling <lingling.kong@intel.com> Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
Kong Lingling [Thu, 23 Mar 2023 06:34:36 +0000 (14:34 +0800)]
[APX EGPR] middle-end: Add insn argument to base_reg_class
Current reload infrastructure does not support selective base_reg_class
for backend insn. Add new macros with insn parameters to base_reg_class
for lra/reload usage.
gcc/ChangeLog:
* addresses.h (base_reg_class): Add insn argument and new macro
INSN_BASE_REG_CLASS.
(regno_ok_for_base_p_1): Add insn argument and new macro
REGNO_OK_FOR_INSN_BASE_P.
(regno_ok_for_base_p): Add insn argument and parse to ok_for_base_p_1.
* doc/tm.texi: Document INSN_BASE_REG_CLASS and
REGNO_OK_FOR_INSN_BASE_P.
* doc/tm.texi.in: Ditto.
* lra-constraints.cc (process_address_1): Pass insn to
base_reg_class.
(curr_insn_transform): Ditto.
* reload.cc (find_reloads): Ditto.
(find_reloads_address): Ditto.
(find_reloads_address_1): Ditto.
(find_reloads_subreg_address): Ditto.
* reload1.cc (maybe_fix_stack_asms): Ditto.
Co-authored-by: Hongyu Wang <hongyu.wang@intel.com> Co-authored-by: Hongtao Liu <hongtao.liu@intel.com>
* gcc.target/riscv/rvv/rvv.exp: Add zfa for building.
* gcc.target/riscv/rvv/autovec/unop/math-ceil-run-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-floor-run-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-nearbyint-run-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-rint-run-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-round-run-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-roundeven-run-0.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-roundeven-run-1.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-roundeven-run-2.c: New test.
* gcc.target/riscv/rvv/autovec/unop/math-trunc-run-0.c: New test.
Currently, we have the pattern "movsf_from_si2" which was trying
to support moving high part DI to SF.
But current pattern only accepts "ashiftrt":
XX:SF=bitcast:SF(subreg(YY:DI>>32),0), but actually "lshiftrt" should
also be ok.
And current pattern only supports BE.
Here, updating the pattern to support BE and "lshiftrt".
PR target/108338
gcc/ChangeLog:
* config/rs6000/predicates.md (lowpart_subreg_operator): New
define_predicate.
* config/rs6000/rs6000.md (any_rshift): New code_iterator.
(movsf_from_si2): Rename to ...
(movsf_from_si2_<code>): ... this.
When handling (plus (plus (mult (a) (mem_shadd_constant)) (fp)) (C)) case,
the fp will be the lo_sum operand as above. We have assumption that the fp
is reg but actually not here. It will have ICE when building with option
--enable-checking=rtl.
This patch would like to fix it by adding the REG_P to ensure the operand
is a register. The test case gcc/testsuite/gcc.dg/pr109417.c covered this
fix when build with --enable-checking=rtl.
PR target/111634
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_address): Ensure
object is a REG before extracting its' REGNO.
Roger Sayle [Fri, 6 Oct 2023 19:11:44 +0000 (20:11 +0100)]
i386: Implement doubleword shift left by 1 bit using add+adc.
This patch tweaks the i386 back-end's ix86_split_ashl to implement
doubleword left shifts by 1 bit, using an add followed by an add-with-carry
(i.e. a doubleword x+x) instead of using the x86's shld instruction.
The replacement sequence both requires fewer bytes and is faster on
both Intel and AMD architectures (from Agner Fog's latency tables and
confirmed by my own micro-benchmarking).
For the test case:
__int128 foo(__int128 x) { return x << 1; }
This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
and make -k check, both with and without --target_board=unix{-m32}
with no new failures. Ok for mainline?
2023-10-06 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/i386/i386-expand.cc (ix86_split_ashl): Split shifts by
one into add3_cc_overflow_1 followed by add3_carry.
* config/i386/i386.md (@add<mode>3_cc_overflow_1): Renamed from
"*add<mode>3_cc_overflow_1" to provide generator function.
gcc/testsuite/ChangeLog
* gcc.target/i386/ashldi3-2.c: New 32-bit test case.
* gcc.target/i386/ashlti3-3.c: New 64-bit test case.
Makefile.tpl: disable -Werror for feedback stage [PR111663]
Without the change profiled bootstrap fails for various warnings on
master branch as:
$ ../gcc/configure
$ make profiledbootstrap
...
gcc/genmodes.cc: In function ‘int main(int, char**)’:
gcc/genmodes.cc:2152:1: error: ‘gcc/build/genmodes.gcda’ profile count data file not found [-Werror=missing-profile]
...
gcc/gengtype-parse.cc: In function ‘void parse_error(const char*, ...)’:
gcc/gengtype-parse.cc:142:21: error: ‘%s’ directive argument is null [-Werror=format-overflow=]
The change removes -Werror just like autofeedback does today.
Roger Sayle [Fri, 6 Oct 2023 19:07:53 +0000 (20:07 +0100)]
i386: Split lea into shorter left shift by 2 or 3 bits with -Oz.
This patch avoids long lea instructions for performing x<<2 and x<<3
by splitting them into shorter sal and move (or xchg instructions).
Because this increases the number of instructions, but reduces the
total size, its suitable for -Oz (but not -Os).
The impact can be seen in the new test case:
int foo(int x) { return x<<2; }
int bar(int x) { return x<<3; }
long long fool(long long x) { return x<<2; }
long long barl(long long x) { return x<<3; }
Over the entirety of the CSiBE code size benchmark this saves 1347
bytes (0.037%) for x86_64, and 1312 bytes (0.036%) with -m32.
Conveniently, there's already a backend function in i386.cc for
deciding whether to split an lea into its component instructions,
ix86_avoid_lea_for_addr, all that's required is an additional
clause checking for -Oz (i.e. optimize_size > 1).
2023-10-06 Roger Sayle <roger@nextmovesoftware.com>
Uros Bizjak <ubizjak@gmail.com>
gcc/ChangeLog
* config/i386/i386.cc (ix86_avoid_lea_for_addr): Split LEAs used
to perform left shifts into shorter instructions with -Oz.
gcc/testsuite/ChangeLog
* gcc.target/i386/lea-2.c: New test case.
Vineet Gupta [Fri, 6 Oct 2023 18:21:51 +0000 (11:21 -0700)]
RISC-V: const: hide mvconst splitter from IRA
Vlad recently introduced a new gate @ira_in_progress, similar to
counterparts @{reload,lra}_in_progress.
Use this to hide the constant synthesis splitter from being recog* ()
by IRA register equivalence logic which is eager to undo the splits,
generating worse code for constants (and sometimes no code at all).
See PR/109279 (large constant), PR/110748 (const -0.0) ...
Granted the IRA logic is subsided with -fsched-pressure which is now
enabled for RISC-V backend, the gate makes this future-proof in
addition to helping with -O1 etc.
This fixes 1 addition test
========= Summary of gcc testsuite =========
| # of unexpected case / # of unique unexpected case
| gcc | g++ | gfortran |
Andrew Pinski [Thu, 5 Oct 2023 19:21:19 +0000 (12:21 -0700)]
MATCH: Fix infinite loop between `vec_cond(vec_cond(a,b,0), c, d)` and `a & b`
Match has a pattern which converts `vec_cond(vec_cond(a,b,0), c, d)`
into `vec_cond(a & b, c, d)` but since in this case a is a comparison
fold will change `a & b` back into `vec_cond(a,b,0)` which causes an
infinite loop.
The best way to fix this is to enable the patterns for vec_cond(*,vec_cond,*)
only for GIMPLE so we don't get an infinite loop for fold any more.
Jakub Jelinek [Fri, 6 Oct 2023 06:54:42 +0000 (08:54 +0200)]
ipa: Remove ipa_bits
The following patch removes ipa_bits struct pointer/vector from ipa
jump functions and ipa cp transformations.
The reason is because the struct uses widest_int to represent
mask/value pair, which in the RFC patches to allow larger precisions
for wide_int/widest_int is GC unfriendly because those types become
non-trivially default constructible/copyable/destructible.
One option would be to use trailing_wide_int for that instead, but
as pointed out by Aldy, irange_storage which we already use under
the hood for ipa_vr when type of parameter is integral or pointer
already stores the mask/value pair because VRP now does the bit cp
as well.
So, this patch just uses m_vr to store both the value range and
the bitmask. There is still separate propagation of the
ipcp_bits_lattice from propagation of the ipcp_vr_lattice, but
when storing we merge the two into the same container.
2023-10-06 Jakub Jelinek <jakub@redhat.com>
* ipa-prop.h (ipa_bits): Remove.
(struct ipa_jump_func): Remove bits member.
(struct ipcp_transformation): Remove bits member, adjust
ctor and dtor.
(ipa_get_ipa_bits_for_value): Remove.
* ipa-prop.cc (struct ipa_bit_ggc_hash_traits): Remove.
(ipa_bits_hash_table): Remove.
(ipa_print_node_jump_functions_for_edge): Don't print bits.
(ipa_get_ipa_bits_for_value): Remove.
(ipa_set_jfunc_bits): Remove.
(ipa_compute_jump_functions_for_edge): For pointers query
pointer alignment before ipa_set_jfunc_vr and update_bitmask
in there. For integral types, just rely on bitmask already
being handled in value ranges.
(ipa_check_create_edge_args): Don't create ipa_bits_hash_table.
(ipcp_transformation_initialize): Neither here.
(ipcp_transformation_t::duplicate): Don't copy bits vector.
(ipa_write_jump_function): Don't stream bits here.
(ipa_read_jump_function): Neither here.
(useful_ipcp_transformation_info_p): Don't test bits vec.
(write_ipcp_transformation_info): Don't stream bits here.
(read_ipcp_transformation_info): Neither here.
(ipcp_get_parm_bits): Get mask and value from m_vr rather
than bits.
(ipcp_update_bits): Remove.
(ipcp_update_vr): For pointers, set_ptr_info_alignment from
bitmask stored in value range.
(ipcp_transform_function): Don't test bits vector, don't call
ipcp_update_bits.
* ipa-cp.cc (propagate_bits_across_jump_function): Don't use
jfunc->bits, instead get mask and value from jfunc->m_vr.
(ipcp_store_bits_results): Remove.
(ipcp_store_vr_results): Incorporate parts of
ipcp_store_bits_results here, merge the bitmasks with value
range if both are supplied.
(ipcp_driver): Don't call ipcp_store_bits_results.
* ipa-sra.cc (zap_useless_ipcp_results): Remove *ts->bits
clearing.
ipa-utils: avoid uninitialized probabilities on ICF [PR111559]
r14-3459-g0c78240fd7d519 "Check that passes do not forget to define profile"
exposed check failures in cases when gcc produces uninitialized profile
probabilities. In case of PR/111559 uninitialized profile is generated
by edges executed 0 times reported by IPA profile:
$ gcc -O2 -fprofile-generate pr111559.c -o b -fopt-info
$ ./b
$ gcc -O2 -fprofile-use -fprofile-correction pr111559.c -o b -fopt-info
pr111559.c: In function 'rule1':
pr111559.c:6:13: error: probability of edge 3->4 not initialized
6 | static void rule1(void) { if (p) edge(); }
| ^~~~~
during GIMPLE pass: fixup_cfg
pr111559.c:6:13: internal compiler error: verify_flow_info failed
The change conservatively ignores updates with zero execution counts and
uses initially assigned probabilities (`always` probability in case of
the example).
PR ipa/111283
PR gcov-profile/111559
gcc/
* ipa-utils.cc (ipa_merge_profiles): Avoid producing
uninitialized probabilities when merging counters with zero
denominators.
gcc/testsuite/
* gcc.dg/tree-prof/pr111559.c: New test.
Uros Bizjak [Thu, 5 Oct 2023 15:40:37 +0000 (17:40 +0200)]
i386: Improve memory copy from named address space [PR111657]
The stringop strategy selection algorithm falls back to a libcall strategy
when it exhausts its pool of available strategies. The memory area copy
function (memcpy) is not availabe from the system library for non-default
address spaces, so the compiler emits the most trivial byte-at-a-time
copy loop instead.
The compiler should instead emit an optimized copy loop as a fallback for
non-default address spaces.
PR target/111657
gcc/ChangeLog:
* config/i386/i386-expand.cc (alg_usable_p): Reject libcall
strategy for non-default address spaces.
(decide_alg): Use loop strategy as a fallback strategy for
non-default address spaces.
Andrea Corallo [Tue, 3 Oct 2023 12:19:03 +0000 (14:19 +0200)]
contrib: add mdcompact
Hello all,
this patch checks in mdcompact, the tool written in elisp that I used
to mass convert all the multi choice pattern in the aarch64 back-end to
the new compact syntax.
I tested it on Emacs 29 (might run on older versions as well not
sure), also I verified it runs cleanly on a few other back-ends (arm,
loongarch).
The tool can be used to convert a single pattern, an open buffer or
all md files in a directory.
The tool might need further adjustment to run on some specific
back-end, in case very happy to help.
LibF7: Use monic denominator polynomials to save a multiplication.
libgcc/config/avr/libf7/
* libf7.h (F7_FLAGNO_plusx, F7_FLAG_plusx): New macros.
* libf7.c (f7_horner): Handle F7_FLAG_plusx in highest coefficient.
* libf7-const.def [F7MOD_atan_]: Denominator: Set F7_FLAG_plusx
and omit highest term.
[F7MOD_asinacos_]: Use rational function with normalized denominator.
Jakub Jelinek [Thu, 5 Oct 2023 12:28:44 +0000 (14:28 +0200)]
sreal: Fix typo in function name
My earlier version of the ipa_bits removal patch resulted in self-test
failures in sreal. When debugging it, I was really confused that I couldn't
find verify_arithmetics function in the source. Turns out it had bad
spelling...
Remove old ccfsm responsible for conditional execution support in ARC.
This machinery is not needed as the current gcc conditional execution
support is mature.
Richard Biener [Thu, 5 Oct 2023 08:26:34 +0000 (10:26 +0200)]
Fix SIMD call SLP discovery
When we do SLP discovery of SIMD calls we run into the issue that
when the call is neither builtin nor internal function we have
cfn == CFN_LAST but internal_fn_p of that returns true. Since
IFN_LAST isn't vectorizable we fail spuriously.
Fixed by checking for cfn != CFN_LAST && internal_fn_p (cfn)
instead.
* tree-vect-slp.cc (vect_build_slp_tree_1): Do not
ask for internal_fn_p (CFN_LAST).
Richard Biener [Wed, 4 Oct 2023 13:25:33 +0000 (15:25 +0200)]
Avoid left around copies when value-numbering BBs
The following makes sure to treat values whose definition we didn't
visit as available since those by definition must dominate the entry
of the region. That avoids unpropagated copies after if-conversion
and resulting SLP discovery fails (which doesn't handle plain copies).
* tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Not
visited value numbers are available itself.
The following clarifies the flatten attribute documentation to mention
the inlining applies also to calls formed as part of inlining earlier
calls but not calls to the function itself.
Roger Sayle [Wed, 4 Oct 2023 16:17:03 +0000 (17:17 +0100)]
ARC: Split SImode shifts pre-reload on !TARGET_BARREL_SHIFTER.
This patch splits SImode shifts, for !TARGET_BARREL_SHIFTER targets,
after combine and before reload, in the split1 pass, as suggested by
the FIXME comment above output_shift in arc.cc. To do this I've
copied the implementation of the x86_pre_reload_split function from
the i386 backend, and renamed it arc_pre_reload_split.
Although the actual implementations of shifts remain the same
(as in output_shift), having them as explicit instructions in
the RTL stream allows better scheduling and use of compact forms
when available. The benefits can be seen in two short examples
below.
For the function:
unsigned int foo(unsigned int x, unsigned int y) {
return y << 2;
}
GCC with -O2 -mcpu=em would previously generate:
foo: add r1,r1,r1
add r1,r1,r1
j_s.d [blink]
mov_s r0,r1 ;4
and with this patch now generates:
foo: asl_s r0,r1
j_s.d [blink]
asl_s r0,r0
Notice the original (from shift_si3's output_shift) requires the
shift sequence to be monolithic with the same destination register
as the source (requiring an extra mov_s). The new version can
eliminate this move, and schedule the second asl in the branch
delay slot of the return.
where each shift by 3, uses ARC's add3 instruction, which is similar
to x86's lea implementing x = (y<<3) + z, but requires the value zero
to be placed in a temporary register "z". Splitting this before reload
allows these pseudos to be shared/reused. With this patch, we get
Unfortunately, register allocation means that we only share two of the
three "mov_s z,0", but this is sufficient to reduce register pressure
enough to avoid spilling r13 in the prologue/epilogue.
2023-10-04 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/arc/arc-protos.h (emit_shift): Delete prototype.
(arc_pre_reload_split): New function prototype.
* config/arc/arc.cc (emit_shift): Delete function.
(arc_pre_reload_split): New predicate function, copied from i386,
to schedule define_insn_and_split splitters to the split1 pass.
* config/arc/arc.md (ashlsi3): Expand RTL template unconditionally.
(ashrsi3): Likewise.
(lshrsi3): Likewise.
(shift_si3): Move after other shift patterns, and disable when
operands[2] is one (which is handled by its own define_insn).
Use shiftr4_operator, instead of shift4_operator, as this is no
longer used for left shifts.
(shift_si3_loop): Likewise. Additionally remove match_scratch.
(*ashlsi3_nobs): New pre-reload define_insn_and_split.
(*ashrsi3_nobs): Likewise.
(*lshrsi3_nobs): Likewise.
(rotrsi3_cnt1): Rename define_insn from *rotrsi3_cnt1.
(add_shift): Rename define_insn from *add_shift.
* config/arc/predicates.md (shiftl4_operator): Delete.
(shift4_operator): Delete.
gcc/testsuite/ChangeLog
* gcc.target/arc/ashrsi-1.c: New TARGET_BARREL_SHIFTER test case.
* gcc.target/arc/ashrsi-2.c: New !TARGET_BARREL_SHIFTER test case.
* gcc.target/arc/ashrsi-3.c: Likewise.
* gcc.target/arc/ashrsi-4.c: Likewise.
* gcc.target/arc/ashrsi-5.c: Likewise.
* gcc.target/arc/lshrsi-1.c: New TARGET_BARREL_SHIFTER test case.
* gcc.target/arc/lshrsi-2.c: New !TARGET_BARREL_SHIFTER test case.
* gcc.target/arc/lshrsi-3.c: Likewise.
* gcc.target/arc/lshrsi-4.c: Likewise.
* gcc.target/arc/lshrsi-5.c: Likewise.
* gcc.target/arc/shlsi-1.c: New TARGET_BARREL_SHIFTER test case.
* gcc.target/arc/shlsi-2.c: New !TARGET_BARREL_SHIFTER test case.
* gcc.target/arc/shlsi-3.c: Likewise.
* gcc.target/arc/shlsi-4.c: Likewise.
* gcc.target/arc/shlsi-5.c: Likewise.
projects / thirdparty / gcc.git / log
