This patch adds uses of force_highpart_subreg to places that
already use force_lowpart_subreg.
gcc/
* config/aarch64/aarch64.cc (aarch64_addti_scratch_regs): Use
force_highpart_subreg instead of gen_highpart and simplify_gen_subreg.
(aarch64_subvti_scratch_regs): Likewise.
This patch makes target-independent code use force_lowpart_subreg
instead of simplify_gen_subreg and lowpart_subreg in some places.
The criteria were:
(1) The code is obviously specific to expand (where new pseudos
can be created), or at least would be invalid to call when
!can_create_pseudo_p () and temporaries are needed.
(2) The value is obviously an rvalue rather than an lvalue.
Doing this should reduce the likelihood of bugs like PR115464
occuring in other situations.
gcc/
* builtins.cc (expand_builtin_issignaling): Use force_lowpart_subreg
instead of simplify_gen_subreg and lowpart_subreg.
* expr.cc (convert_mode_scalar, expand_expr_real_2): Likewise.
* optabs.cc (expand_doubleword_mod): Likewise.
optabs had a local function called lowpart_subreg_maybe_copy
that is very similar to the lowpart version of force_subreg.
This patch adds a force_lowpart_subreg wrapper around
force_subreg and uses it in optabs.cc.
The only difference between the old and new functions is that
the old one asserted success while the new one doesn't.
It's common not to assert elsewhere when taking subregs;
normally a null result is enough.
Later patches will make more use of the new function.
gcc/
* explow.h (force_lowpart_subreg): Declare.
* explow.cc (force_lowpart_subreg): New function.
* optabs.cc (lowpart_subreg_maybe_copy): Delete.
(expand_absneg_bit): Use force_lowpart_subreg instead of
lowpart_subreg_maybe_copy.
(expand_copysign_bit): Likewise.
This patch makes target-independent code use force_subreg instead
of simplify_gen_subreg in some places. The criteria were:
(1) The code is obviously specific to expand (where new pseudos
can be created), or at least would be invalid to call when
!can_create_pseudo_p () and temporaries are needed.
(2) The value is obviously an rvalue rather than an lvalue.
(3) The offset wasn't a simple lowpart or highpart calculation;
a later patch will deal with those.
Doing this should reduce the likelihood of bugs like PR115464
occuring in other situations.
While adding more uses of force_subreg, I realised that it should
be more careful to emit no instructions on failure. This kind of
failure should be very rare, so I don't think it's a case worth
optimising for.
gcc/
* explow.cc (force_subreg): Emit no instructions on failure.
Martin Uecker [Sat, 18 May 2024 20:00:04 +0000 (22:00 +0200)]
c23: Fix for redeclared enumerator initialized with different type [PR115109]
c23 specifies that the type of a redeclared enumerator is the one of the
previous declaration. Convert initializers with different type accordingly
and emit an error when the value does not fit.
2024-06-01 Martin Uecker <uecker@tugraz.at>
PR c/115109
gcc/c/
* c-decl.cc (build_enumerator): When redeclaring an
enumerator convert value to previous type. For redeclared
enumerators use underlying type for computing the next value.
gcc/testsuite/
* gcc.dg/pr115109.c: New test.
* gcc.dg/c23-tag-enum-6.c: New test.
* gcc.dg/c23-tag-enum-7.c: New test.
While my r15-1001-g4cf2de9b5268224 PCH PIE power fix change decreased the
.data section sizes (219792 -> 189336), it increased the size of already
huge rs6000_init_generated_builtins generated function, from 218328
to 228668 bytes. That is because there are thousands of array references
to global arrays and we keep constructing the addresses of the arrays
again and again.
Ideally some optimization would figure out we have a single function which
has
461 rs6000_overload_info
1257 rs6000_builtin_info_fntype
1768 rs6000_builtin_decls
2548 rs6000_instance_info_fntype
array references and that maybe it might be a good idea to just preload
the addresses of those arrays into some register if it decreases code size
and doesn't slow things down.
The function actually is called just once and is huge, so code size is even
more important than speed, which is dominated by all the GC allocations
anyway.
Until that is done, here is a slightly cleaner version of the hack, which
makes the function noipa (so that LTO doesn't undo it) for GCC 8.1+ and
passes the 4 arrays as arguments to the function from the caller.
This decreases the function size from 228668 bytes to 207572 bytes.
2024-06-18 Jakub Jelinek <jakub@redhat.com>
PR target/115324
* config/rs6000/rs6000-gen-builtins.cc (write_decls): Change
declaration of rs6000_init_generated_builtins from no arguments
to 4 pointer arguments.
(write_init_bif_table): Change rs6000_builtin_info_fntype to
builtin_info_fntype and rs6000_builtin_decls to builtin_decls.
(write_init_ovld_table): Change rs6000_instance_info_fntype to
instance_info_fntype, rs6000_builtin_decls to builtin_decls and
rs6000_overload_info to overload_info.
(write_init_file): Add __noipa__ attribute to
rs6000_init_generated_builtins for GCC 8.1+ and change the function
from no arguments to 4 pointer arguments. Change rs6000_builtin_decls
to builtin_decls.
* config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Adjust
rs6000_init_generated_builtins caller.
Richard Biener [Fri, 14 Jun 2024 12:46:08 +0000 (14:46 +0200)]
Enhance if-conversion for automatic arrays
Automatic arrays that are not address-taken should not be subject to
store data races. This applies to OMP SIMD in-branch lowered
functions result array which for the testcase otherwise prevents
vectorization with SSE and for AVX and AVX512 ends up with spurious
.MASK_STORE to the stack surviving.
This inefficiency was noted in PR111793.
I've introduced ref_can_have_store_data_races, commonizing uses
of flag_store_data_races in if-conversion, cselim and store motion.
PR tree-optimization/111793
* tree-ssa-alias.h (ref_can_have_store_data_races): Declare.
* tree-ssa-alias.cc (ref_can_have_store_data_races): New
function.
* tree-if-conv.cc (ifcvt_memrefs_wont_trap): Use
ref_can_have_store_data_races to allow more unconditional
stores.
* tree-ssa-loop-im.cc (execute_sm): Likewise.
* tree-ssa-phiopt.cc (cond_store_replacement): Likewise.
Kewen Lin [Tue, 18 Jun 2024 02:46:53 +0000 (21:46 -0500)]
testsuite, rs6000: Replace powerpc_altivec_ok with powerpc_altivec [PR114842]
As noted in PR114842, most of the test cases which require
effective target check powerpc_altivec_ok actually care about
if ALTIVEC feature is enabled, and they should adopt effective
target powerpc_altivec instead. Otherwise, when users are
specifying extra option -mno-altivec in RUNTESTFLAGS, the check
powerpc_altivec_ok returns true then the test case would be
tested without ALTIVEC so it would fail. With commit r15-716,
dg-options and dg-additional-options can be taken into account
when evaluating powerpc_altivec, so this patch also moves
dg-{additional,}-options lines before dg-require-effective-target
to make it effective.
Andrew Pinski [Mon, 17 Jun 2024 23:45:34 +0000 (16:45 -0700)]
aarch64: Add testcase for PR97405
This aarch64 sve specific code was fixed by r15-917-gc9842f99042454
which added a riscv specific testcase so adding an aarch64 one to test
the fix does not regress is a good idea.
Committed as obvious after testing the testcase for aarch64-linux-gnu.
PR tree-optimization/97405
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/pr97405-1.c: New test.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Jeff Law [Mon, 17 Jun 2024 23:24:03 +0000 (17:24 -0600)]
[to-be-committed,RISC-V] Handle zero_extract destination for single bit insertions
Combine will use zero_extract destinations for certain bitfield
insertions. If the bitfield is a single bit constant, then we can use
bset/bclr.
In this case we are only dealing with word_mode objects, so we don't
have to worry about the SI->DI extension issues for TARGET_64BIT.
The testcase was derived from 502.gcc in spec from the RAU team.
An earlier version of this (TARGET_64BIT only) went through Ventana's CI
system. This version has gone though mine after generalizing it to
handle rv32 as well. I'll wait for pre-commit CI to render its verdict
before moving forward.
gcc/
* config/riscv/bitmanip.md (bsetclr_zero_extract): New pattern.
The option_map array for most entries contains just non-NULL opt0
{ "-Wno-", NULL, "-W", false, true },
{ "-fno-", NULL, "-f", false, true },
{ "-gno-", NULL, "-g", false, true },
{ "-mno-", NULL, "-m", false, true },
{ "--debug=", NULL, "-g", false, false },
{ "--machine-", NULL, "-m", true, false },
{ "--machine-no-", NULL, "-m", false, true },
{ "--machine=", NULL, "-m", false, false },
{ "--machine=no-", NULL, "-m", false, true },
{ "--machine", "", "-m", false, false },
{ "--machine", "no-", "-m", false, true },
{ "--optimize=", NULL, "-O", false, false },
{ "--std=", NULL, "-std=", false, false },
{ "--std", "", "-std=", false, false },
{ "--warn-", NULL, "-W", true, false },
{ "--warn-no-", NULL, "-W", false, true },
{ "--", NULL, "-f", true, false },
{ "--no-", NULL, "-f", false, true }
and so add_misspelling_candidates works correctly for it, but 3 out of
these,
{ "--machine", "", "-m", false, false },
{ "--machine", "no-", "-m", false, true },
and
{ "--std", "", "-std=", false, false },
use non-NULL opt1. That says that
--machine foo
should map to
-mfoo
and
--machine no-foo
should map to
-mno-foo
and
--std c++17
should map to
-std=c++17
add_misspelling_canidates was not handling this, so it hapilly
registered say
--stdc++17
or
--machineavx512
(twice) as spelling alternatives, when those options aren't recognized.
Instead we support
--std c++17
or
--machine avx512
--machine no-avx512
The following patch fixes that. On this particular testcase, we no longer
suggest anything, even when among the suggestion is say that
--std c++17
or
-std=c++17
etc.
2024-06-17 Jakub Jelinek <jakub@redhat.com>
PR driver/115440
* opts-common.cc (add_misspelling_candidates): If opt1 is non-NULL,
add a space and opt1 to the alternative suggestion text.
Joseph Myers [Mon, 17 Jun 2024 19:45:43 +0000 (19:45 +0000)]
c: Implement C2Y alignof on incomplete arrays
C2Y has adopted support for alignof applied to incomplete array types
(N3273). Add this support to GCC. As the relevant checks are in
c-family code that doesn't have access to functions such as
pedwarn_c23, this remains a hard error for older versions and isn't
handled by -Wc23-c2y-compat, although preferably it would work like
pedwarn_c23 (pedwarn-if-pedantic for older versions, warning with
-Wc23-c2y-compat in C2Y mode).
Bootstrapped with no regressions for x86_64-pc-linux-gnu.
gcc/c-family/
* c-common.cc (c_sizeof_or_alignof_type): Allow alignof on an
incomplete array type for C2Y.
gcc/testsuite/
* gcc.dg/c23-align-10.c, gcc.dg/c2y-align-1.c,
gcc.dg/c2y-align-2.c: New tests.
The warning code uses %D to print the ARRAY_REF first operands.
That works in the most common case where those operands are decls, but
as can be seen on the following testcase, they can be other expressions
with array type.
Just changing %D to %E isn't enough, because then the diagnostics can
suggest something like
note: use '&(x) != 0 ? (int (*)[32])&a : (int (*)[32])&b[0] == &(y) != 0 ? (int (*)[32])&a : (int (*)[32])&b[0]' to compare the addresses
which is a bad suggestion, the %E printing doesn't know that the
warning code will want to add & before it and [0] after it.
So, the following patch adds ()s around the operand as well, but does
that only for non-decls, for decls keeps it as &arr[0] like before.
2024-06-17 Jakub Jelinek <jakub@redhat.com>
PR c/115290
* c-warn.cc (do_warn_array_compare): Use %E rather than %D for
printing op0 and op1; if those operands aren't decls, also print
parens around them.
Jakub Jelinek [Mon, 17 Jun 2024 16:53:21 +0000 (18:53 +0200)]
c++: Fix up floating point conversion rank comparison for _Float32 and float if float/double are same size [PR115511]
On AVR and SH with some options sizeof (float) == sizeof (double) and
the 2 types have the same set of values.
http://eel.is/c++draft/conv.rank#2.2 for this says that double still
has bigger rank than float and http://eel.is/c++draft/conv.rank#2.2
says that extended type with the same set of values as more than one
standard floating point type shall have the same rank as double.
I've implemented the latter rule as
if (cnt > 1 && mv2 == long_double_type_node)
return -2;
with the _Float64/double/long double case having same mode case (various
targets with -mlong-double-64) in mind.
But never thought there are actually targets where float and double
are the same, that needs handling too, if cnt > 1 (that is the extended
type mv1 has same set of values as 2 or 3 of float/double/long double)
and mv2 is float, we need to return 2, because mv1 in that case should
have same rank as double and double has bigger rank than float.
2024-06-17 Jakub Jelinek <jakub@redhat.com>
PR target/111343
PR c++/115511
* typeck.cc (cp_compare_floating_point_conversion_ranks): If an
extended floating point type mv1 has same set of values as more
than one standard floating point type and mv2 is float, return 2.
Patrick O'Neill [Mon, 17 Jun 2024 16:46:05 +0000 (09:46 -0700)]
RISC-V: Add configure check for Zaamo/Zalrsc assembler support
Binutils 2.42 and before don't support Zaamo/Zalrsc. Add a configure
check to prevent emitting Zaamo/Zalrsc in the arch string when the
assember does not support it.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::to_string): Skip zaamo/zalrsc when not
supported by the assembler.
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Add zaamo/zalrsc assmeber check.
Peter Bergner [Fri, 14 Jun 2024 19:36:20 +0000 (14:36 -0500)]
rs6000: Compute rop_hash_save_offset for non-Altivec compiles [PR115389]
We currently only compute the offset for the ROP hash save location in
the stack frame for Altivec compiles. For non-Altivec compiles when we
emit ROP mitigation instructions, we use a default offset of zero which
corresponds to the backchain save location which will get clobbered on
any call. The fix is to compute the ROP hash save location for all
compiles.
Jeff Law [Mon, 17 Jun 2024 13:04:13 +0000 (07:04 -0600)]
[to-be-committed,RISC-V] Improve variable bit set for rv64
Another case of being able to safely use bset for 1 << n. In this case
the (1 << n) is explicitly zero extended from SI to DI. Two things to
keep in mind. The (1 << n) is done in SImode. So it doesn't directly
define bits 32..63 and those bits are cleared by the explicit zero
extension. Second if N is out of SImode's range, then the original
source level construct was undefined.
Thus we can use bset with x0 as our source input.
I think this testcase was from the RAU team. It doesn't immediately
look like something from SPEC, but that's where they were primarily focused.
This has been through Ventana's CI system in the past. I've also
recently added zbs testing to my own tester and naturally this passed
there as well. I'll wait for the pre-commit CI to do its thing before
moving forward. The plan would be to commit after passing.
gcc/
* config/riscv/bitmanip.md (bsetdi_2): New pattern.
Richard Biener [Mon, 17 Jun 2024 12:36:56 +0000 (14:36 +0200)]
tree-optimization/115508 - fix ICE with SLP scheduling and extern vector
When there's a permute after an extern vector we can run into a case
that didn't consider the scheduled node being a permute which lacks
a representative.
PR tree-optimization/115508
* tree-vect-slp.cc (vect_schedule_slp_node): Guard check on
representative.
Aldy Hernandez [Tue, 4 Jun 2024 05:35:51 +0000 (07:35 +0200)]
Rename Value_Range to value_range.
Now that all remaining users of value_range have been renamed to
int_range<>, we can reclaim value_range as a temporary, thus removing
the annoying CamelCase.
Fix ICE when compiling with -fcoarray=single, when derefing a non-array.
PR fortran/96418
PR fortran/103112
gcc/fortran/ChangeLog:
* trans.cc (gfc_deallocate_with_status): Check that object to deref
is an array, before applying array deref.
gcc/testsuite/ChangeLog:
* gfortran.dg/coarray_alloc_comp_3.f08: Moved to...
* gfortran.dg/coarray/alloc_comp_8.f90: ...here.
Should be tested for both -fcoarray=single and lib, resp.
* gfortran.dg/coarray_alloc_comp_4.f08: Fix program name.
Levy Hsu [Thu, 13 Jun 2024 05:50:04 +0000 (15:20 +0930)]
x86: Emit cvtne2ps2bf16 for odd increasing perm in __builtin_shufflevector
This patch updates the GCC x86 backend to efficiently handle
odd, incrementally increasing permutations of BF16 vectors
using the cvtne2ps2bf16 instruction.
It modifies ix86_vectorize_vec_perm_const to support these operations
and adds a specific predicate to ensure proper sequence handling.
gcc/ChangeLog:
* config/i386/i386-expand.cc
(ix86_vectorize_vec_perm_const): Convert BF to HI using subreg.
* config/i386/predicates.md
(vcvtne2ps2bf_parallel): New define_insn_and_split.
* config/i386/sse.md
(vpermt2_sepcial_bf16_shuffle_<mode>): New predicates matches odd increasing perm.
gcc/testsuite/ChangeLog:
* gcc.target/i386/vpermt2-special-bf16-shufflue.c: New test.
For the moment I deliberately left out one-element QHS vectors since it
is unclear whether these are pathological cases or whether they are
really used. If we ever get an extend for V1DI -> V1TI we should
reconsider this.
As a side-effect this fixes PR115261.
gcc/ChangeLog:
PR target/115261
* config/s390/s390.md (any_extend,extend_insn,zero_extend):
New code attributes and code iterator.
* config/s390/vector.md (V_EXTEND): New mode iterator.
(<extend_insn><V_EXTEND:mode><vec_2x_wide>2): New insn.
gcc/testsuite/ChangeLog:
* gcc.target/s390/vector/vec-extend-1.c: New test.
* gcc.target/s390/vector/vec-extend-2.c: New test.
Kewen Lin [Mon, 17 Jun 2024 02:50:19 +0000 (21:50 -0500)]
m2: Remove uses of {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE
Joseph pointed out "floating types should have their mode,
not a poorly defined precision value" in the discussion[1],
as he and Richi suggested, the existing macros
{FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE will be replaced with a
hook mode_for_floating_type. To be prepared for that, this
patch is to remove uses of {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE
in m2. Currently they are used for assertion and can be
replaced with TYPE_SIZE check on the corresponding type node,
since we dropped the call to layout_type which would early
return once TYPE_SIZE is set and this assertion ensures it's
safe to drop that call.
Currrently the size of the array reg_is_wrapped_separately is LAST_SAVED_REGNUM.
But LAST_SAVED_REGNUM could be regno that is being saved. So the size needs
to be `LAST_SAVED_REGNUM + 1` like aarch64_frame->reg_offset is.
Committed as obvious after a bootstrap/test for aarch64-linux-gnu.
gcc/ChangeLog:
PR target/100211
* config/aarch64/aarch64.h (machine_function): Fix the size
of reg_is_wrapped_separately.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
Jeff Law [Sun, 16 Jun 2024 14:36:27 +0000 (08:36 -0600)]
[to-be-committed] [RISC-V] Improve (1 << N) | C for rv64
Another improvement for generating Zbs instructions.
In this case we're looking at stuff like (1 << N) | C where N varies and C is a
single bit constant.
In this pattern the (1 << N) happens in SImode, but is zero extended out to
DImode before the bit manipulation. The fact that we're modifying a DImode
object in the logical op is important as it means we don't have to worry about
whether or not the resulting value is sign extended from SI to DI.
This has run through Ventana's CI system. I'll wait for it to roll through
pre-commit CI before moving forward.
gcc/
* config/riscv/bitmanip.md ((1 << N) | C): New splitter for IOR/XOR
of a single bit an a DImode object.
Jeff Law [Sun, 16 Jun 2024 03:17:10 +0000 (21:17 -0600)]
[committed] Fix minor SH scan-asm failure after recent IOR->ADD changes
This fixes minor fallout from the IOR->ADD change for rotates that I installed
a little while ago.
Basically the SH backend has a special pattern for setting the T register that
has elements similar to a rotate. With the IOR->ADD change that pattern no
longer matches and we get scan-asm failures.
Fixing isn't a trivial case of just replacing IOR with ADD as the IOR->ADD
change changes some of the simplifications/canonicalizations along the way.
The net is we need a pattern with a slightly different structure. I've
regression tested this on sh3[eb]-linux-gnu and bootstrapped sh4-linux-gnu
(without a regression test).
gcc/
* config/sh/sh.md (neg_zero_extract_4b): New pattern.
Peter Damianov [Mon, 3 Jun 2024 17:07:10 +0000 (10:07 -0700)]
pretty-print: Don't translate escape sequences to windows console API
Modern versions of windows (after windows 10 v1511) support VT100 escape
sequences, so translation for them is not necessary. The translation also
mangles embedded warning documentation links.
gcc/ChangeLog:
* pretty-print.cc (mingw_ansi_fputs): Don't translate escape sequences if
the console has ENABLE_VIRTUAL_TERMINAL_PROCESSING.
Signed-off-by: Peter Damianov <peter0x44@disroot.org>
Peter Damianov [Mon, 3 Jun 2024 17:07:09 +0000 (10:07 -0700)]
diagnostics: Don't hardcode auto_enable_urls to false for mingw hosts
Windows terminal and mintty both have support for link escape sequences, and so
auto_enable_urls shouldn't be hardcoded to false. For older versions of the
windows console, mingw_ansi_fputs's console API translation logic does mangle
these sequences, but there's nothing useful it could do even if this weren't
the case, so check if the ansi escape sequences are supported at all.
conhost.exe doesn't support link escape sequences, but printing them does not
cause any problems.
gcc/ChangeLog:
* diagnostic-color.cc (auto_enable_urls): Don't hardcode to return
false on mingw hosts.
(auto_enable_urls): Return true if console
supports ansi escape sequences.
Signed-off-by: Peter Damianov <peter0x44@disroot.org>
Peter Damianov [Mon, 3 Jun 2024 17:07:08 +0000 (10:07 -0700)]
diagnostics: Enable escape sequence processing on windows consoles
Since windows 10 release v1511, the windows console has had support for VT100
escape sequences. We should try to enable this, and utilize it where possible.
gcc/ChangeLog:
* diagnostic-color.cc (should_colorize): Enable processing of VT100
escape sequences on windows consoles
Signed-off-by: Peter Damianov <peter0x44@disroot.org>
Pan Li [Sat, 15 Jun 2024 12:27:01 +0000 (20:27 +0800)]
RISC-V: Add testcases for vector unsigned SAT_SUB form 2
The previous RISC-V backend .SAT_SUB enabling patch missed the form 2
testcases of vector modes. Aka:
Form 2:
#define DEF_VEC_SAT_U_SUB_FMT_2(T) \
void __attribute__((noinline)) \
vec_sat_u_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
out[i] = (x - y) & (-(T)(x > y)); \
} \
}
This patch would like to make it up to ensure form 2 of .SAT_SUB vector
is covered.
Passed the rv64gcv rvv.exp tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-8.c: New test.
I triggered an ICE on Ubuntu 24.04 when compiling code that uses
function attributes. Looking into the sources shows that we have
a systematic issue in the attribute handling code:
* we determine the length with strlen() (excluding the terminating null)
* we allocate a buffer with this length
* we copy the original string using strcpy() (incl. the terminating null)
To quote the man page of strcpy():
"The programmer is responsible for allocating a destination buffer
large enough, that is, strlen(src) + 1."
The ICE looks like this:
*** buffer overflow detected ***: terminated
xtheadmempair_bench.c:14:1: internal compiler error: Aborted
14 | {
| ^
0xaf3b99 crash_signal
/home/ubuntu/src/gcc/scaleff/gcc/toplev.cc:319
0xe5b957 strcpy
/usr/include/riscv64-linux-gnu/bits/string_fortified.h:79
0xe5b957 riscv_process_target_attr
/home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:339
0xe5baaf riscv_process_target_attr
/home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:314
0xe5bc5f riscv_option_valid_attribute_p(tree_node*, tree_node*, tree_node*, int)
/home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:389
0x6a31e5 handle_target_attribute
/home/ubuntu/src/gcc/scaleff/gcc/c-family/c-attribs.cc:5915
0x5d3a07 decl_attributes(tree_node**, tree_node*, int, tree_node*)
/home/ubuntu/src/gcc/scaleff/gcc/attribs.cc:900
0x5db403 c_decl_attributes
/home/ubuntu/src/gcc/scaleff/gcc/c/c-decl.cc:5501
0x5e8965 start_function(c_declspecs*, c_declarator*, tree_node*)
/home/ubuntu/src/gcc/scaleff/gcc/c/c-decl.cc:10562
0x6318ed c_parser_declaration_or_fndef
/home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:2914
0x63a8ad c_parser_external_declaration
/home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:2048
0x63b219 c_parser_translation_unit
/home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:1902
0x63b219 c_parse_file()
/home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:27277
0x68fec5 c_common_parse_file()
/home/ubuntu/src/gcc/scaleff/gcc/c-family/c-opts.cc:1311
Please submit a full bug report, with preprocessed source (by using -freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
Andrew MacLeod [Fri, 14 Jun 2024 15:01:08 +0000 (11:01 -0400)]
Dont add varying values to gori_on_edge mass calculations.
gori_on_edge will return an ssa_lazy_cache with all contextual ranges
that can be generated by an edge. This patch adjusts it so that
a VARYING range is never added.
* gimple-range-gori.cc (gori_calc_operands): Do not continue nor
add the range when VARYING is produced for an operand.
Andrew MacLeod [Thu, 13 Jun 2024 19:35:55 +0000 (15:35 -0400)]
Add merge facility to ssa_lazy_cache.
The ssa_lazy_cache has a routine to merge a range for an ssa-name with
an existing range in the cache. This adds a method which will merge all
elements of another ssa_lazy_cache.
* gimple-range-cache.cc (ssa_lazy_cache::merge): New.
* gimple-range-cache.h (ssa_lazy_cache::merge): New prototype.
Jakub Jelinek [Fri, 14 Jun 2024 17:57:59 +0000 (19:57 +0200)]
testsuite: Add -Wno-psabi to vshuf-mem.C test
The newly added test FAILs on i686-linux.
On x86_64-linux
make check-g++ RUNTESTFLAGS='--target_board=unix\{-m64,-m32/-msse2,-m32/-mno-sse/-mno-mmx\} dg-torture.exp=vshuf-mem.C'
shows that as well.
The problem is that without SSE2/MMX the vector is passed differently
than normally and so GCC warns about that.
-Wno-psabi is the usual way to shut it up.
Also wonder about the
// { dg-additional-options "-march=z14" { target s390*-*-* } }
line, doesn't that mean the test will FAIL on all pre-z14 HW?
Shouldn't it use some z14_runtime or similar effective target, or
check in main (in that case copied over to g++.target/s390) whether
z14 instructions can be actually used at runtime?
2024-06-14 Jakub Jelinek <jakub@redhat.com>
* g++.dg/torture/vshuf-mem.C: Add -Wno-psabi to dg-options.
Jonathan Wakely [Tue, 11 Jun 2024 14:52:30 +0000 (15:52 +0100)]
libstdc++: Make std::type_info::operator== always_inline for C++23 [PR110572]
Commit r12-6266-g3633cc54284450 implemented P1328 for C++23, making
std::type_info::operator== usable in constant expressions. For targets
such as mingw-w64 where that function was not previously inline, making
it constexpr required making it inline for C++23 and later. For
statically linked programs this can result in multiple definition
errors, because there's a non-inline definition in libstdc++.a as well.
For those targets make it always_inline for C++23, so that there is no
symbol generated for the inline definition, and the non-inline
definition in libstdc++.a will be the only definition.
libstdc++-v3/ChangeLog:
PR libstdc++/110572
* libsupc++/typeinfo (type_info::operator==): Add always_inline
attribute for targets where the ABI requries equality to be
non-inline.
* testsuite/18_support/type_info/110572.cc: New test.
Pan Li [Fri, 14 Jun 2024 02:08:59 +0000 (10:08 +0800)]
RISC-V: Add testcases for scalar unsigned SAT_SUB form 10
After the middle-end support the form 10 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 10 of unsigned .SAT_SUB.
Form 10:
#define SAT_SUB_U_10(T) \
T sat_sub_u_10_##T (T x, T y) \
{ \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return !overflow ? ret : 0; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-37.c: New test.
* gcc.target/riscv/sat_u_sub-38.c: New test.
* gcc.target/riscv/sat_u_sub-39.c: New test.
* gcc.target/riscv/sat_u_sub-40.c: New test.
* gcc.target/riscv/sat_u_sub-run-37.c: New test.
* gcc.target/riscv/sat_u_sub-run-38.c: New test.
* gcc.target/riscv/sat_u_sub-run-39.c: New test.
* gcc.target/riscv/sat_u_sub-run-40.c: New test.
Pan Li [Fri, 14 Jun 2024 02:03:15 +0000 (10:03 +0800)]
RISC-V: Add testcases for scalar unsigned SAT_SUB form 9
After the middle-end support the form 9 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 9 of unsigned .SAT_SUB.
Form 9:
#define SAT_SUB_U_9(T) \
T sat_sub_u_9_##T (T x, T y) \
{ \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return overflow ? 0 : ret; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-33.c: New test.
* gcc.target/riscv/sat_u_sub-34.c: New test.
* gcc.target/riscv/sat_u_sub-35.c: New test.
* gcc.target/riscv/sat_u_sub-36.c: New test.
* gcc.target/riscv/sat_u_sub-run-33.c: New test.
* gcc.target/riscv/sat_u_sub-run-34.c: New test.
* gcc.target/riscv/sat_u_sub-run-35.c: New test.
* gcc.target/riscv/sat_u_sub-run-36.c: New test.
Pan Li [Fri, 14 Jun 2024 01:57:22 +0000 (09:57 +0800)]
RISC-V: Add testcases for scalar unsigned SAT_SUB form 8
After the middle-end support the form 8 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 8 of unsigned .SAT_SUB.
Form 8:
#define SAT_SUB_U_8(T) \
T sat_sub_u_8_##T (T x, T y) \
{ \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return ret & (T)-(!overflow); \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-29.c: New test.
* gcc.target/riscv/sat_u_sub-30.c: New test.
* gcc.target/riscv/sat_u_sub-31.c: New test.
* gcc.target/riscv/sat_u_sub-32.c: New test.
* gcc.target/riscv/sat_u_sub-run-29.c: New test.
* gcc.target/riscv/sat_u_sub-run-30.c: New test.
* gcc.target/riscv/sat_u_sub-run-31.c: New test.
* gcc.target/riscv/sat_u_sub-run-32.c: New test.
Pan Li [Fri, 14 Jun 2024 01:49:22 +0000 (09:49 +0800)]
RISC-V: Add testcases for scalar unsigned SAT_SUB form 7
After the middle-end support the form 7 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 7 of unsigned .SAT_SUB.
Form 7:
#define SAT_SUB_U_7(T) \
T sat_sub_u_7_##T (T x, T y) \
{ \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return ret & (T)(overflow - 1); \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-25.c: New test.
* gcc.target/riscv/sat_u_sub-26.c: New test.
* gcc.target/riscv/sat_u_sub-27.c: New test.
* gcc.target/riscv/sat_u_sub-28.c: New test.
* gcc.target/riscv/sat_u_sub-run-25.c: New test.
* gcc.target/riscv/sat_u_sub-run-26.c: New test.
* gcc.target/riscv/sat_u_sub-run-27.c: New test.
* gcc.target/riscv/sat_u_sub-run-28.c: New test.
Pan Li [Thu, 13 Jun 2024 15:05:00 +0000 (23:05 +0800)]
RISC-V: Add testcases for scalar unsigned SAT_SUB form 6
After the middle-end support the form 6 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 6 of unsigned .SAT_SUB.
Form 6:
#define SAT_SUB_U_6(T) \
T sat_sub_u_6_##T (T x, T y) \
{ \
return x <= y ? 0 : x - y; \
}
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-21.c: New test.
* gcc.target/riscv/sat_u_sub-22.c: New test.
* gcc.target/riscv/sat_u_sub-23.c: New test.
* gcc.target/riscv/sat_u_sub-24.c: New test.
* gcc.target/riscv/sat_u_sub-run-21.c: New test.
* gcc.target/riscv/sat_u_sub-run-22.c: New test.
* gcc.target/riscv/sat_u_sub-run-23.c: New test.
* gcc.target/riscv/sat_u_sub-run-24.c: New test.
Pan Li [Thu, 13 Jun 2024 14:43:31 +0000 (22:43 +0800)]
RISC-V: Add testcases for scalar unsigned SAT_SUB form 5
After the middle-end support the form 5 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 5 of unsigned .SAT_SUB.
Form 5:
#define SAT_SUB_U_5(T) \
T sat_sub_u_5_##T (T x, T y) \
{ \
return x < y ? 0 : x - y; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-17.c: New test.
* gcc.target/riscv/sat_u_sub-18.c: New test.
* gcc.target/riscv/sat_u_sub-19.c: New test.
* gcc.target/riscv/sat_u_sub-20.c: New test.
* gcc.target/riscv/sat_u_sub-run-17.c: New test.
* gcc.target/riscv/sat_u_sub-run-18.c: New test.
* gcc.target/riscv/sat_u_sub-run-19.c: New test.
* gcc.target/riscv/sat_u_sub-run-20.c: New test.
Pan Li [Thu, 13 Jun 2024 14:35:21 +0000 (22:35 +0800)]
RISC-V: Add testcases for scalar unsigned SAT_SUB form 4
After the middle-end support the form 4 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 4 of unsigned .SAT_SUB.
Form 4:
#define SAT_SUB_U_4(T) \
T sat_sub_u_4_##T (T x, T y) \
{ \
return x >= y ? x - y : 0; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-13.c: New test.
* gcc.target/riscv/sat_u_sub-14.c: New test.
* gcc.target/riscv/sat_u_sub-15.c: New test.
* gcc.target/riscv/sat_u_sub-16.c: New test.
* gcc.target/riscv/sat_u_sub-run-13.c: New test.
* gcc.target/riscv/sat_u_sub-run-14.c: New test.
* gcc.target/riscv/sat_u_sub-run-15.c: New test.
* gcc.target/riscv/sat_u_sub-run-16.c: New test.
Pan Li [Thu, 13 Jun 2024 14:06:09 +0000 (22:06 +0800)]
RISC-V: Add testcases for scalar unsigned SAT_SUB form 3
After the middle-end support the form 3 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 3 of unsigned .SAT_SUB.
Form 3:
#define SAT_SUB_U_3(T) \
T sat_sub_u_3_##T (T x, T y) \
{ \
return x > y ? x - y : 0; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-10.c: New test.
* gcc.target/riscv/sat_u_sub-11.c: New test.
* gcc.target/riscv/sat_u_sub-12.c: New test.
* gcc.target/riscv/sat_u_sub-9.c: New test.
* gcc.target/riscv/sat_u_sub-run-10.c: New test.
* gcc.target/riscv/sat_u_sub-run-11.c: New test.
* gcc.target/riscv/sat_u_sub-run-12.c: New test.
* gcc.target/riscv/sat_u_sub-run-9.c: New test.
Pan Li [Wed, 12 Jun 2024 06:28:09 +0000 (14:28 +0800)]
Match: Support more forms for the scalar unsigned .SAT_SUB
After we support the scalar unsigned form 1 and 2, we would like
to introduce more forms include the branch and branchless. There
are forms 3-10 list as below:
Form 3:
#define SAT_SUB_U_3(T) \
T sat_sub_u_3_##T (T x, T y) \
{ \
return x > y ? x - y : 0; \
}
Form 4:
#define SAT_SUB_U_4(T) \
T sat_sub_u_4_##T (T x, T y) \
{ \
return x >= y ? x - y : 0; \
}
Form 5:
#define SAT_SUB_U_5(T) \
T sat_sub_u_5_##T (T x, T y) \
{ \
return x < y ? 0 : x - y; \
}
Form 6:
#define SAT_SUB_U_6(T) \
T sat_sub_u_6_##T (T x, T y) \
{ \
return x <= y ? 0 : x - y; \
}
Form 7:
#define SAT_SUB_U_7(T) \
T sat_sub_u_7_##T (T x, T y) \
{ \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return ret & (T)(overflow - 1); \
}
Form 8:
#define SAT_SUB_U_8(T) \
T sat_sub_u_8_##T (T x, T y) \
{ \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return ret & (T)-(!overflow); \
}
Form 9:
#define SAT_SUB_U_9(T) \
T sat_sub_u_9_##T (T x, T y) \
{ \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return overflow ? 0 : ret; \
}
Form 10:
#define SAT_SUB_U_10(T) \
T sat_sub_u_10_##T (T x, T y) \
{ \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return !overflow ? ret : 0; \
}
The below test suites are passed for this patch:
1. The rv64gcv fully regression test with newlib.
2. The rv64gcv build with glibc.
3. The x86 bootstrap test.
4. The x86 fully regression test.
gcc/ChangeLog:
* match.pd: Add more match for unsigned sat_sub.
* tree-ssa-math-opts.cc (match_unsigned_saturation_sub): Add new
func impl to match phi node for .SAT_SUB.
(math_opts_dom_walker::after_dom_children): Try match .SAT_SUB
for the phi node, MULT_EXPR, BIT_XOR_EXPR and BIT_AND_EXPR.
Jan Beulich [Fri, 14 Jun 2024 11:28:40 +0000 (13:28 +0200)]
configure: adjustments for building with in-tree binutils
For one setting ld_ver in a conditional (no in-tree ld) when it's used,
for x86 at least, in unconditional ways can't be quite right. And then
prefixing relative paths to binaries with ${objdir}/, when ${objdir}
nowadays resolves to just .libs, can at best be a leftover that wasn't
properly cleaned up at some earlier point.
gcc/
* configure.ac: Drop ${objdir}/ from NM and AR. Move setting of
ld_ver out of conditional.
* configure: Re-generate.
Richard Biener [Fri, 14 Jun 2024 09:31:53 +0000 (11:31 +0200)]
Adjust gcc.target/i386/vect-strided-3.c
The following disables SSE4 instead of just AVX to avoid
pextrq being used, confusing the assembler scanning. This
avoids the reported failure with -march=cascadelake but adds
a FAIL for -march=cascadelake -m32 (I've opened PR115487 for that).
* gcc.target/i386/vect-strided-3.c: Disable SSE4 instead of AVX.
Richard Biener [Thu, 13 Jun 2024 12:42:25 +0000 (14:42 +0200)]
Support single def-use cycle optimization for SLP reduction vectorization
We can at least mimic single def-use cycle optimization when doing
single-lane SLP reductions and that's required to avoid regressing
compared to non-SLP.
* tree-vect-loop.cc (vectorizable_reduction): Allow
single-def-use cycles with SLP.
(vect_transform_reduction): Handle SLP single def-use cycles.
(vect_transform_cycle_phi): Likewise.
Pan Li [Fri, 14 Jun 2024 06:54:22 +0000 (14:54 +0800)]
RISC-V: Bugfix vec_extract v mode iterator restriction mismatch
We have vec_extract pattern which takes ZVFHMIN as the mode
iterator of the V mode. Aka VF_ZVFHMIN iterator. But it will
expand to pred_extract_first pattern which takes the ZVFH as the mode
iterator of the V mode. AKa VF. The mismatch will result in one ICE
similar as below:
Eric Botcazou [Mon, 29 Apr 2024 07:48:48 +0000 (09:48 +0200)]
ada: Fix return mechanism reported by -gnatRm
The return mechanism of functions is reported when the -gnatRm switch is
specified, but it is incorrect when the result type is not a by-reference
type in the language sense but is nevertheless returned by reference.
gcc/ada/
* gcc-interface/decl.cc: Include function.h.
(gnat_to_gnu_param): Minor comment tweaks.
(gnat_to_gnu_subprog_type): Take into account the default for the
computation of the return mechanism. Give a warning if a by-copy
specified mechanism cannot be honored.
Entities of kind E_Subprogram_Body, used on bodies of subprograms for
which there is a separate declaration, have been added in the entities
linked from a scope in order to get the representation information on
their enclosed object and type declarations. Skip these entities in gigi.
gcc/ada/
* gcc-interface/trans.cc (elaborate_all_entities_for_package)
(process_freeze_entity): Skip entities of kind E_Subprogram_Body.
Eric Botcazou [Mon, 29 Apr 2024 07:15:13 +0000 (09:15 +0200)]
ada: Do not create null GCC thunks
This prevents Gigi from creating null GCC thunks, i.e. thunks that have all
their internal parameters set to zero, replacing them with aliases. They
can arise in degenerate cases and null thunks would trip on an assertion in
former_thunk_p when they are later optimized.
gcc/ada/
PR ada/109817
* gcc-interface/trans.cc (maybe_make_gnu_thunk): Create an alias
instead of a null thunk.
Eric Botcazou [Mon, 13 May 2024 14:15:10 +0000 (16:15 +0200)]
ada: Fix parts of classification of aspects
Many aspects are (correctly) marked as GNAT-specific but nevertheless not
listed in the Implementation_Defined_Aspect array, so this aligns the two
sides and also removes Default_Initial_Condition and Object_Size from the
list, since they are defined in Ada 2022.
This also moves No_Controlled_Parts and No_Task_Parts to the subclass of
boolean aspects, and completes the list of nonoverridable aspects defined
in Ada 2022.
gcc/ada/
* aspects.ads (Aspect_Id): Alphabetize, remove the GNAT tag from
Default_Initial_Condition and Object_Size, move No_Controlled_Parts
and No_Task_Parts to boolean subclass.
(Nonoverridable_Aspect_Id): Add missing Ada 2022 aspects.
(Implementation_Defined_Aspect): Add all missing aspects, remove
Max_Entry_Queue_Length and Object_Size
(Aspect_Argument): Remove specific entries for No_Controlled_Parts
and No_Task_Parts, list boolean aspects last.
(Is_Representation_Aspect ): Move boolean aspects last.
(Aspect_Names): Alphabetize.
* sem_ch13.adb (Analyze_Aspect_Disable_Controlled): Adjust.
(Analyze_Aspect_Specifications): Move around processing for
No_Controlled_Parts and No_Task_Parts.
(Check_Aspect_At_Freeze_Point): Remove specific entries for
No_Controlled_Parts and No_Task_Parts
Steve Baird [Wed, 8 May 2024 00:04:28 +0000 (17:04 -0700)]
ada: Bad tree built for Obj.Discrim_Dep_Component'Loop_Entry in assertion
The Etype for an N_Selected_Component node usually should not match the Etype
of the referenced component if the component is subject to a
discriminant-dependent constraint. Instead Build_Actual_Subtype_Of_Component
should be called. Fix a case where this rule was not being followed (because
B_A_S_O_C is not called during preanalysis of a component selection), resulting
in a tree that confused CodePeer because the subtype was wrong.
gcc/ada/
* exp_attr.adb
(Expand_Loop_Entry_Attribute):
Ensure that Etype of the saved expression is set correctly.
Jerome Guitton [Fri, 10 May 2024 13:16:17 +0000 (13:16 +0000)]
ada: Simplify handling of VxWorks-specific error codes for ENOENT
These error codes were defined on older versions of VxWorks (5, 6, 7
SR0540) and now they are either not defined or they fallback to
ENOENT. To handle these cases without using complex tests against
vxworks versions, leverage on __has_include and provide a fallback to
ENOENT if these error codes are not defined.
gcc/ada/
* sysdep.c (S_dosFsLib_FILE_NOT_FOUND, S_nfsLib_NFSERR_NOENT):
New macros, falback to ENOENT when not already defined.
(__gnat_is_file_not_found_error): Use these new macros to remove
tests against VxWorks flavors.
Justin Squirek [Thu, 9 May 2024 05:04:03 +0000 (05:04 +0000)]
ada: Add prototype for mutably tagged types
This patch implements mutably tagged types via the new Size'Class aspect.
gcc/ada/
* doc/gnat_rm/gnat_language_extensions.rst: Add documentation for
mutably tagged type feature.
* aspects.ads: Add registration for 'Size'Class.
* einfo.ads: Add documentation for new components
Class_Wide_Equivalent_Type and Is_Mutably_Tagged_Type.
* exp_aggr.adb (Gen_Assign): Assume associated mutably tagged type
when class-wide equivalent type is encountered.
(Contains_Mutably_Tagged_Type): New subprogram.
(Convert_To_Positional): Assume associated mutably tagged type
when class-wide equivalent type is encountered.
(Is_Static_Element): Assume associated mutably tagged type when
class-wide equivalent type is encountered.
(Expand_Array_Aggregate): Assume associated mutably tagged type
when class-wide equivalent type is encountered.
(Expand_Record_Aggregate): Force mutably tagged records to be
expanded into assignments.
* exp_ch3.adb (Build_Array_Init_Proc): Assume associated mutably
tagged type when class-wide equivalent type is encountered.
(Simple_Initialization_OK): Disallow simple initialization for
class-wide equivalent types.
(Build_Init_Statements): Assume associated mutably tagged type
when class-wide equivalent type is encountered.
(Expand_Freeze_Array_Type): Ignore building of record init procs
for mutably tagged types.
(Expand_N_Full_Type_Declaration): Replace mutably tagged type
declarations with their associated class-wide equivalent types.
(Default_Initialize_Object): Add special handling for mutably
tagged types.
* exp_ch4.adb (Expand_N_Allocator): Add initialization for mutably
tagged types.
(Expand_Record_Equality): Generate mutably tagged unchecked
conversions.
* exp_ch5.adb (Expand_N_Assignment_Statement): Generate a special
assignment case for class-wide equivalent types which does tag
assignments and ignores certain checks.
* exp_ch6.adb (Expand_Call_Helper): Propagate constrained extra
formal actuals for mutably tagged types.
* exp_ch7.adb (Make_Init_Call): Handle mutably tagged type
initialization.
* exp_util.adb (Make_CW_Equivalent_Type): Modify to handle mutably
tagged objects which contain no initialization expression.
(Make_Subtype_From_Expr): Modify call to Make_CW_Equivalent_Type.
* exp_util.ads (Make_CW_Equivalent_Type): Move declaration from
body to spec.
* freeze.adb (Size_Known): No longer return false automatically
when a class-wide type is encountered.
(Freeze_Entity): Ignore error messages about size not being known
for mutably tagged types.
* gen_il-fields.ads: Register new fields
Class_Wide_Equivalent_Type and Is_Mutably_Tagged_Type.
* gen_il-gen-gen_entities.adb: Register new fields
Class_Wide_Equivalent_Type and Is_Mutably_Tagged_Type for type
entities.
* mutably_tagged.adb, mutably_tagged.ads
(Corresponding_Mutably_Tagged_Type): New subprogram.
(Depends_On_Mutably_Tagged_Ext_Comp): New subprogram.
(Get_Corresponding_Mutably_Tagged_Type_If_Present): New
subprogram.
(Get_Corresponding_Tagged_Type_If_Present): New subprogram.
(Is_Mutably_Tagged_Conversion): New subprogram.
(Is_Mutably_Tagged_CW_Equivalent_Type): New subprogram.
(Make_Mutably_Tagged_Conversion): New subprogram.
(Make_CW_Size_Compile_Check): New subprogram.
(Make_Mutably_Tagged_CW_Check): New subprogram.
* sem_aggr.adb (Resolve_Array_Aggregate): Skip tag checks for
class-wide equivalent types.
(Resolve_Aggr_Expr): Assume associated mutably tagged type when
class-wide equivalent type is encountered.
* sem_attr.adb (Analyze_Attribute): Allow 'Tag on mutably tagged
types.
(Resolve_Attribute): Detect errors for dependence of mutably
tagged extension type component.
* sem_ch12.adb (Instantiate_Object): Detect errors for dependence
of mutably tagged extension type component.
* sem_ch13.adb (Analyze_One_Aspect): Propagate 'Size'Class to
class-wide type.
(Analyze_Attribute_Definition_Clause): Add handling of 'Size'Class
by generating class-wide equivalent types and checking for illegal
uses.
* sem_ch2.adb (Analyze_Identifier): Generate unchecked conversion
for class-wide equivalent types.
* sem_ch3.adb (Analyze_Component_Declaration): Avoid unconstrained
errors on mutably tagged types.
(Analyze_Object_Declaration): Rewrite declarations of mutably
tagged types to use class-wide equivalent types.
(Array_Type_Declaration): Modify arrays of mutably tagged types to
use their corresponding class-wide equivalent types.
(Derived_Type_Declaration): Add various checks for mutably tagged
derived types.
* sem_ch4.adb (Analyze_Allocator): Replace reference to mutably
tagged type with cooresponding tagged type.
(Process_Indexed_Component): Generate unchecked conversion for
class-wide equivalent type.
(Analyze_One_Call): Generate unchecked conversion for class-wide
equivalent types.
(Analyze_Selected_Component): Assume reference to class-wide
equivalent type is associated mutably tagged type.
(Analyze_Type_Conversion): Generate unchecked conversion for
class-wide equivalent type.
* sem_ch5.adb (Analyze_Assignment): Assume associated mutably
tagged type when class-wide equivalent type is encountered.
(Analyze_Iterator_Specification): Detect errors for dependence of
mutably tagged extension type component.
* sem_ch6.adb (Create_Extra_Formals): Add code to generate extra
formal for mutably tagged types to signal if they are constrained.
* sem_ch8.adb (Analyze_Object_Renaming): Detect error on renaming
of mutably tagged extension type component.
(Analyze_Renaming_Primitive_Operation): Detect error on renaming
of mutably tagged extension type component.
* sem_res.adb (Resolve_Actuals): Allow class-wide arguments on
class-wide equivalent types.
(Valid_Conversion): Assume associated mutably tagged type when
class-wide equivalent type is encountered.
* sem_util.adb (Is_Fully_Initialized_Type): Flag mutably tagged
types as fully initialized.
(Needs_Simple_Initalization): Flag class-wide equivalent types as
needing initialization.
* gnat_rm.texi: Regenerate.
* gcc-interface/Make-lang.in: Add entry for mutably_tagged.o.
Justin Squirek [Fri, 10 May 2024 11:18:01 +0000 (11:18 +0000)]
ada: Crash checking accessibility level on private type
This patch fixes an issue in the compiler whereby calculating a static
accessibility level on a private type with an access discriminant resulted
in a compile time crash when No_Dynamic_Accessibility_Checks is enabled.
gcc/ada/
* accessibility.adb:
(Accessibility_Level): Replace call Get_Full_View with call to
Full_View since Get_Full_View only works with incomplete types.
Eric Botcazou [Fri, 10 May 2024 15:11:24 +0000 (17:11 +0200)]
ada: Minor tweaks to processing of Aggregate aspect
The main one is to give the error for Aggregate applied to array types from
Analyze_Aspects_At_Freeze_Point instead of Check_Aspect_At_Freeze_Point, as
for the other aspects. The message is also changed to be more direct.
gcc/ada/
* aspects.ads (Operational_Aspect): Alphabetize.
* sem_ch13.ads (Analyze_Aspects_At_Freeze_Point): Fix description.
* sem_ch13.adb (Analyze_Aspects_At_Freeze_Point) <Aggregate>: Give
the error for array types here instead of...
(Analyze_Aspect_Specifications) <Aggregate>: Adjust comment.
(Check_Aspect_At_Freeze_Point) <Aggregate>: ...here.
Javier Miranda [Thu, 9 May 2024 21:48:18 +0000 (21:48 +0000)]
ada: Missing initialization of multidimensional array using sliding
When a multidimensional array is initialized with an array
aggregate, and inner dimensions of the array are initialized
with array subaggregates using sliding, the code generated
by the compiler does not initialize the inner dimensions
of the array.
gcc/ada/
* exp_aggr.adb (Must_Slide): Add missing support for
multidimensional arrays.
Eric Botcazou [Thu, 9 May 2024 18:18:57 +0000 (20:18 +0200)]
ada: Couple of small cleanups in semantic analysis of aspects
The first cleanup is to expose a consistent interface from Sem_Ch13 for the
analysis of aspects at various points of the program. The second cleanup is
to fix the awkward implementation of the analysis of the specification for
the aspects Stable_Properties, Designated_Storage_Model, Storage_Model_Type
and Aggregate, which are always delayed, and the incorrect placement of that
of the aspect Local_Restrictions, which is never delayed.
gcc/ada/
* freeze.adb (Freeze_All): Call Check_Aspects_At_End_Of_Declarations
to perform the visibility check for aspects.
* sem_ch13.ads (Check_Aspects_At_End_Of_Declarations): Declare.
(Check_Aspect_At_Freeze_Point): Move to...
(Check_Aspect_At_End_Of_Declarations): Move to...
* sem_ch13.adb (Check_Aspect_At_Freeze_Point): ...here.
(Check_Aspect_At_End_Of_Declarations): ...here.
(Analyze_Aspect_Specifications): Remove peculiar processing for
Stable_Properties, Designated_Storage_Model, Storage_Model_Type
and Aggregate. Move that of Local_Restrictions around. Reset
Aitem at the beginning of the loop for each aspect.
(Check_Aspects_At_End_Of_Declarations): New procedure.
Richard Biener [Fri, 14 Jun 2024 05:54:15 +0000 (07:54 +0200)]
Fix fallout of peeling for gap improvements
The following hopefully addresses an observed bootstrap issue on aarch64
where maybe-uninit diagnostics occur. It also fixes bogus napkin math
from myself when I was confusing rounded up size of a single access
with rounded up size of the group accessed in a single scalar iteration.
So the following puts in a correctness check, leaving a set of peeling
for gaps as insufficient. This could be rectified by splitting the
last load into multiple ones but I'm leaving this for a followup, better
quickly fix the reported wrong-code.
* tree-vect-stmts.cc (get_group_load_store_type): Do not
re-use poly-int remain but re-compute with non-poly values.
Verify the shortened load is good enough to be covered with
a single scalar gap iteration before accepting it.
* gcc.dg/vect/pr115385.c: Enable AVX2 if available.
* config/i386/i386.cc (ix86_rtx_costs): Adjust rtx_cost for
pternlog_operand under AVX512, also adjust VEC_DUPLICATE
according since vec_dup:mem can't be that cheap.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx2-pr98461.c: Scan either notl or
vpternlog.
* gcc.target/i386/avx512f-pr96891-3.c: Also scan for inversed
condition.
* gcc.target/i386/avx512f-vpternlogd-3.c: Adjust vpternlog
number to 673.
* gcc.target/i386/avx512f-vpternlogd-4.c: Ditto.
* gcc.target/i386/avx512f-vpternlogd-5.c: Ditto.
* gcc.target/i386/sse2-v1ti-vne.c: Add -mno-avx512f.
liuhongt [Mon, 3 Jun 2024 02:38:19 +0000 (10:38 +0800)]
Remove one_if_conv for latest Intel processors.
The tune is added by PR79390 for SciMark2 on Broadwell.
For latest GCC, with and without the -mtune-ctrl=^one_if_conv_insn.
GCC will generate the same binary for SciMark2. And for SPEC2017,
there's no big impact for SKX/CLX/ICX, and small improvements on SPR
and later.
Roger Sayle [Fri, 14 Jun 2024 05:29:27 +0000 (06:29 +0100)]
i386: More use of m{32,64}bcst addressing modes with ternlog.
This patch makes more use of m32bcst and m64bcst addressing modes in
ix86_expand_ternlog. Previously, the i386 backend would only consider
using a m32bcst if the inner mode of the vector was 32-bits, or using
m64bcst if the inner mode was 64-bits. For ternlog (and other logic
operations) this is a strange restriction, as how the same constant
is materialized is dependent upon the mode it is used/operated on.
Hence, the V16QI constant {2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2} wouldn't
use m??bcst, but (V4SI){0x02020202,0x02020202,0x02020202,0x02020202}
which has the same bit pattern would. This can optimized by (re)checking
whether a CONST_VECTOR can be broadcast from memory after casting it
to VxSI (or for m64bst to VxDI) where x has the appropriate vector size.
Taking the test case from pr115407:
__attribute__((__vector_size__(64))) char v;
void foo() {
v = v | v << 7;
}
Compiled with -O2 -mcmodel=large -mavx512bw
GCC 14 generates a 64-byte (512-bit) load from the constant pool:
2024-06-14 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/i386/i386-expand.cc (ix86_expand_ternlog): Try performing
logic operation in a different vector mode if that enables use of
a 32-bit or 64-bit broadcast addressing mode.
gcc/testsuite/ChangeLog
* gcc.target/i386/pr115407.c: New test case.
Andrew Pinski [Thu, 13 Jun 2024 20:07:10 +0000 (13:07 -0700)]
expand: constify sepops operand to expand_expr_real_2 and expand_widen_pattern_expr [PR113212]
While working on an expand patch back in January I noticed that
the first argument (of sepops type) of expand_expr_real_2 could be
constified as it was not to be touched by the function (nor should it be).
There is code in internal-fn.cc that depends on expand_expr_real_2 not touching
the ops argument so constification makes this more obvious.
Bootstrapped and tested on x86_64-linux-gnu with no regressions.
gcc/ChangeLog:
PR middle-end/113212
* expr.h (const_seqpops): New typedef.
(expand_expr_real_2): Constify the first argument.
* optabs.cc (expand_widen_pattern_expr): Likewise.
* optabs.h (expand_widen_pattern_expr): Likewise.
* expr.cc (expand_expr_real_2): Likewise
(do_store_flag): Likewise. Remove incorrect store to ops->code.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
projects / thirdparty / gcc.git / log
