Bill Schmidt [Mon, 8 Jan 2018 23:08:34 +0000 (23:08 +0000)]
re PR target/83677 (PPC: The xxpermr instruction is not generated correctly)
[gcc]
2018-01-08 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR target/83677
* config/rs6000/altivec.md (*altivec_vpermr_<mode>_internal):
Reverse order of second and third operands in first alternative.
* config/rs6000/rs6000.c (rs6000_expand_vector_set): Reverse order
of first and second elements in UNSPEC_VPERMR vector.
(altivec_expand_vec_perm_le): Likewise.
[gcc/testsuite]
2018-01-08 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR target/83677
* gcc.target/powerpc/pr83677.c: New file.
quad-float128.h (IBM128_TYPE): Explicitly use __ibm128, instead of trying to use long double.
2018-01-08 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/quad-float128.h (IBM128_TYPE): Explicitly use
__ibm128, instead of trying to use long double.
(CVT_FLOAT128_TO_IBM128): Use TFtype instead of __float128 to
accomidate -mabi=ieeelongdouble multilibs.
(CVT_IBM128_TO_FLOAT128): Likewise.
* config/rs6000/ibm-ldouble.c (IBM128_TYPE): New macro to define
the appropriate IBM extended double type.
(__gcc_qadd): Change all occurances of long double to IBM128_TYPE.
(__gcc_qsub): Likewise.
(__gcc_qmul): Likewise.
(__gcc_qdiv): Likewise.
(pack_ldouble): Likewise.
(__gcc_qneg): Likewise.
(__gcc_qeq): Likewise.
(__gcc_qne): Likewise.
(__gcc_qge): Likewise.
(__gcc_qle): Likewise.
(__gcc_stoq): Likewise.
(__gcc_dtoq): Likewise.
(__gcc_itoq): Likewise.
(__gcc_utoq): Likewise.
(__gcc_qunord): Likewise.
* config/rs6000/_mulkc3.c (toplevel): Include soft-fp.h and
quad-float128.h for the definitions.
(COPYSIGN): Use the f128 version instead of the q version.
(INFINITY): Likewise.
(__mulkc3): Use TFmode/TCmode for float128 scalar/complex types.
* config/rs6000/_divkc3.c (toplevel): Include soft-fp.h and
quad-float128.h for the definitions.
(COPYSIGN): Use the f128 version instead of the q version.
(INFINITY): Likewise.
(FABS): Likewise.
(__divkc3): Use TFmode/TCmode for float128 scalar/complex types.
* config/rs6000/extendkftf2-sw.c (__extendkftf2_sw): Likewise.
* config/rs6000/trunctfkf2-sw.c (__trunctfkf2_sw): Likewise.
quad-float128.h (IBM128_TYPE): Explicitly use __ibm128, instead of trying to use long double.
2018-01-08 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/quad-float128.h (IBM128_TYPE): Explicitly use
__ibm128, instead of trying to use long double.
(CVT_FLOAT128_TO_IBM128): Use TFtype instead of __float128 to
accomidate -mabi=ieeelongdouble multilibs.
(CVT_IBM128_TO_FLOAT128): Likewise.
* config/rs6000/ibm-ldouble.c (IBM128_TYPE): New macro to define
the appropriate IBM extended double type.
(__gcc_qadd): Change all occurances of long double to IBM128_TYPE.
(__gcc_qsub): Likewise.
(__gcc_qmul): Likewise.
(__gcc_qdiv): Likewise.
(pack_ldouble): Likewise.
(__gcc_qneg): Likewise.
(__gcc_qeq): Likewise.
(__gcc_qne): Likewise.
(__gcc_qge): Likewise.
(__gcc_qle): Likewise.
(__gcc_stoq): Likewise.
(__gcc_dtoq): Likewise.
(__gcc_itoq): Likewise.
(__gcc_utoq): Likewise.
(__gcc_qunord): Likewise.
* config/rs6000/_mulkc3.c (toplevel): Include soft-fp.h and
quad-float128.h for the definitions.
(COPYSIGN): Use the f128 version instead of the q version.
(INFINITY): Likewise.
(__mulkc3): Use TFmode/TCmode for float128 scalar/complex types.
* config/rs6000/_divkc3.c (toplevel): Include soft-fp.h and
quad-float128.h for the definitions.
(COPYSIGN): Use the f128 version instead of the q version.
(INFINITY): Likewise.
(FABS): Likewise.
(__divkc3): Use TFmode/TCmode for float128 scalar/complex types.
* config/rs6000/extendkftf2-sw.c (__extendkftf2_sw): Likewise.
* config/rs6000/trunctfkf2-sw.c (__trunctfkf2_sw): Likewise.
* config/rs6000/rs6000-string.c (do_load_for_compare_from_addr): New
function.
(do_ifelse): New function.
(do_isel): New function.
(do_sub3): New function.
(do_add3): New function.
(do_load_mask_compare): New function.
(do_overlap_load_compare): New function.
(expand_compare_loop): New function.
(expand_block_compare): Call expand_compare_loop() when appropriate.
* config/rs6000/rs6000.opt (-mblock-compare-inline-limit): Change
option description.
(-mblock-compare-inline-loop-limit): New option.
Jeff Law [Mon, 8 Jan 2018 18:20:21 +0000 (11:20 -0700)]
re PR rtl-optimization/81308 (ICE in calc_dfs_tree, at dominance.c:458)
PR rtl-optimizatin/81308
* tree-switch-conversion.c (cfg_altered): New file scoped static.
(process_switch): If group_case_labels makes a change, then set
cfg_altered.
(pass_convert_switch::execute): If a switch is converted, then
set cfg_altered. Return TODO_cfg_cleanup if cfg_altered is true.
PR rtl-optimizatin/81308
* g++.dg/pr81308-1.C: New test.
* g++.dg/pr81308-2.C: New test.
Aaron Sawdey [Mon, 8 Jan 2018 16:35:31 +0000 (10:35 -0600)]
rs6000.c (rs6000_legitimate_combined_insn): Updated with the new names of the branch decrement patterns...
* config/rs6000/rs6000.c (rs6000_legitimate_combined_insn): Updated
with the new names of the branch decrement patterns, and added the
names of the branch decrement conditional patterns.
Vidya Praveen [Mon, 8 Jan 2018 16:24:49 +0000 (16:24 +0000)]
PR target/83663 - Revert r255946
gcc/
2018-01-08 Vidya Praveen <vidyapraveen@arm.com>
PR target/83663 - Revert r255946
* config/aarch64/aarch64.c (aarch64_expand_vector_init): Modify code
generation for cases where splatting a value is not useful.
* simplify-rtx.c (simplify_ternary_operation): Simplify vec_merge
across a vec_duplicate and a paradoxical subreg forming a vector
mode to a vec_concat.
Kyrylo Tkachov [Mon, 8 Jan 2018 15:15:08 +0000 (15:15 +0000)]
[arm] Add -march=armv8.3-a and dotprod multilib selection rules
We don't have the t-aprofile, t-multilib and t-arm-elf mapping
rules for multilibs when using the variants of -march=armv8.3-a
and the dotproduct extension.
This patch adds them. -march=armv8.3-a behaves in the same
way as -march=armv8.2-a in this regard.
Bootstrapped and tested with the aprofile multilib list.
Checked that --print-multi-directory gives sensible results
with armv8.3-a options and extensions.
I've also added some armv8.3-a, fp16 and dotprod
combination tests to multilib.exp
* config/rs6000/rs6000.md (cceq_ior_compare): Remove * so I can use it
to generate rtl.
(cceq_ior_compare_complement): Give it a name so I can use it, and
change boolean_or_operator predicate to boolean_operator so it can
be used to generate a crand.
(eqne): New code iterator.
(bd/bd_neg): New code_attrs.
(<bd>_<mode>): New name for ctr<mode>_internal[12] now combined into
a single define_insn.
(<bd>tf_<mode>): A new insn pattern for the conditional form branch
decrement (bdnzt/bdnzf/bdzt/bdzf).
* config/rs6000/rs6000.c (rs6000_legitimate_combined_insn): Updated
with the new names of the branch decrement patterns, and added the
names of the branch decrement conditional patterns.
Janne Blomqvist [Mon, 8 Jan 2018 12:12:05 +0000 (14:12 +0200)]
PR 78534 Regression on 32-bit targets
By switching from int to size_t in order to handle larger values,
r256322 introduced a bug that manifested itself on 32-bit
targets. Fixed by using the correct type to store the result of a
next_array_record call.
Regtested on x86_64-pc-linux-gnu and i686-pc-linux-gnu, committed to
trunk as obvious.
libgfortran/ChangeLog:
2018-01-08 Janne Blomqvist <jb@gcc.gnu.org>
PR 78534, bugfix for r256322
* io/transfer.c (next_record_w): Use correct type for return value
of next_array_record.
Paul Thomas [Mon, 8 Jan 2018 11:20:33 +0000 (11:20 +0000)]
re PR fortran/83611 ([PDT] Assignment of parameterized types causes double free error in runtime)
2018-01-08 Paul Thomas <pault@gcc.gnu.org>
PR fortran/83611
* decl.c (gfc_get_pdt_instance): If parameterized arrays have
an initializer, convert the kind parameters and add to the
component if the instance.
* trans-array.c (structure_alloc_comps): Add 'is_pdt_type' and
use it with case COPY_ALLOC_COMP. Call 'duplicate_allocatable'
for parameterized arrays. Clean up typos in comments. Convert
parameterized array initializers and copy into the array.
* trans-expr.c (gfc_trans_scalar_assign): Do a deep copy for
parameterized types.
*trans-stmt.c (trans_associate_var): Deallocate associate vars
as necessary, when they are PDT function results for example.
PR fortran/83731
* trans-array.c (structure_alloc_comps): Only compare len parms
when they are declared explicitly.
2018-01-08 Paul Thomas <pault@gcc.gnu.org>
PR fortran/83611
* gfortran.dg/pdt_15.f03 : Bump count of 'n.data = 0B' to 8.
* gfortran.dg/pdt_26.f03 : Bump count of '_malloc' to 9.
* gfortran.dg/pdt_27.f03 : New test.
PR fortran/83731
* gfortran.dg/pdt_28.f03 : New test.
Janne Blomqvist [Sun, 7 Jan 2018 10:17:52 +0000 (12:17 +0200)]
PR 78534, 83704 Handle large formatted I/O
In order to handle large characters when doing formatted I/O, use
size_t and ptrdiff_t for lengths. Compared to the previous patch,
based on discussions on IRC use size_t for sizes that don't need to be
negative rather than ptrdiff_t everywhere.
Regtested on x86_64-pc-linux-gnu, approved as part of the PR 78534
approval, committed to trunk.
libgfortran/ChangeLog:
2018-01-07 Janne Blomqvist <jb@gcc.gnu.org>
PR fortran/78534
PR fortran/83704
* io/fbuf.c (fbuf_init): Use size_t instead of int for length.
(fbuf_debug): Convert debug output to unsigned long.
(fbuf_reset): Use ptrdiff_t for return value.
(fbuf_alloc): Use size_t for length argument.
(fbuf_flush): Handle large buffers.
(fbuf_flush_list): Likewise.
(fbuf_seek): Use ptrdiff_t for offset and return value.
(fbuf_read): Use size_t for length argument.
(fbuf_getc_refill): Use size_t to match fbuf_read.
* io/fbuf.h (struct fbuf): Use size_t for lengths.
(fbuf_init): Use size_t instead of int for length.
(fbuf_reset): Use ptrdiff_t for return value.
(fbuf_alloc): Use size_t for length argument.
(fbuf_seek): Use ptrdiff_t for offset and return value.
(fbuf_read): Use size_t for length argument.
* io/io.h (read_block_form): Likewise.
(read_block_form4): Likewise.
(write_block): Likewise.
(read_a): Likewise.
(read_a_char4): Likewise.
(read_x): Likewise.
(write_a): Likewise.
(write_a_char4): Likewise.
* io/list_read.c (list_formatted_read_scalar): Use size_t to
handle large buffers.
* io/read.c (read_l): Likewise.
(read_utf8): Likewise.
(read_utf8_char1): Likewise.
(read_default_char1): Likewise.
(read_utf8_char4): Likewise.
(read_default_char4): Likewise.
(read_a): Likewise.
(read_a_char4): Likewise.
(eat_leading_spaces): Likewise.
(next_char): Likewise.
(read_decimal): Likewise.
(read_radix): Likewise.
(read_f): Likewise.
(read_x): Likewise.
* io/transfer.c (read_sf_internal): Likewise.
(read_sf): Likewise.
(read_block_form): Likewise.
(read_block_form4): Likewise.
(write_block): Likewise.
(formatted_transfer_scalar_write): Likewise.
(next_record_w): Likewise.
* io/unix.c (mem_alloc_r): Likewise.
(mem_alloc_r4): Likewise.
(mem_alloc_w): Likewise.
(mem_alloc_w4): Likewise.
(mem_read): Likewise.
(mem_read4): Likewise.
(mem_write): Likewise.
(mem_write4): Likewise.
(open_internal): Likewise.
(open_internal4): Likewise.
* io/unix.h (open_internal): Likewise.
(open_internal4): Likewise.
(mem_alloc_w): Likewise.
(mem_alloc_r): Likewise.
(mem_alloc_w4): Likewise.
(mem_alloc_r4): Likewise.
* io/write.c (write_check_cc): Likewise.
(write_cc): Likewise.
(write_a): Likewise.
(write_a_char4): Likewise.
Aldy Hernandez [Sun, 7 Jan 2018 05:31:51 +0000 (05:31 +0000)]
re PR middle-end/81897 (spurious -Wmaybe-uninitialized warning)
PR middle-end/81897
* tree-ssa-uninit.c (compute_control_dep_chain): Do not bail on
basic blocks with a small number of successors.
(convert_control_dep_chain_into_preds): Improve handling of
forwarder blocks.
(dump_predicates): Split apart into...
(dump_pred_chain): ...here...
(dump_pred_info): ...and here.
(can_one_predicate_be_invalidated_p): Add debugging printfs.
(can_chain_union_be_invalidated_p): Improve check for invalidation
of paths.
(uninit_uses_cannot_happen): Avoid unnecessary if
convert_control_dep_chain_into_preds yielded nothing.
PR middle-end/81897
* gcc.dg/uninit-pr81897.c: New test.
Martin Sebor [Sun, 7 Jan 2018 04:19:35 +0000 (04:19 +0000)]
re PR tree-optimization/83640 (ICE in generic_overlap, at gimple-ssa-warn-restrict.c:814)
2018-01-06 Martin Sebor <msebor@redhat.com>
PR tree-optimization/83640
* gimple-ssa-warn-restrict.c (builtin_access::builtin_access): Avoid
subtracting negative offset from size.
(builtin_access::overlap): Adjust offset bounds of the access to fall
within the size of the object if possible.
PR tree-optimization/83640
* gcc.dg/Wrestrict-6.c: New test.
* gcc.dg/pr83640.c: New test.
re PR middle-end/83699 (Many 64-bit SPARC gcc.dg/vect tests FAIL)
PR rtl-optimization/83699
* expmed.c (extract_bit_field_1): Restrict the vector usage of
extract_bit_field_as_subreg to cases in which the extracted
value is also a vector.
LRA has code to try to prevent cycling, by avoiding reloads that
look too similar to the instruction being reloaded. E.g. if we
have a R<-C move for some constant C, reloading the source with
another R<-C move is unlikely to be a good idea.
However, this safeguard unnecessarily triggered in tests like
the one in the patch. We started with instructions like:
where r459 didn't get allocated a register and is equivalent to
constant x00. LRA would then handle it like this:
Changing pseudo 459 in operand 1 of insn 12 on equiv `x00'
1 Non-pseudo reload: reject+=2
1 Non input pseudo reload: reject++
-------> Cycle danger: overall += LRA_MAX_REJECT
alt=0,overall=609,losers=1,rld_nregs=1
[...]
alt=13,overall=9,losers=1,rld_nregs=1
[...]
Choosing alt 13 in insn 12: (0) r (1) w {*movdi_aarch64}
In other words, to avoid loading the constant x00 into another GPR,
LRA decided instead to move it into a floating-point register,
then move that floating-point register into x0:
Creating newreg=630, assigning class FP_REGS to r630
Set class ALL_REGS for r631
12: x0:DI=r630:DI
REG_EQUAL `x00'
Inserting insn reload before:
815: r631:DI=high(`x00')
816: r630:DI=r631:DI+low(`x00')
REG_EQUAL `x00'
That's inefficient and doesn't really help to resolve a cycling
problem, since the r630 destination of 816 needs to be reloaded into
a GPR anyway.
The cycling check already had an exception for source values that are
the result of an elimination. This patch extends it to include the
result of equivalence substitution.
2018-01-06 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* lra-constraints.c (process_alt_operands): Test for the equivalence
substitutions when detecting a possible reload cycle.
gcc/testsuite/
* gcc.target/aarch64/reg-alloc-1.c: New test.
Janne Blomqvist [Sat, 6 Jan 2018 10:41:03 +0000 (12:41 +0200)]
PR 50892 Latent bug in char pointer assignment
Due to r256284 (PR 78534) there was a latent bug that reared it's head
due to different character length types in the pointer
assignment. Fixed by this patch, which also adds a reduced testcase.
Regtested on x86_64-pc-linux-gnu, committed to trunk as obvious.
gcc/fortran/ChangeLog:
2018-01-06 Janne Blomqvist <jb@gcc.gnu.org>
PR fortran/50892
* trans-expr.c (gfc_trans_pointer_assignment): fold_convert rhs to
lhs type.
gcc/testsuite/ChangeLog:
2018-01-06 Janne Blomqvist <jb@gcc.gnu.org>
PR fortran/50892
* gfortran.dg/char_pointer_assign_icb_1.f90: New test.
Jakub Jelinek [Sat, 6 Jan 2018 07:47:32 +0000 (08:47 +0100)]
re PR rtl-optimization/83682 (ICE in simplify_subreg, at simplify-rtx.c:6296)
PR rtl-optimization/83682
* rtl.h (const_vec_duplicate_p): Only return true for VEC_DUPLICATE
if it has non-VECTOR_MODE element mode.
(vec_duplicate_p): Likewise.
Janne Blomqvist [Fri, 5 Jan 2018 19:01:12 +0000 (21:01 +0200)]
PR 78534 Change character length from int to size_t
In order to handle large character lengths on (L)LP64 targets, switch
the GFortran character length from an int to a size_t.
This is an ABI change, as procedures with character arguments take
hidden arguments with the character length.
I also changed the _size member in vtables from int to size_t, as
there were some cases where character lengths and sizes were
apparently mixed up and caused regressions otherwise. Although I
haven't tested, this might enable very large derived types as well.
Also, as there are some places in the frontend were negative character
lengths are used as special flag values, in the frontend the character
length is handled as a signed variable of the same size as a size_t,
although in the runtime library it really is size_t.
I haven't changed the character length variables for the co-array
intrinsics, as this is something that may need to be synchronized with
OpenCoarrays.
This is v5 of the patch. v4 was applied but caused breakage on big
endian targets. These have been fixed and tested, thanks to access to
the GCC compile farm.
Overview of v4 of the patch: v3 was applied but had to reverted due to
breaking bootstrap. The fix is in resolve.c:resolve_charlen, where
it's necessary to check that an expression is constant before using
mpz_sgn.
Overview of v3 of the patch: All the issues pointed out by FX's review
of v2 have been fixed. In particular, there are now new functions
gfc_mpz_get_hwi and gfc_mpz_set_hwi, similar to the GMP functions
mpz_get_si and mpz_set_si, except that they get/set a HOST_WIDE_INT
instead of a long value. Similarly, gfc_get_int_expr now takes a
HOST_WIDE_INT instead of a long, gfc_extract_long is replaced by
gfc_extract_hwi. Also, the preliminary work to handle
gfc_charlen_type_node being unsigned has been removed.
Regtested on x86_64-pc-linux-gnu, i686-pc-linux-gnu and
powerpc64-unknown-linux-gnu. Also regtested all three targets by
modifying gfortran-dg.exp to also test with "-g -flto", no new
failures observed.
frontend:
2018-01-05 Janne Blomqvist <jb@gcc.gnu.org>
PR fortran/78534
PR fortran/66310
* array.c (got_charlen): Use gfc_charlen_int_kind.
* class.c (gfc_find_derived_vtab): Use gfc_size_kind instead of
hardcoded kind.
(find_intrinsic_vtab): Likewise.
* decl.c (match_char_length): Use gfc_charlen_int_kind.
(add_init_expr_to_sym): Use gfc_charlen_t and gfc_charlen_int_kind.
(gfc_match_implicit): Use gfc_charlen_int_kind.
* dump-parse-tree.c (show_char_const): Use gfc_charlen_t and size_t.
(show_expr): Use HOST_WIDE_INT_PRINT_DEC.
* expr.c (gfc_get_character_expr): Length parameter of type
gfc_charlen_t.
(gfc_get_int_expr): Value argument of type HOST_WIDE_INT.
(gfc_extract_hwi): New function.
(simplify_const_ref): Make string_len of type gfc_charlen_t.
(gfc_simplify_expr): Use HOST_WIDE_INT for substring refs.
* frontend-passes.c (optimize_trim): Use gfc_charlen_int_kind.
* gfortran.h (gfc_mpz_get_hwi): New prototype.
(gfc_mpz_set_hwi): Likewise.
(gfc_charlen_t): New typedef.
(gfc_expr): Use gfc_charlen_t for character lengths.
(gfc_size_kind): New extern variable.
(gfc_extract_hwi): New prototype.
(gfc_get_character_expr): Use gfc_charlen_t for character length.
(gfc_get_int_expr): Use HOST_WIDE_INT type for value argument.
* gfortran.texi: Update description of hidden string length argument.
* iresolve.c (check_charlen_present): Use gfc_charlen_int_kind.
(gfc_resolve_char_achar): Likewise.
(gfc_resolve_repeat): Pass string length directly without
temporary, use gfc_charlen_int_kind.
(gfc_resolve_transfer): Use gfc_charlen_int_kind.
* match.c (select_intrinsic_set_tmp): Use HOST_WIDE_INT for charlen.
* misc.c (gfc_mpz_get_hwi): New function.
(gfc_mpz_set_hwi): New function.
* module.c (atom_int): Change type from int to HOST_WIDE_INT.
(parse_integer): Don't complain about large integers.
(write_atom): Use HOST_WIDE_INT for integers.
(mio_integer): Handle integer type mismatch.
(mio_hwi): New function.
(mio_intrinsic_op): Use HOST_WIDE_INT.
(mio_array_ref): Likewise.
(mio_expr): Likewise.
* primary.c (match_substring): Use gfc_charlen_int_kind.
* resolve.c (resolve_substring_charlen): Use gfc_charlen_int_kind.
(resolve_character_operator): Likewise.
(resolve_assoc_var): Likewise.
(resolve_select_type): Use HOST_WIDE_INT for charlen, use snprintf.
(resolve_charlen): Use mpz_sgn to determine sign.
* simplify.c (gfc_simplify_repeat): Use HOST_WIDE_INT/gfc_charlen_t
instead of long.
* symbol.c (generate_isocbinding_symbol): Use gfc_charlen_int_kind.
* target-memory.c (size_character): Length argument of type
gfc_charlen_t.
(gfc_encode_character): Likewise.
(gfc_interpret_character): Use gfc_charlen_t.
* target-memory.h (gfc_encode_character): Modify prototype.
* trans-array.c (gfc_trans_array_ctor_element): Use existing type.
(get_array_ctor_var_strlen): Use gfc_conv_mpz_to_tree_type.
(trans_array_constructor): Use existing type.
(get_array_charlen): Likewise.
* trans-const.c (gfc_conv_mpz_to_tree_type): New function.
* trans-const.h (gfc_conv_mpz_to_tree_type): New prototype.
* trans-decl.c (gfc_trans_deferred_vars): Use existing type.
(add_argument_checking): Likewise.
* trans-expr.c (gfc_class_len_or_zero_get): Build const of type
gfc_charlen_type_node.
(gfc_conv_intrinsic_to_class): Use gfc_charlen_int_kind instead of
4, fold_convert to correct type.
(gfc_conv_class_to_class): Build const of type size_type_node for
size.
(gfc_copy_class_to_class): Likewise.
(gfc_conv_string_length): Use same type in expression.
(gfc_conv_substring): Likewise, use HOST_WIDE_INT for charlen.
(gfc_conv_string_tmp): Make sure len is of the right type.
(gfc_conv_concat_op): Use same type in expression.
(gfc_conv_procedure_call): Likewise.
(fill_with_spaces): Comment out memset() block due to spurious
-Wstringop-overflow warnings.
(gfc_trans_string_copy): Use gfc_charlen_type_node.
(alloc_scalar_allocatable_for_subcomponent_assignment):
fold_convert to right type.
(gfc_trans_subcomponent_assign): Likewise.
(trans_class_vptr_len_assignment): Build const of correct type.
(gfc_trans_pointer_assignment): Likewise.
(alloc_scalar_allocatable_for_assignment): fold_convert to right
type in expr.
(trans_class_assignment): Build const of correct type.
* trans-intrinsic.c (gfc_conv_associated): Likewise.
(gfc_conv_intrinsic_repeat): Do calculation in sizetype.
* trans-io.c (gfc_build_io_library_fndecls): Use
gfc_charlen_type_node for character lengths.
(set_string): Convert to right type in assignment.
* trans-stmt.c (gfc_trans_label_assign): Build const of
gfc_charlen_type_node.
(trans_associate_var): Likewise.
(gfc_trans_character_select): Likewise.
(gfc_trans_allocate): Likewise, don't typecast strlen result.
(gfc_trans_deallocate): Don't typecast strlen result.
* trans-types.c (gfc_size_kind): New variable.
(gfc_init_types): Determine gfc_charlen_int_kind and gfc_size_kind
from size_type_node.
* trans-types.h: Fix comment.
testsuite:
2018-01-05 Janne Blomqvist <jb@gcc.gnu.org>
PR fortran/78534
PR fortran/66310
* gfortran.dg/char_cast_1.f90: Update scan pattern.
* gfortran.dg/dependency_49.f90: Likewise.
* gfortran.dg/repeat_4.f90: Use integers of kind C_SIZE_T.
* gfortran.dg/repeat_7.f90: New test for PR 66310.
* gfortran.dg/scan_2.f90: Handle potential cast in assignment.
* gfortran.dg/string_1.f90: Limit to ilp32 targets.
* gfortran.dg/string_1_lp64.f90: New test.
* gfortran.dg/string_3.f90: Limit to ilp32 targets.
* gfortran.dg/string_3_lp64.f90: New test.
libgfortran:
2019-01-05 Janne Blomqvist <jb@gcc.gnu.org>
PR fortran/78534
* intrinsics/args.c (getarg_i4): Use gfc_charlen_type.
(get_command_argument_i4): Likewise.
(get_command_i4): Likewise.
* intrinsics/chmod.c (chmod_internal): Likewise.
* intrinsics/env.c (get_environment_variable_i4): Likewise.
* intrinsics/extends_type_of.c (struct vtype): Use size_t for size
member.
* intrinsics/gerror.c (gerror): Use gfc_charlen_type.
* intrinsics/getlog.c (getlog): Likewise.
* intrinsics/hostnm.c (hostnm_0): Likewise.
* intrinsics/string_intrinsics_inc.c (string_len_trim): Rework to
work if gfc_charlen_type is unsigned.
(string_scan): Likewise.
* io/transfer.c (transfer_character): Modify prototype.
(transfer_character_write): Likewise.
(transfer_character_wide): Likewise.
(transfer_character_wide_write): Likewise.
(transfer_array): Typecast to avoid signed-unsigned comparison.
* io/unit.c (is_trim_ok): Use gfc_charlen_type.
* io/write.c (namelist_write): Likewise.
* libgfortran.h (gfc_charlen_type): Change typedef to size_t.
Jonathan Wakely [Fri, 5 Jan 2018 18:02:18 +0000 (18:02 +0000)]
PR libstdc++/83626 handle ENOENT due to filesystem race
PR libstdc++/83626
* src/filesystem/ops.cc (remove(const path&, error_code&)): Do not
report an error for ENOENT.
(remove_all(const path&)): Fix type of result variable.
(remove_all(const path&, error_code&)): Use non-throwing increment
for directory iterator. Call POSIX remove directly to avoid redundant
calls to symlink_status. Do not report errors for ENOENT.
* src/filesystem/std-ops.cc: Likewise.
* testsuite/27_io/filesystem/operations/remove_all.cc: Test throwing
overload.
* testsuite/experimental/filesystem/operations/remove_all.cc:
Likewise.
Jakub Jelinek [Fri, 5 Jan 2018 16:40:24 +0000 (17:40 +0100)]
re PR target/83604 (ICE in copy_to_mode_reg, at explow.c:630)
PR target/83604
* config/i386/i386-builtin.def
(__builtin_ia32_vgf2p8affineinvqb_v64qi,
__builtin_ia32_vgf2p8affineqb_v64qi, __builtin_ia32_vgf2p8mulb_v64qi):
Require also OPTION_MASK_ISA_AVX512F in addition to
OPTION_MASK_ISA_GFNI.
(__builtin_ia32_vgf2p8affineinvqb_v16qi_mask,
__builtin_ia32_vgf2p8affineqb_v16qi_mask): Require
OPTION_MASK_ISA_AVX512VL instead of OPTION_MASK_ISA_SSE in addition
to OPTION_MASK_ISA_GFNI.
(__builtin_ia32_vgf2p8mulb_v32qi_mask): Require
OPTION_MASK_ISA_AVX512VL in addition to OPTION_MASK_ISA_GFNI and
OPTION_MASK_ISA_AVX512BW.
(__builtin_ia32_vgf2p8mulb_v16qi_mask): Require
OPTION_MASK_ISA_AVX512VL instead of OPTION_MASK_ISA_AVX512BW in
addition to OPTION_MASK_ISA_GFNI.
(__builtin_ia32_vgf2p8affineinvqb_v16qi,
__builtin_ia32_vgf2p8affineqb_v16qi, __builtin_ia32_vgf2p8mulb_v16qi):
Require OPTION_MASK_ISA_SSE2 instead of OPTION_MASK_ISA_SSE in addition
to OPTION_MASK_ISA_GFNI.
* config/i386/i386.c (def_builtin): Change to builtin isa/isa2 being
a requirement for all ISAs rather than any of them with a few
exceptions.
(ix86_add_new_builtins): Clear OPTION_MASK_ISA_64BIT from isa before
processing.
(ix86_expand_builtin): Require all ISAs from builtin's isa and isa2
bitmasks to be enabled with 3 exceptions, instead of requiring any
enabled ISA with lots of exceptions.
* config/i386/sse.md (vgf2p8affineinvqb_<mode><mask_name>,
vgf2p8affineqb_<mode><mask_name>, vgf2p8mulb_<mode><mask_name>):
Change avx512bw in isa attribute to avx512f.
* config/i386/sgxintrin.h: Add license boilerplate.
* config/i386/vaesintrin.h: Likewise. Fix macro spelling __AVX512F
to __AVX512F__ and __AVX512VL to __AVX512VL__.
(_mm256_aesdec_epi128, _mm256_aesdeclast_epi128, _mm256_aesenc_epi128,
_mm256_aesenclast_epi128): Enable temporarily avx if __AVX__ is not
defined.
* config/i386/gfniintrin.h (_mm_gf2p8mul_epi8,
_mm_gf2p8affineinv_epi64_epi8, _mm_gf2p8affine_epi64_epi8): Enable
temporarily sse2 rather than sse if not enabled already.
r241959 included code to stop the vectoriser increasing the alignment of
a "user-aligned" variable. This wasn't the main purpose of the patch,
but was done for consistency with pass_increase_alignment, and was
needed to make the testcase work.
The documentation for the aligned attribute says:
This attribute specifies a minimum alignment for the variable or
structure field, measured in bytes.
so I think it's reasonable for the vectoriser to increase the
alignment further, if that helps us to vectorise code. It's also
useful if the "user" alignment actually came from an earlier pass
rather than the source code.
A possible counterexample came up when this was discussed on the lists.
Users who are trying to collate things from several translation units
into a single section can use:
__attribute__((section ("whatever"), aligned(N)))
and would not want extra padding. It turns out that the supported way
of doing that is to add a "used" attribute, which works even when no
"aligned" attribute is given.
2018-01-05 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* tree-vect-data-refs.c (vect_compute_data_ref_alignment): Don't
punt for user-aligned variables.
gcc/testsuite/
* gcc.dg/vect/vect-align-4.c: New test.
* gcc.dg/vect/vect-nb-iter-ub-2.c (cc): Remove alignment attribute
and redefine as a structure with an unaligned member "b".
(foo): Update accordingly.
This patch add support for the missing transformation of
(x | y) == x -> (y & ~x) == 0. The transformation for (x & y) == x case
already exists in simplify-rtx.c since 2014 as of r218503 and this patch
only adds a couple of extra patterns for the IOR case. This benefits
targets that have the BICS instruction to generate better code. For
targets that do not have the BICS instructions, it still results in
no worse code generation and gives out 2 instructions.
ChangeLog Entries:
*** gcc/ChangeLog ***
2018-01-05 Sudakshina Das <sudi.das@arm.com>
PR target/82439
* simplify-rtx.c (simplify_relational_operation_1): Add simplifications
of (x|y) == x for BICS pattern.
*** gcc/testsuite/ChangeLog ***
2018-01-05 Sudakshina Das <sudi.das@arm.com>
PR target/82439
* gcc.target/aarch64/bics_5.c: New test.
* gcc.target/arm/bics_5.c: Likewise.
Jakub Jelinek [Fri, 5 Jan 2018 08:51:32 +0000 (09:51 +0100)]
re PR tree-optimization/83605 (ICE: verify_gimple failed (error: dead STMT in EH table))
PR tree-optimization/83605
* gimple-ssa-strength-reduction.c: Include tree-eh.h.
(find_candidates_dom_walker::before_dom_children): Ignore stmts that
can throw.
Jakub Jelinek [Thu, 4 Jan 2018 21:54:23 +0000 (22:54 +0100)]
re PR target/83554 (ICE: in ix86_mitigate_rop, at config/i386/i386.c:41274 with -mmitigate-rop)
PR target/83554
* config/i386/i386.md (*<rotate_insn>hi3_1 splitter): Use
QIreg_operand instead of register_operand predicate.
* config/i386/i386.c (ix86_rop_should_change_byte_p,
set_rop_modrm_reg_bits, ix86_mitigate_rop): Use -mmitigate-rop in
comments instead of -fmitigate[-_]rop.
Protect second call to extract_range_from_multiplicative_op_1
Following on from:
* tree-vrp.c (extract_range_from_multiplicative_op_1): Assert
for VR_RANGE only; don't allow VR_ANTI_RANGE.
(extract_range_from_binary_expr_1): Don't call
extract_range_from_multiplicative_op_1 if !range_int_cst_p.
there was a later call to extract_range_from_multiplicative_op_1 too,
that used a negative test for a symbolic (!is_gimple_min_invariant)
range rather than a positive test for an integer range.
2017-11-04 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* tree-vrp.c (extract_range_from_binary_expr_1): Check
range_int_cst_p rather than !symbolic_range_p before calling
extract_range_from_multiplicative_op_1.
Add tree_fits_uhwi_p tests to BIT_FIELD_REF folder
The first BIT_FIELD_REF folding pattern assumed without checking that
operands satisfy tree_fits_uhwi_p. The second pattern does check this:
/* On constants we can use native encode/interpret to constant
fold (nearly) all BIT_FIELD_REFs. */
if (CONSTANT_CLASS_P (arg0)
&& can_native_interpret_type_p (type)
&& BITS_PER_UNIT == 8
&& tree_fits_uhwi_p (op1)
&& tree_fits_uhwi_p (op2))
so this patch adds the checks to the first pattern too. This is needed
for POLY_INT_CST bit positions.
2018-01-04 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* fold-const.c (fold_ternary_loc): Check tree_fits_uhwi_p before
using tree_to_uhwi.
tree-ssa-forwprop.c was asserting that a VEC_PERM_EXPR fold on three
VECTOR_CSTs would always succeed, but it's possible for it to fail
with variable-length vectors.
2017-12-22 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* tree-ssa-forwprop.c (is_combined_permutation_identity): Allow
the VEC_PERM_EXPR fold to fail.
Peter Bergner [Thu, 4 Jan 2018 14:36:35 +0000 (08:36 -0600)]
re PR target/83387 (PowerPC64: Infinite loops in do_reload() with -msoft-float)
PR target/83387
* config/rs6000/rs6000.c (rs6000_discover_homogeneous_aggregate): Do not
allow arguments in FP registers if TARGET_HARD_FLOAT is false.
Jonathan Wakely [Thu, 4 Jan 2018 10:21:29 +0000 (10:21 +0000)]
PR libstdc++/83607 specialize Boyer-Moore searchers for std::byte
PR libstdc++/83607
* include/std/functional (__is_byte_like): New trait.
(__is_std_equal_to): Remove.
(__boyer_moore_base_t): Use __is_byte_like instead of
__is_std_equal_to.
* include/experimental/functional (__is_std_equal_to): Remove.
(__boyer_moore_base_t): Use __is_byte_like instead of
__is_std_equal_to.
* testsuite/20_util/function_objects/83607.cc: New test.
Martin Liska [Thu, 4 Jan 2018 08:55:15 +0000 (09:55 +0100)]
Add version to intermediate gcov file (PR gcov-profile/83669).
2018-01-04 Martin Liska <mliska@suse.cz>
PR gcov-profile/83669
* gcov.c (output_intermediate_file): Add version to intermediate
gcov file.
* doc/gcov.texi: Document new field 'version' in intermediate
file format. Fix location of '-k' option of gcov command.
Jakub Jelinek [Thu, 4 Jan 2018 08:51:09 +0000 (09:51 +0100)]
vect-opt-info-1.c: Moved to ...
* gcc.dg/vect-opt-info-1.c: Moved to ...
* gcc.dg/vect/nodump-vect-opt-info-1.c: ... here. Only run on
vect_int targets, use dg-additional-options instead of dg-options and
use relative line numbers instead of absolute.
Martin Sebor [Wed, 3 Jan 2018 22:52:53 +0000 (22:52 +0000)]
PR tree-optimization/83603 - ICE in builtin_memref at gcc/gimple-ssa-warn-restrict.c:238
gcc/ChangeLog:
PR tree-optimization/83603
* calls.c (maybe_warn_nonstring_arg): Avoid accessing function
arguments past the endof the argument list in functions declared
without a prototype.
* gimple-ssa-warn-restrict.c (wrestrict_dom_walker::check_call):
Avoid checking when arguments are null.
gcc/testsuite/ChangeLog:
PR tree-optimization/83603
* gcc.dg/Wrestrict-4.c: New test.
Make vectorizable_load/store handle IFN_MASK_LOAD/STORE
After the previous patches, it's easier to see that the remaining
inlined transform code in vectorizable_mask_load_store is just a
cut-down version of the VMAT_CONTIGUOUS handling in vectorizable_load
and vectorizable_store. This patch therefore makes those functions
handle masked loads and stores instead.
This makes it easier to handle more forms of masked load and store
without duplicating logic from the unmasked forms. It also helps with
support for fully-masked loops.
2018-01-03 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* tree-vect-stmts.c (vect_get_store_rhs): New function.
(vectorizable_mask_load_store): Delete.
(vectorizable_call): Return false for masked loads and stores.
(vectorizable_store): Handle IFN_MASK_STORE. Use vect_get_store_rhs
instead of gimple_assign_rhs1.
(vectorizable_load): Handle IFN_MASK_LOAD.
(vect_transform_stmt): Don't set is_store for call_vec_info_type.
Split gather load handling out of vectorizable_{mask_load_store,load}
vectorizable_mask_load_store and vectorizable_load used the same
code to build a gather load call, except that the former also
vectorised a mask argument and used it for both the merge and mask
inputs. The latter instead used a merge input of zero and a mask
input of all-ones. This patch splits it out into a subroutine.
2018-01-03 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* tree-vect-stmts.c (vect_build_gather_load_calls): New function,
split out from..,
(vectorizable_mask_load_store): ...here.
(vectorizable_load): ...and here.
This patch splits out the code to build an all-bits-one or all-bits-zero
input to a gather load. The catch is that both masks can have
floating-point type, in which case they are implicitly treated in
the same way as an integer bitmask.
2018-01-03 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* tree-vect-stmts.c (vect_build_all_ones_mask)
(vect_build_zero_merge_argument): New functions, split out from...
(vectorizable_load): ...here.
Split mask checking out of vectorizable_mask_load_store
This patch splits the mask argument checking out of
vectorizable_mask_load_store, so that a later patch can use it in both
vectorizable_load and vectorizable_store. It also adds dump messages
for false returns. This is mostly useful for the TYPE_VECTOR_SUBPARTS
check, which can fail if pattern recognition didn't convert the mask
properly.
2018-01-03 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* tree-vect-stmts.c (vect_check_load_store_mask): New function,
split out from...
(vectorizable_mask_load_store): ...here.
Make vect_model_store_cost take a vec_load_store_type
This patch makes vect_model_store_cost take a vec_load_store_type
instead of a vect_def_type. It's a wash on its own, but it helps
with later patches.
2018-01-03 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* tree-vectorizer.h (vec_load_store_type): Moved from tree-vec-stmts.c
(vect_model_store_cost): Take a vec_load_store_type instead of a
vect_def_type.
* tree-vect-stmts.c (vec_load_store_type): Move to tree-vectorizer.h.
(vect_model_store_cost): Take a vec_load_store_type instead of a
vect_def_type.
(vectorizable_mask_load_store): Update accordingly.
(vectorizable_store): Likewise.
* tree-vect-slp.c (vect_analyze_slp_cost_1): Update accordingly.
vectorizable_mask_load_store replaces scalar IFN_MASK_LOAD calls with
dummy assignments, so that they never survive vectorisation. This patch
moves the code to vect_transform_loop instead, so that we only change
the scalar statements once all of them have been vectorised.
This makes it easier to handle other types of functions that need
stubbing out, and also makes it easier to handle groups and patterns.
2018-01-03 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* tree-vect-loop.c (vect_transform_loop): Stub out scalar
IFN_MASK_LOAD calls here rather than...
* tree-vect-stmts.c (vectorizable_mask_load_store): ...here.
extract_bit_field_1 tries to use vec_extract to extract part of a
vector. However, if that pattern isn't defined or if the operands
aren't suitable, another good approach is to try a direct subreg
reference. This is particularly useful for multi-vector modes on
SVE (e.g. when extracting one vector from an LD2 result).
The function would go on to try the same thing anyway, but only
if there is an integer mode with the same size as the vector mode,
which isn't true for SVE modes (and doesn't seem a good thing to
require in general). Even when there is an integer mode, doing the
operation on the original modes avoids some unnecessary bitcasting.
2018-01-03 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* expmed.c (extract_bit_field_1): For vector extracts,
fall back to extract_bit_field_as_subreg if vec_extract
isn't available.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256209
Once SVE is enabled, a general AArch64 spill slot offset will be
A + B * VL
where A is a constant and B is a multiple of the SVE vector length.
The offsets in SVE load and store instructions are a multiple of VL
(and so can encode some values of B), while offsets for standard AArch64
load and store instructions aren't (and encode some values of A).
We therefore get better spill code if variable-sized slots are grouped
together separately from constant-sized slots, and if variable-sized
slots are not reused for constant-sized data. Then, spills to the
constant-sized slots can add B * VL to the offset first, creating a
common anchor point for spills with the same B component but different
A components. Similarly, spills to variable-sized slots can add A to
the offset first, creating a common anchor point for spills with the same
A component but different B components.
This patch implements the sorting and grouping side of the optimisation.
A later patch creates the anchor points.
The patch is a no-op on other targets.
2018-01-03 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* lra-spills.c (pseudo_reg_slot_compare): Sort slots by whether
they are variable or constant sized.
(assign_stack_slot_num_and_sort_pseudos): Don't reuse variable-sized
slots for constant-sized data.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256208
Improve vectorization COND_EXPR <bool op bool, ...>
This patch allows us to recognise:
... = bool1 != bool2 ? x : y
as equivalent to:
bool tmp = bool1 ^ bool2;
... = tmp ? x : y
For the latter we were already able to find the natural number
of vector units for tmp based on the types that feed bool1 and
bool2, whereas with the former we would simply treat bool1 and
bool2 as vectorised 8-bit values, possibly requiring them to
be packed and unpacked from their natural width.
This is used by a later SVE patch.
2018-01-03 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* tree-vect-patterns.c (vect_recog_mask_conversion_pattern): When
handling COND_EXPRs with boolean comparisons, try to find a better
basis for the mask type than the boolean itself.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256207
The default value of MAX_BITSIZE_MODE_ANY_MODE is calculated
from the initial mode sizes specified in the modes.def file.
The target needs to be able to override it if ADJUST_BYTESIZE
& co. can choose a bigger size.
2018-01-03 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* doc/rtl.texi (MAX_BITSIZE_MODE_ANY_MODE): Describe how the default
is calculated and how it can be overridden.
* genmodes.c (max_bitsize_mode_any_mode): New variable.
(create_modes): Initialize it from MAX_BITSIZE_MODE_ANY_MODE,
if defined.
(emit_max_int): Use it to set the output MAX_BITSIZE_MODE_ANY_MODE,
if nonzero.
This patch reworks aarch64_simd_valid_immediate so that
it's easier to add SVE support. The main changes are:
- make simd_immediate_info easier to construct
- replace the while (1) { ... break; } blocks with checks that use
the full 64-bit value of the constant
- treat floating-point modes as integers if they aren't valid
as floating-point values
2018-01-03 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_output_simd_mov_immediate):
Remove the mode argument.
(aarch64_simd_valid_immediate): Remove the mode and inverse
arguments.
* config/aarch64/iterators.md (bitsize): New iterator.
* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>, and<mode>3)
(ior<mode>3): Update calls to aarch64_output_simd_mov_immediate.
* config/aarch64/constraints.md (Do, Db, Dn): Update calls to
aarch64_simd_valid_immediate.
* config/aarch64/predicates.md (aarch64_reg_or_orr_imm): Likewise.
(aarch64_reg_or_bic_imm): Likewise.
* config/aarch64/aarch64.c (simd_immediate_info): Replace mvn
with an insn_type enum and msl with a modifier_type enum.
Replace element_width with a scalar_mode. Change the shift
to unsigned int. Add constructors for scalar_float_mode and
scalar_int_mode elements.
(aarch64_vect_float_const_representable_p): Delete.
(aarch64_can_const_movi_rtx_p)
(aarch64_simd_scalar_immediate_valid_for_move)
(aarch64_simd_make_constant): Update call to
aarch64_simd_valid_immediate.
(aarch64_advsimd_valid_immediate_hs): New function.
(aarch64_advsimd_valid_immediate): Likewise.
(aarch64_simd_valid_immediate): Remove mode and inverse
arguments. Rewrite to use the above. Use const_vec_duplicate_p
to detect duplicated constants and use aarch64_float_const_zero_rtx_p
and aarch64_float_const_representable_p on the result.
(aarch64_output_simd_mov_immediate): Remove mode argument.
Update call to aarch64_simd_valid_immediate and use of
simd_immediate_info.
(aarch64_output_scalar_simd_mov_immediate): Update call
accordingly.
gcc/testsuite/
* gcc.target/aarch64/vect-movi.c (movi_float_lsl24): New function.
(main): Call it.
Co-Authored-By: Alan Hayward <alan.hayward@arm.com> Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256205
projects / thirdparty / gcc.git / log
