Ville Syrjälä [Thu, 17 Apr 2025 11:44:50 +0000 (14:44 +0300)]
drm/i915/vga: Add more VGACNTRL bits
Define a pile of extra VGACNTRL bits. We don't really have
any real use for most of these but nicer to have them all
in one place rather than trawling the specs when one wants
to know what's in there.
I will have some real use for the CHV pipe select bits later.
Animesh Manna [Wed, 23 Apr 2025 09:23:30 +0000 (14:53 +0530)]
drm/i915/lobf: Add debug interface for lobf
Add an interface in debugfs which will help in debugging LOBF
feature.
v1: Initial version.
v2:
- Remove FORCE_EN flag. [Jouni]
- Change prefix from I915 to INTEL. [Jani]
- Use u8 instead of bool for lobf-debug flag. [Jani]
v3:
- Use intel_connector instead of display. [Jani]
- Remove edp connector check as it was already present
in caller function. [Jani]
- Remove loop of searching edp encoder which is directly
accessible from intel_connector. [Jani]
v4:
- Simplify alpm debug to bool instead of bit-mask. [Jani]
v5:
- Remove READ_ONCE(). [Jani]
- Modify variable name to *_disable_*. [Jouni]
v6: Improved debug print. [Jouni]
Animesh Manna [Wed, 23 Apr 2025 09:23:29 +0000 (14:53 +0530)]
drm/i915/lobf: Update lobf if any change in dependent parameters
For every commit the dependent condition for LOBF is checked
and accordingly update has_lobf flag which will be used
to update the ALPM_CTL register during commit.
v1: Initial version.
v2: Avoid reading h/w register without has_lobf check. [Jani]
v3: Update LOBF in post plane update instead of separate function. [Jouni]
v4:
- Add lobf disable print. [Jouni]
- Simplify condition check for enabling/disabling lobf. [Jouni]
v5: Disable LOBF in pre_plane_update(). [Jouni]
v6: use lobf flag of old_crtc_state and write 0 into ALPM_CTL. [Jouni]
Animesh Manna [Wed, 23 Apr 2025 09:23:27 +0000 (14:53 +0530)]
drm/i915/lobf: Disintegrate alpm_disable from psr_disable
Currently clearing of alpm registers is done through psr_disable()
which is always not correct, without psr also alpm can exist. So
dis-integrate alpm_disable() from psr_disable().
Animesh Manna [Wed, 23 Apr 2025 09:23:26 +0000 (14:53 +0530)]
drm/i915/lobf: Add debug print for LOBF
Lobf is enabled part of ALPM configuration and if has_lobf
is set to true respective bit for LOBF will be set. Add debug
print while setting the bitfield of LOBF.
Animesh Manna [Wed, 23 Apr 2025 09:23:25 +0000 (14:53 +0530)]
drm/i915/lobf: Add lobf enablement in post plane update
Enablement of LOBF is added in post plane update whenever
has_lobf flag is set. As LOBF can be enabled in non-psr
case as well so adding in post plane update. There is no
change of configuring alpm with psr path.
v1: Initial version.
v2: Use encoder-mask to find the associated encoder from
crtc-state. [Jani]
v3: Remove alpm_configure from intel_psr.c. [Jouni]
drm/i915/alpm: use variable from intel_crtc_state instead of intel_psr
Currently code is making assumption that PSR is enabled when
intel_alpm_configure is called. This doesn't work if alpm is configured
before PSR is enabled.
Jani Nikula [Wed, 23 Apr 2025 10:02:13 +0000 (13:02 +0300)]
drm/i915/reg: Add/remove some extra blank lines
Add/remove some blank lines to/from i915_reg.h primarily to help the
scripted refactoring coming up, separating unrelated registers and
keeping the comments together.
Jani Nikula [Wed, 23 Apr 2025 10:02:12 +0000 (13:02 +0300)]
drm/i915/reg: use REG_BIT and friends to define DP registers
Define the DP register contents using the REG_BIT, REG_GENMASK,
etc. macros. Ditch the unhelpful comments. Rename eDP related register
content macros to have EDP_ prefix.
Scope of intel_psr_needs_block_dc_vblank has changed now. Rename it as
intel_psr_needs_vblank_notification. Also rename
intel_crtc::block_dc_for_vblank as intel_crtc:vblank_psr_notify
drm/i915/psr: Apply underrun on PSR idle workaround
This patch is applying workaround for underrun on idle PSR HW issue
(Wa_16025596647) when PSR is getting enabled. It uses vblank enable/disable
status, DC5/6 enabled disabled and enabled pipes count information made
available.
This patch is also adding calls to dc5/dc6, vblank enable/disable and pipe
enable/disable notification functions as needed.
intel_psr_needs_block_dc_vblank is modified to get vblank enable/disable
notification on PSR capable system.
v2: use intel_dmc interface instead of directly writing dmc register
drm/i915/dmc: Add interface to control start of PKG C-state exit
Add interface to control if package C exit starts at the start of the
undelayed vblank. This is needed to implement workaround for underrun on
idle PSR HW issue (Wa_16025596647).
drm/i915/psr: Add mechanism to notify PSR of DC5/6 enable disable
We need to apply/remove workaround for underrun on idle PSR HW issue
(Wa_16025596647) when DC5/6 is enabled/disabled. This patch implements
mechanism to notify PSR about DC5/6 enable/disable and applies/removes the
workaround using this notification.
drm/i915/psr: Add mechanism to notify PSR of pipe enable/disable
We need to apply/remove workaround for underrun on idle PSR HW issue
(Wa_16025596647) when new pipe is enabled or pipe is getting disabled. This
patch implements mechanism to notify PSR about pipe enable/disable and
applies/removes the workaround using this notification.
We need PIPEDMC_BLOCK_PKGC_SW definitions to implement workaround for
underrun on idle PSR HW issue (Wa_16025596647). Add PIPEDMC_BLOCK_PKGC_SW
register definitions.
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647)
we need PIPEDMC_EVT_CTL_4 register. Add PIPEDMC_EVT_CTL_4 register
definitions.
drm/i915/psr: Store enabled non-psr pipes into intel_crtc_state
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647)
we need to know enabled. Figure out which non-PSR pipes we will have active
and store it into intel_crtc_state->active_non_psr_pipes. This is currently
assuming only one eDP on a time. I.e. possible secondary eDP with PSR
capable panel is not considered.
drm/i915/display: Add new interface for getting dc_state
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647)
we need to have current configured DC state available. Add new interface
for this purpose.
Jani Nikula [Thu, 17 Apr 2025 09:10:38 +0000 (12:10 +0300)]
drm/i915/pch: abstract fake PCH detection better
Abstract detection of platforms with south display on the same PCI
device or SoC die as north display, and all around clarify what this
means. Debug log about it for good measure.
Jani Nikula [Thu, 17 Apr 2025 09:10:37 +0000 (12:10 +0300)]
drm/i915/display: drop lots of unnecessary #include i915_drv.h
With the PCH macros switched to use struct intel_display, we have a
number of files that no longer need struct drm_i915_private or anything
else from i915_drv.h anymore. Remove the #include, and add the missing
includes that were previously implicit.
Jani Nikula [Thu, 17 Apr 2025 09:10:36 +0000 (12:10 +0300)]
drm/i915/display: pass struct intel_display to PCH macros
Now that INTEL_PCH_TYPE() and HAS_PCH_*() macros are under display, and
accept a struct intel_display pointer, use that instead of struct
drm_i915_private pointer in display code.
This is done naively by running:
$ sed -i 's/\(INTEL_PCH_TYPE\|HAS_PCH_[A-Z0-9_-]*\)([^)]*)/\1(display)/g' \
$(find drivers/gpu/drm/i915/display -name "*.c")
and fixing the fallout, i.e. removing unused local i915 variables and
adding display variables where needed.
Jani Nikula [Wed, 9 Apr 2025 18:17:55 +0000 (21:17 +0300)]
drm/xe/compat: clean up unused platform check macros
Clean up unused platform check macros from compat i915_drv.h. Display no
longer uses any of the IS_*() platform checks. The remaining users are
part of the soc/ code. Note that in a comment.
Jani Nikula [Wed, 9 Apr 2025 18:17:42 +0000 (21:17 +0300)]
drm/i915/fb: convert intel_fbdev.[ch] and intel_fbdev_fb.[ch] to struct intel_display
Going forward, struct intel_display is the main display device data
pointer. Convert intel_fbdev.[ch] and as much as possible of
intel_fbdev_fb.[ch] to struct intel_display.
drm/i915/pxp: fix undefined reference to `intel_pxp_gsccs_is_ready_for_sessions'
On x86_64 with gcc version 13.3.0, I compile kernel with:
make defconfig
./scripts/kconfig/merge_config.sh .config <(
echo CONFIG_COMPILE_TEST=y
)
make KCFLAGS="-fno-inline-functions -fno-inline-small-functions -fno-inline-functions-called-once"
Then I get a linker error:
ld: vmlinux.o: in function `pxp_fw_dependencies_completed':
kintel_pxp.c:(.text+0x95728f): undefined reference to `intel_pxp_gsccs_is_ready_for_sessions'
This is caused by not having a intel_pxp_gsccs_is_ready_for_sessions()
header stub for CONFIG_DRM_I915_PXP=n. Add it.
Signed-off-by: Chen Linxuan <chenlinxuan@uniontech.com> Fixes: 99afb7cc8c44 ("drm/i915/pxp: Add ARB session creation and cleanup") Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://lore.kernel.org/r/20250415090616.2649889-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Jani Nikula [Wed, 9 Apr 2025 18:47:02 +0000 (21:47 +0300)]
drm/i915/irq: convert ibx_irq_reset() into ibx_display_irq_reset()
Observe that ibx_irq_reset() is really ibx_display_irq_reset(). Make it
so. Move to display, and call it directly from gen8_display_irq_reset()
instead of gen8_irq_reset().
Remove a nearby ancient stale comment while at it.
drm/i915/display: Add link rate and lane count to i915_display_info
Adding link rate and lane count information to i915_display_info makes it
easier and faster to access this data compared to checking kernel logs.
This is particularly beneficial for individuals who are not familiar with
i915 in the following scenarios:
* Debugging DP tunnel bandwidth usage in the Thunderbolt driver.
* During USB4 certification, it is necessary to know the link rate used by
the monitor to prove that the DP tunnel can handle required rates.
* In PHY CTS, when the connector probes are not mounted correctly,
some display lanes may not appear in the DP Oscilloscope, leading to CTS
failures.
This change provides validation teams with an easy way to identify and
troubleshoot issues.
v2: separate seq_printf line (Jani)
v3: separate output line (Jani)
Cc: Imre Deak <imre.deak@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://lore.kernel.org/r/20250409230214.963999-1-khaled.almahallawy@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drm/i915/dp: Check for HAS_DSC_3ENGINES while configuring DSC slices
DSC 12 slices configuration is used for some specific cases with
Ultrajoiner. This can be supported only when each of the 4 joined pipes
have 3 DSC engines each.
Add the missing check for 3 DSC engines support before using 3 DSC
slices per pipe.
Jani Nikula [Mon, 14 Apr 2025 11:29:46 +0000 (14:29 +0300)]
drm/i915: use display snapshot mechanism for display irq regs
Move more display specific parts of GPU error logging behind the display
snapshot interface.
With the display register capture reduced to just one register, DERRMR,
there's quite a bit of boilerplate here. However, it's still a nice
abstraction and removes a DISPLAY_VER() usage from core i915. With this
approach, it's also easy to add to xe as needed.
Jani Nikula [Fri, 11 Apr 2025 10:27:15 +0000 (13:27 +0300)]
drm/i915/dpio: have chv_data_lane_soft_reset() get/put dpio internally
Have chv_data_lane_soft_reset() get/put dpio internally, and use a
locked version of it within intel_dpio_phy.c. This drops the dependency
on vlv sideband from g4x_dp.c and g4x_hdmi.c, and makes that a DPIO PHY
implementation detail.
drm/i915/vrr: Stop writing VRR_CTL_IGN_MAX_SHIFT for MTL onwards
According to Bspec VRR_CTL_IGN_MAX_SHIFT doesn't exist for MTL and
onwards. On LunarLake and onwards Bit 30 is "Mask Block PkgC" instead. Stop
writing the bit for MeteorLake and onwards
v2: "Ignore Max Shift" bit doesn't exist on MeteorLake either
Jani Nikula [Fri, 11 Apr 2025 09:54:14 +0000 (12:54 +0300)]
drm/i915/pch: clean up includes
We no longer need i915_drv.h in intel_pch.c, and we no longer need
intel_pch.h universally.
With intel_pch.h being included from intel_display_core.h, it's still
included pretty much everywhere, but there's no need to include it
explicitly from i915_drv.h or xe_device_types.h.
The only usage of the "PCH" infra is to detect which South Display
Engine we should be using. Move it under display so we can convert
all its callers towards intel_display struct later.
Turns out we've added two similar debugfs files. Consolidate on
intel_display_caps as it has more info and a driver independent name.
IGT has already switched over to intel_display_caps in IGT commit cf837fc17d6c ("lib/dsc: use intel_display_caps instead of
i915_display_capabilities").
Ville Syrjälä [Wed, 2 Apr 2025 17:17:20 +0000 (20:17 +0300)]
drm/i915: Simplify combo PLL frac w/a
We are applying the combo PLL frac w/a to all TGL+ platforms, except
RKL. I *think* all RKL machines use a 24 MHz refclk (certainly all
machines in our CI do) and so technically never need the adjustment.
But let's assume the hardware is exactly the same anyway and simplify
the code by applying the w/a to all TGL+ platforms.
Ville Syrjälä [Tue, 1 Apr 2025 16:37:49 +0000 (19:37 +0300)]
drm/i915: Apply the combo PLL frac w/a on DG1
DG1 apparently needs the combo PLL fractional divider w/a
with 38.4 MHz refclk as well. This isn't listed in bspec, but
looking at the hsd it looks like it was possibly just missed
due to no one having a DG1 around at the time.
This gives us slightly more accurate clocks on DG1.
Jani Nikula [Tue, 8 Apr 2025 13:38:40 +0000 (16:38 +0300)]
drm/i915/wm: convert i9xx_wm.c to intel_de_*() register interface
The registers handled in i9xx_wm.c are mostly display registers. The
MCH_SSKPD and MLTR_ILK registers are not. Convert register access to
intel_de_*() interface where applicaple.
Jani Nikula [Tue, 8 Apr 2025 13:38:35 +0000 (16:38 +0300)]
drm/i915/wm: convert intel_wm.h external interfaces to struct intel_display
Going forward, struct intel_display is the main display device data
pointer. Convert the intel_wm.h interface as well as the hooks in struct
intel_wm_funcs to struct intel_display.
Jani Nikula [Thu, 3 Apr 2025 12:21:34 +0000 (15:21 +0300)]
drm/i915/dsi: unify naming and simplify checks for dphy params
Unify the naming of the data and clock lane timing parameters, and
simplify their bounds checks. Drop the debug messages on out of bounds
parameters as excessive.
Jani Nikula [Thu, 3 Apr 2025 12:21:33 +0000 (15:21 +0300)]
drm/i915/dsi: separate clock and data lane prepare timing
The history of why the max of VBT clock and data lane prepare timing
parameter is used for both instead of each individually is
unknown. Separate them to follow what the Windows driver does.
Imre Deak [Fri, 4 Apr 2025 15:03:10 +0000 (18:03 +0300)]
drm/i915/dp_mst: Rename intel_dp::mst.active_links to mst.active_streams
intel_dp::mst.active_links actually indicates the number of MST streams,
not the number of MST links (one MST link carrying one or more MST
streams), rename the field accordingly.
Imre Deak [Fri, 4 Apr 2025 15:03:08 +0000 (18:03 +0300)]
drm/i915/dp_mst: Rename intel_dp_mst_encoder_active_links() to intel_dp_mst_active_streams()
It's not clear which encoder intel_dp_mst_encoder_active_links() refers
to (primary/stream), but there is also no reason to call the queried
property an encoder property; remove encoder from the name. Also it's
the number of MST streams being queried, vs. the number of MST links
(there is one MST link carrying one or more MST streams), so rename link
to stream as well.
While at it pass intel_dp to the function, which is more logical and
makes it easier to re-use the function later (without the need to get
the digital port pointer).
Also move the function earlier, next to the related ones.
Imre Deak [Fri, 4 Apr 2025 15:03:07 +0000 (18:03 +0300)]
drm/i915/dp_mst: Remove stream count assert from intel_dp_check_mst_status()
There doesn't seem to be a reason to assert for a non-negative stream
counter in intel_dp_check_mst_status() in particular, remove it. There
is now an equivalent assert in intel_dp_mst_dec_active_streams().
Imre Deak [Fri, 4 Apr 2025 15:03:05 +0000 (18:03 +0300)]
drm/i915/dp: Rename intel_dp::link_trained to link.active
The intel_dp::link_trained flag indicates whether the link is active,
regardless of whether the link training passed or failed. For clarity
rename the flag to 'active'. While at it move the flag under
intel_dp::link.
drm/i915/vrr: Add vrr.vsync_{start, end} in vrr_params_changed
Add the missing vrr parameters in vrr_params_changed() helper.
This ensures that changes in vrr.vsync_{start,end} trigger a call to
appropriate helpers to update the VRR registers.
Ville Syrjälä [Wed, 26 Mar 2025 16:25:43 +0000 (18:25 +0200)]
drm/i915: Skip bw stuff if per-crtc sagv state doesn't change
If there are no changes to intel_crtc_can_enable_sagv() there
is no need to do all the sagv bw_state recomputation.
The only slight caveat here is hw state takeover where we
initially disable SAGV, and want it to get re-enabled once
we've determined that it's safe to do so. That can now be
achieved by having intel_crtc_can_enable_sagv() reject SAGV
as long as the crtc_state->inherited flag is set. Once the
flag gets cleared (during initial commit for inactive pipes,
during the first userspace commit for active pipes), we
will naturally recompute all the sagv related state.
Ville Syrjälä [Wed, 26 Mar 2025 16:25:42 +0000 (18:25 +0200)]
drm/i915: Make intel_bw_modeset_checks() internal to intel_bw_atomic_check()
Now that all the sagv computation has been moved from the
skl+ watermark code into intel_bw_atomic_check() there is
no point in calling intel_bw_modeset_checks() before the
wm computation. Hide it within intel_bw_atomic_check().
Ville Syrjälä [Wed, 26 Mar 2025 16:25:41 +0000 (18:25 +0200)]
drm/i915: Make intel_bw_check_sagv_mask() internal to intel_bw.c
The only thing between the current intel_bw_check_sagv_mask() call
site and intel_bw_atomic_check() is skl_wm_add_affected_planes()
which no longer depends on the sagv mask, so we can make life
a lot less confusing by calling intel_bw_check_sagv_mask() from
intel_bw_atomic_check() instead.
Ville Syrjälä [Wed, 26 Mar 2025 16:25:40 +0000 (18:25 +0200)]
drm/i915: Extract intel_bw_check_sagv_mask()
Move the bw_state->pipe_sagv_reject computation into intel_bw.c
where it belongs.
Previously we had a complicated dance between watermarks and
sagv which required this to be computed earlier, but that was
changed in commit 5e8146251f7b ("extract intel_bw_check_sagv_mask()")
which allows the whole thing to be cleaned up quite a bit.
Ville Syrjälä [Wed, 26 Mar 2025 16:25:39 +0000 (18:25 +0200)]
drm/i915: Extract intel_bw_modeset_checks()
Pull the new_bw_state->active_pipes computation out from
intel_compute_sagv_mask() and move it into the intel_bw.c
(which is arguably the correct place for it).
Ville Syrjälä [Wed, 26 Mar 2025 16:25:38 +0000 (18:25 +0200)]
drm/i915: Drop force_check_qgv
Remove the force_check_qgv flag and just fill the pipe_sagv_reject
bitmask properly during readout. This will cause the initial commit
to re-enable SAGV if possible.
Ville Syrjälä [Wed, 26 Mar 2025 16:25:37 +0000 (18:25 +0200)]
drm/i915: Flag even inactive crtcs as "inherited"
I want to use the crtc_state->inherited flag to clean up some
of the early SAGV handling. To make that work nicely I need to
flag even the inactive crtcs as "inherited".
Since we can't expect user space to perform any real commits
on inactive crtcs we'll clear the flag already during
initial_commit().
Ville Syrjälä [Wed, 26 Mar 2025 16:25:36 +0000 (18:25 +0200)]
drm/i915: Do more bw readout
Update a bunch of bw related stuff during readout:
- bw_state->dbuf_bw possible now that the wm readout
has given us access to the plane ddb data
- cdclk_state->bw_min_cdclk
Ville Syrjälä [Wed, 26 Mar 2025 16:25:35 +0000 (18:25 +0200)]
drm/i915: Avoid triggering unwanted cdclk changes due to dbuf bandwidth changes
Currently intel_bw_calc_min_cdclk() always adds the bw_state
to the atomic state. Not only does it result in potentially
redundant work later, it's also currently causing unwanted cdclk
changes during driver load.
Check if the dbuf bw is actually changing before we decide to
pull in the bw state.
Ville Syrjälä [Wed, 26 Mar 2025 16:25:31 +0000 (18:25 +0200)]
drm/i915: Drop the cached per-pipe min_cdclk[] from bw state
intel_bw_crtc_min_cdclk() only depends on the pipe data rate,
which we already have stashed in bw_state->data_rate[]. So
stashing the resulting min_cdclk[] as well is redundant. Get
rid of it.
Ville Syrjälä [Thu, 6 Mar 2025 21:07:40 +0000 (23:07 +0200)]
drm/i915/dp: Reject HBR3 when sink doesn't support TPS4
According to the DP spec TPS4 is mandatory for HBR3. We have
however seen some broken eDP sinks that violate this and
declare support for HBR3 without TPS4 support.
At least in the case of the icl Dell XPS 13 7390 this results
in an unstable output.
Reject HBR3 when TPS4 supports is unavailable on the sink.
v2: Leave breadcrumbs in dmesg to avoid head scratching (Jani)
Jouni Högander [Mon, 31 Mar 2025 09:07:47 +0000 (12:07 +0300)]
drm/i915/psr: Prevent DP Panel Replay as well when CRC is enable
We are seeing timeouts in opening CRC fd when testing on setup where DP
Panel Replay can be enabled. Fix these by checking if CRC is enabled for DP
Panel Replay as well.
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