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Florian Krohm [Sat, 4 Aug 2012 04:25:30 +0000 (04:25 +0000)]

Fix a bug in insn selection. For some reason Iop_1UtoXYZ did no
zero-extension. That is essential, as not all computation is donw
using 8-byte values.
For example
- do a 64-bit computation in r1; assume leftmost 4 bytes != 0
- do a 32-bit computation in r1; leftmost 4 bytes are untouched != 0
- do 32to1 on r1; rightmost 4 bytes == 1; leftmost 4 bytes != 0
- do 1Uto64 on r1
Without zero-extension r1 will contain a value that is not boolean

git-svn-id: svn://svn.valgrind.org/vex/trunk@2458

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Florian Krohm [Fri, 3 Aug 2012 18:41:58 +0000 (18:41 +0000)]

Add IR debugging aid.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2457

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Florian Krohm [Fri, 3 Aug 2012 18:35:39 +0000 (18:35 +0000)]

Support cu12 insn. Part of fixing #289839.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2456

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Florian Krohm [Fri, 3 Aug 2012 00:42:18 +0000 (00:42 +0000)]

Fix a bug in insn selection. Though shalt not modify the
register returned by s390_isel_XYZ_expr...

git-svn-id: svn://svn.valgrind.org/vex/trunk@2455

commit | commitdiff | tree

Philippe Waroquiers [Wed, 1 Aug 2012 22:04:13 +0000 (22:04 +0000)]

VEX part (remove --vex-iropt-precise-memory-exns, add --vex-iropt-register-updates)

git-svn-id: svn://svn.valgrind.org/vex/trunk@2454

commit | commitdiff | tree

Julian Seward [Wed, 1 Aug 2012 20:05:42 +0000 (20:05 +0000)]

Implement VCVT.F32.{S,U}32 S[d], S[d], #frac_bits. Fixes #287175.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2453

commit | commitdiff | tree

Florian Krohm [Sat, 28 Jul 2012 22:18:32 +0000 (22:18 +0000)]

Add support for the CU42 insn. Part of fixing bugzilla #289839.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2452

commit | commitdiff | tree

Florian Krohm [Fri, 27 Jul 2012 20:55:01 +0000 (20:55 +0000)]

Non-functional change. Fix some overly long lines and such..

git-svn-id: svn://svn.valgrind.org/vex/trunk@2451

commit | commitdiff | tree

Florian Krohm [Thu, 26 Jul 2012 02:37:49 +0000 (02:37 +0000)]

Upon decode failure set the guest_IA to the address of the insn that
could not be decoded (current insn). Otherwise, a wrong address will be
reported in the complaint.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2450

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Florian Krohm [Thu, 26 Jul 2012 02:01:50 +0000 (02:01 +0000)]

Clean up IR construction for insns that do not have straight-line
internal control flow. Introduce a few new convenience functions: iterate,
iterate_if, next_insn_if that are now used to build IR for insns with implicit
loops. These functions behave like if_condition_goto, except they do
not terminate the super block and do not call put_IA(next insn). Previously,
the guest_IA was assigned possibly several times for such insn. Now we do
it exactly once as it should be. This improves complaints for cu21 which was
the motivation behind this patch.
As a side effect insns with an implicit loop no longer terminate the super
block. All calls to dummy_put_IA have been eliminated.
No changes in runtime performance were observed.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2449

commit | commitdiff | tree

Florian Krohm [Wed, 25 Jul 2012 17:10:49 +0000 (17:10 +0000)]

Change IR generation for MVCLE to not generate cc=3. This should have been
included in r2446, but was not obvious to spot.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2448

commit | commitdiff | tree

Josef Weidendorfer [Wed, 25 Jul 2012 09:36:54 +0000 (09:36 +0000)]

Fix bug 303963.

Emulation of PCMPxSTRx mode 0x0C was wrong
for searching an empty needle in an empty haystack.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2447

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Florian Krohm [Wed, 25 Jul 2012 00:52:21 +0000 (00:52 +0000)]

Change IR generation for SRST, CLST, and CLCLE to not generate cc=3.
Two reasons:
(1) Consistency in implementation (we don't generate cc=3 for "translate",
   "convert to unicode" and possibly other insns)
(2) There is nothing to be gained. A program that does not handle cc=3
    correctly (by looping back to the insn that generated it) may exhibit
    unpredictable behaviours. And there is no way for us to match that (as
    we cannot know when hardware decides to interrupt the insn). So why
    add complexity for that.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2446

commit | commitdiff | tree

Florian Krohm [Tue, 24 Jul 2012 21:06:34 +0000 (21:06 +0000)]

Use always_goto_and_chase for consistency with other "translate" insns.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2445

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Florian Krohm [Mon, 23 Jul 2012 18:03:47 +0000 (18:03 +0000)]

Back out special handling for opcode 00 (VEX r2189).
This was added based on the following analysis at the time:
(1) during decoding a sequence of insns we run into a 00 opcode (as that
    opcode is sometimes used on purpose to force an abort)
(2) #1 only happens when chasing through unconditional gotos
(3) the path that was decoded in #1 would not be executed because an earlier
    side exit in the super block was taken

But chasing through an unconditional branch should not reach an insn that is
not reached at execution time, because
(a) conditional gotos are supposed to terminate a superblock
(b) side exits that appear in the IR of complex insns will transfer control
    to the very same address (for insns that have implicit loops) and/or to
    the address that immediately follows the current insn (fall through)

Therefore, the special handling of opcode 00 was just fighting the
symptom but not the cause.
Most likely a super block was not correctly terminated.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2444

commit | commitdiff | tree

Florian Krohm [Sat, 21 Jul 2012 20:32:57 +0000 (20:32 +0000)]

Change logic in computed gotos to use if_condition_goto_computed
instead of if_not_condition_goto_computed. Hide the implementation
detail of inverting the condition in if_condition_goto_computed and
fix the call sites. This is clearer as it better matches the semantic
description in the POP.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2443

commit | commitdiff | tree

Florian Krohm [Sat, 21 Jul 2012 17:41:36 +0000 (17:41 +0000)]

Add support for the CU24 insn (s390x). Part of fixing #289839.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2442

commit | commitdiff | tree

Florian Krohm [Fri, 20 Jul 2012 00:06:35 +0000 (00:06 +0000)]

Add support for the CU21 instruction (s390x).

git-svn-id: svn://svn.valgrind.org/vex/trunk@2441

commit | commitdiff | tree

Florian Krohm [Thu, 19 Jul 2012 17:22:33 +0000 (17:22 +0000)]

Handle Iop_32to1 in the amd64 insn selector.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2440

commit | commitdiff | tree

Florian Krohm [Thu, 19 Jul 2012 14:54:03 +0000 (14:54 +0000)]

Fix disassembly for insns using the RRF_M0RERE format.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2439

commit | commitdiff | tree

Julian Seward [Wed, 18 Jul 2012 11:48:23 +0000 (11:48 +0000)]

eqIRConst: handle Ico_V256.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2438

commit | commitdiff | tree

Petar Jovanovic [Mon, 16 Jul 2012 14:25:05 +0000 (14:25 +0000)]

Add more debug print information for the instructions for MIPS.

Extend debug info output for the guest instructions. Useful for debugging.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2437

commit | commitdiff | tree

Julian Seward [Mon, 16 Jul 2012 08:35:31 +0000 (08:35 +0000)]

Fix incorrect instruction decoding for MOVBE. Followup fix for r2435.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2436

commit | commitdiff | tree

Julian Seward [Sun, 15 Jul 2012 10:11:10 +0000 (10:11 +0000)]

Implement MOVBE. Fixes #302287.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2435

commit | commitdiff | tree

Florian Krohm [Sun, 15 Jul 2012 02:25:55 +0000 (02:25 +0000)]

Move helper functions to guest_s390_helpers.c for consistency with
other frontends.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2434

commit | commitdiff | tree

Julian Seward [Sat, 14 Jul 2012 14:31:17 +0000 (14:31 +0000)]

Handle UD2 a bit better. This change causes Vex to decode UD2 like
any other instruction -- so it doesn't complain -- but Valgrind still
complains when synthesising the SIGILL for the guest. Marginally less
confusing than it was before.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2433

commit | commitdiff | tree

Julian Seward [Sat, 14 Jul 2012 14:21:56 +0000 (14:21 +0000)]

Get rid of gcc warnings about uninitialised variables in the arm front end.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2432

commit | commitdiff | tree

Julian Seward [Sat, 14 Jul 2012 14:20:00 +0000 (14:20 +0000)]

Implement VCMPNGESS (and other laneages: SD, PD, PS). Fixes #302578.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2431

commit | commitdiff | tree

Julian Seward [Sat, 14 Jul 2012 09:18:02 +0000 (09:18 +0000)]

Increase max allowed pre-allocation (vreg-ised) block size from 10000
to 15000. In very extreme circumstances the JIT pipeline can create
huge blocks. Fixes #303250, at least for the time being.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2430

commit | commitdiff | tree

Julian Seward [Sat, 14 Jul 2012 08:22:13 +0000 (08:22 +0000)]

ppc front end: fnmadd, fnmsub, fnmadds, fnmsubs: don't negate the
result when it is a NaN. Fixes #302370. (Carl Love, carll@us.ibm.com)

git-svn-id: svn://svn.valgrind.org/vex/trunk@2429

commit | commitdiff | tree

Florian Krohm [Fri, 13 Jul 2012 14:13:06 +0000 (14:13 +0000)]

Use vpanic, not vassert, you silly.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2428

commit | commitdiff | tree

Florian Krohm [Fri, 13 Jul 2012 13:41:41 +0000 (13:41 +0000)]

Use a proper type for sign_mask.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2427

commit | commitdiff | tree

Florian Krohm [Fri, 13 Jul 2012 12:48:39 +0000 (12:48 +0000)]

Remove redundant break statements.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2426

commit | commitdiff | tree

Julian Seward [Wed, 11 Jul 2012 16:46:47 +0000 (16:46 +0000)]

Implement (T1) SMMUL{R}. Fixes #300140. (Evgeniy Stepanov,
eugeni.stepanov@gmail.com) w/ fixes.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2425

commit | commitdiff | tree

Julian Seward [Wed, 11 Jul 2012 13:19:10 +0000 (13:19 +0000)]

ARM: Implement QADD and QSUB. Fixes #286917.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2424

commit | commitdiff | tree

Julian Seward [Tue, 10 Jul 2012 21:41:01 +0000 (21:41 +0000)]

Add Iop_CmpEQ16x8 to the set of known dependency-breakers. Fixes #290006.
(Alexey Samsonov, samsonov@google.com)

git-svn-id: svn://svn.valgrind.org/vex/trunk@2423

commit | commitdiff | tree

Julian Seward [Tue, 10 Jul 2012 16:41:46 +0000 (16:41 +0000)]

Comment/formatting only change, to clarify semantics w.r.t.
relationship between guards and return temporaries from dirty helper
calls.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2422

commit | commitdiff | tree

Philippe Waroquiers [Fri, 6 Jul 2012 21:56:53 +0000 (21:56 +0000)]

fix 303116 Add support for the POWER instruction popcntb (VEX part)
patch from carll@us.ibm.com

git-svn-id: svn://svn.valgrind.org/vex/trunk@2421

commit | commitdiff | tree

Florian Krohm [Thu, 5 Jul 2012 22:05:42 +0000 (22:05 +0000)]

Make the IR sanity checker complain about dirty helpers that return
a value and are executed under a condition. That case is not handled
properly and will cause asserts down the road. As pointed out by Julian.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2420

commit | commitdiff | tree

Julian Seward [Fri, 29 Jun 2012 16:26:17 +0000 (16:26 +0000)]

* add folding rules for CmpNE32(x,x) and CmpEQ32(x,x),
  apparently popular on ARM

* make the printer-outer of missed opportunities be controllable
  by --vex-iropt-verbosity=, and make it not cause sameIRExprs
  to assert

(Should be 2 separate commits really)

git-svn-id: svn://svn.valgrind.org/vex/trunk@2419

commit | commitdiff | tree

Julian Seward [Fri, 29 Jun 2012 15:36:44 +0000 (15:36 +0000)]

Fold some long lines (formatting-only change).

git-svn-id: svn://svn.valgrind.org/vex/trunk@2418

commit | commitdiff | tree

Julian Seward [Fri, 29 Jun 2012 15:33:09 +0000 (15:33 +0000)]

Add folding rules for
CmpEQ32x4 V256to64_0 V256to64_1 V256to64_2 V256to64_3

git-svn-id: svn://svn.valgrind.org/vex/trunk@2417

commit | commitdiff | tree

Julian Seward [Fri, 29 Jun 2012 15:28:24 +0000 (15:28 +0000)]

Add a new IRConst kind -- V256 -- containing an abbreviated vector
immediate with 1 bit per byte, in the style of V128. This is so we
can actually write constants of type V256, which is necessary for some
Memcheck instrumentation of 256 bit primops.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2416

commit | commitdiff | tree

Julian Seward [Fri, 29 Jun 2012 14:44:44 +0000 (14:44 +0000)]

Add some constant folding rules for V128 and V256 types.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2415

commit | commitdiff | tree

Julian Seward [Wed, 27 Jun 2012 10:27:13 +0000 (10:27 +0000)]

Comment-only change re findSSECmpOp.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2414

commit | commitdiff | tree

Julian Seward [Mon, 25 Jun 2012 07:58:53 +0000 (07:58 +0000)]

Enable AVX by default, on processors that support it.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2413

commit | commitdiff | tree

Julian Seward [Mon, 25 Jun 2012 07:46:18 +0000 (07:46 +0000)]

Add IR ops Iop_CmpNEZ32x8 and Iop_CmpNEZ64x4, needed for Memcheck
instrumentation of 256 bit vector arithmetic.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2412

commit | commitdiff | tree

Julian Seward [Mon, 25 Jun 2012 07:40:54 +0000 (07:40 +0000)]

Handle a couple more AVX floating point comparison cases.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2411

commit | commitdiff | tree

Julian Seward [Sun, 24 Jun 2012 15:11:38 +0000 (15:11 +0000)]

More AVX insns:

VAESIMC xmm2/m128, xmm1 = VEX.128.66.0F38.WIG DB /r
VAESENC xmm3/m128, xmm2, xmm1 = VEX.128.66.0F38.WIG DC /r
VAESENCLAST xmm3/m128, xmm2, xmm1 = VEX.128.66.0F38.WIG DD /r
VAESDEC xmm3/m128, xmm2, xmm1 = VEX.128.66.0F38.WIG DE /r
VAESDECLAST xmm3/m128, xmm2, xmm1 = VEX.128.66.0F38.WIG DF /r
VPCLMULQDQ imm8, xmm3/m128,xmm2,xmm1
VAESKEYGENASSIST imm8, xmm2/m128, xmm1 = VEX.128.66.0F3A.WIG DF /r

(Jakub Jelinek, jakub@redhat.com), #273475 comments 138 and 139.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2410

commit | commitdiff | tree

Julian Seward [Sun, 24 Jun 2012 14:57:59 +0000 (14:57 +0000)]

More AVX insns:

VMOVDDUP ymm2/m256, ymm1 = VEX.256.F2.0F.WIG /12 r
VMOVLPS m64, xmm1, xmm2 = VEX.NDS.128.0F.WIG 12 /r
VMOVLPS xmm1, m64 = VEX.128.0F.WIG 13 /r
VRCPSS xmm3/m64(E), xmm2(V), xmm1(G) = VEX.NDS.LIG.F3.0F.WIG 53 /r
VRCPPS xmm2/m128(E), xmm1(G) = VEX.NDS.128.0F.WIG 53 /r
VRCPPS ymm2/m256(E), ymm1(G) = VEX.NDS.256.0F.WIG 53 /r
VPSADBW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG F6 /r
VPSIGNB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 08 /r
VPSIGNW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 09 /r
VPSIGND xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 0A /r
VPMULHRSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 0B /r
VBROADCASTF128 m128, ymm1 = VEX.256.66.0F38.WIG 1A /r
VPEXTRW = VEX.128.66.0F3A.W0 15 /r ib

(Jakub Jelinek, jakub@redhat.com), #273475 comment 137.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2409

commit | commitdiff | tree

Julian Seward [Sun, 24 Jun 2012 14:26:30 +0000 (14:26 +0000)]

More AVX insns:

VPACKSSWB r/m, rV, r ::: r = QNarrowBin16Sto8Sx16(rV, r/m)
VPAVGB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E0 /r
VPAVGW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E3 /r
VPADDSB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG EC /r
VPADDSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG ED /r
VPHADDW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 01 /r
VPHADDD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 02 /r
VPHADDSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 03 /r
VPMADDUBSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 04 /r
VPHSUBW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 05 /r
VPHSUBD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 06 /r
VPHSUBSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 07 /r
VPABSB xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 1C /r
VPABSW xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 1D /r
VPMOVSXBQ xmm2/m16, xmm1 = VEX.128.66.0F38.WIG 22 /r
VPMOVSXWQ xmm2/m32, xmm1 = VEX.128.66.0F38.WIG 24 /r
VPACKUSDW = VEX.NDS.128.66.0F38.WIG 2B /r
VPMOVZXBQ = VEX.128.66.0F38.WIG 32 /r
VPMOVZXWQ xmm2/m32, xmm1 = VEX.128.66.0F38.WIG 34 /r
VPMOVZXDQ xmm2/m64, xmm1 = VEX.128.66.0F38.WIG 35 /r
VMPSADBW = VEX.NDS.128.66.0F3A.WIG 42 /r ib

(Jakub Jelinek, jakub@redhat.com), #273475 comment 136.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2408

commit | commitdiff | tree

Julian Seward [Sun, 24 Jun 2012 14:00:27 +0000 (14:00 +0000)]

Even more AVX isns:

VMOVHPS m64, xmm1, xmm2 = VEX.NDS.128.0F.WIG 16 /r
VMOVHPS xmm1, m64 = VEX.128.0F.WIG 17 /r
VMOVNTPD xmm1, m128 = VEX.128.66.0F.WIG 2B /r
VMOVNTPS xmm1, m128 = VEX.128.0F.WIG 2B /r
VMOVNTPD ymm1, m256 = VEX.256.66.0F.WIG 2B /r
VMOVNTPS ymm1, m256 = VEX.256.0F.WIG 2B /r
VMOVMSKPD xmm2, r32 = VEX.128.66.0F.WIG 50 /r
VMOVMSKPD ymm2, r32 = VEX.256.66.0F.WIG 50 /r
VMOVMSKPS xmm2, r32 = VEX.128.0F.WIG 50 /r
VMOVMSKPS ymm2, r32 = VEX.256.0F.WIG 50 /r
VMINPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 5D /r
VMINPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 5D /r
VMINPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 5D /r
VMAXPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 5F /r
VMAXPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 5F /r
VMAXPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 5F /r
VMOVNTDQ ymm1, m256 = VEX.256.66.0F.WIG E7 /r
VMASKMOVDQU xmm2, xmm1 = VEX.128.66.0F.WIG F7 /r
VMOVNTDQA m128, xmm1 = VEX.128.66.0F38.WIG 2A /r

(Jakub Jelinek, jakub@redhat.com), #273475 comment 135.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2407

commit | commitdiff | tree

Julian Seward [Sun, 24 Jun 2012 13:44:17 +0000 (13:44 +0000)]

Even more AVX insns:

VCVTSD2SI xmm1/m32, r32 = VEX.LIG.F2.0F.W0 2D /r
VCVTSD2SI xmm1/m64, r64 = VEX.LIG.F2.0F.W1 2D /r
VCVTSS2SI xmm1/m32, r32 = VEX.LIG.F3.0F.W0 2D /r
VCVTSS2SI xmm1/m64, r64 = VEX.LIG.F3.0F.W1 2D /r
VHADDPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.F2.0F.WIG 7C /r
VHSUBPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.F2.0F.WIG 7D /r
VHADDPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.F2.0F.WIG 7C /r
VHSUBPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.F2.0F.WIG 7D /r
VHADDPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 7C /r
VHSUBPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 7D /r
VHADDPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 7C /r
VHSUBPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 7D /r
VLDDQU m256, ymm1 = VEX.256.F2.0F.WIG F0 /r
VLDDQU m128, xmm1 = VEX.128.F2.0F.WIG F0 /r
VEXTRACTPS imm8, xmm1, r32/m32 = VEX.128.66.0F3A.WIG 17 /r ib
VDPPS imm8, xmm3/m128,xmm2,xmm1 = VEX.NDS.128.66.0F3A.WIG 40 /r ib
VDPPS imm8, ymm3/m128,ymm2,ymm1 = VEX.NDS.128.66.0F3A.WIG 40 /r ib

(Jakub Jelinek, jakub@redhat.com), #273475 comment 134.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2406

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Julian Seward [Sun, 24 Jun 2012 13:27:46 +0000 (13:27 +0000)]

VCMPPD and VCMPPS incremental fix

(Jakub Jelinek, jakub@redhat.com), #273475 comment 133.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2405

commit | commitdiff | tree

Julian Seward [Sun, 24 Jun 2012 12:12:20 +0000 (12:12 +0000)]

Implement more AVX insns:

VPCMPGTB = VEX.NDS.128.66.0F.WIG 64 /r
VPCMPGTW = VEX.NDS.128.66.0F.WIG 65 /r
VCMPPD ymm3/m256(E=argL), ymm2(V=argR), ymm1(G)
VCMPPS xmm3/m128(E=argL), xmm2(V=argR), xmm1(G)
VCMPPS ymm3/m256(E=argL), ymm2(V=argR), ymm1(G)
VADDSUBPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D0 /r
VADDSUBPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG D0 /r
VADDSUBPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.F2.0F.WIG D0 /r
VADDSUBPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.F2.0F.WIG D0 /r
VPMADDWD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG F5 /r
VPMULDQ xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.WIG 28 /r

(Jakub Jelinek, jakub@redhat.com), #273475 comment 132.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2404

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Julian Seward [Sun, 24 Jun 2012 11:09:37 +0000 (11:09 +0000)]

VROUND{PS,PD}: fix incorrect comments.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2403

commit | commitdiff | tree

Petar Jovanovic [Fri, 22 Jun 2012 12:36:19 +0000 (12:36 +0000)]

Fix for incorrectly passed params to IRExpr_Mux0X in MIPS port.

Input params to IRExpr_Mux0X have swapped positions in a few places inside
disInstr_MIPS_WRK(). This patch fixes none/tests/mips32/MoveIns.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2402

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Julian Seward [Fri, 22 Jun 2012 09:27:54 +0000 (09:27 +0000)]

Implement (inexplicably missing) UHADD16.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2401

commit | commitdiff | tree

Julian Seward [Thu, 21 Jun 2012 09:17:58 +0000 (09:17 +0000)]

Add support for

VPSUBSB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E8 /r
VPSUBSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E9 /r
VROUNDPS imm8, xmm3/m128, xmm2, xmm1
VROUNDPS imm8, ymm3/m256, ymm2, ymm1
VROUNDPD imm8, xmm3/m128, xmm2, xmm1
VROUNDPD imm8, ymm3/m256, ymm2, ymm1
VROUNDSS imm8, xmm3/m32, xmm2, xmm1
VROUNDSD imm8, xmm3/m64, xmm2, xmm1

(Jakub Jelinek, jakub@redhat.com), #273475 comment 130.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2400

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Julian Seward [Thu, 21 Jun 2012 09:08:19 +0000 (09:08 +0000)]

Add support for

VPSRLW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D1 /r
VPSRLD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D2 /r
VPSRLQ xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D3 /r
VPSRAW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E1 /r
VPSRAD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E2 /r
VPSLLW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG F1 /r
VPSLLD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG F2 /r
VPSLLQ xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG F3 /r
VBLENDVPS xmmG, xmmE/memE, xmmV, xmmIS4
VBLENDVPS ymmG, ymmE/memE, ymmV, ymmIS4
VBLENDVPD xmmG, xmmE/memE, xmmV, xmmIS4
VBLENDVPD ymmG, ymmE/memE, ymmV, ymmIS4

(Jakub Jelinek, jakub@redhat.com), #273475 comment 129.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2399

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Julian Seward [Thu, 21 Jun 2012 08:53:48 +0000 (08:53 +0000)]

Add support for

VTESTPS xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 0E /r
VTESTPS ymm2/m256, ymm1 = VEX.256.66.0F38.WIG 0E /r
VTESTPD xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 0F /r
VTESTPD ymm2/m256, ymm1 = VEX.256.66.0F38.WIG 0F /r
VPTEST xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 17 /r
VPTEST ymm2/m256, ymm1 = VEX.256.66.0F38.WIG 17 /r

(Jakub Jelinek, jakub@redhat.com), #273475 comment 127.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2398

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Julian Seward [Thu, 21 Jun 2012 08:34:19 +0000 (08:34 +0000)]

Fix incorrect implementation of VPERMILP{S,D} variable form.
(Jakub Jelinek, jakub@redhat.com), #273475 comment 128.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2397

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Petar Jovanovic [Wed, 20 Jun 2012 17:53:32 +0000 (17:53 +0000)]

Moving Iop_F64toI32S to correct (binary ops) place in iselWordExpr_R_wrk.

In a previous commit (r2393), a break has been misplaced and caused two issues,
and that revelead that Iop_F64toI32S was in the wrong (unary op) case.
This fixes none/tests/mips32/round and memcheck/tests/vcpu_fnfns for MIPS.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2396

commit | commitdiff | tree

Julian Seward [Wed, 20 Jun 2012 11:46:19 +0000 (11:46 +0000)]

Implement

VPERMILPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.W0 0C /r
VPERMILPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.W0 0C /r
VPERMILPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F38.W0 0D /r
VPERMILPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.W0 0D /r

git-svn-id: svn://svn.valgrind.org/vex/trunk@2395

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Julian Seward [Wed, 20 Jun 2012 10:21:05 +0000 (10:21 +0000)]

Add support for

VMOVSLDUP xmm2/m128, xmm1 = VEX.NDS.128.F3.0F.WIG 12 /r
VMOVSLDUP ymm2/m256, ymm1 = VEX.NDS.256.F3.0F.WIG 12 /r
VMOVSHDUP xmm2/m128, xmm1 = VEX.NDS.128.F3.0F.WIG 16 /r
VMOVSHDUP ymm2/m256, ymm1 = VEX.NDS.256.F3.0F.WIG 16 /r

VMOVSS xmm3, xmm2, xmm1 = VEX.LIG.F3.0F.WIG 10 /r
VMOVSS xmm3, xmm2, xmm1 = VEX.LIG.F3.0F.WIG 11 /r

VPSLLW imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 71 /6 ib
VPSRAD imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 72 /4 ib

(Jakub Jelinek, jakub@redhat.com), #273475 comments 121, 122, 124

git-svn-id: svn://svn.valgrind.org/vex/trunk@2394

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Julian Seward [Tue, 19 Jun 2012 16:33:47 +0000 (16:33 +0000)]

Add some missing breaks as spotted by BEAM.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2393

commit | commitdiff | tree

Julian Seward [Tue, 19 Jun 2012 13:29:00 +0000 (13:29 +0000)]

s390_insn_cdas_emit: comment out unused variable r3p1
(a relative of C3PO, perhaps?)

git-svn-id: svn://svn.valgrind.org/vex/trunk@2392

commit | commitdiff | tree

Julian Seward [Tue, 19 Jun 2012 06:57:59 +0000 (06:57 +0000)]

Move new 256-bit FP Iops to a better place.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2391

commit | commitdiff | tree

Julian Seward [Mon, 18 Jun 2012 23:15:16 +0000 (23:15 +0000)]

More AVX insns:

VMOVUPS ymm2/m256, ymm1 = VEX.256.0F.WIG 10 /r
VSQRTSS xmm3/m64(E), xmm2(V), xmm1(G) = VEX.NDS.LIG.F3.0F.WIG 51 /r
VSQRTPS xmm2/m128(E), xmm1(G) = VEX.NDS.128.0F.WIG 51 /r
VSQRTPS ymm2/m256(E), ymm1(G) = VEX.NDS.256.0F.WIG 51 /r
VSQRTPD xmm2/m128(E), xmm1(G) = VEX.NDS.128.66.0F.WIG 51 /r
VSQRTPD ymm2/m256(E), ymm1(G) = VEX.NDS.256.66.0F.WIG 51 /r
VRSQRTSS xmm3/m64(E), xmm2(V), xmm1(G) = VEX.NDS.LIG.F3.0F.WIG 52 /r
VRSQRTPS xmm2/m128(E), xmm1(G) = VEX.NDS.128.0F.WIG 52 /r
VRSQRTPS ymm2/m256(E), ymm1(G) = VEX.NDS.256.0F.WIG 52 /r
VZEROALL = VEX.256.0F.WIG 77
VMOVDQU ymm1, ymm2/m256 = VEX.256.F3.0F.WIG 7F
VCVTPS2PD xmm2/m128, ymm1 = VEX.256.0F.WIG 5A /r
VCVTPS2DQ ymm2/m256, ymm1 = VEX.256.66.0F.WIG 5B /r
VCVTTPS2DQ xmm2/m128, xmm1 = VEX.128.F3.0F.WIG 5B /r
VCVTTPS2DQ ymm2/m256, ymm1 = VEX.256.F3.0F.WIG 5B /r
VCVTDQ2PS xmm2/m128, xmm1 = VEX.128.0F.WIG 5B /r
VCVTDQ2PS ymm2/m256, ymm1 = VEX.256.0F.WIG 5B /r
VCVTTPD2DQ xmm2/m128, xmm1 = VEX.128.66.0F.WIG E6 /r
VCVTTPD2DQ ymm2/m256, xmm1 = VEX.256.66.0F.WIG E6 /r
VCVTPD2DQ xmm2/m128, xmm1 = VEX.128.F2.0F.WIG E6 /r
VCVTPD2DQ ymm2/m256, xmm1 = VEX.256.F2.0F.WIG E6 /r

(Jakub Jelinek, jakub@redhat.com). #273475 comments 115, 116.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2390

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Julian Seward [Mon, 18 Jun 2012 22:09:33 +0000 (22:09 +0000)]

Remove incorrect masking of the imm8 in VSHUFPD.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2389

commit | commitdiff | tree

Julian Seward [Mon, 18 Jun 2012 15:01:30 +0000 (15:01 +0000)]

More AVX insns:

VMOVUPD ymm1, ymm2/m256 = VEX.256.66.0F.WIG 11 /r
VMOVUPS ymm1, ymm2/m256 = VEX.256.0F.WIG 11 /r
VCOMISD xmm2/m64, xmm1 = VEX.LIG.66.0F.WIG 2F /r
VPCMPGTD r/m, rV, r ::: r = rV `>s-by-32s` r/m
VPMOVSXBD xmm2/m32, xmm1
VPMOVZXBD xmm2/m32, xmm1
VDPPD xmm3/m128,xmm2,xmm1 = VEX.NDS.128.66.0F3A.WIG 41 /r ib

and common up duplication in implementation of PINSRW/VPINSRW.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2388

commit | commitdiff | tree

Julian Seward [Mon, 18 Jun 2012 14:05:52 +0000 (14:05 +0000)]

More AVX insns:

VMOVSD xmm3, xmm2, xmm1 = VEX.LIG.F2.0F.WIG 10 /r
VMOVSD xmm3, xmm2, xmm1 = VEX.LIG.F2.0F.WIG 11 /r
VMOVLPD m64, xmm1, xmm2 = VEX.NDS.128.66.0F.WIG 12 /r
VMOVLPD xmm1, m64 = VEX.128.66.0F.WIG 13 /r
VPINSRW r32/m16, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG C4 /r ib
VSHUFPD imm8, xmm3/m128, xmm2, xmm1, xmm2
VSHUFPD imm8, ymm3/m256, ymm2, ymm1, ymm2
VPERMILPS imm8, xmm2/m128, xmm1 = VEX.128.66.0F3A.WIG 04 /r ib
VBLENDPS imm8, ymm3/m256, ymm2, ymm1
VBLENDPS = VEX.NDS.128.66.0F3A.WIG 0C /r ib
VBLENDPD = VEX.NDS.256.66.0F3A.WIG 0D /r ib
VBLENDPD = VEX.NDS.128.66.0F3A.WIG 0D /r ib
VPBLENDW = VEX.NDS.128.66.0F3A.WIG 0E /r ib
VPINSRB r32/m8, xmm2, xmm1 = VEX.NDS.128.66.0F3A.WIG C4 /r ib

(Jakub Jelinek, jakub@redhat.com). #273475 comment 110.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2387

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Julian Seward [Mon, 18 Jun 2012 13:56:55 +0000 (13:56 +0000)]

More AVX insns:

VBROADCASTSS m32, ymm1 = VEX.256.66.0F38.WIG 18 /r
VPALIGNR imm8, xmm3/m128, xmm2, xmm1

(Jakub Jelinek, jakub@redhat.com). #273475 comment 109.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2386

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Florian Krohm [Fri, 15 Jun 2012 20:55:43 +0000 (20:55 +0000)]

Fix a few issues as reported by the BEAM tool.
Patch by Carl Love (cel@linux.vnet.ibm.com).

git-svn-id: svn://svn.valgrind.org/vex/trunk@2385

commit | commitdiff | tree

Julian Seward [Fri, 15 Jun 2012 15:48:07 +0000 (15:48 +0000)]

Add a CPUID emulation which announces AVX support, but don't enable it
yet.

Add support for the following instructions:

0F 01 D0 = XGETBV
VPUNPCKHQDQ r/m, rV, r ::: r = interleave-hi-64bitses(rV, r/m)
VPSRAW imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 71 /4 ib
VSTMXCSR m32 = VEX.LZ.0F.WIG AE /3
VLDMXCSR m32 = VEX.LZ.0F.WIG AE /2
VPMULHW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG E5 /r
VPERMILPS imm8, ymm2/m256, ymm1 = VEX.256.66.0F3A.W0 04 /r ib

git-svn-id: svn://svn.valgrind.org/vex/trunk@2384

commit | commitdiff | tree

Julian Seward [Thu, 14 Jun 2012 23:32:02 +0000 (23:32 +0000)]

Fill in some missing AVX insns:

VANDPS = VEX.NDS.256.0F.WIG 54 /r
VANDNPD = VEX.NDS.256.66.0F.WIG 55 /r
ANDNPS = VEX.NDS.256.0F.WIG 55 /r
VORPD = VEX.NDS.256.66.0F.WIG 56 /r
VORPS = VEX.NDS.256.0F.WIG 56 /r
VXORPS = VEX.NDS.256.0F.WIG 57 /r
VDIVPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 5E /r

Modified version of a patch by Jakub Jelinek, jakub@redhat.com
(bug 273475 comment 96)

git-svn-id: svn://svn.valgrind.org/vex/trunk@2383

commit | commitdiff | tree

Julian Seward [Thu, 14 Jun 2012 08:51:35 +0000 (08:51 +0000)]

Implement even more insns created by gcc-4.7.0 -mavx -O3.

VMOVHPD m64, xmm1, xmm2 = VEX.NDS.128.66.0F.WIG 16 /r
VMOVAPS ymm2/m256, ymm1 = VEX.256.0F.WIG 28 /r
VCVTPD2PS ymm2/m256, xmm1 = VEX.256.66.0F.WIG 5A /r
VPUNPCKHDQ = VEX.NDS.128.66.0F.WIG 6A /r
VPCMPEQW r/m, rV, r ::: r = rV `eq-by-16s` r/m
VPSUBUSW xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG D9 /r
VCVTDQ2PD xmm2/m128, ymm1 = VEX.256.F3.0F.WIG E6 /r
VPADDB r/m, rV, r ::: r = rV + r/m
VBROADCASTSS m32, xmm1 = VEX.128.66.0F38.W0 18 /r
VPMOVSXBW xmm2/m64, xmm1
VPMOVSXWD xmm2/m64, xmm1
VPMOVSXDQ xmm2/m64, xmm1

git-svn-id: svn://svn.valgrind.org/vex/trunk@2382

commit | commitdiff | tree

Julian Seward [Wed, 13 Jun 2012 11:10:20 +0000 (11:10 +0000)]

Implement even more instructions generated by "gcc-4.7.0 -mavx -O3".
This is the first point at which coverage for -O3 generated code could
be construed as "somewhat usable".

git-svn-id: svn://svn.valgrind.org/vex/trunk@2381

commit | commitdiff | tree

Julian Seward [Tue, 12 Jun 2012 14:59:17 +0000 (14:59 +0000)]

Implement a bunch more AVX instructions generated by "gcc-4.7.0 -mavx -O3":

VPSLLQ imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 73 /6 ib
VPEXTRW imm8, xmm1, reg32 = VEX.128.66.0F.W0 C5 /r ib
VPMINUB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG DA /r
VPMAXUB xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG DE /r
VPMINSW r/m, rV, r ::: r = min-signed16s(rV, r/m)
VPMAXSW r/m, rV, r ::: r = max-signed16s(rV, r/m)
VPMULUDQ xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG F4 /r
VPMINSB r/m, rV, r ::: r = min-signed-8s(rV, r/m)
VPMINUW r/m, rV, r ::: r = min-unsigned-16s(rV, r/m)
VPMINUD r/m, rV, r ::: r = min-unsigned-32s(rV, r/m)
VPMAXSB r/m, rV, r ::: r = max-signed-8s(rV, r/m)
VPMAXUW r/m, rV, r ::: r = max-unsigned-16s(rV, r/m)
VPMAXUD r/m, rV, r ::: r = max-unsigned-32s(rV, r/m)
VPMULLD r/m, rV, r ::: r = mul-32s(rV, r/m)
VPHMINPOSUW xmm2/m128, xmm1 = VEX.128.66.0F38.WIG 41 /r
VPERMILPD imm8, ymm2/m256, ymm1 = VEX.256.66.0F3A.W0 05 /r ib
VPERMILPD imm8, xmm2/m128, xmm1 = VEX.128.66.0F3A.W0 05 /r ib
VPERM2F128 imm8, ymm3/m256, ymm2, ymm1 = VEX.NDS.66.0F3A.W0 06 /r ib
VPEXTRB imm8, xmm2, reg/m8 = VEX.128.66.0F3A.W0 14 /r ib

git-svn-id: svn://svn.valgrind.org/vex/trunk@2380

commit | commitdiff | tree

Julian Seward [Tue, 12 Jun 2012 08:45:39 +0000 (08:45 +0000)]

Make a start at implementing 256-bit AVX instructions generated by
"gcc-4.7.0 -mavx -O3":

VMOVUPD xmm2/m128, xmm1 = VEX.128.66.0F.WIG 10 /r
VMOVUPS xmm2/m128, xmm1 = VEX.128.0F.WIG 10 /r
VUNPCKHPS xmm3/m128, xmm2, xmm1 = VEX.NDS.128.0F.WIG 15 /r
VUNPCKLPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 14 /r
VUNPCKHPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 15 /r
VADDPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 58 /r
VADDPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 58 /r
VADDPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 58 /r
VMULPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 59 /r
VMULPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 59 /r
VMULPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 59 /r
VSUBPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 5C /r
VSUBPD xmm3/m128, xmm2, xmm1 = VEX.NDS.128.66.0F.WIG 5C /r
VSUBPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 5C /r
VDIVPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.0F.WIG 5E /r
VDIVPD ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F.WIG 5E /r
VPSRLQ imm8, xmm2, xmm1 = VEX.NDD.128.66.0F.WIG 73 /2 ib
VPCMPEQQ = VEX.NDS.128.66.0F38.WIG 29 /r
VPCMPGTQ = VEX.NDS.128.66.0F38.WIG 37 /r
VPEXTRQ = VEX.128.66.0F3A.W1 16 /r ib

git-svn-id: svn://svn.valgrind.org/vex/trunk@2379

commit | commitdiff | tree

Julian Seward [Mon, 11 Jun 2012 21:54:58 +0000 (21:54 +0000)]

16-bit Thumb PUSH and POP: fix incorrect assertions.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2378

commit | commitdiff | tree

Petar Jovanovic [Thu, 7 Jun 2012 16:52:41 +0000 (16:52 +0000)]

Small improvement for getIReg on MIPS when reading from r0.

zero register on MIPS is actually a constant, and front end should be aware of
that. MIPS port is currently tracked as bug #270777.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2377

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Julian Seward [Thu, 7 Jun 2012 08:59:53 +0000 (08:59 +0000)]

Merge in a port for mips32-linux, by Petar Jovanovic and Dejan Jevtic,
mips-valgrind@rt-rk.com, Bug 270777.

VEX: new files for mips32.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2376

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Julian Seward [Thu, 7 Jun 2012 08:51:02 +0000 (08:51 +0000)]

Merge in a port for mips32-linux, by Petar Jovanovic and Dejan Jevtic,
mips-valgrind@rt-rk.com, Bug 270777.

VEX: changes to existing files.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2375

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Florian Krohm [Wed, 6 Jun 2012 12:53:14 +0000 (12:53 +0000)]

Fix a copy'n paste error spotted by Julian.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2374

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Florian Krohm [Wed, 6 Jun 2012 02:44:53 +0000 (02:44 +0000)]

Fix debug printing of s390 V-insns. Alu ops and such are 2-address insns

git-svn-id: svn://svn.valgrind.org/vex/trunk@2373

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Florian Krohm [Wed, 6 Jun 2012 02:26:01 +0000 (02:26 +0000)]

Support "compare double ansd swap" insns: CDS, CDSY, and CDSG
VEX bits for fixing bugzilla #291865

git-svn-id: svn://svn.valgrind.org/vex/trunk@2372

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Julian Seward [Mon, 4 Jun 2012 07:38:10 +0000 (07:38 +0000)]

dis_AVX128_E_V_to_G is a special case of
dis_VEX_NDS_128_AnySimdPfx_0F_WIG_simple, so implement the former by
calling the latter.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2371

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Julian Seward [Sun, 3 Jun 2012 23:12:33 +0000 (23:12 +0000)]

Implement
VMOVUPD ymm2/m256, ymm1 = VEX.256.66.0F.WIG 10 /r
VMOVUPD ymm1, ymm2/m256 = VEX.256.66.0F.WIG 11 /r

git-svn-id: svn://svn.valgrind.org/vex/trunk@2370

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Julian Seward [Sun, 3 Jun 2012 23:11:49 +0000 (23:11 +0000)]

Move VEX_HWCAPS_PPC32_DFP to a more logical place.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2369

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Florian Krohm [Sun, 3 Jun 2012 02:10:08 +0000 (02:10 +0000)]

Fix two Binop / Unop mixups.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2368

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Julian Seward [Sat, 2 Jun 2012 23:47:02 +0000 (23:47 +0000)]

POWER Processor decimal FP support, part 5 (VEX side). Bug #299694.
(Carl Love, carll@us.ibm.com and Maynard Johnson, maynardj@us.ibm.com)

This patch adds support for Power Decimal Floating Point (DFP) . This
is the fifth patch set in the series of five to add the DFP
instruction support to Valgrind. Adds support for the ddedpd,
ddedpdq, denbcd, denbcdq, dtstsf, and dtstsfq instructions.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2367

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Florian Krohm [Sat, 2 Jun 2012 20:29:22 +0000 (20:29 +0000)]

Put the Triop member into a separate struct (IRTriop) and link to that
from IRExpr. Reduces size of IRExpr from 40 bytes to 32 bytes on LP64
and from 20 bytes to 16 bytes on ILP32.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2366

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Julian Seward [Sat, 2 Jun 2012 11:55:25 +0000 (11:55 +0000)]

Implement
   VMOVAPD ymm1, ymm2/m256 = VEX.256.66.0F.WIG 29 /r
   VMOVAPS ymm1, ymm2/m256 = VEX.256.0F.WIG 29 /r
   VPADDQ r/m, rV, r ::: r = rV + r/m
   VPSUBW r/m, rV, r ::: r = rV - r/m
   VPSUBQ = VEX.NDS.128.66.0F.WIG FB /r
   VPINSRQ r64/m64, xmm2, xmm1 = VEX.NDS.128.66.0F3A.W1 22 /r ib

git-svn-id: svn://svn.valgrind.org/vex/trunk@2365

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Florian Krohm [Fri, 1 Jun 2012 22:04:27 +0000 (22:04 +0000)]

Fix a cut'n paste error.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2364

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Florian Krohm [Fri, 1 Jun 2012 20:41:24 +0000 (20:41 +0000)]

Put the Qop member into a separate struct (IRQop) and link to that
from IRExpr. Reduces size of IRExpr from 48 to 40 bytes on LP64.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2363

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Julian Seward [Fri, 1 Jun 2012 16:09:50 +0000 (16:09 +0000)]

Enhance the guest state effects notation on IRDirty calls, so as to be
able to describe accesses to arrays of non-consecutive guest state
sections. This is needed to describe the behaviour of FXSAVE and
FXRSTOR in an environment where we also support AVX.

The IRDirty struct has got smaller (112 bytes vs 136 before, for a 64
bit target) whilst holding more information.

The new facility is then used to describe said FXSAVE and FXRSTOR on
amd64. For x86 there is no change since we don't model AVX state for
x86.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2362

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Florian Krohm [Thu, 31 May 2012 15:46:18 +0000 (15:46 +0000)]

Reduce size of an IRStmt from 40 bytes to 32 bytes on LP64
by allocating the details of a PutI statement into a struct
of its own and link to that (as is being done for Dirty and CAS).

These are the VEX bits.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2361

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Florian Krohm [Mon, 28 May 2012 03:10:02 +0000 (03:10 +0000)]

Add forgotten update. Should have been part of r2359.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2360

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Florian Krohm [Mon, 28 May 2012 02:58:19 +0000 (02:58 +0000)]

Cleanup after t-chaining changes.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2359

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