Fortran: Set the vptr of a class typed result.

PR fortran/90076

gcc/fortran/ChangeLog:

* trans-decl.cc (gfc_generate_function_code): Set vptr for
results to declared class type.
* trans-expr.cc (gfc_reset_vptr): Allow to provide the typespec
instead of the expression.
* trans.h (gfc_reset_vptr): Same.

gcc/testsuite/ChangeLog:

* gfortran.dg/class_76.f90: Add declared vtab occurrence.
* gfortran.dg/class_78.f90: New test.

xtensa: constantsynth: Reforge to fix some non-fatal issues

The previous constant synthesis logic had some issues that were non-fatal
but worth considering:

- It didn't work with DFmode literals, because those were cast to SImode
   rather SFmode when splitting into two natural-width words by
   split_double().

- It didn't work with large literals when TARGET_AUTO_LITPOOLS was enabled,
   because those were relaxed MOVI immediates rather references to literal
   pool entries,

- It didn't take into account that when literals with the same RTL
   representation are pooled multiple times within a function, those entries
   are shared (especially important when optimizing for size).

This patch addresses the above issues by making appropriate tweaks to the
constant synthesis logic.

gcc/ChangeLog:

* config/xtensa/xtensa-protos.h (xtensa_constantsynth):
Change the second argument from HOST_WIDE_INT to rtx.
* config/xtensa/xtensa.cc (#include):
Add "context.h" and "pass_manager.h".
(machine_function): Add a new hash_map field "litpool_usage".
(xtensa_constantsynth): Make "src" (the second operand) accept
RTX literal instead of its value, and treat both bare and pooled
SI/SFmode literals equally by bit-exact canonicalization into
CONST_INT RTX internally.  And then, make avoid synthesis if
such multiple identical canonicalized literals are found in same
function when optimizing for size.  Finally, for literals where
synthesis is not possible or has been avoided, re-emit "move"
RTXes with canonicalized ones to increase the chances of sharing
literal pool entries.
* config/xtensa/xtensa.md (split patterns for constant synthesis):
Change to simply invoke xtensa_constantsynth() as mentioned above,
and add new patterns for when TARGET_AUTO_LITPOOLS is enabled.

RISC-V: Add testcases for unsigned .SAT_ADD vector form 8

After the middle-end support the form 8 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 8.

Form 8:
  #define DEF_VEC_SAT_U_ADD_FMT_8(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        out[i] = x > (T)(x + y) ? -1 : (x + y);                        \
      }                                                                \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-29.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-30.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-31.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-32.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_ADD vector form 7

After the middle-end support the form 7 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 7.

Form 7:
  #define DEF_VEC_SAT_U_ADD_FMT_7(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_add_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        out[i] = (T)(x + y) < x ? -1 : (x + y);                        \
      }                                                                \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-25.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-26.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-27.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-28.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_ADD vector form 6

After the middle-end support the form 6 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 6.

Form 6:
  #define DEF_VEC_SAT_U_ADD_FMT_6(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        out[i] = x <= (T)(x + y) ? (x + y) : -1;                       \
      }                                                                \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_ADD vector form 5

After the middle-end support the form 5 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 5.

Form 5:
  #define DEF_VEC_SAT_U_ADD_FMT_5(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_add_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        T ret;                                                         \
        out[i] = __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1;  \
      }                                                                \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-17.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-18.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-19.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-20.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_ADD vector form 4

After the middle-end support the form 4 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 4.

Form 4:
  #define DEF_VEC_SAT_U_ADD_FMT_4(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        T ret;                                                         \
        out[i] = __builtin_add_overflow (x, y, &ret) ? -1 : ret;       \
      }                                                                \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-16.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_ADD vector form 3

After the middle-end support the form 3 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 3.

Form 3:
  #define DEF_VEC_SAT_U_ADD_FMT_3(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        T ret;                                                         \
        T overflow = __builtin_add_overflow (x, y, &ret);              \
        out[i] = (T)(-overflow) | ret;                                 \
      }                                                                \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_ADD vector form 2

After the middle-end support the form 2 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 2.

Form 2:
  #define DEF_VEC_SAT_U_ADD_FMT_2(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        out[i] = (T)(x + y) >= x ? (x + y) : -1;                       \
      }                                                                \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_SUB scalar form 12

After the middle-end support the form 12 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 12.

Form 12:
  #define DEF_SAT_U_SUB_FMT_12(T)                        \
  T __attribute__((noinline))                            \
  sat_u_sub_##T##_fmt_12 (T x, T y)                      \
  {                                                      \
    T ret;                                               \
    bool overflow = __builtin_sub_overflow (x, y, &ret); \
    return !overflow ? ret : 0;                          \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for
testing.
* gcc.target/riscv/sat_u_sub-45.c: New test.
* gcc.target/riscv/sat_u_sub-46.c: New test.
* gcc.target/riscv/sat_u_sub-47.c: New test.
* gcc.target/riscv/sat_u_sub-48.c: New test.
* gcc.target/riscv/sat_u_sub-run-45.c: New test.
* gcc.target/riscv/sat_u_sub-run-46.c: New test.
* gcc.target/riscv/sat_u_sub-run-47.c: New test.
* gcc.target/riscv/sat_u_sub-run-48.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for unsigned .SAT_SUB scalar form 11

After the middle-end support the form 11 of unsigned SAT_SUB and
the RISC-V backend implement the SAT_SUB for vector mode, add
more test case to cover the form 11.

Form 11:
  #define DEF_SAT_U_SUB_FMT_11(T)                        \
  T __attribute__((noinline))                            \
  sat_u_sub_##T##_fmt_11 (T x, T y)                      \
  {                                                      \
    T ret;                                               \
    bool overflow = __builtin_sub_overflow (x, y, &ret); \
    return overflow ? 0 : ret;                           \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper
macro for testing.
* gcc.target/riscv/sat_u_sub-41.c: New test.
* gcc.target/riscv/sat_u_sub-42.c: New test.
* gcc.target/riscv/sat_u_sub-43.c: New test.
* gcc.target/riscv/sat_u_sub-44.c: New test.
* gcc.target/riscv/sat_u_sub-run-41.c: New test.
* gcc.target/riscv/sat_u_sub-run-42.c: New test.
* gcc.target/riscv/sat_u_sub-run-43.c: New test.
* gcc.target/riscv/sat_u_sub-run-44.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

[MAINTAINERS] Update my email address and move to DCO.

Signed-off-by: Ramana Radhakrishnan <ramanara@nvidia.com>
* MAINTAINERS: Update my email address.

Daily bump.

RISC-V: Move mode assertion out of conditional branch in emit_insn

When emitting insns, we have an early assertion to ensure the input
operand's mode and the expanded operand's mode are the same; however, it
does not perform this check if the pattern does not have an explicit
machine mode specifying the operand. In this scenario, it will always
assume that mode = Pmode to correctly satisfy the
maybe_legitimize_operand check, however, there may be problems when
working in 32 bit environments.

Make the assert unconditional and replace it with an internal error for
more descriptive logging

gcc/ChangeLog:

* config/riscv/riscv-v.cc: Move assert out of conditional block

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
Co-authored-by: Robin Dapp <rdapp@ventanamicro.com>

RISC-V: Fix vwsll combine on rv32 targets

On rv32 targets, vwsll_zext1_scalar_<mode> would trigger an ice in
maybe_legitimize_instruction when zero extending a uint32 to uint64 due
to a mismatch between the input operand's mode (DI) and the expanded insn
operand's mode (Pmode == SI). Ensure that mode of the operands match

gcc/ChangeLog:

* config/riscv/autovec-opt.md: Fix mode mismatch

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
Co-authored-by: Robin Dapp <rdapp@ventanamicro.com>

[committed] [RISC-V] Fix wrong patch application

Applied the wrong patch which didn't have the final testsuite adjustment to
skip -Os on the new test.  Fixed thusly.

Pushed to the trunk.

gcc/testsuite
* gcc.target/riscv/zbs-ext-2.c: Do not run for -Os.

aarch64: Add comment about thunderxt81/t83 being aliases

Since these were already aliases just make it clear on that.

gcc/ChangeLog:

* config/aarch64/aarch64-cores.def: Add comment
saying thunderxt81/t83 are aliases of octeontx81/83.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

aarch64: make thunderxt88p1 an alias of thunderxt88

Since r7-6575-g71aba51d6460ff, thunderxt88 has been the same as thunderxt88p1 so let's make
them a true alias and remove the odd variant handling and moves it below thunderxt88.

Bootstrapped and tested on aarch64-linux-gnu with no regressions.

gcc/ChangeLog:

* config/aarch64/aarch64-cores.def (thunderxt88p1): Make an alias of thunderxt88 and
move below thunderxt88.
* config/aarch64/aarch64-tune.md: Regenerate.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

diagnostics: rename tree-diagnostic-path.cc to diagnostic-path.cc

Now that nothing in tree-diagnostic-path.cc uses "tree", this patch
renames it to diagnostic-path.cc and moves it from OBJS to
OBJS-libcommon.

No functional change intended.

gcc/ChangeLog:
* Makefile.in (OBJS): Move selftest-diagnostic-path.o,
selftest-logical-location.o, and tree-diagnostic-path.o to...
(OBJS-libcommon): ...here, renaming tree-diagnostic-path.o to
diagnostic-path.o.
* tree-diagnostic-path.cc: Rename to...
* diagnostic-path.cc: ...this.  Drop include of "tree.h".
(tree_diagnostic_path_cc_tests): Rename to...
(diagnostic_path_cc_tests): ...this.
* selftest-run-tests.cc (selftest::run_tests): Update for above
renaming.
* selftest.h (tree_diagnostic_path_cc_tests): Rename decl to...
(diagnostic_path_cc_tests): ...this.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

diagnostics: eliminate diagnostic_context::m_print_path callback

No functional change intended.

gcc/ChangeLog:
* diagnostic-format-json.cc (diagnostic_output_format_init_json):
Replace clearing of diagnostic_context::m_print_path callback with
setting the path format to DPF_NONE.
* diagnostic-format-sarif.cc
(diagnostic_output_format_init_sarif): Likewise.
* diagnostic.cc (diagnostic_context::show_any_path): Replace call
to diagnostic_context::m_print_path callback with a direct call to
diagnostic_context::print_path.
* diagnostic.h (diagnostic_context::print_path): New decl.
(diagnostic_context::m_print_path): Delete callback.
* tree-diagnostic-path.cc (default_tree_diagnostic_path_printer):
Convert to...
(diagnostic_context::print_path): ...this.
* tree-diagnostic.cc (tree_diagnostics_defaults): Delete
initialization of m_print_path.
* tree-diagnostic.h (default_tree_diagnostic_path_printer): Delete
decl.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

diagnostics: introduce diagnostic-macro-unwinding.h/cc

Eliminate a dependency on "tree" from the code used by
diagnostic_path handling.

No functional change intended.

gcc/ChangeLog:
* Makefile.in (OBJS): Add diagnostic-macro-unwinding.o.

gcc/c-family/ChangeLog:
* c-opts.cc: Replace include of "tree-diagnostic.h" with
"diagnostic-macro-unwinding.h".

gcc/ChangeLog:
* diagnostic-macro-unwinding.cc: New file, with material taken
from tree-diagnostic.cc.
* diagnostic-macro-unwinding.h: New file, with material taken
from tree-diagnostic.h.
* tree-diagnostic-path.cc: Repalce include of "tree-diagnostic.h"
with "diagnostic-macro-unwinding.h".
* tree-diagnostic.cc (struct loc_map_pair): Move to
diagnostic-macro-unwinding.cc.
(maybe_unwind_expanded_macro_loc): Likewise.
(virt_loc_aware_diagnostic_finalizer): Likewise.
* tree-diagnostic.h (virt_loc_aware_diagnostic_finalizer): Move
decl to diagnostic-macro-unwinding.h.
(maybe_unwind_expanded_macro_loc): Likewise.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

diagnostics: eliminate diagnostic_context::m_make_json_for_path

Now that the path-handling code for json_output_format no longer
needs "tree", and thus can be in OBJS-libcommon we can move it
from tree-diagnostic-path.cc to diagnostic-format-json.cc where it
should have been all along.

No functional change intended.

gcc/ChangeLog:
* diagnostic-format-json.cc: Include "diagnostic-path.h" and
"logical-location.h".
(make_json_for_path): Move tree-diagnostic-path.cc's
default_tree_make_json_for_path here, renaming it and making it
static.
(json_output_format::on_end_diagnostic): Replace call of
m_context's m_make_json_for_path callback with a direct call to
make_json_for_path.
* diagnostic.h (diagnostic_context::m_make_json_for_path): Drop
field.
* tree-diagnostic-path.cc: Drop include of "json.h".
(default_tree_make_json_for_path): Rename to make_json_for_path
and move to diagnostic-format-json.cc.
* tree-diagnostic.cc (tree_diagnostics_defaults): Drop
initialization of m_make_json_for_path.
* tree-diagnostic.h (default_tree_make_json_for): Delete decl.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

diagnostics: remove tree usage from tree-diagnostic-path.cc

No functional change intended.

gcc/ChangeLog:
* Makefile.in (OBJS): Add selftest-diagnostic-path.o and
selftest-logical-location.o.
* logical-location.h: Include "label-text.h".
(class logical_location): Update leading comment.
* selftest-diagnostic-path.cc: New file, adapted from
simple-diagnostic-path.cc and from material in
tree-diagnostic-path.cc.
* selftest-diagnostic-path.h: New file, adapted from
simple-diagnostic-path.h and from material in
tree-diagnostic-path.cc.
* selftest-logical-location.cc: New file.
* selftest-logical-location.h: New file.
* tree-diagnostic-path.cc: Remove includes of "tree-pretty-print.h",
"langhooks.h", and "simple-diagnostic-path.h".  Add include of
"selftest-diagnostic-path.h".
(class test_diagnostic_path): Delete, in favor of new
implementation in selftest-diagnostic-path.{h,cc}, which is
directly derived from diagnostic_path, rather than from
simple_diagnostic_path.
(selftest::test_intraprocedural_path): Eliminate tree usage,
via change to test_diagnostic_path, using strings rather than
function_decls for identifying functions in the test.
(selftest::test_interprocedural_path_1): Likewise.
(selftest::test_interprocedural_path_2): Likewise.
(selftest::test_recursion): Likewise.
(selftest::test_control_flow_1): Likewise.
(selftest::test_control_flow_2): Likewise.
(selftest::test_control_flow_3): Likewise.
(selftest::assert_cfg_edge_path_streq): Likewise.
(selftest::test_control_flow_5): Likewise.
(selftest::test_control_flow_6): Likewise.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

diagnostics: eliminate "tree" from diagnostic_{event,path}

This patch eliminates the use of "tree" from diagnostic_{event,path} in
favor of const logical_location *.

No functional change intended.

gcc/analyzer/ChangeLog:
* checker-event.h (checker_event::fndecl): Drop "final" and
"override", converting from a vfunc implementation to a plain
accessor.
* checker-path.cc (checker_path::same_function_p): New.
* checker-path.h (checker_path::same_function_p): New decl.

gcc/ChangeLog:
* diagnostic.cc: Include "logical-location.h".
(diagnostic_path::get_first_event_in_a_function): Fix typo in
leading comment.  Rewrite to use logical_location rather than
tree.  Drop test on stack depth.
(diagnostic_path::interprocedural_p): Rewrite to use
logical_location rather than tree.
(logical_location::function_p): New.
* diagnostic-path.h (diagnostic_event::get_fndecl): Eliminate
vfunc.
(diagnostic_path::same_function_p): New pure virtual func.
* logical-location.h (logical_location::get_name_for_path_output):
New pure virtual func.
* simple-diagnostic-path.cc
(simple_diagnostic_path::same_function_p): New.
(simple_diagnostic_event::simple_diagnostic_event): Initialize
m_logical_loc.
* simple-diagnostic-path.h: Include "tree-logical-location.h".
(simple_diagnostic_event::get_fndecl): Convert from a vfunc
implementation to an accessor.
(simple_diagnostic_event::get_logical_location): Use
m_logical_loc.
(simple_diagnostic_event::m_logical_loc): New field.
(simple_diagnostic_path::same_function_p): New decl.
* tree-diagnostic-path.cc: Move pragma disabling -Wformat-diag to
cover the whole file.
(can_consolidate_events): Add params "path", "ev1_idx", and
"ev2_idx".  Rewrite to use diagnostic_path::same_function_p rather
than tree.
(per_thread_summary::per_thread_summary): Add "path" param
(per_thread_summary::m_path): New field.
(event_range::event_range): Update for conversion of m_fndecl to
m_logical_loc.
(event_range::maybe_add_event): Rename param "idx" to
"new_ev_idx".  Update call to can_consolidate_events to pass in
"m_path", "m_start_idx", and "new_ev_idx".
(event_range::m_fndecl): Replace with...
(event_range::m_logical_loc): ...this.
(path_summary::get_or_create_events_for_thread_id): Pass "path" to
per_thread_summary ctor.
(per_thread_summary::interprocedural_p): Rewrite to use
diagnostic_path::same_function_p rather than tree.
(print_fndecl): Delete.
(thread_event_printer::print_swimlane_for_event_range): Update for
conversion from tree to logical_location.
(default_tree_diagnostic_path_printer): Likewise.
(default_tree_make_json_for_path): Likewise.
* tree-logical-location.cc: Include "intl.h".
(compiler_logical_location::get_name_for_tree_for_path_output):
New.
(tree_logical_location::get_name_for_path_output): New.
(current_fndecl_logical_location::get_name_for_path_output): New.
* tree-logical-location.h
(compiler_logical_location::get_name_for_tree_for_path_output):
New decl.
(tree_logical_location::get_name_for_path_output): New decl.
(current_fndecl_logical_location::get_name_for_path_output): New
decl.

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

diagnostics: move simple_diagnostic_{path,thread,event} to their own .h/cc

As work towards eliminating the dependency on "tree" from
path-printing, move these classes to a new simple-diagnostic-path.h/cc.

No functional change intended.

gcc/analyzer/ChangeLog:
* checker-path.h: Include "simple-diagnostic-path.h".

gcc/ChangeLog:
* Makefile.in (OBJS): Add simple-diagnostic-path.o.
* diagnostic-path.h (class simple_diagnostic_event): Move to
simple-diagnostic-path.h.
(class simple_diagnostic_thread): Likewise.
(class simple_diagnostic_path): Likewise.
* diagnostic.cc (simple_diagnostic_path::simple_diagnostic_path):
Move to simple-diagnostic-path.cc.
(simple_diagnostic_path::num_events): Likewise.
(simple_diagnostic_path::get_event): Likewise.
(simple_diagnostic_path::num_threads): Likewise.
(simple_diagnostic_path::get_thread): Likewise.
(simple_diagnostic_path::add_thread): Likewise.
(simple_diagnostic_path::add_event): Likewise.
(simple_diagnostic_path::add_thread_event): Likewise.
(simple_diagnostic_path::connect_to_next_event): Likewise.
(simple_diagnostic_event::simple_diagnostic_event): Likewise.
(simple_diagnostic_event::~simple_diagnostic_event): Likewise.
* selftest-run-tests.cc (selftest::run_tests): Call
selftest::simple_diagnostic_path_cc_tests.
* selftest.h (selftest::simple_diagnostic_path_cc_tests): New
decl.
* simple-diagnostic-path.cc: New file, from the above material.
* simple-diagnostic-path.h: New file, from the above material
from diagnostic-path.h.
* tree-diagnostic-path.cc: Include "simple-diagnostic-path.h".

gcc/testsuite/ChangeLog
* gcc.dg/plugin/diagnostic_plugin_test_paths.c: Include
"simple-diagnostic-path.h".

Signed-off-by: David Malcolm <dmalcolm@redhat.com>

Match: Support forms 7 and 8 for the unsigned .SAT_ADD

When investigate the vectorization of .SAT_ADD,  we notice there
are additional 2 forms,  aka form 7 and 8 for .SAT_ADD.

Form 7:
  #define DEF_SAT_U_ADD_FMT_7(T)          \
  T __attribute__((noinline))             \
  sat_u_add_##T##_fmt_7 (T x, T y)        \
  {                                       \
    return x > (T)(x + y) ? -1 : (x + y); \
  }

Form 8:
  #define DEF_SAT_U_ADD_FMT_8(T)           \
  T __attribute__((noinline))              \
  sat_u_add_##T##_fmt_8 (T x, T y)         \
  {                                        \
    return x <= (T)(x + y) ? (x + y) : -1; \
  }

Thus,  add above 2 forms to the match gimple_unsigned_integer_sat_add,
and then the vectorizer can try to recog the pattern like form 7 and
form 8.

The below test suites are passed for this patch:
1. The rv64gcv fully regression test with newlib.
2. The rv64gcv build with glibc.
3. The x86 bootstrap test.
4. The x86 fully regression test.

gcc/ChangeLog:

* match.pd: Add form 7 and 8 for the unsigned .SAT_ADD match.

Signed-off-by: Pan Li <pan2.li@intel.com>

Match: Support form 11 for the unsigned scalar .SAT_SUB

We missed one match pattern for the unsigned scalar .SAT_SUB,  aka
form 11.

Form 11:
  #define SAT_SUB_U_11(T) \
  T sat_sub_u_11_##T (T x, T y) \
  { \
    T ret; \
    bool overflow = __builtin_sub_overflow (x, y, &ret); \
    return overflow ? 0 : ret; \
  }

Thus,  add above form 11 to the match pattern gimple_unsigned_integer_sat_sub.

The below test suites are passed for this patch:
1. The rv64gcv fully regression test with newlib.
2. The rv64gcv build with glibc.
3. The x86 bootstrap test.
4. The x86 fully regression test.

gcc/ChangeLog:

* match.pd: Add form 11 match pattern for .SAT_SUB.

Signed-off-by: Pan Li <pan2.li@intel.com>

tree-optimization/115537 - ICE with SLP condition reduction vectorization

The condition rejecting "multiple-type" SLP condition reduction lacks
handling EXTRACT_LAST reductions.

PR tree-optimization/115537
* tree-vect-loop.cc (vectorizable_reduction): Also reject
SLP condition reductions of EXTRACT_LAST kind when multiple
statement copies are involved.

* gcc.dg/vect/pr115537.c: New testcase.

[to-be-committed,RISC-V] Improve bset generation when bit position is limited

  So more work in the ongoing effort to make better use of the Zbs
extension.  This time we're trying to exploit knowledge of the shift
count/bit position to allow us to use a bset instruction.

Consider this expression in SImode

  (1 << (pos & 0xf)

None of the resulting values will have bit 31 set.  So if there's an
explicit zero or sign extension to DI we can drop that explicit
extension and generate a simple bset with x0 as the input value.

Or another example (which I think came from spec at some point and IIRC
was the primary motivation for this patch):

(1 << (7-(pos) % 8))

Before this change they'd generate something like this respectively:

         li      a5,1
         andi    a0,a0,15
         sllw    a0,a5,a0

         li      a5,7
         andn    a0,a5,a0
         li      a5,1
         sllw    a0,a5,a0

After this change they generate:

         andi    a0,a0,15        # 9     [c=4 l=4]  *anddi3/1
         bset    a0,x0,a0        # 17    [c=8 l=4]  *bsetdi_2

         li      a5,7            # 27    [c=4 l=4]  *movdi_64bit/1
         andn    a0,a5,a0        # 28    [c=4 l=4]  and_notdi3
         bset    a0,x0,a0        # 19    [c=8 l=4]  *bsetdi_2

We achieve this with simple define_splits which target the bsetdi_2
pattern I recently added.  Much better than the original implementation
I did a few months back :-)  I've got a bclr/binv variant from a few
months back as well, but it needs to be updated to the simpler
implementation found here.

Just ran this through my tester.  Will wait for the precommit CI to
render its verdict before moving forward.

gcc/
* config/riscv/bitmanip.md (bset splitters): New patterns for
generating bset when bit position is limited.

libstdc++: Fix outdated comment about standard integer types

The long long and unsigned long long types have been standard since
C++11, so are not extensions. There are also the char8_t, char16_t and
char32_t types. Just refer to the standard integer types, without saying
how many there are.

libstdc++-v3/ChangeLog:

* include/bits/cpp_type_traits.h: Fix outdated comment about the
number of standard integer types.

analyzer: Fix g++ 4.8 bootstrap without using std::move to return std::unique_ptr

Revert the changes in r15-1111-ge22b7f741ab54f and fix bootstrap with
GCC 4.8 a different way. The original problem is not related to C++17
guaranteed copy elision, it's related to Core DR 1579 [1], which was
part of C++14 but only implemented in G++ as a C++11 DR with
r5-1576-gfb682f9458c6cf (so GCC 4.8 doesn't implement it).

The original fix causes -Wredundant-move warnings with GCC trunk.

[1] https://cplusplus.github.io/CWG/issues/1579.html

gcc/analyzer/ChangeLog
* constraint-manager.cc (equiv_class::make_dump_widget): Change
return type to match return value and do not use std::move on
return value.
(bounded_ranges_constraint::make_dump_widget): Likewise.
(constraint_manager::make_dump_widget): Likewise.
* constraint-manager.h (equiv_class::make_dump_widget): Change
return type.
(bounded_ranges_constraint::make_dump_widget): Likewise.
(constraint_manager::make_dump_widget): Likewise.
* program-state.cc (sm_state_map::make_dump_widget): Likewise.
(program_state::make_dump_widget): Likewise.
* program-state.h (sm_state_map::make_dump_widget): Likewise.
(program_state::make_dump_widget): Likewise.
* region-model.cc (region_to_value_map::make_dump_widget): Likewise.
(region_model::make_dump_widget): Likewise.
* region-model.h (region_to_value_map::make_dump_widget): Likewise.
(region_model::make_dump_widget): Likewise.
* region.cc (region::make_dump_widget): Likewise.
* region.h (region::make_dump_widget): Likewise.
* store.cc (binding_cluster::make_dump_widget): Likewise.
(store::make_dump_widget): Likewise.
* store.h (binding_cluster::make_dump_widget): Likewise.
(store::make_dump_widget): Likewise.
* svalue.cc (svalue::make_dump_widget): Likewise.
* svalue.h (svalue::make_dump_widget): Likewise.

[MAINTAINERS] Update my email address

Pushing to trunk.

* MAINTAINERS (aarch64 port): Update my email address.
(DCO section): Likewise.

Signed-off-by: Kyrylo Tkachov <ktkachov@nvidia.com>

aarch64: Add some uses of force_highpart_subreg

This patch adds uses of force_highpart_subreg to places that
already use force_lowpart_subreg.

gcc/
* config/aarch64/aarch64.cc (aarch64_addti_scratch_regs): Use
force_highpart_subreg instead of gen_highpart and simplify_gen_subreg.
(aarch64_subvti_scratch_regs): Likewise.

Add force_highpart_subreg

This patch adds a force_highpart_subreg to go along with the
recently added force_lowpart_subreg.

gcc/
* explow.h (force_highpart_subreg): Declare.
* explow.cc (force_highpart_subreg): New function.
* builtins.cc (expand_builtin_issignaling): Use it.
* expmed.cc (emit_store_flag_1): Likewise.

Make more use of force_lowpart_subreg

This patch makes target-independent code use force_lowpart_subreg
instead of simplify_gen_subreg and lowpart_subreg in some places.
The criteria were:

(1) The code is obviously specific to expand (where new pseudos
    can be created), or at least would be invalid to call when
    !can_create_pseudo_p () and temporaries are needed.

(2) The value is obviously an rvalue rather than an lvalue.

Doing this should reduce the likelihood of bugs like PR115464
occuring in other situations.

gcc/
* builtins.cc (expand_builtin_issignaling): Use force_lowpart_subreg
instead of simplify_gen_subreg and lowpart_subreg.
* expr.cc (convert_mode_scalar, expand_expr_real_2): Likewise.
* optabs.cc (expand_doubleword_mod): Likewise.

aarch64: Add some uses of force_lowpart_subreg

This patch makes more use of force_lowpart_subreg, similarly
to the recent patch for force_subreg.  The criteria were:

(1) The code is obviously specific to expand (where new pseudos
    can be created).

(2) The value is obviously an rvalue rather than an lvalue.

gcc/
PR target/115464
* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin)
(aarch64_expand_rwsr_builtin): Use force_lowpart_subreg instead of
simplify_gen_subreg and lowpart_subreg.
* config/aarch64/aarch64-sve-builtins-base.cc
(svset_neonq_impl::expand): Likewise.
* config/aarch64/aarch64-sve-builtins-sme.cc
(add_load_store_slice_operand): Likewise.
* config/aarch64/aarch64.cc (aarch64_sve_reinterpret): Likewise.
(aarch64_addti_scratch_regs, aarch64_subvti_scratch_regs): Likewise.

gcc/testsuite/
PR target/115464
* gcc.target/aarch64/sve/acle/general/pr115464_2.c: New test.

Add force_lowpart_subreg

optabs had a local function called lowpart_subreg_maybe_copy
that is very similar to the lowpart version of force_subreg.
This patch adds a force_lowpart_subreg wrapper around
force_subreg and uses it in optabs.cc.

The only difference between the old and new functions is that
the old one asserted success while the new one doesn't.
It's common not to assert elsewhere when taking subregs;
normally a null result is enough.

Later patches will make more use of the new function.

gcc/
* explow.h (force_lowpart_subreg): Declare.
* explow.cc (force_lowpart_subreg): New function.
* optabs.cc (lowpart_subreg_maybe_copy): Delete.
(expand_absneg_bit): Use force_lowpart_subreg instead of
lowpart_subreg_maybe_copy.
(expand_copysign_bit): Likewise.

Make more use of force_subreg

This patch makes target-independent code use force_subreg instead
of simplify_gen_subreg in some places.  The criteria were:

(1) The code is obviously specific to expand (where new pseudos
    can be created), or at least would be invalid to call when
    !can_create_pseudo_p () and temporaries are needed.

(2) The value is obviously an rvalue rather than an lvalue.

(3) The offset wasn't a simple lowpart or highpart calculation;
    a later patch will deal with those.

Doing this should reduce the likelihood of bugs like PR115464
occuring in other situations.

gcc/
* expmed.cc (store_bit_field_using_insv): Use force_subreg
instead of simplify_gen_subreg.
(store_bit_field_1): Likewise.
(extract_bit_field_as_subreg): Likewise.
(extract_integral_bit_field): Likewise.
(emit_store_flag_1): Likewise.
* expr.cc (convert_move): Likewise.
(convert_modes): Likewise.
(emit_group_load_1): Likewise.
(emit_group_store): Likewise.
(expand_assignment): Likewise.

aarch64: Use force_subreg in more places

This patch makes the aarch64 code use force_subreg instead of
simplify_gen_subreg in more places.  The criteria were:

(1) The code is obviously specific to expand (where new pseudos
    can be created).

(2) The value is obviously an rvalue rather than an lvalue.

(3) The offset wasn't a simple lowpart or highpart calculation;
    a later patch will deal with those.

gcc/
* config/aarch64/aarch64-builtins.cc (aarch64_expand_fcmla_builtin):
Use force_subreg instead of simplify_gen_subreg.
* config/aarch64/aarch64-simd.md (ctz<mode>2): Likewise.
* config/aarch64/aarch64-sve-builtins-base.cc
(svget_impl::expand): Likewise.
(svget_neonq_impl::expand): Likewise.
* config/aarch64/aarch64-sve-builtins-functions.h
(multireg_permute::expand): Likewise.

Make force_subreg emit nothing on failure

While adding more uses of force_subreg, I realised that it should
be more careful to emit no instructions on failure.  This kind of
failure should be very rare, so I don't think it's a case worth
optimising for.

gcc/
* explow.cc (force_subreg): Emit no instructions on failure.

c23: Fix for redeclared enumerator initialized with different type [PR115109]

c23 specifies that the type of a redeclared enumerator is the one of the
previous declaration.  Convert initializers with different type accordingly
and emit an error when the value does not fit.

2024-06-01 Martin Uecker  <uecker@tugraz.at>

PR c/115109

gcc/c/
* c-decl.cc (build_enumerator): When redeclaring an
enumerator convert value to previous type.  For redeclared
enumerators use underlying type for computing the next value.

gcc/testsuite/
* gcc.dg/pr115109.c: New test.
* gcc.dg/c23-tag-enum-6.c: New test.
* gcc.dg/c23-tag-enum-7.c: New test.

rs6000: Shrink rs6000_init_generated_builtins size [PR115324]

While my r15-1001-g4cf2de9b5268224 PCH PIE power fix change decreased the
.data section sizes (219792 -> 189336), it increased the size of already
huge rs6000_init_generated_builtins generated function, from 218328
to 228668 bytes.  That is because there are thousands of array references
to global arrays and we keep constructing the addresses of the arrays
again and again.

Ideally some optimization would figure out we have a single function which
has
    461   rs6000_overload_info
   1257   rs6000_builtin_info_fntype
   1768   rs6000_builtin_decls
   2548   rs6000_instance_info_fntype
array references and that maybe it might be a good idea to just preload
the addresses of those arrays into some register if it decreases code size
and doesn't slow things down.
The function actually is called just once and is huge, so code size is even
more important than speed, which is dominated by all the GC allocations
anyway.

Until that is done, here is a slightly cleaner version of the hack, which
makes the function noipa (so that LTO doesn't undo it) for GCC 8.1+ and
passes the 4 arrays as arguments to the function from the caller.
This decreases the function size from 228668 bytes to 207572 bytes.

2024-06-18  Jakub Jelinek  <jakub@redhat.com>

PR target/115324
* config/rs6000/rs6000-gen-builtins.cc (write_decls): Change
declaration of rs6000_init_generated_builtins from no arguments
to 4 pointer arguments.
(write_init_bif_table): Change rs6000_builtin_info_fntype to
builtin_info_fntype and rs6000_builtin_decls to builtin_decls.
(write_init_ovld_table): Change rs6000_instance_info_fntype to
instance_info_fntype, rs6000_builtin_decls to builtin_decls and
rs6000_overload_info to overload_info.
(write_init_file): Add __noipa__ attribute to
rs6000_init_generated_builtins for GCC 8.1+ and change the function
from no arguments to 4 pointer arguments.  Change rs6000_builtin_decls
to builtin_decls.
* config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Adjust
rs6000_init_generated_builtins caller.

tree-optimization/115493 - fix wrong code with SLP induction cond reduction

The following fixes a bad final value being used when doing single-lane
SLP integer induction cond reduction vectorization.

PR tree-optimization/115493
* tree-vect-loop.cc (vect_create_epilog_for_reduction): Use
the first scalar result.

Enhance if-conversion for automatic arrays

Automatic arrays that are not address-taken should not be subject to
store data races.  This applies to OMP SIMD in-branch lowered
functions result array which for the testcase otherwise prevents
vectorization with SSE and for AVX and AVX512 ends up with spurious
.MASK_STORE to the stack surviving.

This inefficiency was noted in PR111793.

I've introduced ref_can_have_store_data_races, commonizing uses
of flag_store_data_races in if-conversion, cselim and store motion.

PR tree-optimization/111793
* tree-ssa-alias.h (ref_can_have_store_data_races): Declare.
* tree-ssa-alias.cc (ref_can_have_store_data_races): New
function.
* tree-if-conv.cc (ifcvt_memrefs_wont_trap): Use
ref_can_have_store_data_races to allow more unconditional
stores.
* tree-ssa-loop-im.cc (execute_sm): Likewise.
* tree-ssa-phiopt.cc (cond_store_replacement): Likewise.

* gcc.dg/vect/vect-simd-clone-21.c: New testcase.

testsuite, rs6000: Replace powerpc_altivec_ok with powerpc_altivec [PR114842]

As noted in PR114842, most of the test cases which require
effective target check powerpc_altivec_ok actually care about
if ALTIVEC feature is enabled, and they should adopt effective
target powerpc_altivec instead.  Otherwise, when users are
specifying extra option -mno-altivec in RUNTESTFLAGS, the check
powerpc_altivec_ok returns true then the test case would be
tested without ALTIVEC so it would fail.  With commit r15-716,
dg-options and dg-additional-options can be taken into account
when evaluating powerpc_altivec, so this patch also moves
dg-{additional,}-options lines before dg-require-effective-target
to make it effective.

PR testsuite/114842

gcc/testsuite/ChangeLog:

* c-c++-common/pr72747-1.c: Replace powerpc_altivec_ok with
powerpc_altivec, move dg-options and dg-additional-options lines
before dg-require-effective-target lines when it doesn't cause
any side effect like note message.
* c-c++-common/pr72747-2.c: Likewise.
* g++.dg/torture/pr79905.C: Likewise.
* g++.target/powerpc/altivec-1.C: Likewise.
* g++.target/powerpc/altivec-10.C: Likewise.
* g++.target/powerpc/altivec-11.C: Likewise.
* g++.target/powerpc/altivec-12.C: Likewise.
* g++.target/powerpc/altivec-13.C: Likewise.
* g++.target/powerpc/altivec-14.C: Likewise.
* g++.target/powerpc/altivec-15.C: Likewise.
* g++.target/powerpc/altivec-16.C: Likewise.
* g++.target/powerpc/altivec-17.C: Likewise.
* g++.target/powerpc/altivec-18.C: Likewise.
* g++.target/powerpc/altivec-2.C: Likewise.
* g++.target/powerpc/altivec-4.C: Likewise.
* g++.target/powerpc/altivec-5.C: Likewise.
* g++.target/powerpc/altivec-6.C: Likewise.
* g++.target/powerpc/altivec-7.C: Likewise.
* g++.target/powerpc/altivec-8.C: Likewise.
* g++.target/powerpc/altivec-9.C: Likewise.
* g++.target/powerpc/altivec-cell-1.C: Likewise.
* g++.target/powerpc/altivec-cell-5.C: Likewise.
* g++.target/powerpc/altivec-types-1.C: Likewise.
* g++.target/powerpc/altivec-types-2.C: Likewise.
* g++.target/powerpc/altivec-types-3.C: Likewise.
* g++.target/powerpc/altivec-types-4.C: Likewise.
* gcc.target/powerpc/altivec-1-runnable.c: Likewise.
* gcc.target/powerpc/altivec-11.c: Likewise.
* gcc.target/powerpc/altivec-13.c: Likewise.
* gcc.target/powerpc/altivec-14.c: Likewise.
* gcc.target/powerpc/altivec-15.c: Likewise.
* gcc.target/powerpc/altivec-16.c: Likewise.
* gcc.target/powerpc/altivec-17.c: Likewise.
* gcc.target/powerpc/altivec-18.c: Likewise.
* gcc.target/powerpc/altivec-19.c: Likewise.
* gcc.target/powerpc/altivec-2.c: Likewise.
* gcc.target/powerpc/altivec-21.c: Likewise.
* gcc.target/powerpc/altivec-22.c: Likewise.
* gcc.target/powerpc/altivec-23.c: Likewise.
* gcc.target/powerpc/altivec-25.c: Likewise.
* gcc.target/powerpc/altivec-26.c: Likewise.
* gcc.target/powerpc/altivec-27.c: Likewise.
* gcc.target/powerpc/altivec-28.c: Likewise.
* gcc.target/powerpc/altivec-29.c: Likewise.
* gcc.target/powerpc/altivec-30.c: Likewise.
* gcc.target/powerpc/altivec-31.c: Likewise.
* gcc.target/powerpc/altivec-32.c: Likewise.
* gcc.target/powerpc/altivec-33.c: Likewise.
* gcc.target/powerpc/altivec-34.c: Likewise.
* gcc.target/powerpc/altivec-35.c: Likewise.
* gcc.target/powerpc/altivec-36.c: Likewise.
* gcc.target/powerpc/altivec-4.c: Likewise.
* gcc.target/powerpc/altivec-5.c: Likewise.
* gcc.target/powerpc/altivec-6.c: Likewise.
* gcc.target/powerpc/altivec-7.c: Likewise.
* gcc.target/powerpc/altivec-8.c: Likewise.
* gcc.target/powerpc/altivec-9.c: Likewise.
* gcc.target/powerpc/altivec-cell-1.c: Likewise.
* gcc.target/powerpc/altivec-cell-5.c: Likewise.
* gcc.target/powerpc/altivec-cell-6.c: Likewise.
* gcc.target/powerpc/altivec-cell-7.c: Likewise.
* gcc.target/powerpc/altivec-perm-1.c: Likewise.
* gcc.target/powerpc/altivec-perm-2.c: Likewise.
* gcc.target/powerpc/altivec-perm-3.c: Likewise.
* gcc.target/powerpc/altivec-perm-4.c: Likewise.
* gcc.target/powerpc/altivec-pr22085.c: Likewise.
* gcc.target/powerpc/altivec-splat.c: Likewise.
* gcc.target/powerpc/altivec-types-1.c: Likewise.
* gcc.target/powerpc/altivec-types-2.c: Likewise.
* gcc.target/powerpc/altivec-types-3.c: Likewise.
* gcc.target/powerpc/altivec-types-4.c: Likewise.
* gcc.target/powerpc/altivec-volatile.c: Likewise.
* gcc.target/powerpc/altivec_vld_vst_addr-1.c: Likewise.
* gcc.target/powerpc/bool2-av.c: Likewise.
* gcc.target/powerpc/bool2-p5.c: Likewise.
* gcc.target/powerpc/bool3-av.c: Likewise.
* gcc.target/powerpc/builtin-vec-sums-be-int.c: Likewise.
* gcc.target/powerpc/builtins-3.c: Likewise.
* gcc.target/powerpc/cell_builtin-3.c: Likewise.
* gcc.target/powerpc/cell_builtin-5.c: Likewise.
* gcc.target/powerpc/cell_builtin-6.c: Likewise.
* gcc.target/powerpc/cell_builtin-7.c: Likewise.
* gcc.target/powerpc/cell_builtin-8.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-char-fwrapv.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-char.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int-fwrapv.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int-fwrapv.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-int.p8.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-short-fwrapv.c: Likewise.
* gcc.target/powerpc/fold-vec-abs-short.c: Likewise.
* gcc.target/powerpc/fold-vec-add-1.c: Likewise.
* gcc.target/powerpc/fold-vec-add-2.c: Likewise.
* gcc.target/powerpc/fold-vec-add-3.c: Likewise.
* gcc.target/powerpc/fold-vec-add-5.c: Likewise.
* gcc.target/powerpc/fold-vec-extract-double.p7.c: Likewise.
* gcc.target/powerpc/fold-vec-ld-char.c: Likewise.
* gcc.target/powerpc/fold-vec-ld-float.c: Likewise.
* gcc.target/powerpc/fold-vec-ld-int.c: Likewise.
* gcc.target/powerpc/fold-vec-ld-short.c: Likewise.
* gcc.target/powerpc/fold-vec-madd-short.c: Likewise.
* gcc.target/powerpc/fold-vec-mergehl-char.c: Likewise.
* gcc.target/powerpc/fold-vec-mergehl-float.c: Likewise.
* gcc.target/powerpc/fold-vec-mergehl-int.c: Likewise.
* gcc.target/powerpc/fold-vec-mergehl-short.c: Likewise.
* gcc.target/powerpc/fold-vec-minmax-char.c: Likewise.
* gcc.target/powerpc/fold-vec-minmax-int.c: Likewise.
* gcc.target/powerpc/fold-vec-minmax-short.c: Likewise.
* gcc.target/powerpc/fold-vec-missing-lhs.c: Likewise.
* gcc.target/powerpc/fold-vec-msum-char.c: Likewise.
* gcc.target/powerpc/fold-vec-msum-short.c: Likewise.
* gcc.target/powerpc/fold-vec-mule-char.c: Likewise.
* gcc.target/powerpc/fold-vec-mule-short.c: Likewise.
* gcc.target/powerpc/fold-vec-mult-char.c: Likewise.
* gcc.target/powerpc/fold-vec-mult-short.c: Likewise.
* gcc.target/powerpc/fold-vec-pack-int.c: Likewise.
* gcc.target/powerpc/fold-vec-pack-short.c: Likewise.
* gcc.target/powerpc/fold-vec-perm-char.c: Likewise.
* gcc.target/powerpc/fold-vec-perm-float.c: Likewise.
* gcc.target/powerpc/fold-vec-perm-int.c: Likewise.
* gcc.target/powerpc/fold-vec-perm-pixel.c: Likewise.
* gcc.target/powerpc/fold-vec-perm-short.c: Likewise.
* gcc.target/powerpc/fold-vec-shift-char.c: Likewise.
* gcc.target/powerpc/fold-vec-shift-int.c: Likewise.
* gcc.target/powerpc/fold-vec-shift-left-fwrapv.c: Likewise.
* gcc.target/powerpc/fold-vec-shift-left.c: Likewise.
* gcc.target/powerpc/fold-vec-shift-short.c: Likewise.
* gcc.target/powerpc/fold-vec-splat-32.c: Likewise.
* gcc.target/powerpc/fold-vec-splat-8.c: Likewise.
* gcc.target/powerpc/fold-vec-splat-char.c: Likewise.
* gcc.target/powerpc/fold-vec-splat-int.c: Likewise.
* gcc.target/powerpc/fold-vec-splat-short.c: Likewise.
* gcc.target/powerpc/fold-vec-splats-char.c: Likewise.
* gcc.target/powerpc/fold-vec-splats-int.c: Likewise.
* gcc.target/powerpc/fold-vec-splats-short.c: Likewise.
* gcc.target/powerpc/fold-vec-st-char.c: Likewise.
* gcc.target/powerpc/fold-vec-st-float.c: Likewise.
* gcc.target/powerpc/fold-vec-st-int.c: Likewise.
* gcc.target/powerpc/fold-vec-st-short.c: Likewise.
* gcc.target/powerpc/fold-vec-sub-char.c: Likewise.
* gcc.target/powerpc/fold-vec-sub-float.c: Likewise.
* gcc.target/powerpc/fold-vec-sub-int.c: Likewise.
* gcc.target/powerpc/fold-vec-sub-short.c: Likewise.
* gcc.target/powerpc/fold-vec-sums-int.c: Likewise.
* gcc.target/powerpc/fold-vec-unpack-char.c: Likewise.
* gcc.target/powerpc/fold-vec-unpack-pixel.c: Likewise.
* gcc.target/powerpc/fold-vec-unpack-short.c: Likewise.
* gcc.target/powerpc/ppc-fma-3.c: Likewise.
* gcc.target/powerpc/ppc-fma-4.c: Likewise.
* gcc.target/powerpc/ppc-fma-7.c: Likewise.
* gcc.target/powerpc/ppc-vector-memcpy.c: Likewise.
* gcc.target/powerpc/ppc-vector-memset.c: Likewise.
* gcc.target/powerpc/pr100645.c: Likewise.
* gcc.target/powerpc/pr101384-1.c: Likewise.
* gcc.target/powerpc/pr101384-2.c: Likewise.
* gcc.target/powerpc/pr103353.c: Likewise.
* gcc.target/powerpc/pr103702.c: Likewise.
* gcc.target/powerpc/pr108348-1.c: Likewise.
* gcc.target/powerpc/pr108348-2.c: Likewise.
* gcc.target/powerpc/pr109932-1.c: Likewise.
* gcc.target/powerpc/pr109932-2.c: Likewise.
* gcc.target/powerpc/pr110776.c: Likewise.
* gcc.target/powerpc/pr16155.c: Likewise.
* gcc.target/powerpc/pr16286.c: Likewise.
* gcc.target/powerpc/pr27158.c: Likewise.
* gcc.target/powerpc/pr37168.c: Likewise.
* gcc.target/powerpc/pr47197.c: Likewise.
* gcc.target/powerpc/pr67071-1.c: Likewise.
* gcc.target/powerpc/pr67071-2.c: Likewise.
* gcc.target/powerpc/pr67071-3.c: Likewise.
* gcc.target/powerpc/pr70010-2.c: Likewise.
* gcc.target/powerpc/pr70010-3.c: Likewise.
* gcc.target/powerpc/pr71297.c: Likewise.
* gcc.target/powerpc/pr82112.c: Likewise.
* gcc.target/powerpc/pr84220-sld.c: Likewise.
* gcc.target/powerpc/pr84878.c: Likewise.
* gcc.target/powerpc/pr86731-fwrapv.c: Likewise.
* gcc.target/powerpc/pr86731.c: Likewise.
* gcc.target/powerpc/pr88100.c: Likewise.
* gcc.target/powerpc/pragma_power6.c: Likewise.
* gcc.target/powerpc/pragma_power7.c: Likewise.
* gcc.target/powerpc/pragma_power9.c: Likewise.
* gcc.target/powerpc/swaps-p8-21.c: Likewise.
* gcc.target/powerpc/unpack-vectorize-1.c: Likewise.
* gcc.target/powerpc/vec-cg.c: Likewise.
* gcc.target/powerpc/vec-cmpne.c: Likewise.
* gcc.target/powerpc/vec-constvolatile.c: Likewise.
* gcc.target/powerpc/vec-mult-char-2.c: Likewise.
* gcc.target/powerpc/vec-rotate-1.c: Likewise.
* gcc.target/powerpc/vec-rotate-3.c: Likewise.
* gcc.target/powerpc/vec-shift.c: Likewise.
* g++.target/powerpc/altivec-3.C: Likewise.
* g++.target/powerpc/altivec-cell-2.C: Likewise.
* g++.target/powerpc/altivec-cell-3.C: Likewise.
* g++.target/powerpc/altivec-cell-4.C: Likewise.
* g++.target/powerpc/const2.C: Likewise.
* gcc.dg/debug/dwarf2/const-2.c: Likewise.
* gcc.dg/dfp/altivec-types.c: Likewise.
* gcc.dg/ubsan/pr88234.c: Likewise.
* gcc.dg/vect/vect-82_64.c: Likewise.
* gcc.dg/vect/vect-83_64.c: Likewise.
* gcc.target/powerpc/altivec-1.c: Likewise.
* gcc.target/powerpc/altivec-10.c: Likewise.
* gcc.target/powerpc/altivec-12.c: Likewise.
* gcc.target/powerpc/altivec-20.c: Likewise.
* gcc.target/powerpc/altivec-24.c: Likewise.
* gcc.target/powerpc/altivec-3.c: Likewise.
* gcc.target/powerpc/altivec-cell-2.c: Likewise.
* gcc.target/powerpc/altivec-cell-3.c: Likewise.
* gcc.target/powerpc/altivec-cell-4.c: Likewise.
* gcc.target/powerpc/altivec-consts.c: Likewise.
* gcc.target/powerpc/altivec-macros.c: Likewise.
* gcc.target/powerpc/altivec-varargs-1.c: Likewise.
* gcc.target/powerpc/altivec-vec-merge.c: Likewise.
* gcc.target/powerpc/darwin-save-world-1.c: Likewise.
* gcc.target/powerpc/le-altivec-consts.c: Likewise.
* gcc.target/powerpc/pr35907.c: Likewise.
* gcc.target/powerpc/vec-mult-char-1.c: Likewise.

i386: Handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx

gcc/ChangeLog:

* config/i386/avxintrin.h: Move cmp[p|s][s|d] to [e|x]mmintrin.h,
and move macros to xmmintrin.h
* config/i386/emmintrin.h: Add cmp[p|s]s intrins.
* config/i386/i386-builtin.def: Modify __builtin_ia32_cmp[p|s][s|d].
* config/i386/i386-expand.cc
(ix86_expand_args_builtin): Raise error when imm is in range of
[8, 32] without avx.
* config/i386/predicates.md (cmpps_imm_operand): New predicate.
* config/i386/sse.md (avx_cmp<mode>3): Modefy define_insn.
(avx_vmcmp<mode>3): Ditto.
* config/i386/xmmintrin.h (_CMP_EQ_OQ): New macro for sse/sse2.
(_CMP_LT_OS): Ditto
(_CMP_LE_OS): Ditto
(_CMP_UNORD_Q): Ditto
(_CMP_NEQ_UQ): Ditto
(_CMP_NLT_US): Ditto
(_CMP_NLE_US): Ditto
(_CMP_ORD_Q): Ditto
(_mm_cmp_ps): Move intrin from avxintrin.h to xmmintrin.h
(_mm_cmp_ss): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/i386/sse-cmp-1.c: New test.
* gcc.target/i386/sse-cmp-2.c: Ditto.
* gcc.target/i386/sse-cmp-error.c: Ditto.

Daily bump.

aarch64: Add testcase for PR97405

This aarch64 sve specific code was fixed by r15-917-gc9842f99042454
which added a riscv specific testcase so adding an aarch64 one to test
the fix does not regress is a good idea.

Committed as obvious after testing the testcase for aarch64-linux-gnu.

PR tree-optimization/97405

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/sve/pr97405-1.c: New test.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

[to-be-committed,RISC-V] Handle zero_extract destination for single bit insertions

Combine will use zero_extract destinations for certain bitfield
insertions.  If the bitfield is a single bit constant, then we can use
bset/bclr.

In this case we are only dealing with word_mode objects, so we don't
have to worry about the SI->DI extension issues for TARGET_64BIT.

The testcase was derived from 502.gcc in spec from the RAU team.

An earlier version of this (TARGET_64BIT only) went through Ventana's CI
system.  This version has gone though mine after generalizing it to
handle rv32 as well.  I'll wait for pre-commit CI to render its verdict
before moving forward.

gcc/
* config/riscv/bitmanip.md (bsetclr_zero_extract): New pattern.

gcc/testsuite/

* gcc.target/riscv/zbs-zext-3.c: New test.

Add minimal support for __bf16 to -fdump-ada-spec

gcc/c-family/
* c-ada-spec.cc (is_float16): New predicate.
(dump_ada_node) <REAL_TYPE>: Call it.

diagnostics: Fix add_misspelling_candidates [PR115440]

The option_map array for most entries contains just non-NULL opt0
    { "-Wno-", NULL, "-W", false, true },
    { "-fno-", NULL, "-f", false, true },
    { "-gno-", NULL, "-g", false, true },
    { "-mno-", NULL, "-m", false, true },
    { "--debug=", NULL, "-g", false, false },
    { "--machine-", NULL, "-m", true, false },
    { "--machine-no-", NULL, "-m", false, true },
    { "--machine=", NULL, "-m", false, false },
    { "--machine=no-", NULL, "-m", false, true },
    { "--machine", "", "-m", false, false },
    { "--machine", "no-", "-m", false, true },
    { "--optimize=", NULL, "-O", false, false },
    { "--std=", NULL, "-std=", false, false },
    { "--std", "", "-std=", false, false },
    { "--warn-", NULL, "-W", true, false },
    { "--warn-no-", NULL, "-W", false, true },
    { "--", NULL, "-f", true, false },
    { "--no-", NULL, "-f", false, true }
and so add_misspelling_candidates works correctly for it, but 3 out of
these,
    { "--machine", "", "-m", false, false },
    { "--machine", "no-", "-m", false, true },
and
    { "--std", "", "-std=", false, false },
use non-NULL opt1.  That says that
--machine foo
should map to
-mfoo
and
--machine no-foo
should map to
-mno-foo
and
--std c++17
should map to
-std=c++17
add_misspelling_canidates was not handling this, so it hapilly
registered say
--stdc++17
or
--machineavx512
(twice) as spelling alternatives, when those options aren't recognized.
Instead we support
--std c++17
or
--machine avx512
--machine no-avx512

The following patch fixes that.  On this particular testcase, we no longer
suggest anything, even when among the suggestion is say that
--std c++17
or
-std=c++17
etc.

2024-06-17  Jakub Jelinek  <jakub@redhat.com>

PR driver/115440
* opts-common.cc (add_misspelling_candidates): If opt1 is non-NULL,
add a space and opt1 to the alternative suggestion text.

* g++.dg/cpp1z/pr115440.C: New test.

vshuf-mem.C: Make -march=z14 depend on s390_vxe

gcc/testsuite/ChangeLog:

* g++.dg/torture/vshuf-mem.C: Use -march=z14 only, if the we are
on a machine which can actually run it.

c: Implement C2Y alignof on incomplete arrays

C2Y has adopted support for alignof applied to incomplete array types
(N3273).  Add this support to GCC.  As the relevant checks are in
c-family code that doesn't have access to functions such as
pedwarn_c23, this remains a hard error for older versions and isn't
handled by -Wc23-c2y-compat, although preferably it would work like
pedwarn_c23 (pedwarn-if-pedantic for older versions, warning with
-Wc23-c2y-compat in C2Y mode).

Bootstrapped with no regressions for x86_64-pc-linux-gnu.

gcc/c-family/
* c-common.cc (c_sizeof_or_alignof_type): Allow alignof on an
incomplete array type for C2Y.

gcc/testsuite/
* gcc.dg/c23-align-10.c, gcc.dg/c2y-align-1.c,
gcc.dg/c2y-align-2.c: New tests.

c-family: Fix -Warray-compare warning ICE [PR115290]

The warning code uses %D to print the ARRAY_REF first operands.
That works in the most common case where those operands are decls, but
as can be seen on the following testcase, they can be other expressions
with array type.
Just changing %D to %E isn't enough, because then the diagnostics can
suggest something like
note: use '&(x) != 0 ? (int (*)[32])&a : (int (*)[32])&b[0] == &(y) != 0 ? (int (*)[32])&a : (int (*)[32])&b[0]' to compare the addresses
which is a bad suggestion, the %E printing doesn't know that the
warning code will want to add & before it and [0] after it.
So, the following patch adds ()s around the operand as well, but does
that only for non-decls, for decls keeps it as &arr[0] like before.

2024-06-17  Jakub Jelinek  <jakub@redhat.com>

PR c/115290
* c-warn.cc (do_warn_array_compare): Use %E rather than %D for
printing op0 and op1; if those operands aren't decls, also print
parens around them.

* c-c++-common/Warray-compare-3.c: New test.

c++: Fix up floating point conversion rank comparison for _Float32 and float if float/double are same size [PR115511]

On AVR and SH with some options sizeof (float) == sizeof (double) and
the 2 types have the same set of values.
http://eel.is/c++draft/conv.rank#2.2 for this says that double still
has bigger rank than float and http://eel.is/c++draft/conv.rank#2.2
says that extended type with the same set of values as more than one
standard floating point type shall have the same rank as double.
I've implemented the latter rule as
   if (cnt > 1 && mv2 == long_double_type_node)
     return -2;
with the _Float64/double/long double case having same mode case (various
targets with -mlong-double-64) in mind.
But never thought there are actually targets where float and double
are the same, that needs handling too, if cnt > 1 (that is the extended
type mv1 has same set of values as 2 or 3 of float/double/long double)
and mv2 is float, we need to return 2, because mv1 in that case should
have same rank as double and double has bigger rank than float.

2024-06-17  Jakub Jelinek  <jakub@redhat.com>

PR target/111343
PR c++/115511
* typeck.cc (cp_compare_floating_point_conversion_ranks): If an
extended floating point type mv1 has same set of values as more
than one standard floating point type and mv2 is float, return 2.

* g++.dg/cpp23/ext-floating18.C: New test.

RISC-V: Add configure check for Zaamo/Zalrsc assembler support

Binutils 2.42 and before don't support Zaamo/Zalrsc. Add a configure
check to prevent emitting Zaamo/Zalrsc in the arch string when the
assember does not support it.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_subset_list::to_string): Skip zaamo/zalrsc when not
supported by the assembler.
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Add zaamo/zalrsc assmeber check.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com> # RISC-V
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> # RISC-V

doc: Mark up __cxa_atexit as @code.

gcc:
* doc/install.texi (Configuration): Mark up __cxa_atexit as @code.

rs6000: Compute rop_hash_save_offset for non-Altivec compiles [PR115389]

We currently only compute the offset for the ROP hash save location in
the stack frame for Altivec compiles.  For non-Altivec compiles when we
emit ROP mitigation instructions, we use a default offset of zero which
corresponds to the backchain save location which will get clobbered on
any call.  The fix is to compute the ROP hash save location for all
compiles.

2024-06-14  Peter Bergner  <bergner@linux.ibm.com>

gcc/
PR target/115389
* config/rs6000/rs6000-logue.cc (rs6000_stack_info): Compute
rop_hash_save_offset for non-Altivec compiles.

gcc/testsuite
PR target/115389
* gcc.target/powerpc/pr115389.c: New test.

[to-be-committed,RISC-V] Improve variable bit set for rv64

Another case of being able to safely use bset for 1 << n.  In this case
the (1 << n)  is explicitly zero extended from SI to DI.  Two things to
keep in mind.  The (1 << n) is done in SImode.  So it doesn't directly
define bits 32..63 and those bits are cleared by the explicit zero
extension.  Second if N is out of SImode's range, then the original
source level construct was undefined.

Thus we can use bset with x0 as our source input.

I think this testcase was from the RAU team.  It doesn't immediately
look like something from SPEC, but that's where they were primarily focused.

This has been through Ventana's CI system in the past.  I've also
recently added zbs testing to my own tester and naturally this passed
there as well.  I'll wait for the pre-commit CI to do its thing before
moving forward.  The plan would be to commit after passing.

gcc/
* config/riscv/bitmanip.md (bsetdi_2): New pattern.

gcc/testsuite/

* gcc.target/riscv/zbs-zext-2.c: New test.

tree-optimization/115508 - fix ICE with SLP scheduling and extern vector

When there's a permute after an extern vector we can run into a case
that didn't consider the scheduled node being a permute which lacks
a representative.

PR tree-optimization/115508
* tree-vect-slp.cc (vect_schedule_slp_node): Guard check on
representative.

* gcc.target/i386/pr115508.c: New testcase.

Testcase for PR115492

This adds a testcase for the PR fixed with reversal of
r15-204-g7c469a9fc78550.

PR tree-optimization/115492
* gcc.dg/torture/pr115492.c: New testcase.

Revert "tree-optimization/100923 - re-do VN with contextual PTA info fix"

This reverts commit 7c469a9fc785505dc350aba60311812c2bb0c1b5.

Rename Value_Range to value_range.

Now that all remaining users of value_range have been renamed to
int_range<>, we can reclaim value_range as a temporary, thus removing
the annoying CamelCase.

gcc/ChangeLog:

* data-streamer-in.cc (streamer_read_value_range): Rename
Value_Range to value_range.
* data-streamer.h (streamer_read_value_range): Same.
* gimple-pretty-print.cc (dump_ssaname_info): Same.
* gimple-range-cache.cc (ssa_block_ranges::dump): Same.
(ssa_lazy_cache::merge): Same.
(block_range_cache::dump): Same.
(ssa_cache::merge_range): Same.
(ssa_cache::dump): Same.
(ranger_cache::edge_range): Same.
(ranger_cache::propagate_cache): Same.
(ranger_cache::fill_block_cache): Same.
(ranger_cache::resolve_dom): Same.
(ranger_cache::range_from_dom): Same.
(ranger_cache::register_inferred_value): Same.
* gimple-range-fold.cc (op1_range): Same.
(op2_range): Same.
(fold_relations): Same.
(fold_using_range::range_of_range_op): Same.
(fold_using_range::range_of_phi): Same.
(fold_using_range::range_of_call): Same.
(fold_using_range::condexpr_adjust): Same.
(fold_using_range::range_of_cond_expr): Same.
(fur_source::register_outgoing_edges): Same.
* gimple-range-fold.h (gimple_range_type): Same.
(gimple_range_ssa_p): Same.
* gimple-range-gori.cc (gori_compute::compute_operand_range): Same.
(gori_compute::logical_combine): Same.
(gori_compute::refine_using_relation): Same.
(gori_compute::compute_operand1_range): Same.
(gori_compute::compute_operand2_range): Same.
(gori_compute::compute_operand1_and_operand2_range): Same.
(gori_calc_operands): Same.
(gori_name_helper): Same.
* gimple-range-infer.cc (gimple_infer_range::check_assume_func): Same.
(gimple_infer_range::gimple_infer_range): Same.
(infer_range_manager::maybe_adjust_range): Same.
(infer_range_manager::add_range): Same.
* gimple-range-infer.h: Same.
* gimple-range-op.cc
(gimple_range_op_handler::gimple_range_op_handler): Same.
(gimple_range_op_handler::calc_op1): Same.
(gimple_range_op_handler::calc_op2): Same.
(gimple_range_op_handler::maybe_builtin_call): Same.
* gimple-range-path.cc (path_range_query::internal_range_of_expr): Same.
(path_range_query::ssa_range_in_phi): Same.
(path_range_query::compute_ranges_in_phis): Same.
(path_range_query::compute_ranges_in_block): Same.
(path_range_query::add_to_exit_dependencies): Same.
* gimple-range-trace.cc (debug_seed_ranger): Same.
* gimple-range.cc (gimple_ranger::range_of_expr): Same.
(gimple_ranger::range_on_entry): Same.
(gimple_ranger::range_on_edge): Same.
(gimple_ranger::range_of_stmt): Same.
(gimple_ranger::prefill_stmt_dependencies): Same.
(gimple_ranger::register_inferred_ranges): Same.
(gimple_ranger::register_transitive_inferred_ranges): Same.
(gimple_ranger::export_global_ranges): Same.
(gimple_ranger::dump_bb): Same.
(assume_query::calculate_op): Same.
(assume_query::calculate_phi): Same.
(assume_query::dump): Same.
(dom_ranger::range_of_stmt): Same.
* ipa-cp.cc (ipcp_vr_lattice::meet_with_1): Same.
(ipa_vr_operation_and_type_effects): Same.
(ipa_value_range_from_jfunc): Same.
(propagate_bits_across_jump_function): Same.
(propagate_vr_across_jump_function): Same.
(ipcp_store_vr_results): Same.
* ipa-cp.h: Same.
* ipa-fnsummary.cc (evaluate_conditions_for_known_args): Same.
(evaluate_properties_for_edge): Same.
* ipa-prop.cc (struct ipa_vr_ggc_hash_traits): Same.
(ipa_vr::get_vrange): Same.
(ipa_vr::streamer_read): Same.
(ipa_vr::streamer_write): Same.
(ipa_vr::dump): Same.
(ipa_set_jfunc_vr): Same.
(ipa_compute_jump_functions_for_edge): Same.
(ipcp_get_parm_bits): Same.
(ipcp_update_vr): Same.
(ipa_record_return_value_range): Same.
(ipa_return_value_range): Same.
* ipa-prop.h (ipa_return_value_range): Same.
(ipa_record_return_value_range): Same.
* range-op.h (range_cast): Same.
* tree-ssa-dom.cc
(dom_opt_dom_walker::set_global_ranges_from_unreachable_edges): Same.
(cprop_operand): Same.
* tree-ssa-loop-ch.cc (loop_static_stmt_p): Same.
* tree-ssa-loop-niter.cc (record_nonwrapping_iv): Same.
* tree-ssa-loop-split.cc (split_at_bb_p): Same.
* tree-ssa-phiopt.cc (value_replacement): Same.
* tree-ssa-strlen.cc (get_range): Same.
* tree-ssa-threadedge.cc (hybrid_jt_simplifier::simplify): Same.
(hybrid_jt_simplifier::compute_exit_dependencies): Same.
* tree-ssanames.cc (set_range_info): Same.
(duplicate_ssa_name_range_info): Same.
* tree-vrp.cc (remove_unreachable::handle_early): Same.
(remove_unreachable::remove_and_update_globals): Same.
(execute_ranger_vrp): Same.
* value-query.cc (range_query::value_of_expr): Same.
(range_query::value_on_edge): Same.
(range_query::value_of_stmt): Same.
(range_query::value_on_entry): Same.
(range_query::value_on_exit): Same.
(range_query::get_tree_range): Same.
* value-range-storage.cc (vrange_storage::set_vrange): Same.
* value-range.cc (Value_Range::dump): Same.
(value_range::dump): Same.
(debug): Same.
* value-range.h (enum value_range_discriminator): Same.
(class vrange): Same.
(class Value_Range): Same.
(class value_range): Same.
(Value_Range::Value_Range): Same.
(value_range::value_range): Same.
(Value_Range::~Value_Range): Same.
(value_range::~value_range): Same.
(Value_Range::set_type): Same.
(value_range::set_type): Same.
(Value_Range::init): Same.
(value_range::init): Same.
(Value_Range::operator=): Same.
(value_range::operator=): Same.
(Value_Range::operator==): Same.
(value_range::operator==): Same.
(Value_Range::operator!=): Same.
(value_range::operator!=): Same.
(Value_Range::supports_type_p): Same.
(value_range::supports_type_p): Same.
* vr-values.cc (simplify_using_ranges::fold_cond_with_ops): Same.
(simplify_using_ranges::legacy_fold_cond): Same.

[APX ZU] Fix test for target-support check

gcc/testsuite/ChangeLog:

* gcc.target/i386/apx-zu-1.c: Add attribute for noinline,
and target apx.
* gcc.target/i386/apx-zu-2.c: Add target-support check.

i386: Refine all cvtt* instructions with UNSPEC instead of FIX/UNSIGNED_FIX.

gcc/ChangeLog:

PR target/115161
* config/i386/i386-builtin.def: Change CODE_FOR_* for cvtt*'s builtins.
* config/i386/sse.md:
(unspec_avx512fp16_fix<vcvtt_uns_suffix>
_trunc<mode>2<mask_name><round_saeonly_name>):
Use UNSPEC instead of FIX/UNSIGNED_FIX.
(unspec_avx512fp16_fix<vcvtt_uns_suffix>_trunc<mode>2<mask_name>):
Ditto.
(unspec_avx512fp16_fix<vcvtt_uns_suffix>_truncv2di2<mask_name>): Ditto.
(unspec_avx512fp16_fix<vcvtt_uns_suffix>_trunc<mode>2<round_saeonly_name>):
Ditto.
(unspec_sse_cvttps2pi): Ditto.
(unspec_sse_cvttss2si<rex64namesuffix><round_saeonly_name>): Ditto.
(unspec_fix<vcvtt_uns_suffix>_truncv16sfv16si2<mask_name><round_saeonly_name>):
Ditto.
(unspec_fix_truncv8sfv8si2<mask_name>): Ditto.
(unspec_fix_truncv4sfv4si2<mask_name>): Ditto.
(unspec_sse2_cvttpd2pi): Ditto.
(unspec_fixuns_truncv2dfv2si2): Ditto.
(unspec_avx512f_vcvttss2usi<rex64namesuffix><round_saeonly_name>):
Ditto.
(unspec_avx512f_vcvttsd2usi<rex64namesuffix><round_saeonly_name>):
Ditto.
(unspec_sse2_cvttsd2si<rex64namesuffix><round_saeonly_name>): Ditto.
(unspec_fix<vcvtt_uns_suffix>_truncv8dfv8si2<mask_name><round_saeonly_name>):
Ditto.
(*unspec_fixuns_truncv2dfv2si2): Ditto.
(unspec_fixuns_truncv2dfv2si2_mask): Ditto.
(unspec_fix_truncv4dfv4si2<mask_name>): Ditto.
(unspec_fixuns_truncv4dfv4si2<mask_name>): Ditto.
(unspec_fix<vcvtt_uns_suffix>
_trunc<mode><sseintvecmodelower>2<mask_name><round_saeonly_name>):
Ditto.
(unspec_fix<vcvtt_uns_suffix>
_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>):
Ditto.
(unspec_avx512dq_fix<vcvtt_uns_suffix>_truncv2sfv2di2<mask_name>):
Ditto.
(<mask_codefor>unspec_fixuns_trunc<mode><sseintvecmodelower>2<mask_name>):
Ditto.
(unspec_sse2_cvttpd2dq<mask_name>): Ditto.

gcc/testsuite/ChangeLog:

PR target/115161
* gcc.target/i386/pr115161-1.c: New test.

Fix ICE when compiling with -fcoarray=single, when derefing a non-array.

    PR fortran/96418
    PR fortran/103112

gcc/fortran/ChangeLog:

* trans.cc (gfc_deallocate_with_status): Check that object to deref
is an array, before applying array deref.

gcc/testsuite/ChangeLog:

* gfortran.dg/coarray_alloc_comp_3.f08: Moved to...
* gfortran.dg/coarray/alloc_comp_8.f90: ...here.
Should be tested for both -fcoarray=single and lib, resp.
* gfortran.dg/coarray_alloc_comp_4.f08: Fix program name.

x86: Emit cvtne2ps2bf16 for odd increasing perm in __builtin_shufflevector

This patch updates the GCC x86 backend to efficiently handle
odd, incrementally increasing permutations of BF16 vectors
using the cvtne2ps2bf16 instruction.
It modifies ix86_vectorize_vec_perm_const to support these operations
and adds a specific predicate to ensure proper sequence handling.

gcc/ChangeLog:

* config/i386/i386-expand.cc
(ix86_vectorize_vec_perm_const): Convert BF to HI using subreg.
* config/i386/predicates.md
(vcvtne2ps2bf_parallel): New define_insn_and_split.
* config/i386/sse.md
(vpermt2_sepcial_bf16_shuffle_<mode>): New predicates matches odd increasing perm.

gcc/testsuite/ChangeLog:

* gcc.target/i386/vpermt2-special-bf16-shufflue.c: New test.

s390: Delete mistakenly added tests

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/vgm-df-1.c: Removed.
* gcc.target/s390/vector/vgm-di-1.c: Removed.
* gcc.target/s390/vector/vgm-hi-1.c: Removed.
* gcc.target/s390/vector/vgm-int128-1.c: Removed.
* gcc.target/s390/vector/vgm-longdouble-1.c: Removed.
* gcc.target/s390/vector/vgm-qi-1.c: Removed.
* gcc.target/s390/vector/vgm-sf-1.c: Removed.
* gcc.target/s390/vector/vgm-si-1.c: Removed.
* gcc.target/s390/vector/vgm-ti-1.c: Removed.

s390: Extend two element float vector

This implements a V2SF -> V2DF extend.

gcc/ChangeLog:

* config/s390/vector.md (*vmrhf_half<mode>): New.
(extendv2sfv2df2): New.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/vec-extend-3.c: New test.

s390: Extend two/four element integer vectors

For the moment I deliberately left out one-element QHS vectors since it
is unclear whether these are pathological cases or whether they are
really used.  If we ever get an extend for V1DI -> V1TI we should
reconsider this.

As a side-effect this fixes PR115261.

gcc/ChangeLog:

PR target/115261
* config/s390/s390.md (any_extend,extend_insn,zero_extend):
New code attributes and code iterator.
* config/s390/vector.md (V_EXTEND): New mode iterator.
(<extend_insn><V_EXTEND:mode><vec_2x_wide>2): New insn.

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/vec-extend-1.c: New test.
* gcc.target/s390/vector/vec-extend-2.c: New test.

s390: testsuite: Fix nobp-table-jump-*.c

Starting with r14-5628-g53ba8d669550d3 interprocedural VRP became strong
enough in order to render these tests useless.  Fixed by disabling IPA.

gcc/testsuite/ChangeLog:

* gcc.target/s390/nobp-table-jump-inline-z10.c: Do not perform
IPA.
* gcc.target/s390/nobp-table-jump-inline-z900.c: Dito.
* gcc.target/s390/nobp-table-jump-z10.c: Dito.
* gcc.target/s390/nobp-table-jump-z900.c: Dito.

s390: testsuite: Fix ifcvt-one-insn-bool.c

With the change of r15-787-g57e04879389f9c I forgot to also update this
test.

gcc/testsuite/ChangeLog:

* gcc.target/s390/ifcvt-one-insn-bool.c: Fix loc.

m2: Remove uses of {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE

Joseph pointed out "floating types should have their mode,
not a poorly defined precision value" in the discussion[1],
as he and Richi suggested, the existing macros
{FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE will be replaced with a
hook mode_for_floating_type.  To be prepared for that, this
patch is to remove uses of {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE
in m2.  Currently they are used for assertion and can be
replaced with TYPE_SIZE check on the corresponding type node,
since we dropped the call to layout_type which would early
return once TYPE_SIZE is set and this assertion ensures it's
safe to drop that call.

[1] https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651209.html

gcc/m2/ChangeLog:

* gm2-gcc/m2type.cc (build_m2_short_real_node): Adjust assertion with
TYPE_SIZE check.
(build_m2_real_node): Likewise.
(build_m2_long_real_node): Add assertion with TYPE_SIZE check.

Daily bump.

libbacktrace: it's OK if zstd decompressor sees no backward bits

* elf.c (elf_fetch_bits_backward) Don't fail if no bits are
available.

aarch64: Fix reg_is_wrapped_separately array size [PR100211]

Currrently the size of the array reg_is_wrapped_separately is LAST_SAVED_REGNUM.
But LAST_SAVED_REGNUM could be regno that is being saved. So the size needs
to be `LAST_SAVED_REGNUM + 1` like aarch64_frame->reg_offset is.

Committed as obvious after a bootstrap/test for aarch64-linux-gnu.

gcc/ChangeLog:

PR target/100211
* config/aarch64/aarch64.h (machine_function): Fix the size
of reg_is_wrapped_separately.

Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>

[to-be-committed] [RISC-V] Improve (1 << N) | C for rv64

Another improvement for generating Zbs instructions.

In this case we're looking at stuff like (1 << N) | C where N varies and C is a
single bit constant.

In this pattern the (1 << N) happens in SImode, but is zero extended out to
DImode before the bit manipulation.  The fact that we're modifying a DImode
object in the logical op is important as it means we don't have to worry about
whether or not the resulting value is sign extended from SI to DI.

This has run through Ventana's CI system.  I'll wait for it to roll through
pre-commit CI before moving forward.

gcc/
* config/riscv/bitmanip.md ((1 << N) | C): New splitter for IOR/XOR
of a single bit an a DImode object.

gcc/testsuite/

* gcc.target/riscv/zbs-zext.c: New test.

[committed] Fix minor SH scan-asm failure after recent IOR->ADD changes

This fixes minor fallout from the IOR->ADD change for rotates that I installed
a little while ago.

Basically the SH backend has a special pattern for setting the T register that
has elements similar to a rotate.  With the IOR->ADD change that pattern no
longer matches and we get scan-asm failures.

Fixing isn't a trivial case of just replacing IOR with ADD as the IOR->ADD
change changes some of the simplifications/canonicalizations along the way.

The net is we need a pattern with a slightly different structure.   I've
regression tested this on sh3[eb]-linux-gnu and bootstrapped sh4-linux-gnu
(without a regression test).

gcc/
* config/sh/sh.md (neg_zero_extract_4b): New pattern.

pretty-print: Don't translate escape sequences to windows console API

Modern versions of windows (after windows 10 v1511) support VT100 escape
sequences, so translation for them is not necessary. The translation also
mangles embedded warning documentation links.

gcc/ChangeLog:
* pretty-print.cc (mingw_ansi_fputs): Don't translate escape sequences if
the console has ENABLE_VIRTUAL_TERMINAL_PROCESSING.

Signed-off-by: Peter Damianov <peter0x44@disroot.org>

diagnostics: Don't hardcode auto_enable_urls to false for mingw hosts

Windows terminal and mintty both have support for link escape sequences, and so
auto_enable_urls shouldn't be hardcoded to false. For older versions of the
windows console, mingw_ansi_fputs's console API translation logic does mangle
these sequences, but there's nothing useful it could do even if this weren't
the case, so check if the ansi escape sequences are supported at all.

conhost.exe doesn't support link escape sequences, but printing them does not
cause any problems.

gcc/ChangeLog:
* diagnostic-color.cc (auto_enable_urls): Don't hardcode to return
false on mingw hosts.
(auto_enable_urls): Return true if console
supports ansi escape sequences.

Signed-off-by: Peter Damianov <peter0x44@disroot.org>

diagnostics: Enable escape sequence processing on windows consoles

Since windows 10 release v1511, the windows console has had support for VT100
escape sequences. We should try to enable this, and utilize it where possible.

gcc/ChangeLog:
* diagnostic-color.cc (should_colorize): Enable processing of VT100
escape sequences on windows consoles

Signed-off-by: Peter Damianov <peter0x44@disroot.org>

Daily bump.

RISC-V: Add testcases for vector unsigned SAT_SUB form 2

The previous RISC-V backend .SAT_SUB enabling patch missed the form 2
testcases of vector modes.  Aka:

Form 2:
  #define DEF_VEC_SAT_U_SUB_FMT_2(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        out[i] = (x - y) & (-(T)(x > y));                              \
      }                                                                \
  }

This patch would like to make it up to ensure form 2 of .SAT_SUB vector
is covered.

Passed the rv64gcv rvv.exp tests.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

riscv: Allocate enough space to strcpy() string

I triggered an ICE on Ubuntu 24.04 when compiling code that uses
function attributes. Looking into the sources shows that we have
a systematic issue in the attribute handling code:
* we determine the length with strlen() (excluding the terminating null)
* we allocate a buffer with this length
* we copy the original string using strcpy() (incl. the terminating null)

To quote the man page of strcpy():
"The programmer is responsible for allocating a  destination  buffer
large  enough,  that  is, strlen(src)  + 1."

The ICE looks like this:

*** buffer overflow detected ***: terminated
xtheadmempair_bench.c:14:1: internal compiler error: Aborted
   14 | {
      | ^
0xaf3b99 crash_signal
        /home/ubuntu/src/gcc/scaleff/gcc/toplev.cc:319
0xe5b957 strcpy
        /usr/include/riscv64-linux-gnu/bits/string_fortified.h:79
0xe5b957 riscv_process_target_attr
        /home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:339
0xe5baaf riscv_process_target_attr
        /home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:314
0xe5bc5f riscv_option_valid_attribute_p(tree_node*, tree_node*, tree_node*, int)
        /home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:389
0x6a31e5 handle_target_attribute
        /home/ubuntu/src/gcc/scaleff/gcc/c-family/c-attribs.cc:5915
0x5d3a07 decl_attributes(tree_node**, tree_node*, int, tree_node*)
        /home/ubuntu/src/gcc/scaleff/gcc/attribs.cc:900
0x5db403 c_decl_attributes
        /home/ubuntu/src/gcc/scaleff/gcc/c/c-decl.cc:5501
0x5e8965 start_function(c_declspecs*, c_declarator*, tree_node*)
        /home/ubuntu/src/gcc/scaleff/gcc/c/c-decl.cc:10562
0x6318ed c_parser_declaration_or_fndef
        /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:2914
0x63a8ad c_parser_external_declaration
        /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:2048
0x63b219 c_parser_translation_unit
        /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:1902
0x63b219 c_parse_file()
        /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:27277
0x68fec5 c_common_parse_file()
        /home/ubuntu/src/gcc/scaleff/gcc/c-family/c-opts.cc:1311
Please submit a full bug report, with preprocessed source (by using -freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

gcc/ChangeLog:

* config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
Fix allocation size of buffer.
(riscv_process_one_target_attr): Likewise.
(riscv_process_target_attr): Likewise.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

RISC-V: Refine the SAT_ARITH test help header files [NFC]

Separate the vector part code to one standalone header file,  which
is independent with the scalar part.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Leverage
the new header file for vector part.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-4.c: Ditto.
* gcc.target/riscv/sat_arith.h: Move vector part out.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

doc: Remove pointer to old versions of binutils

The oldest release in the advertised location dates back to August 2002,
which is way older than we remotely want to cover here.

gcc:
PR target/69374
* doc/install.texi (Specific): Remove pointer to old versions
of binutils.

Daily bump.

Dont add varying values to gori_on_edge mass calculations.

gori_on_edge will return an ssa_lazy_cache with all contextual ranges
that can be generated by an edge.   This patch adjusts it so that
a VARYING range is never added.

* gimple-range-gori.cc (gori_calc_operands): Do not continue nor
add the range when VARYING is produced for an operand.

Add merge facility to ssa_lazy_cache.

The ssa_lazy_cache has a routine to merge a range for an ssa-name with
an existing range in the cache.  This adds a method which will merge all
elements of another ssa_lazy_cache.

* gimple-range-cache.cc (ssa_lazy_cache::merge): New.
* gimple-range-cache.h (ssa_lazy_cache::merge): New prototype.

Do not assume LHS of call is an ssa-name.

gimple_range_fold makes an assumption that the LHS of a call is an
ssa_name, which later in compilation may not be true.

* gimple-range-fold.cc (fold_using_range::range_of_call): Ensure
LHS is an SSA_NAME before invoking gimple_range_global.

testsuite: Add -Wno-psabi to vshuf-mem.C test

The newly added test FAILs on i686-linux.
On x86_64-linux
make check-g++ RUNTESTFLAGS='--target_board=unix\{-m64,-m32/-msse2,-m32/-mno-sse/-mno-mmx\} dg-torture.exp=vshuf-mem.C'
shows that as well.

The problem is that without SSE2/MMX the vector is passed differently
than normally and so GCC warns about that.
-Wno-psabi is the usual way to shut it up.

Also wonder about the
// { dg-additional-options "-march=z14" { target s390*-*-* } }
line, doesn't that mean the test will FAIL on all pre-z14 HW?
Shouldn't it use some z14_runtime or similar effective target, or
check in main (in that case copied over to g++.target/s390) whether
z14 instructions can be actually used at runtime?

2024-06-14  Jakub Jelinek  <jakub@redhat.com>

* g++.dg/torture/vshuf-mem.C: Add -Wno-psabi to dg-options.

AVR: target/115419 - Tie breaks are rounded-to-even.

libgcc/config/avr/libf7/
PR target/115419
* libf7.c (f7_get_double): Round tie breaks to even LSB.

libstdc++: Make std::type_info::operator== always_inline for C++23 [PR110572]

Commit r12-6266-g3633cc54284450 implemented P1328 for C++23, making
std::type_info::operator== usable in constant expressions. For targets
such as mingw-w64 where that function was not previously inline, making
it constexpr required making it inline for C++23 and later. For
statically linked programs this can result in multiple definition
errors, because there's a non-inline definition in libstdc++.a as well.

For those targets make it always_inline for C++23, so that there is no
symbol generated for the inline definition, and the non-inline
definition in libstdc++.a will be the only definition.

libstdc++-v3/ChangeLog:

PR libstdc++/110572
* libsupc++/typeinfo (type_info::operator==): Add always_inline
attribute for targets where the ABI requries equality to be
non-inline.
* testsuite/18_support/type_info/110572.cc: New test.

libstdc++: Fix declaration of posix_memalign for freestanding

Thanks to Jérôme Duval for noticing this.

libstdc++-v3/ChangeLog:

* libsupc++/new_opa.cc [!_GLIBCXX_HOSTED]: Fix declaration of
posix_memalign.

RISC-V: Add testcases for scalar unsigned SAT_SUB form 10

After the middle-end support the form 10 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 10 of unsigned .SAT_SUB.

Form 10:
  #define SAT_SUB_U_10(T) \
  T sat_sub_u_10_##T (T x, T y) \
  { \
    T ret; \
    T overflow = __builtin_sub_overflow (x, y, &ret); \
    return !overflow ? ret : 0; \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-37.c: New test.
* gcc.target/riscv/sat_u_sub-38.c: New test.
* gcc.target/riscv/sat_u_sub-39.c: New test.
* gcc.target/riscv/sat_u_sub-40.c: New test.
* gcc.target/riscv/sat_u_sub-run-37.c: New test.
* gcc.target/riscv/sat_u_sub-run-38.c: New test.
* gcc.target/riscv/sat_u_sub-run-39.c: New test.
* gcc.target/riscv/sat_u_sub-run-40.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for scalar unsigned SAT_SUB form 9

After the middle-end support the form 9 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 9 of unsigned .SAT_SUB.

Form 9:
  #define SAT_SUB_U_9(T) \
  T sat_sub_u_9_##T (T x, T y) \
  { \
    T ret; \
    T overflow = __builtin_sub_overflow (x, y, &ret); \
    return overflow ? 0 : ret; \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-33.c: New test.
* gcc.target/riscv/sat_u_sub-34.c: New test.
* gcc.target/riscv/sat_u_sub-35.c: New test.
* gcc.target/riscv/sat_u_sub-36.c: New test.
* gcc.target/riscv/sat_u_sub-run-33.c: New test.
* gcc.target/riscv/sat_u_sub-run-34.c: New test.
* gcc.target/riscv/sat_u_sub-run-35.c: New test.
* gcc.target/riscv/sat_u_sub-run-36.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for scalar unsigned SAT_SUB form 8

After the middle-end support the form 8 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 8 of unsigned .SAT_SUB.

Form 8:
  #define SAT_SUB_U_8(T) \
  T sat_sub_u_8_##T (T x, T y) \
  { \
    T ret; \
    T overflow = __builtin_sub_overflow (x, y, &ret); \
    return ret & (T)-(!overflow); \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-29.c: New test.
* gcc.target/riscv/sat_u_sub-30.c: New test.
* gcc.target/riscv/sat_u_sub-31.c: New test.
* gcc.target/riscv/sat_u_sub-32.c: New test.
* gcc.target/riscv/sat_u_sub-run-29.c: New test.
* gcc.target/riscv/sat_u_sub-run-30.c: New test.
* gcc.target/riscv/sat_u_sub-run-31.c: New test.
* gcc.target/riscv/sat_u_sub-run-32.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for scalar unsigned SAT_SUB form 7

After the middle-end support the form 7 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 7 of unsigned .SAT_SUB.

Form 7:
  #define SAT_SUB_U_7(T) \
  T sat_sub_u_7_##T (T x, T y) \
  { \
    T ret; \
    T overflow = __builtin_sub_overflow (x, y, &ret); \
    return ret & (T)(overflow - 1); \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-25.c: New test.
* gcc.target/riscv/sat_u_sub-26.c: New test.
* gcc.target/riscv/sat_u_sub-27.c: New test.
* gcc.target/riscv/sat_u_sub-28.c: New test.
* gcc.target/riscv/sat_u_sub-run-25.c: New test.
* gcc.target/riscv/sat_u_sub-run-26.c: New test.
* gcc.target/riscv/sat_u_sub-run-27.c: New test.
* gcc.target/riscv/sat_u_sub-run-28.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for scalar unsigned SAT_SUB form 6

After the middle-end support the form 6 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 6 of unsigned .SAT_SUB.

Form 6:
  #define SAT_SUB_U_6(T) \
  T sat_sub_u_6_##T (T x, T y) \
  { \
    return x <= y ? 0 : x - y; \
  }

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-21.c: New test.
* gcc.target/riscv/sat_u_sub-22.c: New test.
* gcc.target/riscv/sat_u_sub-23.c: New test.
* gcc.target/riscv/sat_u_sub-24.c: New test.
* gcc.target/riscv/sat_u_sub-run-21.c: New test.
* gcc.target/riscv/sat_u_sub-run-22.c: New test.
* gcc.target/riscv/sat_u_sub-run-23.c: New test.
* gcc.target/riscv/sat_u_sub-run-24.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

RISC-V: Add testcases for scalar unsigned SAT_SUB form 5

After the middle-end support the form 5 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 5 of unsigned .SAT_SUB.

Form 5:
  #define SAT_SUB_U_5(T) \
  T sat_sub_u_5_##T (T x, T y) \
  { \
    return x < y ? 0 : x - y; \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-17.c: New test.
* gcc.target/riscv/sat_u_sub-18.c: New test.
* gcc.target/riscv/sat_u_sub-19.c: New test.
* gcc.target/riscv/sat_u_sub-20.c: New test.
* gcc.target/riscv/sat_u_sub-run-17.c: New test.
* gcc.target/riscv/sat_u_sub-run-18.c: New test.
* gcc.target/riscv/sat_u_sub-run-19.c: New test.
* gcc.target/riscv/sat_u_sub-run-20.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>