backport: htmintrin.h (_TEXASR_INSTRUCTION_FETCH_CONFLICT): Fix typo in macro name.
[gcc]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline
2013-12-03 Peter Bergner <bergner@vnet.ibm.com>
* config/rs6000/htmintrin.h (_TEXASR_INSTRUCTION_FETCH_CONFLICT): Fix
typo in macro name.
(_TEXASRU_INSTRUCTION_FETCH_CONFLICT): Likewise.
Backport from mainline r205233.
2013-11-21 Peter Bergner <bergner@vnet.ibm.com>
* doc/extend.texi: Document htm builtins.
Backport from mainline
2013-07-17 Iain Sandoe <iain@codesourcery.com>
* config/rs6000/darwin.h (REGISTER_NAMES): Add HTM registers.
Backport from mainline
2013-07-16 Peter Bergner <bergner@vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_option_override_internal): Do not
enable extra ISA flags with TARGET_HTM.
2013-07-16 Jakub Jelinek <jakub@redhat.com>
Peter Bergner <bergner@vnet.ibm.com>
* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTERS): Mention HTM
registers in the comment.
(DWARF_FRAME_REGISTERS): Subtract also the 3 HTM registers.
(DWARF_REG_TO_UNWIND_COLUMN): Use DWARF_FRAME_REGISTERS
rather than FIRST_PSEUDO_REGISTERS.
* config.gcc (powerpc*-*-*): Install htmintrin.h and htmxlintrin.h.
* config/rs6000/t-rs6000 (MD_INCLUDES): Add htm.md.
* config/rs6000/rs6000.opt: Add -mhtm option.
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add OPTION_MASK_HTM.
(ISA_2_7_MASKS_SERVER): Add OPTION_MASK_HTM.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
__HTM__ if the HTM instructions are available.
* config/rs6000/predicates.md (u3bit_cint_operand, u10bit_cint_operand)
(htm_spr_reg_operand): New define_predicates.
* config/rs6000/rs6000.md (define_attr "type"): Add htm.
(TFHAR_REGNO, TFIAR_REGNO, TEXASR_REGNO): New define_constants.
Include htm.md.
* config/rs6000/rs6000-builtin.def (BU_HTM_0, BU_HTM_1, BU_HTM_2)
(BU_HTM_3, BU_HTM_SPR0, BU_HTM_SPR1): Add support macros for defining
HTM builtin functions.
* config/rs6000/rs6000.c (RS6000_BUILTIN_H): New macro.
(rs6000_reg_names, alt_reg_names): Add HTM SPR register names.
(rs6000_init_hard_regno_mode_ok): Add support for HTM instructions.
(rs6000_builtin_mask_calculate): Likewise.
(rs6000_option_override_internal): Likewise.
(bdesc_htm): Add new HTM builtin support.
(htm_spr_num): New function.
(htm_spr_regno): Likewise.
(rs6000_htm_spr_icode): Likewise.
(htm_expand_builtin): Likewise.
(htm_init_builtins): Likewise.
(rs6000_expand_builtin): Add support for HTM builtin functions.
(rs6000_init_builtins): Likewise.
(rs6000_invalid_builtin, rs6000_opt_mask): Add support for -mhtm option.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Add support for -mhtm.
(TARGET_HTM, MASK_HTM): Define macros.
(FIRST_PSEUDO_REGISTER): Adjust for new HTM SPR registers.
(FIXED_REGISTERS): Likewise.
(CALL_USED_REGISTERS): Likewise.
(CALL_REALLY_USED_REGISTERS): Likewise.
(REG_ALLOC_ORDER): Likewise.
(enum reg_class): Likewise.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(REGISTER_NAMES): Likewise.
(ADDITIONAL_REGISTER_NAMES): Likewise.
(RS6000_BTC_SPR, RS6000_BTC_VOID, RS6000_BTC_32BIT, RS6000_BTC_64BIT)
(RS6000_BTC_MISC_MASK, RS6000_BTM_HTM): New macros.
(RS6000_BTM_COMMON): Add RS6000_BTM_HTM.
* config/rs6000/htm.md: New file.
* config/rs6000/htmintrin.h: New file.
* config/rs6000/htmxlintrin.h: New file.
[libitm]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline
* acinclude.m4 (LIBITM_CHECK_AS_HTM): New.
* configure: Rebuild.
* configure.tgt (target_cpu): Add -mhtm to XCFLAGS.
* config/powerpc/target.h: Include sys/auxv.h and htmintrin.h.
(USE_HTM_FASTPATH): Define.
(_TBEGIN_STARTED, _TBEGIN_INDETERMINATE, _TBEGIN_PERSISTENT)
(_HTM_RETRIES) New macros.
(htm_abort, htm_abort_should_retry, htm_available, htm_begin, htm_init)
(htm_begin_success, htm_commit, htm_transaction_active): New functions.
[gcc/testsuite]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline
* lib/target-supports.exp (check_effective_target_powerpc_htm_ok): New
function to test if HTM is available.
* gcc.target/powerpc/htm-xl-intrin-1.c: New test.
* gcc.target/powerpc/htm-builtin-1.c: New test.
From-SVN: r209088
Backport PRs 57615, 57744, 58160, 58587, 58673, 59054
[gcc]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Apply mainline
2013-11-23 Alan Modra <amodra@gmail.com>
* config/rs6000/vsx.md (fusion peepholes): Disable when !TARGET_VSX.
Backport from mainline
2013-11-12 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/59054
* config/rs6000/rs6000.md (movdi_internal32): Eliminate
constraints that would allow DImode into the traditional Altivec
registers, but cause undesirable code generation when loading 0 as
a constant.
(movdi_internal64): Likewise.
(cmp<mode>_fpr): Do not use %x for CR register output.
(extendsfdf2_fpr): Fix constraints when -mallow-upper-df and
-mallow-upper-sf debug switches are used.
Backport from mainline
2013-10-17 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (enum rs6000_reload_reg_type): Add new
fields to the reg_addr array that describes the valid addressing
mode for any register, general purpose registers, floating point
registers, and Altivec registers.
(FIRST_RELOAD_REG_CLASS): Likewise.
(LAST_RELOAD_REG_CLASS): Likewise.
(struct reload_reg_map_type): Likewise.
(reload_reg_map_type): Likewise.
(RELOAD_REG_VALID): Likewise.
(RELOAD_REG_MULTIPLE): Likewise.
(RELOAD_REG_INDEXED): Likewise.
(RELOAD_REG_OFFSET): Likewise.
(RELOAD_REG_PRE_INCDEC): Likewise.
(RELOAD_REG_PRE_MODIFY): Likewise.
(reg_addr): Likewise.
(mode_supports_pre_incdec_p): New helper functions to say whether
a given mode supports PRE_INC, PRE_DEC, and PRE_MODIFY.
(mode_supports_pre_modify_p): Likewise.
(rs6000_debug_vector_unit): Rearrange the -mdebug=reg output to
print the valid address mode bits for each mode.
(rs6000_debug_print_mode): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_setup_reg_addr_masks): New function to set up the address
mask bits for each type.
(rs6000_init_hard_regno_mode_ok): Use memset to clear arrays.
Call rs6000_setup_reg_addr_masks to set up the address mask bits.
(rs6000_legitimate_address_p): Use mode_supports_pre_incdec_p and
mode_supports_pre_modify_p to determine if PRE_INC, PRE_DEC, and
PRE_MODIFY are supported.
(rs6000_output_move_128bit): Change to use {src,dest}_vmx_p for altivec
registers, instead of {src,dest}_av_p.
(rs6000_print_options_internal): Tweak the debug output slightly.
Backport from mainline
2013-10-03 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-builtin.def (XSRDPIM): Use floatdf2,
ceildf2, btruncdf2, instead of vsx_* name.
* config/rs6000/vsx.md (vsx_add<mode>3): Change arithmetic
iterators to only do V2DF and V4SF here. Move the DF code to
rs6000.md where it is combined with SF mode. Replace <VSv> with
just 'v' since only vector operations are handled with these insns
after moving the DF support to rs6000.md.
(vsx_sub<mode>3): Likewise.
(vsx_mul<mode>3): Likewise.
(vsx_div<mode>3): Likewise.
(vsx_fre<mode>2): Likewise.
(vsx_neg<mode>2): Likewise.
(vsx_abs<mode>2): Likewise.
(vsx_nabs<mode>2): Likewise.
(vsx_smax<mode>3): Likewise.
(vsx_smin<mode>3): Likewise.
(vsx_sqrt<mode>2): Likewise.
(vsx_rsqrte<mode>2): Likewise.
(vsx_fms<mode>4): Likewise.
(vsx_nfma<mode>4): Likewise.
(vsx_copysign<mode>3): Likewise.
(vsx_btrunc<mode>2): Likewise.
(vsx_floor<mode>2): Likewise.
(vsx_ceil<mode>2): Likewise.
(vsx_smaxsf3): Delete scalar ops that were moved to rs6000.md.
(vsx_sminsf3): Likewise.
(vsx_fmadf4): Likewise.
(vsx_fmsdf4): Likewise.
(vsx_nfmadf4): Likewise.
(vsx_nfmsdf4): Likewise.
(vsx_cmpdf_internal1): Likewise.
* config/rs6000/rs6000.h (TARGET_SF_SPE): Define macros to make it
simpler to select whether a target has SPE or traditional floating
point support in iterators.
(TARGET_DF_SPE): Likewise.
(TARGET_SF_FPR): Likewise.
(TARGET_DF_FPR): Likewise.
(TARGET_SF_INSN): Macros to say whether floating point support
exists for a given operation for expanders.
(TARGET_DF_INSN): Likewise.
* config/rs6000/rs6000.c (Ftrad): New mode attributes to allow
combining of SF/DF mode operations, using both traditional and VSX
registers.
(Fvsx): Likewise.
(Ff): Likewise.
(Fv): Likewise.
(Fs): Likewise.
(Ffre): Likewise.
(FFRE): Likewise.
(abs<mode>2): Combine SF/DF modes using traditional floating point
instructions. Add support for using the upper DF registers with
VSX support, and SF registers with power8-vector support. Update
expanders for operations supported by both the SPE and traditional
floating point units.
(abs<mode>2_fpr): Likewise.
(nabs<mode>2): Likewise.
(nabs<mode>2_fpr): Likewise.
(neg<mode>2): Likewise.
(neg<mode>2_fpr): Likewise.
(add<mode>3): Likewise.
(add<mode>3_fpr): Likewise.
(sub<mode>3): Likewise.
(sub<mode>3_fpr): Likewise.
(mul<mode>3): Likewise.
(mul<mode>3_fpr): Likewise.
(div<mode>3): Likewise.
(div<mode>3_fpr): Likewise.
(sqrt<mode>3): Likewise.
(sqrt<mode>3_fpr): Likewise.
(fre<Fs>): Likewise.
(rsqrt<mode>2): Likewise.
(cmp<mode>_fpr): Likewise.
(smax<mode>3): Likewise.
(smin<mode>3): Likewise.
(smax<mode>3_vsx): Likewise.
(smin<mode>3_vsx): Likewise.
(negsf2): Delete SF operations that are merged with DF.
(abssf2): Likewise.
(addsf3): Likewise.
(subsf3): Likewise.
(mulsf3): Likewise.
(divsf3): Likewise.
(fres): Likewise.
(fmasf4_fpr): Likewise.
(fmssf4_fpr): Likewise.
(nfmasf4_fpr): Likewise.
(nfmssf4_fpr): Likewise.
(sqrtsf2): Likewise.
(rsqrtsf_internal1): Likewise.
(smaxsf3): Likewise.
(sminsf3): Likewise.
(cmpsf_internal1): Likewise.
(copysign<mode>3_fcpsgn): Add VSX/power8-vector support.
(negdf2): Delete DF operations that are merged with SF.
(absdf2): Likewise.
(nabsdf2): Likewise.
(adddf3): Likewise.
(subdf3): Likewise.
(muldf3): Likewise.
(divdf3): Likewise.
(fred): Likewise.
(rsqrtdf_internal1): Likewise.
(fmadf4_fpr): Likewise.
(fmsdf4_fpr): Likewise.
(nfmadf4_fpr): Likewise.
(nfmsdf4_fpr): Likewise.
(sqrtdf2): Likewise.
(smaxdf3): Likewise.
(smindf3): Likewise.
(cmpdf_internal1): Likewise.
(lrint<mode>di2): Use TARGET_<MODE>_FPR macro.
(btrunc<mode>2): Delete separate expander, and combine with the
insn and add VSX instruction support. Use TARGET_<MODE>_FPR.
(btrunc<mode>2_fpr): Likewise.
(ceil<mode>2): Likewise.
(ceil<mode>2_fpr): Likewise.
(floor<mode>2): Likewise.
(floor<mode>2_fpr): Likewise.
(fma<mode>4_fpr): Combine SF and DF fused multiply/add support.
Add support for using the upper registers with VSX and
power8-vector. Move insns to be closer to the define_expands. On
VSX systems, prefer the traditional form of FMA over the VSX
version, since the traditional form allows the target not to
overlap with the inputs.
(fms<mode>4_fpr): Likewise.
(nfma<mode>4_fpr): Likewise.
(nfms<mode>4_fpr): Likewise.
Backport from mainline
2013-09-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Allow
DFmode, DImode, and SFmode in the upper VSX registers based on the
-mupper-regs-{df,sf} flags. Fix wu constraint to be ALTIVEC_REGS
if -mpower8-vector. Combine -mvsx-timode handling with the rest
of the VSX register handling.
* config/rs6000/rs6000.md (f32_lv): Use %x0 for VSX regsters.
(f32_sv): Likewise.
(zero_extendsidi2_lfiwzx): Add support for loading into the
Altivec registers with -mpower8-vector. Use wu/wv constraints to
only do VSX memory options on Altivec registers.
(extendsidi2_lfiwax): Likewise.
(extendsfdf2_fpr): Likewise.
(mov<mode>_hardfloat, SF/SD modes): Likewise.
(mov<mode>_hardfloat32, DF/DD modes): Likewise.
(mov<mode>_hardfloat64, DF/DD modes): Likewise.
(movdi_internal64): Likewise.
Backport from mainline
2013-09-23 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_vector_reload): Delete, combine
reload helper function arrays into a single array reg_addr.
(reload_fpr_gpr): Likewise.
(reload_gpr_vsx): Likewise.
(reload_vsx_gpr): Likewise.
(struct rs6000_reg_addr): Likewise.
(reg_addr): Likewise.
(rs6000_debug_reg_global): Change rs6000_vector_reload,
reload_fpr_gpr, reload_gpr_vsx, reload_vsx_gpr uses to reg_addr.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_secondary_reload_direct_move): Likewise.
(rs6000_secondary_reload): Likewise.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add new
constraints: wu, ww, and wy. Repurpose wv constraint added during
power8 changes. Put wg constraint in alphabetical order.
* config/rs6000/rs6000.opt (-mvsx-scalar-float): New debug switch
for future work to add ISA 2.07 VSX single precision support.
(-mvsx-scalar-double): Change default from -1 to 1, update
documentation comment.
(-mvsx-scalar-memory): Rename debug switch to -mupper-regs-df.
(-mupper-regs-df): New debug switch to control whether DF values
can go in the traditional Altivec registers.
(-mupper-regs-sf): New debug switch to control whether SF values
can go in the traditional Altivec registers.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Print wu, ww,
and wy constraints.
(rs6000_init_hard_regno_mode_ok): Use ssize_t instead of int for
loop variables. Rename -mvsx-scalar-memory to -mupper-regs-df.
Add new constraints, wu/ww/wy. Repurpose wv constraint.
(rs6000_debug_legitimate_address_p): Print if we are running
before, during, or after reload.
(rs6000_secondary_reload): Add a comment.
(rs6000_opt_masks): Add -mupper-regs-df, -mupper-regs-sf.
* config/rs6000/constraints.md (wa constraint): Sort w<x>
constraints. Update documentation string.
(wd constraint): Likewise.
(wf constraint): Likewise.
(wg constraint): Likewise.
(wn constraint): Likewise.
(ws constraint): Likewise.
(wt constraint): Likewise.
(wx constraint): Likewise.
(wz constraint): Likewise.
(wu constraint): New constraint for ISA 2.07 SFmode scalar
instructions.
(ww constraint): Likewise.
(wy constraint): Likewise.
(wv constraint): Repurpose ISA 2.07 constraint that did not use in
the previous submissions.
* doc/md.texi (PowerPC and IBM RS6000): Likewise.
Backport from mainline
2013-10-17 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/58673
* config/rs6000/rs6000.c (rs6000_legitimate_address_p): Only
restrict TImode addresses to single indirect registers if both
-mquad-memory and -mvsx-timode are used.
(rs6000_output_move_128bit): Use quad_load_store_p to determine if
we should emit load/store quad. Remove using %y for quad memory
addresses.
* config/rs6000/rs6000.md (mov<mode>_ppc64, TI/PTImode): Add
constraints to allow load/store quad on machines where TImode is
not allowed in VSX registers. Use 'n' instead of 'F' constraint
for TImode to load integer constants.
Backport from mainline
2013-10-02 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/58587
* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Turn off
setting -mvsx-timode by default until the underlying problem is
fixed.
(RS6000_CPU, power7 defaults): Likewise.
Backport from trunk
2013-08-16 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/58160
* config/rs6000/predicates.md (fusion_gpr_mem_load): Allow the
memory rtx to contain ZERO_EXTEND and SIGN_EXTEND.
* config/rs6000/rs6000-protos.h (fusion_gpr_load_p): Pass operands
array instead of each individual operand as a separate argument.
(emit_fusion_gpr_load): Likewise.
(expand_fusion_gpr_load): Add new function declaration.
* config/rs6000/rs6000.c (fusion_gpr_load_p): Change the calling
signature to have the operands passed as an array, instead of as
separate arguments. Allow ZERO_EXTEND to be in the memory
address, and also SIGN_EXTEND if -mpower8-fusion-sign. Do not
depend on the register live/dead flags when peepholes are run.
(expand_fusion_gpr_load): New function to be called from the
peephole2 pass, to change the register that addis sets to be the
target register.
(emit_fusion_gpr_load): Change the calling signature to have the
operands passed as an array, instead of as separate arguments.
Allow ZERO_EXTEND to be in the memory address, and also
SIGN_EXTEND if -mpower8-fusion-sign.
* config/rs6000/rs6000.md (UNSPEC_FUSION_GPR): Delete unused
unspec enumeration.
(power8 fusion peephole/peephole2): Rework the fusion peepholes to
adjust the register addis loads up in the peephole2 pass. Do not
depend on the register live/dead state when the peephole pass is
done.
Backport from trunk
2013-07-23 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vector.md (xor<mode>3): Move 128-bit boolean
expanders to rs6000.md.
(ior<mode>3): Likewise.
(and<mode>3): Likewise.
(one_cmpl<mode>2): Likewise.
(nor<mode>3): Likewise.
(andc<mode>3): Likewise.
(eqv<mode>3): Likewise.
(nand<mode>3): Likewise.
(orc<mode>3): Likewise.
* config/rs6000/rs6000-protos.h (rs6000_split_logical): New
declaration.
* config/rs6000/rs6000.c (rs6000_split_logical_inner): Add support
to split multi-word logical operations.
(rs6000_split_logical_di): Likewise.
(rs6000_split_logical): Likewise.
* config/rs6000/vsx.md (VSX_L2): Delete, no longer used.
(vsx_and<mode>3_32bit): Move 128-bit logical insns to rs6000.md,
and allow TImode operations in 32-bit.
(vsx_and<mode>3_64bit): Likewise.
(vsx_ior<mode>3_32bit): Likewise.
(vsx_ior<mode>3_64bit): Likewise.
(vsx_xor<mode>3_32bit): Likewise.
(vsx_xor<mode>3_64bit): Likewise.
(vsx_one_cmpl<mode>2_32bit): Likewise.
(vsx_one_cmpl<mode>2_64bit): Likewise.
(vsx_nor<mode>3_32bit): Likewise.
(vsx_nor<mode>3_64bit): Likewise.
(vsx_andc<mode>3_32bit): Likewise.
(vsx_andc<mode>3_64bit): Likewise.
(vsx_eqv<mode>3_32bit): Likewise.
(vsx_eqv<mode>3_64bit): Likewise.
(vsx_nand<mode>3_32bit): Likewise.
(vsx_nand<mode>3_64bit): Likewise.
(vsx_orc<mode>3_32bit): Likewise.
(vsx_orc<mode>3_64bit): Likewise.
* config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Always allow vector
logical types in GPRs.
* config/rs6000/altivec.md (altivec_and<mode>3): Move 128-bit
logical insns to rs6000.md, and allow TImode operations in
32-bit.
(altivec_ior<mode>3): Likewise.
(altivec_xor<mode>3): Likewise.
(altivec_one_cmpl<mode>2): Likewise.
(altivec_nor<mode>3): Likewise.
(altivec_andc<mode>3): Likewise.
* config/rs6000/rs6000.md (BOOL_128): New mode iterators and mode
attributes for moving the 128-bit logical operations into
rs6000.md.
(BOOL_REGS_OUTPUT): Likewise.
(BOOL_REGS_OP1): Likewise.
(BOOL_REGS_OP2): Likewise.
(BOOL_REGS_UNARY): Likewise.
(BOOL_REGS_AND_CR0): Likewise.
(one_cmpl<mode>2): Add support for DI logical operations on
32-bit, splitting the operations to 32-bit.
(anddi3): Likewise.
(iordi3): Likewise.
(xordi3): Likewise.
(and<mode>3, 128-bit types): Rewrite 2013-06-06 logical operator
changes to combine the 32/64-bit code, allow logical operations on
TI mode in 32-bit, and to use similar match_operator patterns like
scalar mode uses. Combine the Altivec and VSX code for logical
operations, and move it here.
(ior<mode>3, 128-bit types): Likewise.
(xor<mode>3, 128-bit types): Likewise.
(one_cmpl<mode>3, 128-bit types): Likewise.
(nor<mode>3, 128-bit types): Likewise.
(andc<mode>3, 128-bit types): Likewise.
(eqv<mode>3, 128-bit types): Likewise.
(nand<mode>3, 128-bit types): Likewise.
(orc<mode>3, 128-bit types): Likewise.
(and<mode>3_internal): Likewise.
(bool<mode>3_internal): Likewise.
(boolc<mode>3_internal1): Likewise.
(boolc<mode>3_internal2): Likewise.
(boolcc<mode>3_internal1): Likewise.
(boolcc<mode>3_internal2): Likewise.
(eqv<mode>3_internal1): Likewise.
(eqv<mode>3_internal2): Likewise.
(one_cmpl1<mode>3_internal): Likewise.
Back port from mainline:
2013-06-06 Michael Meissner <meissner@linux.vnet.ibm.com>
Pat Haugen <pthaugen@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
* lib/target-supports.exp (check_p8vector_hw_available) Add power8
support.
(check_effective_target_powerpc_p8vector_ok): Likewise.
(is-effective-target): Likewise.
(check_vect_support_and_set_flags): Likewise.
Backport from mainline
2013-07-31 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/predicates.md (fusion_gpr_addis): New predicates
to support power8 load fusion.
(fusion_gpr_mem_load): Likewise.
* config/rs6000/rs6000-modes.def (PTImode): Update a comment.
* config/rs6000/rs6000-protos.h (fusion_gpr_load_p): New
declarations for power8 load fusion.
(emit_fusion_gpr_load): Likewise.
* config/rs6000/rs6000.c (rs6000_option_override_internal): If
tuning for power8, turn on fusion mode by default. Turn on sign
extending fusion mode if normal fusion mode is on, and we are at
-O2 or -O3.
(fusion_gpr_load_p): New function, return true if we can fuse an
addis instruction with a dependent load to a GPR.
(emit_fusion_gpr_load): Emit the instructions for power8 load
fusion to GPRs.
* config/rs6000/vsx.md (VSX_M2): New iterator for fusion
peepholes.
(VSX load fusion peepholes): New peepholes to fuse together an
addi instruction with a VSX load instruction.
* config/rs6000/rs6000.md (GPR load fusion peepholes): New
peepholes to fuse an addis instruction with a load to a GPR base
register. If we are supporting sign extending fusions, convert
sign extending loads to zero extending loads and add an explicit
sign extension.
Backport from mainline
2013-07-18 Pat Haugen <pthaugen@us.ibm.com>
* config/rs6000/rs6000.c (rs6000_option_override_internal): Adjust flag
interaction for new Power8 flags and VSX.
Back port from the trunk
2013-06-28 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/57744
* config/rs6000/rs6000.h (MODES_TIEABLE_P): Do not allow PTImode
to tie with any other modes. Eliminate Altivec vector mode tests,
since these are a subset of ALTIVEC or VSX vector modes. Simplify
code, to return 0 if testing MODE2 for a condition, if we've
already tested MODE1 for the same condition.
Backport from mainline
2013-06-28 Pat Haugen <pthaugen@us.ibm.com>
* config/rs6000/rs6000.md (define_insn ""): Fix insn type.
Back port from the trunk
2013-06-26 Michael Meissner <meissner@linux.vnet.ibm.com>
Pat Haugen <pthaugen@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
* config/rs6000/power8.md: New.
* config/rs6000/rs6000-cpus.def (RS6000_CPU table): Adjust processor
setting for power8 entry.
* config/rs6000/t-rs6000 (MD_INCLUDES): Add power8.md.
* config/rs6000/rs6000.c (is_microcoded_insn, is_cracked_insn): Adjust
test for Power4/Power5 only.
(insn_must_be_first_in_group, insn_must_be_last_in_group): Add Power8
support.
(force_new_group): Adjust comment.
* config/rs6000/rs6000.md: Include power8.md.
Back port from the trunk
2013-06-14 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/57615
* config/rs6000/rs6000.md (mov<mode>_ppc64): Call
rs6000_output_move_128bit to handle emitting quad memory
operations. Set attribute length to 8 bytes.
Back port from the trunk
2013-06-13 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_option_override_internal): Move
test for clearing quad memory on 32-bit later.
Back port from the trunk
2013-06-12 Michael Meissner <meissner@linux.vnet.ibm.com>
Pat Haugen <pthaugen@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
* config/rs6000/rs6000.c (emit_load_locked): Add support for
power8 byte, half-word, and quad-word atomic instructions.
(emit_store_conditional): Likewise.
(rs6000_expand_atomic_compare_and_swap): Likewise.
(rs6000_expand_atomic_op): Likewise.
* config/rs6000/sync.md (larx): Add new modes for power8.
(stcx): Likewise.
(AINT): New mode iterator to include TImode as well as normal
integer modes on power8.
(fetchop_pred): Use int_reg_operand instead of gpc_reg_operand so
that VSX registers are not considered. Use AINT mode iterator
instead of INT1 to allow inclusion of quad word atomic operations
on power8.
(load_locked<mode>): Likewise.
(store_conditional<mode>): Likewise.
(atomic_compare_and_swap<mode>): Likewise.
(atomic_exchange<mode>): Likewise.
(atomic_nand<mode>): Likewise.
(atomic_fetch_<fetchop_name><mode>): Likewise.
(atomic_nand_fetch<mode>): Likewise.
(mem_thread_fence): Use gen_loadsync_<mode> instead of enumerating
each type.
(ATOMIC): On power8, add QImode, HImode modes.
(load_locked<QHI:mode>_si): Varients of load_locked for QI/HI
modes that promote to SImode.
(load_lockedti): Convert TImode arguments to PTImode, so that we
get a guaranteed even/odd register pair.
(load_lockedpti): Likewise.
(store_conditionalti): Likewise.
(store_conditionalpti): Likewise.
* config/rs6000/rs6000.md (QHI): New mode iterator for power8
atomic load/store instructions.
(HSI): Likewise.
Back port from the trunk
2013-06-10 Michael Meissner <meissner@linux.vnet.ibm.com>
Pat Haugen <pthaugen@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
* config/rs6000/vector.md (GPR move splitter): Do not split moves
of vectors in GPRS if they are direct moves or quad word load or
store moves.
* config/rs6000/rs6000-protos.h (rs6000_output_move_128bit): Add
declaration.
(direct_move_p): Likewise.
(quad_load_store_p): Likewise.
* config/rs6000/rs6000.c (enum rs6000_reg_type): Simplify register
classes into bins based on the physical register type.
(reg_class_to_reg_type): Likewise.
(IS_STD_REG_TYPE): Likewise.
(IS_FP_VECT_REG_TYPE): Likewise.
(reload_fpr_gpr): Arrays to determine what insn to use if we can
use direct move instructions.
(reload_gpr_vsx): Likewise.
(reload_vsx_gpr): Likewise.
(rs6000_init_hard_regno_mode_ok): Precalculate the register type
information that is a simplification of register classes. Also
precalculate direct move reload helpers.
(direct_move_p): New function to return true if the operation can
be done as a direct move instruciton.
(quad_load_store_p): New function to return true if the operation
is a quad memory operation.
(rs6000_legitimize_address): If quad memory, only allow register
indirect for TImode addresses.
(rs6000_legitimate_address_p): Likewise.
(enum reload_reg_type): Delete, replace with rs6000_reg_type.
(rs6000_reload_register_type): Likewise.
(register_to_reg_type): Return register type.
(rs6000_secondary_reload_simple_move): New helper function for
secondary reload and secondary memory needed to identify anything
that is a simple move, and does not need reloading.
(rs6000_secondary_reload_direct_move): New helper function for
secondary reload to identify cases that can be done with several
instructions via the direct move instructions.
(rs6000_secondary_reload_move): New helper function for secondary
reload to identify moves between register types that can be done.
(rs6000_secondary_reload): Add support for quad memory operations
and for direct move.
(rs6000_secondary_memory_needed): Likewise.
(rs6000_debug_secondary_memory_needed): Change argument names.
(rs6000_output_move_128bit): New function to return the move to
use for 128-bit moves, including knowing about the various
limitations of quad memory operations.
* config/rs6000/vsx.md (vsx_mov<mode>): Add support for quad
memory operations. call rs6000_output_move_128bit for the actual
instruciton(s) to generate.
(vsx_movti_64bit): Likewise.
* config/rs6000/rs6000.md (UNSPEC_P8V_FMRGOW): New unspec values.
(UNSPEC_P8V_MTVSRWZ): Likewise.
(UNSPEC_P8V_RELOAD_FROM_GPR): Likewise.
(UNSPEC_P8V_MTVSRD): Likewise.
(UNSPEC_P8V_XXPERMDI): Likewise.
(UNSPEC_P8V_RELOAD_FROM_VSX): Likewise.
(UNSPEC_FUSION_GPR): Likewise.
(FMOVE128_GPR): New iterator for direct move.
(f32_lv): New mode attribute for load/store of SFmode/SDmode
values.
(f32_sv): Likewise.
(f32_dm): Likewise.
(zero_extend<mode>di2_internal1): Add support for power8 32-bit
loads and direct move instructions.
(zero_extendsidi2_lfiwzx): Likewise.
(extendsidi2_lfiwax): Likewise.
(extendsidi2_nocell): Likewise.
(floatsi<mode>2_lfiwax): Likewise.
(lfiwax): Likewise.
(floatunssi<mode>2_lfiwzx): Likewise.
(lfiwzx): Likewise.
(fix_trunc<mode>_stfiwx): Likewise.
(fixuns_trunc<mode>_stfiwx): Likewise.
(mov<mode>_hardfloat, 32-bit floating point): Likewise.
(mov<move>_hardfloat64, 64-bit floating point): Likewise.
(parity<mode>2_cmpb): Set length/type attr.
(unnamed shift right patterns, mov<mode>_internal2): Change type attr
for 'mr.' to fast_compare.
(bpermd_<mode>): Change type attr to popcnt.
(p8_fmrgow_<mode>): New insns for power8 direct move support.
(p8_mtvsrwz_1): Likewise.
(p8_mtvsrwz_2): Likewise.
(reload_fpr_from_gpr<mode>): Likewise.
(p8_mtvsrd_1): Likewise.
(p8_mtvsrd_2): Likewise.
(p8_xxpermdi_<mode>): Likewise.
(reload_vsx_from_gpr<mode>): Likewise.
(reload_vsx_from_gprsf): Likewise.
(p8_mfvsrd_3_<mode>): LIkewise.
(reload_gpr_from_vsx<mode>): Likewise.
(reload_gpr_from_vsxsf): Likewise.
(p8_mfvsrd_4_disf): Likewise.
(multi-word GPR splits): Do not split direct moves or quad memory
operations.
Backport from the trunk
2013-06-06 Michael Meissner <meissner@linux.vnet.ibm.com>
Pat Haugen <pthaugen@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
* doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
Document new power8 builtins.
* config/rs6000/vector.md (and<mode>3): Add a clobber/scratch of a
condition code register, to allow 128-bit logical operations to be
done in the VSX or GPR registers.
(nor<mode>3): Use the canonical form for nor.
(eqv<mode>3): Add expanders for power8 xxleqv, xxlnand, xxlorc,
vclz*, and vpopcnt* vector instructions.
(nand<mode>3): Likewise.
(orc<mode>3): Likewise.
(clz<mode>2): LIkewise.
(popcount<mode>2): Likewise.
* config/rs6000/predicates.md (int_reg_operand): Rework tests so
that only the GPRs are recognized.
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
support for new power8 builtins.
* config/rs6000/rs6000-builtin.def (xscvspdpn): Add new power8
builtin functions.
(xscvdpspn): Likewise.
(vclz): Likewise.
(vclzb): Likewise.
(vclzh): Likewise.
(vclzw): Likewise.
(vclzd): Likewise.
(vpopcnt): Likewise.
(vpopcntb): Likewise.
(vpopcnth): Likewise.
(vpopcntw): Likewise.
(vpopcntd): Likewise.
(vgbbd): Likewise.
(vmrgew): Likewise.
(vmrgow): Likewise.
(eqv): Likewise.
(eqv_v16qi3): Likewise.
(eqv_v8hi3): Likewise.
(eqv_v4si3): Likewise.
(eqv_v2di3): Likewise.
(eqv_v4sf3): Likewise.
(eqv_v2df3): Likewise.
(nand): Likewise.
(nand_v16qi3): Likewise.
(nand_v8hi3): Likewise.
(nand_v4si3): Likewise.
(nand_v2di3): Likewise.
(nand_v4sf3): Likewise.
(nand_v2df3): Likewise.
(orc): Likewise.
(orc_v16qi3): Likewise.
(orc_v8hi3): Likewise.
(orc_v4si3): Likewise.
(orc_v2di3): Likewise.
(orc_v4sf3): Likewise.
(orc_v2df3): Likewise.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Only
allow power8 quad mode in 64-bit.
(rs6000_builtin_vectorized_function): Add support to vectorize
ISA 2.07 count leading zeros, population count builtins.
(rs6000_expand_vector_init): On ISA 2.07 use xscvdpspn to form
V4SF vectors instead of xscvdpsp to avoid IEEE related traps.
(builtin_function_type): Add vgbbd builtin function which takes an
unsigned argument.
(altivec_expand_vec_perm_const): Add support for new power8 merge
instructions.
* config/rs6000/vsx.md (VSX_L2): New iterator for 128-bit types,
that does not include TImdoe for use with 32-bit.
(UNSPEC_VSX_CVSPDPN): Support for power8 xscvdpspn and xscvspdpn
instructions.
(UNSPEC_VSX_CVDPSPN): Likewise.
(vsx_xscvdpspn): Likewise.
(vsx_xscvspdpn): Likewise.
(vsx_xscvdpspn_scalar): Likewise.
(vsx_xscvspdpn_directmove): Likewise.
(vsx_and<mode>3): Split logical operations into 32-bit and
64-bit. Add support to do logical operations on TImode as well as
VSX vector types. Allow logical operations to be done in either
VSX registers or in general purpose registers in 64-bit mode. Add
splitters if GPRs were used. For AND, add clobber of CCmode to
allow use of ANDI on GPRs. Rewrite nor to use the canonical RTL
encoding.
(vsx_and<mode>3_32bit): Likewise.
(vsx_and<mode>3_64bit): Likewise.
(vsx_ior<mode>3): Likewise.
(vsx_ior<mode>3_32bit): Likewise.
(vsx_ior<mode>3_64bit): Likewise.
(vsx_xor<mode>3): Likewise.
(vsx_xor<mode>3_32bit): Likewise.
(vsx_xor<mode>3_64bit): Likewise.
(vsx_one_cmpl<mode>2): Likewise.
(vsx_one_cmpl<mode>2_32bit): Likewise.
(vsx_one_cmpl<mode>2_64bit): Likewise.
(vsx_nor<mode>3): Likewise.
(vsx_nor<mode>3_32bit): Likewise.
(vsx_nor<mode>3_64bit): Likewise.
(vsx_andc<mode>3): Likewise.
(vsx_andc<mode>3_32bit): Likewise.
(vsx_andc<mode>3_64bit): Likewise.
(vsx_eqv<mode>3_32bit): Add support for power8 xxleqv, xxlnand,
and xxlorc instructions.
(vsx_eqv<mode>3_64bit): Likewise.
(vsx_nand<mode>3_32bit): Likewise.
(vsx_nand<mode>3_64bit): Likewise.
(vsx_orc<mode>3_32bit): Likewise.
(vsx_orc<mode>3_64bit): Likewise.
* config/rs6000/rs6000.h (VLOGICAL_REGNO_P): Update comment.
* config/rs6000/altivec.md (UNSPEC_VGBBD): Add power8 vgbbd
instruction.
(p8_vmrgew): Add power8 vmrgew and vmrgow instructions.
(p8_vmrgow): Likewise.
(altivec_and<mode>3): Add clobber of CCmode to allow AND using
GPRs to be split under VSX.
(p8v_clz<mode>2): Add power8 count leading zero support.
(p8v_popcount<mode>2): Add power8 population count support.
(p8v_vgbbd): Add power8 gather bits by bytes by doubleword
support.
* config/rs6000/rs6000.md (eqv<mode>3): Add support for powerp eqv
instruction.
* config/rs6000/altivec.h (vec_eqv): Add defines to export power8
builtin functions.
(vec_nand): Likewise.
(vec_vclz): Likewise.
(vec_vclzb): Likewise.
(vec_vclzd): Likewise.
(vec_vclzh): Likewise.
(vec_vclzw): Likewise.
(vec_vgbbd): Likewise.
(vec_vmrgew): Likewise.
(vec_vmrgow): Likewise.
(vec_vpopcnt): Likewise.
(vec_vpopcntb): Likewise.
(vec_vpopcntd): Likewise.
(vec_vpopcnth): Likewise.
(vec_vpopcntw): Likewise.
Backport from trunk
2013-05-29 Michael Meissner <meissner@linux.vnet.ibm.com>
Pat Haugen <pthaugen@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
* config/rs6000/vector.md (VEC_I): Add support for new power8 V2DI
instructions.
(VEC_A): Likewise.
(VEC_C): Likewise.
(vrotl<mode>3): Likewise.
(vashl<mode>3): Likewise.
(vlshr<mode>3): Likewise.
(vashr<mode>3): Likewise.
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
support for power8 V2DI builtins.
* config/rs6000/rs6000-builtin.def (abs_v2di): Add support for
power8 V2DI builtins.
(vupkhsw): Likewise.
(vupklsw): Likewise.
(vaddudm): Likewise.
(vminsd): Likewise.
(vmaxsd): Likewise.
(vminud): Likewise.
(vmaxud): Likewise.
(vpkudum): Likewise.
(vpksdss): Likewise.
(vpkudus): Likewise.
(vpksdus): Likewise.
(vrld): Likewise.
(vsld): Likewise.
(vsrd): Likewise.
(vsrad): Likewise.
(vsubudm): Likewise.
(vcmpequd): Likewise.
(vcmpgtsd): Likewise.
(vcmpgtud): Likewise.
(vcmpequd_p): Likewise.
(vcmpgtsd_p): Likewise.
(vcmpgtud_p): Likewise.
(vupkhsw): Likewise.
(vupklsw): Likewise.
(vaddudm): Likewise.
(vmaxsd): Likewise.
(vmaxud): Likewise.
(vminsd): Likewise.
(vminud): Likewise.
(vpksdss): Likewise.
(vpksdus): Likewise.
(vpkudum): Likewise.
(vpkudus): Likewise.
(vrld): Likewise.
(vsld): Likewise.
(vsrad): Likewise.
(vsrd): Likewise.
(vsubudm): Likewise.
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Add
support for power8 V2DI instructions.
* config/rs6000/altivec.md (UNSPEC_VPKUHUM): Add support for
power8 V2DI instructions. Combine pack and unpack insns to use an
iterator for each mode. Check whether a particular mode supports
Altivec instructions instead of just checking TARGET_ALTIVEC.
(UNSPEC_VPKUWUM): Likewise.
(UNSPEC_VPKSHSS): Likewise.
(UNSPEC_VPKSWSS): Likewise.
(UNSPEC_VPKUHUS): Likewise.
(UNSPEC_VPKSHUS): Likewise.
(UNSPEC_VPKUWUS): Likewise.
(UNSPEC_VPKSWUS): Likewise.
(UNSPEC_VPACK_SIGN_SIGN_SAT): Likewise.
(UNSPEC_VPACK_SIGN_UNS_SAT): Likewise.
(UNSPEC_VPACK_UNS_UNS_SAT): Likewise.
(UNSPEC_VPACK_UNS_UNS_MOD): Likewise.
(UNSPEC_VUPKHSB): Likewise.
(UNSPEC_VUNPACK_HI_SIGN): Likewise.
(UNSPEC_VUNPACK_LO_SIGN): Likewise.
(UNSPEC_VUPKHSH): Likewise.
(UNSPEC_VUPKLSB): Likewise.
(UNSPEC_VUPKLSH): Likewise.
(VI2): Likewise.
(VI_char): Likewise.
(VI_scalar): Likewise.
(VI_unit): Likewise.
(VP): Likewise.
(VP_small): Likewise.
(VP_small_lc): Likewise.
(VU_char): Likewise.
(add<mode>3): Likewise.
(altivec_vaddcuw): Likewise.
(altivec_vaddu<VI_char>s): Likewise.
(altivec_vadds<VI_char>s): Likewise.
(sub<mode>3): Likewise.
(altivec_vsubcuw): Likewise.
(altivec_vsubu<VI_char>s): Likewise.
(altivec_vsubs<VI_char>s): Likewise.
(altivec_vavgs<VI_char>): Likewise.
(altivec_vcmpbfp): Likewise.
(altivec_eq<mode>): Likewise.
(altivec_gt<mode>): Likewise.
(altivec_gtu<mode>): Likewise.
(umax<mode>3): Likewise.
(smax<mode>3): Likewise.
(umin<mode>3): Likewise.
(smin<mode>3): Likewise.
(altivec_vpkuhum): Likewise.
(altivec_vpkuwum): Likewise.
(altivec_vpkshss): Likewise.
(altivec_vpkswss): Likewise.
(altivec_vpkuhus): Likewise.
(altivec_vpkshus): Likewise.
(altivec_vpkuwus): Likewise.
(altivec_vpkswus): Likewise.
(altivec_vpks<VI_char>ss): Likewise.
(altivec_vpks<VI_char>us): Likewise.
(altivec_vpku<VI_char>us): Likewise.
(altivec_vpku<VI_char>um): Likewise.
(altivec_vrl<VI_char>): Likewise.
(altivec_vsl<VI_char>): Likewise.
(altivec_vsr<VI_char>): Likewise.
(altivec_vsra<VI_char>): Likewise.
(altivec_vsldoi_<mode>): Likewise.
(altivec_vupkhsb): Likewise.
(altivec_vupkhs<VU_char>): Likewise.
(altivec_vupkls<VU_char>): Likewise.
(altivec_vupkhsh): Likewise.
(altivec_vupklsb): Likewise.
(altivec_vupklsh): Likewise.
(altivec_vcmpequ<VI_char>_p): Likewise.
(altivec_vcmpgts<VI_char>_p): Likewise.
(altivec_vcmpgtu<VI_char>_p): Likewise.
(abs<mode>2): Likewise.
(vec_unpacks_hi_v16qi): Likewise.
(vec_unpacks_hi_v8hi): Likewise.
(vec_unpacks_lo_v16qi): Likewise.
(vec_unpacks_hi_<VP_small_lc>): Likewise.
(vec_unpacks_lo_v8hi): Likewise.
(vec_unpacks_lo_<VP_small_lc>): Likewise.
(vec_pack_trunc_v8h): Likewise.
(vec_pack_trunc_v4si): Likewise.
(vec_pack_trunc_<mode>): Likewise.
* config/rs6000/altivec.h (vec_vaddudm): Add defines for power8
V2DI builtins.
(vec_vmaxsd): Likewise.
(vec_vmaxud): Likewise.
(vec_vminsd): Likewise.
(vec_vminud): Likewise.
(vec_vpksdss): Likewise.
(vec_vpksdus): Likewise.
(vec_vpkudum): Likewise.
(vec_vpkudus): Likewise.
(vec_vrld): Likewise.
(vec_vsld): Likewise.
(vec_vsrad): Likewise.
(vec_vsrd): Likewise.
(vec_vsubudm): Likewise.
(vec_vupkhsw): Likewise.
(vec_vupklsw): Likewise.
2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com>
Pat Haugen <pthaugen@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
* doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Add
documentation for the power8 crypto builtins.
* config/rs6000/t-rs6000 (MD_INCLUDES): Add crypto.md.
* config/rs6000/rs6000-builtin.def (BU_P8V_AV_1): Add support
macros for defining power8 builtin functions.
(BU_P8V_AV_2): Likewise.
(BU_P8V_AV_P): Likewise.
(BU_P8V_VSX_1): Likewise.
(BU_P8V_OVERLOAD_1): Likewise.
(BU_P8V_OVERLOAD_2): Likewise.
(BU_CRYPTO_1): Likewise.
(BU_CRYPTO_2): Likewise.
(BU_CRYPTO_3): Likewise.
(BU_CRYPTO_OVERLOAD_1): Likewise.
(BU_CRYPTO_OVERLOAD_2): Likewise.
(XSCVSPDP): Fix typo, point to the correct instruction.
(VCIPHER): Add power8 crypto builtins.
(VCIPHERLAST): Likewise.
(VNCIPHER): Likewise.
(VNCIPHERLAST): Likewise.
(VPMSUMB): Likewise.
(VPMSUMH): Likewise.
(VPMSUMW): Likewise.
(VPERMXOR_V2DI): Likewise.
(VPERMXOR_V4SI: Likewise.
(VPERMXOR_V8HI: Likewise.
(VPERMXOR_V16QI: Likewise.
(VSHASIGMAW): Likewise.
(VSHASIGMAD): Likewise.
(VPMSUM): Likewise.
(VPERMXOR): Likewise.
(VSHASIGMA): Likewise.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
__CRYPTO__ if the crypto instructions are available.
(altivec_overloaded_builtins): Add support for overloaded power8
builtins.
* config/rs6000/rs6000.c (rs6000_expand_ternop_builtin): Add
support for power8 crypto builtins.
(builtin_function_type): Likewise.
(altivec_init_builtins): Add support for builtins that take vector
long long (V2DI) arguments.
* config/rs6000/crypto.md: New file, define power8 crypto
instructions.
2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com>
Pat Haugen <pthaugen@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
* doc/invoke.texi (Option Summary): Add power8 options.
(RS/6000 and PowerPC Options): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Update to use
constraints.md instead of rs6000.h. Reorder w* constraints. Add
wm, wn, wr documentation.
* gcc/config/rs6000/constraints.md (wm): New constraint for VSX
registers if direct move instructions are enabled.
(wn): New constraint for no registers.
(wq): New constraint for quad word even GPR registers.
(wr): New constraint if 64-bit instructions are enabled.
(wv): New constraint if power8 vector instructions are enabled.
(wQ): New constraint for quad word memory locations.
* gcc/config/rs6000/predicates.md (const_0_to_15_operand): New
constraint for 0..15 for crypto instructions.
(gpc_reg_operand): If VSX allow registers in VSX registers as well
as GPR and floating point registers.
(int_reg_operand): New predicate to match only GPR registers.
(base_reg_operand): New predicate to match base registers.
(quad_int_reg_operand): New predicate to match even GPR registers
for quad memory operations.
(vsx_reg_or_cint_operand): New predicate to allow vector logical
operations in both GPR and VSX registers.
(quad_memory_operand): New predicate for quad memory operations.
(reg_or_indexed_operand): New predicate for direct move support.
* gcc/config/rs6000/rs6000-cpus.def (ISA_2_5_MASKS_EMBEDDED):
Inherit from ISA_2_4_MASKS, not ISA_2_2_MASKS.
(ISA_2_7_MASKS_SERVER): New mask for ISA 2.07 (i.e. power8).
(POWERPC_MASKS): Add power8 options.
(power8 cpu): Use ISA_2_7_MASKS_SERVER instead of specifying the
various options.
* gcc/config/rs6000/rs6000-c.c (rs6000_target_modify_macros):
Define _ARCH_PWR8 and __POWER8_VECTOR__ for power8.
* gcc/config/rs6000/rs6000.opt (-mvsx-timode): Add documentation.
(-mpower8-fusion): New power8 options.
(-mpower8-fusion-sign): Likewise.
(-mpower8-vector): Likewise.
(-mcrypto): Likewise.
(-mdirect-move): Likewise.
(-mquad-memory): Likewise.
* gcc/config/rs6000/rs6000.c (power8_cost): Initial definition for
power8.
(rs6000_hard_regno_mode_ok): Make PTImode only match even GPR
registers.
(rs6000_debug_reg_print): Print the base register class if
-mdebug=reg.
(rs6000_debug_vector_unit): Add p8_vector.
(rs6000_debug_reg_global): If -mdebug=reg, print power8 constraint
definitions. Also print fusion state.
(rs6000_init_hard_regno_mode_ok): Set up power8 constraints.
(rs6000_builtin_mask_calculate): Add power8 builtin support.
(rs6000_option_override_internal): Add support for power8.
(rs6000_common_init_builtins): Add debugging for skipped builtins
if -mdebug=builtin.
(rs6000_adjust_cost): Add power8 support.
(rs6000_issue_rate): Likewise.
(insn_must_be_first_in_group): Likewise.
(insn_must_be_last_in_group): Likewise.
(force_new_group): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_POWER8_SPEC): If we don't have a
power8 capable assembler, default to power7 options.
(TARGET_DIRECT_MOVE): Likewise.
(TARGET_CRYPTO): Likewise.
(TARGET_P8_VECTOR): Likewise.
(VECTOR_UNIT_P8_VECTOR_P): Define power8 vector support.
(VECTOR_UNIT_VSX_OR_P8_VECTOR_P): Likewise.
(VECTOR_MEM_P8_VECTOR_P): Likewise.
(VECTOR_MEM_VSX_OR_P8_VECTOR_P): Likewise.
(VECTOR_MEM_ALTIVEC_OR_VSX_P): Likewise.
(TARGET_XSCVDPSPN): Likewise.
(TARGET_XSCVSPDPN): Likewsie.
(TARGET_SYNC_HI_QI): Likewise.
(TARGET_SYNC_TI): Likewise.
(MASK_CRYPTO): Likewise.
(MASK_DIRECT_MOVE): Likewise.
(MASK_P8_FUSION): Likewise.
(MASK_P8_VECTOR): Likewise.
(REG_ALLOC_ORDER): Move fr13 to be lower in priority so that the
TFmode temporary used by some of the direct move instructions to
get two FP temporary registers does not force creation of a stack
frame.
(VLOGICAL_REGNO_P): Allow vector logical operations in GPRs.
(MODES_TIEABLE_P): Move the VSX tests above the Altivec tests so
that any VSX registers are tieable, even if they are also an
Altivec vector mode.
(r6000_reg_class_enum): Add wm, wr, wv constraints.
(RS6000_BTM_P8_VECTOR): Power8 builtin support.
(RS6000_BTM_CRYPTO): Likewise.
(RS6000_BTM_COMMON): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add power8.
* config/rs6000/rs6000-opts.h (PROCESSOR_POWER8): Likewise.
(enum rs6000_vector): Add power8 vector support.
Backport from mainline
2013-03-20 Pat Haugen <pthaugen@us.ibm.com>
* config/rs6000/predicates.md (indexed_address, update_address_mem
update_indexed_address_mem): New predicates.
* config/rs6000/vsx.md (vsx_extract_<mode>_zero): Set correct "type"
attribute for load/store instructions.
* config/rs6000/dfp.md (movsd_store): Likewise.
(movsd_load): Likewise.
* config/rs6000/rs6000.md (zero_extend<mode>di2_internal1): Likewise.
(unnamed HI->DI extend define_insn): Likewise.
(unnamed SI->DI extend define_insn): Likewise.
(unnamed QI->SI extend define_insn): Likewise.
(unnamed QI->HI extend define_insn): Likewise.
(unnamed HI->SI extend define_insn): Likewise.
(unnamed HI->SI extend define_insn): Likewise.
(extendsfdf2_fpr): Likewise.
(movsi_internal1): Likewise.
(movsi_internal1_single): Likewise.
(movhi_internal): Likewise.
(movqi_internal): Likewise.
(movcc_internal1): Correct mnemonic for stw insn. Set correct "type"
attribute for load/store instructions.
(mov<mode>_hardfloat): Set correct "type" attribute for load/store
instructions.
(mov<mode>_softfloat): Likewise.
(mov<mode>_hardfloat32): Likewise.
(mov<mode>_hardfloat64): Likewise.
(mov<mode>_softfloat64): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
(probe_stack_<mode>): Likewise.
Backport from mainline
2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vector.md (VEC_R): Add 32-bit integer, binary
floating point, and decimal floating point to reload iterator.
* config/rs6000/constraints.md (wl constraint): New constraints to
return FLOAT_REGS if certain options are used to reduce the number
of separate patterns that exist in the file.
(wx constraint): Likewise.
(wz constraint): Likewise.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): If
-mdebug=reg, print wg, wl, wx, and wz constraints.
(rs6000_init_hard_regno_mode_ok): Initialize new constraints.
Initialize the reload functions for 64-bit binary/decimal floating
point types.
(reg_offset_addressing_ok_p): If we are on a power7 or later, use
LFIWZX and STFIWX to load/store 32-bit decimal types, and don't
create the buffer on the stack to overcome not having a 32-bit
load and store.
(rs6000_emit_move): Likewise.
(rs6000_secondary_memory_needed_rtx): Likewise.
(rs6000_alloc_sdmode_stack_slot): Likewise.
(rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f
via xxlxor, just like DFmode 0.0.
* config/rs6000/rs6000.h (TARGET_NO_SDMODE_STACK): New macro)
(define as 1 if we are running on a power7 or newer.
(enum r6000_reg_class_enum): Add new constraints.
* config/rs6000/dfp.md (movsd): Delete, combine with binary
floating point moves in rs6000.md. Combine power6x (mfpgpr) moves
with other moves by using conditional constraits (wg). Use LFIWZX
and STFIWX for loading SDmode on power7. Use xxlxor to create
0.0f.
(movsd splitter): Likewise.
(movsd_hardfloat): Likewise.
(movsd_softfloat): Likewise.
* config/rs6000/rs6000.md (FMOVE32): New iterators to combine
binary and decimal floating point moves.
(fmove_ok): New attributes to combine binary and decimal floating
point moves, and to combine power6x (mfpgpr) moves along normal
floating moves.
(real_value_to_target): Likewise.
(f32_lr): Likewise.
(f32_lm): Likewise.
(f32_li): Likewise.
(f32_sr): Likewise.
(f32_sm): Likewise.
(f32_si): Likewise.
(movsf): Combine binary and decimal floating point moves. Combine
power6x (mfpgpr) moves with other moves by using conditional
constraits (wg). Use LFIWZX and STFIWX for loading SDmode on
power7.
(mov<mode> for SFmode/SDmode); Likewise.
(SFmode/SDmode splitters): Likewise.
(movsf_hardfloat): Likewise.
(mov<mode>_hardfloat for SFmode/SDmode): Likewise.
(movsf_softfloat): Likewise.
(mov<mode>_softfloat for SFmode/SDmode): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document wl)
(wx and wz constraints.
* config/rs6000/constraints.md (wg constraint): New constraint to
return FLOAT_REGS if -mmfpgpr (power6x) was used.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wg
constraint.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): If
-mdebug=reg, print wg, wl, wx, and wz constraints.
(rs6000_init_hard_regno_mode_ok): Initialize new constraints.
Initialize the reload functions for 64-bit binary/decimal floating
point types.
(reg_offset_addressing_ok_p): If we are on a power7 or later, use
LFIWZX and STFIWX to load/store 32-bit decimal types, and don't
create the buffer on the stack to overcome not having a 32-bit
load and store.
(rs6000_emit_move): Likewise.
(rs6000_secondary_memory_needed_rtx): Likewise.
(rs6000_alloc_sdmode_stack_slot): Likewise.
(rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f
via xxlxor, just like DFmode 0.0.
* config/rs6000/dfp.md (movdd): Delete, combine with binary
floating point moves in rs6000.md. Combine power6x (mfpgpr) moves
with other moves by using conditional constraits (wg). Use LFIWZX
and STFIWX for loading SDmode on power7.
(movdd splitters): Likewise.
(movdd_hardfloat32): Likewise.
(movdd_softfloat32): Likewise.
(movdd_hardfloat64_mfpgpr): Likewise.
(movdd_hardfloat64): Likewise.
(movdd_softfloat64): Likewise.
* config/rs6000/rs6000.md (FMOVE64): New iterators to combine
64-bit binary and decimal floating point moves.
(FMOVE64X): Likewise.
(movdf): Combine 64-bit binary and decimal floating point moves.
Combine power6x (mfpgpr) moves with other moves by using
conditional constraits (wg).
(mov<mode> for DFmode/DDmode): Likewise.
(DFmode/DDmode splitters): Likewise.
(movdf_hardfloat32): Likewise.
(mov<mode>_hardfloat32 for DFmode/DDmode): Likewise.
(movdf_softfloat32): Likewise.
(movdf_hardfloat64_mfpgpr): Likewise.
(movdf_hardfloat64): Likewise.
(mov<mode>_hardfloat64 for DFmode/DDmode): Likewise.
(movdf_softfloat64): Likewise.
(mov<mode>_softfloat64 for DFmode/DDmode): Likewise.
(reload_<mode>_load): Move to later in the file so they aren't in
the middle of the floating point move insns.
(reload_<mode>_store): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document wg
constraint.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Print out wg
constraint if -mdebug=reg.
(rs6000_initi_hard_regno_mode_ok): Enable wg constraint if
-mfpgpr. Enable using dd reload support if needed.
* config/rs6000/dfp.md (movtd): Delete, combine with 128-bit
binary and decimal floating point moves in rs6000.md.
(movtd_internal): Likewise.
* config/rs6000/rs6000.md (FMOVE128): Combine 128-bit binary and
decimal floating point moves.
(movtf): Likewise.
(movtf_internal): Likewise.
(mov<mode>_internal, TDmode/TFmode): Likewise.
(movtf_softfloat): Likewise.
(mov<mode>_softfloat, TDmode/TFmode): Likewise.
* config/rs6000/rs6000.md (movdi_mfpgpr): Delete, combine with
movdi_internal64, using wg constraint for move direct operations.
(movdi_internal64): Likewise.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Print
MODES_TIEABLE_P for selected modes. Print the numerical value of
the various virtual registers. Use GPR/FPR first/last values)
(instead of hard coding the register numbers. Print which modes
have reload functions registered.
(rs6000_option_override_internal): If -mdebug=reg, trace the
options settings before/after setting cpu, target and subtarget
settings.
(rs6000_secondary_reload_trace): Improve the RTL dump for
-mdebug=addr and for secondary reload failures in
rs6000_secondary_reload_inner.
(rs6000_secondary_reload_fail): Likewise.
(rs6000_secondary_reload_inner): Likewise.
* config/rs6000/rs6000.md (FIRST_GPR_REGNO): Add convenience
macros for first/last GPR and FPR registers.
(LAST_GPR_REGNO): Likewise.
(FIRST_FPR_REGNO): Likewise.
(LAST_FPR_REGNO): Likewise.
* config/rs6000/vector.md (mul<mode>3): Use the combined macro
VECTOR_UNIT_ALTIVEC_OR_VSX_P instead of separate calls to
VECTOR_UNIT_ALTIVEC_P and VECTOR_UNIT_VSX_P.
(vcond<mode><mode>): Likewise.
(vcondu<mode><mode>): Likewise.
(vector_gtu<mode>): Likewise.
(vector_gte<mode>): Likewise.
(xor<mode>3): Don't allow logical operations on TImode in 32-bit
to prevent the compiler from converting DImode operations to
TImode.
(ior<mode>3): Likewise.
(and<mode>3): Likewise.
(one_cmpl<mode>2): Likewise.
(nor<mode>3): Likewise.
(andc<mode>3): Likewise.
* config/rs6000/constraints.md (wt constraint): New constraint
that returns VSX_REGS if TImode is allowed in VSX registers.
* config/rs6000/predicates.md (easy_fp_constant): 0.0f is an easy
constant under VSX.
* config/rs6000/rs6000-modes.def (PTImode): Define, PTImode is
similar to TImode, but it is restricted to being in the GPRs.
* config/rs6000/rs6000.opt (-mvsx-timode): New switch to allow
TImode to occupy a single VSX register.
* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Default to
-mvsx-timode for power7/power8.
(power7 cpu): Likewise.
(power8 cpu): Likewise.
* config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Make
sure that TFmode/TDmode take up two registers if they are ever
allowed in the upper VSX registers.
(rs6000_hard_regno_mode_ok): If -mvsx-timode, allow TImode in VSX
registers.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_debug_reg_global): Add debugging for PTImode and wt
constraint. Print if LRA is turned on.
(rs6000_option_override_internal): Give an error if -mvsx-timode
and VSX is not enabled.
(invalid_e500_subreg): Handle PTImode, restricting it to GPRs. If
-mvsx-timode, restrict TImode to reg+reg addressing, and PTImode
to reg+offset addressing. Use PTImode when checking offset
addresses for validity.
(reg_offset_addressing_ok_p): Likewise.
(rs6000_legitimate_offset_address_p): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_legitimize_reload_address): Likewise.
(rs6000_legitimate_address_p): Likewise.
(rs6000_eliminate_indexed_memrefs): Likewise.
(rs6000_emit_move): Likewise.
(rs6000_secondary_reload): Likewise.
(rs6000_secondary_reload_inner): Handle PTImode. Allow 64-bit
reloads to fpr registers to continue to use reg+offset addressing)
(but 64-bit reloads to altivec registers need reg+reg addressing.
Drop test for PRE_MODIFY, since VSX loads/stores no longer support
it. Treat LO_SUM like a PLUS operation.
(rs6000_secondary_reload_class): If type is 64-bit, prefer to use
FLOAT_REGS instead of VSX_RGS to allow use of reg+offset
addressing.
(rs6000_cannot_change_mode_class): Do not allow TImode in VSX
registers to share a register with a smaller sized type, since VSX
puts scalars in the upper 64-bits.
(print_operand): Add support for PTImode.
(rs6000_register_move_cost): Use VECTOR_MEM_VSX_P instead of
VECTOR_UNIT_VSX_P to catch types that can be loaded in VSX
registers, but don't have arithmetic support.
(rs6000_memory_move_cost): Add test for VSX.
(rs6000_opt_masks): Add -mvsx-timode.
* config/rs6000/vsx.md (VSm): Change to use 64-bit aligned moves
for TImode.
(VSs): Likewise.
(VSr): Use wt constraint for TImode.
(VSv): Drop TImode support.
(vsx_movti): Delete, replace with versions for 32-bit and 64-bit.
(vsx_movti_64bit): Likewise.
(vsx_movti_32bit): Likewise.
(vec_store_<mode>): Use VSX iterator instead of vector iterator.
(vsx_and<mode>3): Delete use of '?' constraint on inputs, just put
one '?' on the appropriate output constraint. Do not allow TImode
logical operations on 32-bit systems.
(vsx_ior<mode>3): Likewise.
(vsx_xor<mode>3): Likewise.
(vsx_one_cmpl<mode>2): Likewise.
(vsx_nor<mode>3): Likewise.
(vsx_andc<mode>3): Likewise.
(vsx_concat_<mode>): Likewise.
(vsx_xxpermdi_<mode>): Fix thinko for non V2DF/V2DI modes.
* config/rs6000/rs6000.h (MASK_VSX_TIMODE): Map from
OPTION_MASK_VSX_TIMODE.
(enum rs6000_reg_class_enum): Add RS6000_CONSTRAINT_wt.
(STACK_SAVEAREA_MODE): Use PTImode instead of TImode.
* config/rs6000/rs6000.md (INT mode attribute): Add PTImode.
(TI2 iterator): New iterator for TImode, PTImode.
(wd mode attribute): Add values for vector types.
(movti_string): Replace TI move operations with operations for
TImode and PTImode. Add support for TImode being allowed in VSX
registers.
(mov<mode>_string, TImode/PTImode): Likewise.
(movti_ppc64): Likewise.
(mov<mode>_ppc64, TImode/PTImode): Likewise.
(TI mode splitters): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document wt
constraint.
[gcc/testsuite]
2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline
2013-11-22 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/59054
* gcc.target/powerpc/direct-move.h (VSX_REG_ATTR): Allow test to
specify an appropriate register class for VSX operations.
(load_vsx): Use it.
(load_gpr_to_vsx): Likewise.
(load_vsx_to_gpr): Likewise.
* gcc.target/powerpc/direct-move-vint1.c: Use an appropriate
register class for VSX registers that the type can handle. Remove
checks for explicit number of instructions generated, just check
if the instruction is generated.
* gcc.target/powerpc/direct-move-vint2.c: Likewise.
* gcc.target/powerpc/direct-move-float1.c: Likewise.
* gcc.target/powerpc/direct-move-float2.c: Likewise.
* gcc.target/powerpc/direct-move-double1.c: Likewise.
* gcc.target/powerpc/direct-move-double2.c: Likewise.
* gcc.target/powerpc/direct-move-long1.c: Likewise.
* gcc.target/powerpc/direct-move-long2.c: Likewise.
* gcc.target/powerpc/bool3-av.c: Limit to 64-bit mode for now.
* gcc.target/powerpc/bool3-p7.c: Likewise.
* gcc.target/powerpc/bool3-p8.c: Likewise.
* gcc.target/powerpc/p8vector-ldst.c: Just check that the
appropriate instructions are generated, don't check the count.
2013-11-12 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/59054
* gcc.target/powerpc/pr59054.c: New test.
2013-08-22 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/pr57744.c: Declare abort.
2013-07-18 Pat Haugen <pthaugen@us.ibm.com>
* gcc.target/powerpc/pr57744.c: Fix typo.
Back port from mainline
2013-10-03 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p8vector-fp.c: New test for floating point
scalar operations when using -mupper-regs-sf and -mupper-regs-df.
* gcc.target/powerpc/ppc-target-1.c: Update tests to allow either
VSX scalar operations or the traditional floating point form of
the instruction.
* gcc.target/powerpc/ppc-target-2.c: Likewise.
* gcc.target/powerpc/recip-3.c: Likewise.
* gcc.target/powerpc/recip-5.c: Likewise.
* gcc.target/powerpc/pr72747.c: Likewise.
* gcc.target/powerpc/vsx-builtin-3.c: Likewise.
Back port from mainline
2013-09-27 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p8vector-ldst.c: New test for -mupper-regs-sf
and -mupper-regs-df.
Back port from mainline
2013-10-17 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/58673
* gcc.target/powerpc/pr58673-1.c: New file to test whether
-mquad-word + -mno-vsx-timode causes errors.
* gcc.target/powerpc/pr58673-2.c: Likewise.
Backport from trunk.
2013-07-23 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/bool2.h: New file, test the code generation
of logical operations for power5, altivec, power7, and power8 systems.
* gcc.target/powerpc/bool2-p5.c: Likewise.
* gcc.target/powerpc/bool2-av.c: Likewise.
* gcc.target/powerpc/bool2-p7.c: Likewise.
* gcc.target/powerpc/bool2-p8.c: Likewise.
* gcc.target/powerpc/bool3.h: Likewise.
* gcc.target/powerpc/bool3-av.c: Likewise.
* gcc.target/powerpc/bool2-p7.c: Likewise.
* gcc.target/powerpc/bool2-p8.c: Likewise.
Backport from trunk.
2013-07-31 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/fusion.c: New file, test power8 fusion support.
Back port from the trunk
2013-06-28 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/57744
* gcc.target/powerpc/pr57744.c: New test to make sure lqarx and
stqcx. get even registers.
Back port from the trunk
2013-06-12 Michael Meissner <meissner@linux.vnet.ibm.com>
Pat Haugen <pthaugen@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
* gcc.target/powerpc/atomic-p7.c: New file, add tests for atomic
load/store instructions on power7, power8.
* gcc.target/powerpc/atomic-p8.c: Likewise.
Back port from the trunk
2013-06-10 Michael Meissner <meissner@linux.vnet.ibm.com>
Pat Haugen <pthaugen@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
* gcc.target/powerpc/direct-move-vint1.c: New tests for power8
direct move instructions.
* gcc.target/powerpc/direct-move-vint2.c: Likewise.
* gcc.target/powerpc/direct-move.h: Likewise.
* gcc.target/powerpc/direct-move-float1.c: Likewise.
* gcc.target/powerpc/direct-move-float2.c: Likewise.
* gcc.target/powerpc/direct-move-double1.c: Likewise.
* gcc.target/powerpc/direct-move-double2.c: Likewise.
* gcc.target/powerpc/direct-move-long1.c: Likewise.
* gcc.target/powerpc/direct-move-long2.c: Likewise.
Backport from the trunk
2013-06-06 Michael Meissner <meissner@linux.vnet.ibm.com>
Pat Haugen <pthaugen@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
* gcc.target/powerpc/p8vector-builtin-1.c: New test to test
power8 builtin functions.
* gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c: Likewise.
* gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c: Likewise.
* gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c: Likewise.
* gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c: Likewise.
* gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c: Likewise.
* gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c: Likewise.
* gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c: New
tests to test power8 auto-vectorization.
* gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c: Likewise.
* gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c: Likewise.
* gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c: Likewise.
* gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c: Likewise.
* gcc.target/powerpc/crypto-builtin-1.c: Use effective target
powerpc_p8vector_ok instead of powerpc_vsx_ok.
* gcc.target/powerpc/bool.c: New file, add eqv, nand, nor tests.
* lib/target-supports.exp (check_p8vector_hw_available) Add power8
support.
(check_effective_target_powerpc_p8vector_ok): Likewise.
(is-effective-target): Likewise.
(check_vect_support_and_set_flags): Likewise.
Backport from trunk
2013-05-22 Michael Meissner <meissner@linux.vnet.ibm.com>
Pat Haugen <pthaugen@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
* gcc.target/powerpc/crypto-builtin-1.c: New file, test for power8
crypto builtins.
Backport from mainline
2013-03-20 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/mmfpgpr.c: New test.
* gcc.target/powerpc/sd-vsx.c: Likewise.
* gcc.target/powerpc/sd-pwr6.c: Likewise.
* gcc.target/powerpc/vsx-float0.c: Likewise.
From-SVN: r209087
tree-ssanames.c (make_ssa_name_fn): Fix assert.
2014-04-04 Richard Biener <rguenther@suse.de>
* tree-ssanames.c (make_ssa_name_fn): Fix assert.
From-SVN: r209080
re PR target/43751 (dsymutil is not called for fortran and, under some circumstances not for other FEs.)
2014-03-26 Dominique d'Humieres <dominiq@lps.ens.fr>
PR target/43751
* lib/prune.exp: Modify the regular express to prune
the new warnings introduced by r205679 on darwin9.
From-SVN: r209070
Daily bump.
From-SVN: r209067
Daily bump.
From-SVN: r209044
Daily bump.
From-SVN: r209006
gimple.h (struct gimple_statement_base): Align subcode to 16 bits.
2014-04-01 Richard Biener <rguenther@suse.de>
* gimple.h (struct gimple_statement_base): Align subcode to
16 bits.
From-SVN: r208977
* doc/invoke.texi (mapp-regs): Clarify.
From-SVN: r208974
Daily bump.
From-SVN: r208968
Daily bump.
From-SVN: r208952
Daily bump.
From-SVN: r208943
re PR fortran/60677 (FAIL: gfortran.dg/ichar_3.f90 -O (test for excess errors))
fortran/
PR fortran/60677
* trans-intrinsic.c (gfc_conv_intrinsic_ichar): Enlarge argument
list buffer.
From-SVN: r208932
Daily bump.
From-SVN: r208929
Daily bump.
From-SVN: r208885
Daily bump.
From-SVN: r208858
futex_bits.h: Include errno.h.
* config/linux/futex_bits.h: Include errno.h.
(sys_futex0): If syscall returns -1, return -errno rather than
-1.
From-SVN: r208856
re PR rtl-optimization/60452 (wrong code at -O1 with large offsets in the frame)
PR rtl-optimization/60452
* rtlanal.c (rtx_addr_can_trap_p_1): Fix head comment.
<case REG>: Return 1 for invalid offsets from the frame pointer.
From-SVN: r208838
Daily bump.
From-SVN: r208828
Daily bump.
From-SVN: r208801
Daily bump.
From-SVN: r208778
Daily bump.
From-SVN: r208768
Daily bump.
From-SVN: r208761
Daily bump.
From-SVN: r208742
config.host (v850*-*-*): Add to tmake_file instead of resetting it.
2014-03-20 Joel Sherrill <joel.sherrill@oarcorp.com>
* config.host (v850*-*-*): Add to tmake_file instead of resetting
it. This was removing the v850*-*-rtems* settings.
From-SVN: r208709
re PR target/60568 (lto1: internal compiler error: in insn_min_length, at config/i386/i386.md:1599)
PR target/60568
* config/i386/i386.c (x86_output_mi_thunk): Surround UNSPEC_GOT
into CONST, put pic register as first operand of PLUS. Use
gen_const_mem for both 32-bit and 64-bit PIC got loads.
From-SVN: r208707
sparc.c (sparc_do_work_around_errata): Implement work around for store forwarding issue in the FPU on the UT699.
* config/sparc/sparc.c (sparc_do_work_around_errata): Implement work
around for store forwarding issue in the FPU on the UT699.
* config/sparc/sparc.md (in_branch_delay): Return false for single FP
loads and operations if -mfix-ut699 is specified.
(divtf3_hq): Tweak attribute.
(sqrttf2_hq): Likewise.
From-SVN: r208696
Daily bump.
From-SVN: r208690
Daily bump.
From-SVN: r208671
re PR libstdc++/60564 ([C++11] The std::packaged_task constructor taking a reference to a functor does not copy its argument.)
PR libstdc++/60564
* include/std/future (__future_base::_Task_state<>): Change
constructors to template functions using perfect forwarding.
(__create_task_state): Use decayed type as stored task.
(packaged_task::packaged_task(_Fn&&)): Forward instead of moving.
* testsuite/30_threads/packaged_task/60564.cc: New.
From-SVN: r208655
sparc.c (sparc_do_work_around_errata): Speed up and use proper constant for the store mode.
* config/sparc/sparc.c (sparc_do_work_around_errata): Speed up and use
proper constant for the store mode.
From-SVN: r208639
Daily bump.
From-SVN: r208627
backport: re PR rtl-optimization/57425 (RTL alias analysis unprepared to handle stack slot sharing)
gcc/
2014-03-17 Mikael Pettersson <mikpelinux@gmail.com>
Committed by Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline:
2013-06-20 Joern Rennecke <joern.rennecke@embecosm.com>
PR rtl-optimization/57425
PR rtl-optimization/57569
* alias.c (write_dependence_p): Remove parameters mem_mode and
canon_mem_addr. Add parameters x_mode, x_addr and x_canonicalized.
Changed all callers.
(canon_anti_dependence): Get comments and semantics in sync.
Add parameter mem_canonicalized. Changed all callers.
* rtl.h (canon_anti_dependence): Update prototype.
2013-06-16 Joern Rennecke <joern.rennecke@embecosm.com>
PR rtl-optimization/57425
PR rtl-optimization/57569
* alias.c (write_dependence_p): Add new parameters mem_mode,
canon_mem_addr and mem_canonicalized. Change type of writep to bool.
Changed all callers.
(canon_anti_dependence): New function.
* cse.c (check_dependence): Use canon_anti_dependence.
* cselib.c (cselib_invalidate_mem): Likewise.
* rtl.h (canon_anti_dependence): Declare.
gcc/testsuite/
2014-03-17 Mikael Pettersson <mikpelinux@gmail.com>
Committed by Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline:
2013-06-16 Joern Rennecke <joern.rennecke@embecosm.com>
PR rtl-optimization/57425
PR rtl-optimization/57569
* gcc.dg/torture/pr57425-1.c, gcc.dg/torture/pr57425-2.c: New files.
* gcc.dg/torture/pr57425-3.c, gcc.dg/torture/pr57569.c: Likewise.
Co-Authored-By: Bill Schmidt <wschmidt@linux.vnet.ibm.com>
From-SVN: r208620
backport: re PR middle-end/60429 (Miscompilation (aliasing) with -finline-functions)
2014-03-17 Richard Biener <rguenther@suse.de>
Backport from mainline
2014-03-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/60429
PR tree-optimization/60485
* tree-ssa-structalias.c (set_union_with_increment): Properly
take into account all fields that overlap the shifted vars.
(do_sd_constraint): Likewise.
(do_ds_constraint): Likewise.
(get_constraint_for_ptr_offset): Likewise.
* gcc.dg/pr60485-1.c: New testcase.
* gcc.dg/pr60485-2.c: Likewise.
From-SVN: r208615
Daily bump.
From-SVN: r208608
Daily bump.
From-SVN: r208601
sparc-protos.h (tls_call_delay): Delete.
* config/sparc/sparc-protos.h (tls_call_delay): Delete.
(eligible_for_call_delay): New prototype.
* config/sparc/sparc.c (tls_call_delay): Rename into...
(eligible_for_call_delay): ...this. Return false if the instruction
cannot be put in the delay slot of a branch.
(eligible_for_restore_insn): Simplify.
(eligible_for_return_delay): Return false if the instruction cannot be
put in the delay slot of a branch and simplify.
(eligible_for_sibcall_delay): Return false if the instruction cannot be
put in the delay slot of a branch.
* config/sparc/sparc.md (fix_ut699): New attribute.
(tls_call_delay): Delete.
(in_call_delay): Reimplement.
(eligible_for_sibcall_del1ay): Rename into...
(in_sibcall_delay): ...this.
(eligible_for_return_delay): Rename into...
(in_return_delay): ...this.
(in_branch_delay): Reimplement.
(in_uncond_branch_delay): Delete.
(in_annul_branch_delay): Delete.
From-SVN: r208598
backport: re PR fortran/58324 (Bogus END-of-line error with list-directed I/O of file without trailing sequential record marker)
2014-03-15 Jerry DeLisle <jvdelisle@gcc.gnu>
Backport from mainline
PR libfortran/58324
* gfortran.dg/list_read_12.f90: New test.
From-SVN: r208596
backport: re PR fortran/58324 (Bogus END-of-line error with list-directed I/O of file without trailing sequential record marker)
2014-03-15 Jerry DeLisle <jvdelisle@gcc.gnu>
Backport from mainline
PR libfortran/58324
PR libfortran/38199
* io/list_read.c (finish_list_read): Read one character to check
for the end of the file. If it is the end, then issue the file
end error message. If not, use eat_line to reach the end
without giving error. The next attempt to read will then
issue the error as described above.
* io/read.c (read_decimal): Quickly skip spaces to avoid calls
to next_char.
* io/unit.c (is_trim_ok): New helper function to check various
conditions to see if its OK to trim the internal unit string.
(get_internal_unit): Use LEN_TRIM to shorten selected internal
unit strings for optimizing READ. Enable this optimization for
formatted READ.
From-SVN: r208595
Daily bump.
From-SVN: r208584
Daily bump.
From-SVN: r208560
re PR ada/51483 (cstand.adb:Register_Float_Type makes invalid assumption about FP modes)
PR ada/51483
* back_end.ads (Register_Type_Proc): Add 'precision' parameter.
* cstand.adb (Register_Float_Type): Add 'precision' parameter and use
it to set the RM size. Use directly 'size' for the Esize.
* gcc-interface/gigi.h (enumerate_modes): Add integer parameter.
* gcc-interface/misc.c (enumerate_modes): Likewise. Do not register
types for vector modes, pass the size in addition to the precision.
From-SVN: r208547
backport: re PR target/60486 ([avr] superfluous or missing comparision after addition or subtraction)
Backport from 2014-03-13 trunk r208532.
PR target/60486
* config/avr/avr.c (avr_out_plus): Swap cc_plus and cc_minus in
calls of avr_out_plus_1.
From-SVN: r208534
backport: re PR tree-optimization/60454 (Code mistakenly detected as doing bswap)
2014-03-13 Joey Ye <joey.ye@arm.com>
Backport from mainline
2014-03-12 Thomas Preud'homme <thomas.preudhomme@arm.com>
PR tree-optimization/60454
* tree-ssa-math-opts.c (find_bswap_1): Fix bswap detection.
testsuite:
* gcc.c-torture/execute/pr60454.c: New test.
From-SVN: r208529
Daily bump.
From-SVN: r208524
PR libstdc++/59392: Fix ARM EABI uncaught throw from unexpected exception handler
libstdc++-v3/
PR libstdc++/59392
* libsupc++/eh_call.cc (__cxa_call_unexpected): Call __do_catch with
the address of a null pointer, not with a null pointer to pointer.
Copy comment for this case from eh_personality.cc:__cxa_call_unexpected.
* testsuite/18_support/bad_exception/59392.cc: New file.
Co-Authored-By: Mark Seaborn <mseaborn@google.com>
From-SVN: r208520
Daily bump.
From-SVN: r208503
backport: re PR libstdc++/59738 (r206444 caused FAIL: 23_containers/vector/52591.cc)
Backport from mainline.
2014-01-09 Jonathan Wakely <jwakely@redhat.com>
PR libstdc++/59738
* include/bits/stl_vector.h (vector<>::_M_move_assign): Restore
support for non-Movable types.
2014-01-08 François Dumont <fdumont@gcc.gnu.org>
* include/bits/stl_vector.h (std::vector<>::_M_move_assign): Pass
*this allocator instance when building temporary vector instance
so that *this allocator does not get moved.
* testsuite/23_containers/vector/allocator/move.cc (test01): Add
check on a vector iterator.
* testsuite/23_containers/vector/allocator/move_assign.cc
(test02): Likewise.
(test03): New, test with a non-propagating allocator.
2013-11-15 Jonathan Wakely <jwakely.gcc@gmail.com>
* testsuite/23_containers/vector/allocator/move.cc: New
From-SVN: r208494
natObject.cc (_Jv_MonitorEnter): Add missing parenthesis around comparison with (address | LOCKED) in JvAssert.
* java/lang/natObject.cc (_Jv_MonitorEnter): Add missing parenthesis
around comparison with (address | LOCKED) in JvAssert.
From-SVN: r208492
Daily bump.
From-SVN: r208468
Daily bump.
From-SVN: r208446
Daily bump.
From-SVN: r208436
Daily bump.
From-SVN: r208421
runtime: Fix GC bug caused by Entersyscall modifying reg.
This patch fixes a rare but serious bug. The Go garbage
collector only examines Go stacks. When Go code calls a
function that is not written in Go, it first calls
syscall.Entersyscall. Entersyscall records the position of
the Go stack pointer and saves a copy of all the registers.
If the garbage collector runs while the thread is executing
the non-Go code, the garbage collector fetches the stack
pointer and registers from the saved location.
Entersyscall saves the registers using the getcontext
function. Unfortunately I didn't consider the possibility
that Entersyscall might itself change a register before
calling getcontext. This only matters for callee-saved
registers, as caller-saved registers would be visible on the
saved stack. And it only matters if Entersyscall is compiled
to save and modify a callee-saved register before it calls
getcontext. And it only matters if a garbage collection
occurs while the non-Go code is executing. And it only
matters if the only copy of a valid Go pointer happens to be
in the callee-saved register when Entersyscall is called.
When all those conditions are true, the Go pointer might get
collected incorrectly, leading to memory corruption.
This patch tries to avoid the problem by splitting
Entersyscall into two functions. The first is a simple
function that just calls getcontext and then calls the rest of
Entersyscall. This should fix the problem, provided the
simple Entersyscall function does not itself modify any
callee-saved registers before calling getcontext. That seems
to be true on the systems I checked. But since the argument
to getcontext is an offset from a TLS variable, it won't be
true on a system which needs to save callee-saved registers in
order to get the address of a TLS variable. I don't know why
any system would work that way, but I don't know how to rule
it out. I think that on any such system this will have to be
implemented in assembler. I can't put the ucontext_t
structure on the stack, because this function can not split
stacks, and the ucontext_t structure is large enough that it
could cause a stack overflow.
From-SVN: r208391
Daily bump.
From-SVN: r208388
Makefile.in (s-mlib): Only pass MULTIARCH_DIRNAME if MULTILIB_OSDIRNAMES is not defined.
2014-03-06 Matthias Klose <doko@ubuntu.com>
* Makefile.in (s-mlib): Only pass MULTIARCH_DIRNAME if
MULTILIB_OSDIRNAMES is not defined.
From-SVN: r208384
backport: re PR target/43546 (ICE: in assign_stack_local_1, at function.c:353 with -mpreferred-stack-boundary=2 -msseregparm)
Backport from mainline
2014-02-13 Jakub Jelinek <jakub@redhat.com>
PR target/43546
* expr.c (compress_float_constant): If x is a hard register,
extend into a pseudo and then move to x.
* gcc.target/i386/pr43546.c: New test.
From-SVN: r208369
backport: re PR c/60101 (Long compile times when mixed complex floating point datatypes are used in lengthy expressions)
Backport from mainline
2014-02-12 Jakub Jelinek <jakub@redhat.com>
PR c/60101
* c-common.c (merge_tlist): If copy is true, call new_tlist,
if false, add ADD itself, rather than vice versa.
(verify_tree): For COND_EXPR, don't call merge_tlist with non-zero
copy. For SAVE_EXPR, only call merge_tlist once.
* c-c++-common/pr60101.c: New test.
From-SVN: r208368
backport: re PR fortran/52370 (Spurious "may be used uninitialized" warning for check of optional argument)
Backport from mainline
2014-02-11 Jakub Jelinek <jakub@redhat.com>
PR fortran/52370
* trans-decl.c (gfc_build_dummy_array_decl): Set TREE_NO_WARNING
on decl if sym->attr.optional.
* gfortran.dg/pr52370.f90: New test.
From-SVN: r208367
backport: re PR middle-end/59776 (gcc -g -O1 ICE in expand_debug_locations, at cfgexpand.c:3865)
Backport from mainline
2014-02-11 Richard Henderson <rth@redhat.com>
Jakub Jelinek <jakub@redhat.com>
PR debug/59776
* tree-sra.c (load_assign_lhs_subreplacements): Add VIEW_CONVERT_EXPR
around drhs if type conversion to lacc->type is not useless.
* gcc.dg/guality/pr59776.c: New test.
From-SVN: r208366
backport: re PR preprocessor/56824 (pragma GCC diagnostic push/pop fail with GCC diagnostic ignored "-Waggregate-return")
Backport from mainline
2014-02-07 Jakub Jelinek <jakub@redhat.com>
PR preprocessor/56824
* line-map.c (linemap_compare_locations): Look through adhoc locations
for both l0 and l1.
* gcc.dg/pr56824.c: New test.
From-SVN: r208365
backport: re PR ipa/60026 (ICE at -O3 on valid code (with the optimize pragma) on x86_64-linux-gnu)
Backport from mainline
2014-02-08 Jakub Jelinek <jakub@redhat.com>
PR ipa/60026
* ipa-cp.c (determine_versionability): Fail at -O0
or __attribute__((optimize (0))) or -fno-ipa-cp functions.
* tree-sra.c (ipa_sra_preliminary_function_checks): Similarly.
2014-02-06 Jakub Jelinek <jakub@redhat.com>
PR target/60062
* tree.h (opts_for_fn): New inline function.
(opt_for_fn): Define.
* config/i386/i386.c (ix86_function_regparm): Use
opt_for_fn (decl, optimize) instead of optimize.
* gcc.c-torture/execute/pr60062.c: New test.
* gcc.c-torture/execute/pr60072.c: New test.
2014-02-04 Jakub Jelinek <jakub@redhat.com>
PR ipa/60026
* c-c++-common/torture/pr60026.c: New test.
From-SVN: r208364
backport: re PR middle-end/57499 (ICE when noreturn destructor returns after throw with -O)
Backport from mainline
2014-02-05 Jakub Jelinek <jakub@redhat.com>
PR middle-end/57499
* tree-eh.c (cleanup_empty_eh): Bail out on totally empty
bb with no successors.
* g++.dg/torture/pr57499.C: New test.
From-SVN: r208363
Daily bump.
From-SVN: r208356
Daily bump.
From-SVN: r208337
re PR tree-optimization/60382 (ICE on valid code at -O3 on x86_64-linux-gnu (in vect_create_epilog_for_reduction, at tree-vect-loop.c:4352))
2014-03-04 Richard Biener <rguenther@suse.de>
PR tree-optimization/60382
* tree-vect-loop.c (vect_is_simple_reduction_1): Do not consider
dead PHIs a reduction.
* gcc.dg/vect/pr60382.c: New testcase.
From-SVN: r208310
Daily bump.
From-SVN: r208298
Daily bump.
From-SVN: r208264
Daily bump.
From-SVN: r208253
projects / thirdparty / gcc.git / log
