Jonathan Wakely [Wed, 27 May 2020 21:08:15 +0000 (22:08 +0100)]
libstdc++: Fix view adaptors for mixed-const sentinels and iterators (PR 95322)
The bug report is that transform_view's sentinel<false> cannot be
compared to its iterator<true>. The comparison is supposed to use
operator==(iterator<Const>, sentinel<Const>) after converting
sentinel<false> to sentinel<true>. However, the operator== is a hidden
friend so is not a candidate when comparing iterator<true> with
sentinel<false>. The required conversion would only happen if we'd found
the operator, but we can't find the operator until after the conversion
happens.
A new LWG issue has been reported, but not yet assigned a number. The
solution suggested by Casey Carter is to make the hidden friends of the
sentinel types work with iterators of any const-ness, so that no
conversions are required.
Patrick Palka observed that join_view has a similar problem and a
similar fix is used for its sentinel.
PR libstdc++/95322
* include/std/ranges (transform_view::_Sentinel): Allow hidden
friends to work with _Iterator<true> and _Iterator<false>.
(join_view::_Sentinel): Likewise.
* testsuite/std/ranges/adaptors/95322.cc: New test.
Jonathan Wakely [Mon, 4 May 2020 12:34:23 +0000 (13:34 +0100)]
libstdc++: Make pmr::synchronized_pool_resource work without libpthread (PR 94936)
I implicitly assumed that programs using pmr::synchronized_pool_resource
would also be using multiple threads, and so the weak symbols in
gthr-posix.h would be resolved by linking to libpthread. If that isn't
true then it crashes when trying to use pthread_key_create.
This commit makes the pool resource check __gthread_active_p() before
using thread-specific data, and just use a single set of memory pools
when there's only a single thread.
PR libstdc++/94936
* src/c++17/memory_resource.cc (synchronized_pool_resource::_TPools):
Add comment about single-threaded behaviour.
(synchronized_pool_resource::_TPools::move_nonempty_chunks()): Hoist
class member access out of loop.
(synchronized_pool_resource::synchronized_pool_resource())
(synchronized_pool_resource::~synchronized_pool_resource())
(synchronized_pool_resource::release()): Check __gthread_active_p
before creating and/or deleting the thread-specific data key.
(synchronized_pool_resource::_M_thread_specific_pools()): Adjust
assertions.
(synchronized_pool_resource::do_allocate(size_t, size_t)): Add fast
path for single-threaded case.
(synchronized_pool_resource::do_deallocate(void*, size_t, size_t)):
Likewise. Return if unable to find a pool that owns the allocation.
* testsuite/20_util/synchronized_pool_resource/allocate_single.cc:
New test.
* testsuite/20_util/synchronized_pool_resource/cons_single.cc: New
test.
* testsuite/20_util/synchronized_pool_resource/release_single.cc: New
test.
Jonathan Wakely [Tue, 19 May 2020 15:49:21 +0000 (16:49 +0100)]
libstdc++: Use RDRAND as fallback if RDSEED keeps failing (PR 94087)
It's not difficult for multiple threads to drain the entropy available
to the RDSEED instruction, at which point we throw an exception. This
change will try to use RDRAND after RDSEED fails repeatedly, and only
throw if RDRAND also fails repeatedly. This doesn't guarantee a random
value can always be read, but reduces the likelihood of failure when
using the RDSEED instruction.
PR libstdc++/94087
* src/c++11/random.cc (__x86_rdseed): Allow fallback function to be
passed in.
(__x86_rdseed_rdrand): New function that uses rdseed with rdrand
fallback.
(random_device::_M_init): Use __x86_rdseed_rdrand when both
instructions are available.
* testsuite/26_numerics/random/random_device/94087.cc: New test.
Kito Cheng [Fri, 3 Jul 2020 05:49:51 +0000 (13:49 +0800)]
RISC-V: Disable remove unneeded save-restore call optimization if there are any arguments on stack.
- This optimization will adjust stack, but it not check/update other
stack pointer use-site, the example is when the arguments put on
stack, the offset become wrong after optimization.
- However adjust stack frame usage after register allocation could be
error prone, so we decide to turn off this optimization for such case.
- Ye-Ting Kuo report this issue on github:
https://github.com/riscv/riscv-gcc/pull/192
gcc/ChangeLog:
* config/riscv/riscv-sr.c (riscv_remove_unneeded_save_restore_calls):
Abort if any arguments on stack.
Kito Cheng [Fri, 19 Jun 2020 06:07:39 +0000 (14:07 +0800)]
RISC-V: Fix compilation failed for frflags builtin in C++ mode
- g++ will complain too few arguments for frflags builtin like bellow
message:
error: too few arguments to function 'unsigned int __builtin_riscv_frflags(void)'
- However it's no arguments needed, it because we declare the function
type with VOID arguments, that seems like require a VOID argument
in the c++ front-end when GCC tried to resolve the function.
gcc/ChangeLog
* config/riscv/riscv-builtins.c (RISCV_FTYPE_NAME0): New.
(RISCV_FTYPE_ATYPES0): New.
(riscv_builtins): Using RISCV_USI_FTYPE for frflags.
* config/riscv/riscv-ftypes.def: Remove VOID argument.
Kito Cheng [Tue, 16 Jun 2020 02:14:13 +0000 (10:14 +0800)]
RISC-V: Fix ICE on riscv_gpr_save_operation_p [PR95683]
- riscv_gpr_save_operation_p might try to match parallel on other
patterns like inline asm pattern, and then it might trigger ther
assertion checking there, so we could trun it into a early exit check.
gcc/ChangeLog:
PR target/95683
* config/riscv/riscv.c (riscv_gpr_save_operation_p): Remove
assertion and turn it into a early exit check.
Keith Packard [Wed, 29 Apr 2020 16:49:56 +0000 (09:49 -0700)]
RISC-V: Make unique SECCAT_SRODATA names start with .srodata (not .sdata2)
default_unique_section uses ".sdata2" as a prefix for SECCAT_SRODATA
unique sections, but RISC-V uses ".srodata" instead. Override the
TARGET_ASM_UNIQUE_SECTION function to catch this case, allowing the
default to be used for all other sections.
aarch64: Fix arm_sve_vector_bits on typedefs [PR95105]
Compiling this testcase with -march=armv8.2-a+sve
-msve-vector-bits=512:
----------------------------------------------------------
typedef __SVFloat32_t foo;
typedef foo bar __attribute__((arm_sve_vector_bits(512)));
template<typename T> struct s { T x; };
extern s<bar> a;
bar &b = a.x;
----------------------------------------------------------
gave the bogus error:
cannot bind non-const lvalue reference of type ‘bar&’ to an rvalue
of type ‘bar’
The testcase works if the attribute is applied directly
to __SVFloat32_t instead of via foo.
This shows a more general problem with the way that we were handling
the arm_sve_vector_bits attribute: we started by building a distinct
copy of the type to which the attribute was applied, instead of starting
with its main variant. This new type then became its own main variant,
meaning that the relationship between types that have the attribute
could be different from the relationship between types that don't have
the attribute.
This patch instead copies the main variant of the original type and then
reapplies all the differences.
gcc/
PR target/95105
* config/aarch64/aarch64-sve-builtins.cc
(handle_arm_sve_vector_bits_attribute): Create a copy of the
original type's TYPE_MAIN_VARIANT, then reapply all the differences
between the original type and its main variant.
gcc/testsuite/
PR target/95105
* gcc.target/aarch64/sve/acle/general/attributes_8.c: New test.
* g++.target/aarch64/sve/acle/general-c++/attributes_1.C: Likewise.
This fixes bogus misalignment calculation for negative steps
since an assertion a previous comment indicated no longer holds:
/* DR_STEP(dr) is the same as -TYPE_SIZE of the scalar type,
otherwise we wouldn't be here. */
Thus the following replaces DR_STEP by -TYPE_SIZE.
2020-07-06 Richard Biener <rguenther@suse.de>
PR tree-optimization/96075
* tree-vect-data-refs.c (vect_compute_data_ref_alignment): Use
TYPE_SIZE_UNIT of the vector component type instead of DR_STEP
for the misalignment calculation for negative step.
Richard Biener [Mon, 6 Jul 2020 09:30:53 +0000 (11:30 +0200)]
fix LTO streaming order dependence on randomness
This fixes the sorting of to copy symbols in lto_output introduced
with GCC 10 to not depend on the actual values of the randomness
we append to LTO section names but instead on the order they appear
in the unsorted array.
This fixed observed debug info differences due to tree merging
prevailing different early debug pointers.
2020-07-06 Richard Biener <rguenther@suse.de>
* lto-streamer-out.c (cmp_symbol_files): Use the computed
order map to sort symbols from the same sub-file together.
(lto_output): Compute a map of sub-file to an order number
it appears in the symbol output array.
Will Schmidt [Mon, 8 Jun 2020 15:39:18 +0000 (10:39 -0500)]
Backport to gcc-10
[PATCH, PR target/94954] Fix wrong codegen for vec_pack_to_short_fp32() builtin
Hi,
Fix codegen for builtin vec_pack_to_short_fp32. This includes adding
a define_insn for xvcvsphp, and adding a new define_expand for
convert_4f32_8f16.
[v2]
Comment on altivec.md "convert_4f32_8f16" enhanced.
Testsuite builtins-1-p9-runnable.c updated.
OK for trunk and backports?
Thanks
-Will
PR target/94954
gcc/Changelog:
* config/rs6000/altivec.h (vec_pack_to_short_fp32): Update.
* config/rs6000/altivec.md (UNSPEC_CONVERT_4F32_8F16): New unspec.
(convert_4f32_8f16): New define_expand
* config/rs6000/rs6000-builtin.def (convert_4f32_8f16): New builtin define
and overload.
* config/rs6000/rs6000-call.c (P9V_BUILTIN_VEC_CONVERT_4F32_8F16): New
overloaded builtin entry.
* config/rs6000/vsx.md (UNSPEC_VSX_XVCVSPHP): New unspec.
(vsx_xvcvsphp): New define_insn.
Harald Anlauf [Thu, 2 Jul 2020 18:41:51 +0000 (20:41 +0200)]
PR fortran/93337 - ICE in gfc_dt_upper_string, at fortran/module.c:441
When declaring a polymorphic variable that is not a dummy, allocatable or
pointer, an ICE occurred due to a NULL pointer dereference. Check for
that situation and punt.
gcc/fortran/
PR fortran/93337
* class.c (gfc_find_derived_vtab): Punt if name is not set.
Thomas Koenig [Tue, 30 Jun 2020 11:01:36 +0000 (13:01 +0200)]
Use CHARACTER(kind) string for calculating the type hash.
This regression came about because of a change in the way
types are displayed in error messages. The character
representation is also used to calculate the hashes for
our types, so this patch restores the old behavior if
we are indeed calculating a hash.
The test case also checks for the specific hash value because
changing that would be an ABI change, which we should not
be doing unintentionally.
gcc/fortran/ChangeLog:
2020-06-30 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/95366
* gfortran.h (gfc_typename): Add optional argument for_hash.
* misc.c (gfc_typename): When for_hash is true, just retur
CHARACTER(kind).
* class.c (gfc_intrinsic_hash_value): Call gfc_typename with
for_hash = true.
Martin Jambor [Sat, 4 Jul 2020 17:46:52 +0000 (19:46 +0200)]
ipa-sra: Avoid transitive splits with type mismatches (PR 96040)
PR 96040 revealed IPA-SRA, when checking whether an intended split is
the same as the one in a called function does not also check if the
types match and the transformation code does not handle any resulting
type mismatches. This patch simply avoids the the split in the case
of mismatches, so that we do not have to be careful about invalid
floating-point values being passed in floating point registers and
related issues.
gcc/ChangeLog:
2020-07-03 Martin Jambor <mjambor@suse.cz>
PR ipa/96040
* ipa-sra.c (all_callee_accesses_present_p): Do not accept type
mismatched accesses.
Martin Jambor [Fri, 3 Jul 2020 12:51:02 +0000 (14:51 +0200)]
ipa-sra: Prevent constructing debug info from wrong argument
The mechanism generating debug info for removed parameters did not
adjust index of the argument in the call statement to take into
account extra arguments IPA-SRA might have produced when splitting a
strucutre. This patch addresses that omission and stops gdb from
showing incorrect value for the removed parameter and says "value
optimized out" instead. The guality testcase will end up as
UNSUPPORTED in the results which is how Richi told me on IRC we deal
with this.
It is possible to generate debug info to actually show the value of
the removed parameter but so far my approaches to do just that seem
toocontroversial
(https://gcc.gnu.org/pipermail/gcc-patches/2020-May/546705.html), so
before I come up with something better I'd like to push this to master
and the gcc-10 branch in time for the GCC 10.2 release.
gcc/ChangeLog:
2020-07-01 Martin Jambor <mjambor@suse.cz>
PR debug/95343
* ipa-param-manipulation.c (ipa_param_adjustments::modify_call): Adjust
argument index if necessary.
gcc/testsuite/ChangeLog:
2020-07-01 Martin Jambor <mjambor@suse.cz>
PR debug/95343
* gcc.dg/guality/pr95343.c: New test.
PR libstdc++/91807
* include/std/variant
(_Copy_assign_base::operator=(const _Copy_assign_base&):
Do the move-assignment from a temporary so that the temporary
is constructed with an explicit index.
* testsuite/20_util/variant/91807.cc: New.
These tests fail with AIX double double. Use different floating point
values that behave less surprisingly.
libstdc++-v3/ChangeLog:
PR libstdc++/91153
PR target/93224
* testsuite/29_atomics/atomic_float/1.cc: Use different values
for tests.
* testsuite/29_atomics/atomic_ref/float.cc: Likewise.
This patch adds support for the two new HWCAP2 fields used by the
__builtin_cpu_supports function. It adds support in the target_clones
attribute for -mcpu=power10.
The two new __builtin_cpu_supports tests are:
__builtin_cpu_supports ("arch_3_1")
__builtin_cpu_supports ("mma")
The bits used are the bits that the Linux kernel engineers will be using for
these new features.
2020-06-05 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER10): Allocate
'power10' PowerPC platform.
(PPC_FEATURE2_ARCH_3_1): New HWCAP2 bit for ARCH 3.1.
(PPC_FEATURE2_MMA): New HWCAP2 bit for MMA.
* config/rs6000/rs6000-call.c (cpu_supports_info): Add ARCH 3.1 and
MMA HWCAP2 bits.
gcc/testsuite/
* gcc.target/powerpc/clone3.c: New test for using 'power10' with
the target_clones attribute.
Martin Liska [Thu, 2 Jul 2020 08:51:06 +0000 (10:51 +0200)]
gcc-changelog: sync from master.
contrib/ChangeLog:
* gcc-changelog/git_check_commit.py: New file.
* gcc-changelog/git_commit.py: New file.
* gcc-changelog/git_email.py: New file.
* gcc-changelog/git_repository.py: New file.
* gcc-changelog/git_update_version.py: New file.
* gcc-changelog/test_email.py: New file.
* gcc-changelog/test_patches.txt: New file.
Jonathan Wakely [Wed, 27 May 2020 21:55:21 +0000 (22:55 +0100)]
libstdc++: Strip cv-qualifiers in std::atomic<FP> (PR 95282)
This squashes two commits, r11-674 and r11-1401.
PR libstdc++/95282
* include/bits/atomic_base.h (__atomic_impl::load): Add
const-qualifier to parameter so that _Tp is deduced as the
non-const type, and use _Val to get the unqualified type.
(__atomic_impl::exchange): Use the _Val alias to remove
volatile from the reinterpret_cast result type.
* testsuite/29_atomics/atomic_float/95282.cc: New test.
coroutines: Collect the function body rewrite code.
The standard describes a rewrite of the body of the user-authored
function (which wraps it in a try-catch block and provides the
initial and final suspend expressions). The exact arrangement of
this was still in flux right up until the DIS and as a consequence
was a bit of a moving target.
The net result was a fragmented implementation of the parts of
the rewrite which is now impeding progress in fixing other issues.
This patch collates the rewrite action into a single function and
carries this out earlier.
gcc/cp/ChangeLog:
* coroutines.cc (expand_one_await_expression): Remove
code dealing with initial suspend.
(build_actor_fn): Remove code special-casing initial
and final suspend. Handle the final suspend and marking
of the coroutine as done.
(coro_rewrite_function_body): New.
(bind_expr_find_in_subtree): Remove.
(coro_body_contains_bind_expr_p): Remove.
(morph_fn_to_coro): Split the rewrite of the original
function into coro_rewrite_function_body and call it.
arm: Fix the failing mve scalar shift execution tests.
In GCC testsuite the MVE scalar shift execution tests (mve_scalar_shifts[1-4].c) are failings
because of executing them on target hardware which doesn't support MVE instructions. This patch
restricts those tests to execute only on target hardware that support MVE instructions.
* config/rs6000/driver-rs6000.c (asm_names): Use -mpwr10 for power10
on AIX, and -mpower10 elsewhere.
* config/rs6000/future.md: Delete.
* config/rs6000/linux64.h: Update comments. Use TARGET_POWER10, not
TARGET_FUTURE.
* config/rs6000/power10.md: New file.
* config/rs6000/rs6000-builtin.def: Update comments.
* config/rs6000/rs6000-call.c: Use P10_BUILTIN_*, not FUTURE_BUILTIN_*.
Update compiler messages.
* config/rs6000/rs6000-cpus.def: Update comments. Use ISA_3_1_*, not
ISA_FUTURE_*. Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE.
* config/rs6000/rs6000-opts.h: Use PROCESSOR_POWER10, not
PROCESSOR_FUTURE.
* config/rs6000/rs6000-string.c: Ditto.
* config/rs6000/rs6000-tables.opt (rs6000_cpu_opt_value): Use "power10"
instead of "future", reorder it to right after "power9".
* config/rs6000/rs6000.c: Update comments. Use OPTION_MASK_POWER10,
not OPTION_MASK_FUTURE. Use TARGET_POWER10, not TARGET_FUTURE. Use
RS6000_BTM_P10, not RS6000_BTM_FUTURE. Update compiler messages.
Use PROCESSOR_POWER10, not PROCESSOR_FUTURE. Use ISA_3_1_MASKS_SERVER,
not ISA_FUTURE_MASKS_SERVER.
(rs6000_opt_masks): Use "power10" instead of "future".
(rs6000_builtin_mask_names): Ditto.
(rs6000_disable_incompatible_switches): Ditto.
* config/rs6000/rs6000.h: Use -mpower10, not -mfuture. Use
-mcpu=power10, not -mcpu=future. Use MASK_POWER10, not MASK_FUTURE.
Use OPTION_MASK_POWER10, not OPTION_MASK_FUTURE. Use RS6000_BTM_P10,
not RS6000_BTM_FUTURE.
* config/rs6000/rs6000.md: Use "power10", not "future". Use
TARGET_POWER10, not TARGET_FUTURE. Include "power10.md", not
"future.md".
* config/rs6000/rs6000.opt (mfuture): Delete.
(mpower10): New.
* config/rs6000/t-rs6000: Use "power10.md", not "future.md".
* config/rs6000/vsx.md: Use TARGET_POWER10, not TARGET_FUTURE.
Alex Coplan [Mon, 18 May 2020 15:29:04 +0000 (16:29 +0100)]
arm: Don't generate invalid LDRD insns
This fixes a bug in the arm backend where GCC generates invalid LDRD
instructions. The LDRD instruction requires the first transfer register to be
even, but GCC attempts to use odd registers here. For example, with the
following C code:
struct c {
double a;
} __attribute((aligned)) __attribute((packed));
struct c d;
struct c f(struct c);
void e() { f(d); }
The struct d is passed in registers r1 and r2 to the function f, and GCC
attempted to do this with a LDRD instruction when compiling with -march=armv7-a
on a soft float toolchain.
The fix is analogous to the corresponding one for STRD in the same function:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=52057dc4ac5295caebf83147f688d769c93cbc8d
gcc/:
* config/arm/arm.c (output_move_double): Fix codegen when loading into
a register pair with an odd base register.
gcc/testsuite/:
* gcc.c-torture/compile/packed-aligned-1.c: New test.
* gcc.c-torture/execute/packed-aligned.c: New test.
Thomas Koenig [Mon, 29 Jun 2020 21:11:06 +0000 (23:11 +0200)]
Do not generate recursion check for compiler-generated procedures.
This one-line fix removes a check for recursion for procedures
which are compiler-generated, such as finalizers or deallocation.
These need to be recursive, even if the user code should not be.
gcc/fortran/ChangeLog:
PR fortran/95743
* trans-decl.c (gfc_generate_function_code): Do not generate
recursion check for compiler-generated procedures.
Iain Sandoe [Tue, 30 Jun 2020 07:18:34 +0000 (08:18 +0100)]
coroutines: Handle awaiters that are sub-objects [PR95736]
Move deciding on initializers for awaitables to the build of the
co_await, this allows us to analyse cases that do not need
a temporary at that point.
As the PR shows, the late analysis meant that we were not
checking properly for the case that an awaiter is a sub-object
of an existing variable outside the current function scope (and
therefore does not need to be duplicated in the frame).
gcc/cp/ChangeLog:
PR c++/95736
* coroutines.cc (get_awaitable_var): New helper.
(build_co_await): Check more carefully before
copying an awaitable.
(expand_one_await_expression): No initializer
is required when the awaitable is not a temp.
(register_awaits): Remove handling that is now
completed when the await expression is built.
gcc/testsuite/ChangeLog:
PR c++/95736
* g++.dg/coroutines/pr95736.C: New test.
Iain Sandoe [Tue, 30 Jun 2020 06:54:39 +0000 (07:54 +0100)]
coroutines: Improve diagnostics for one allocator case.
If the user provides operator new and that is noexcept, this
implies that it can fail with a null return. At that point, we expect
to be able to call get_return_object_on_allocation_failure().
This diagnoses the case where such an operator new has been
provided, but the g-r-o-o-a-f is either missing or unusable.
The PR points out that the standard does not restrict promise
expressions to methods, but the current implementation does.
The patch factors out the building of a general promise expression,
and then uses it in a fairly mechanical replacement of each case
that we need such an expressions.
This extends the handling for p.xxxxxx() expressions to cover the
cases where the promise member is some form callable.
Tests are added for each of the promise expressions.
It's somewhat tortuous to find good uses for this for the
get-return-object and get-return-object-on-allocation-failure
cases, but they are included anyway.
PR c++/95519
* coroutines.cc (struct coroutine_info):Add a field
to hold computed p.return_void expressions.
(coro_build_promise_expression): New.
(get_coroutine_return_void_expr): New.
(finish_co_yield_expr): Build the promise expression
using coro_build_promise_expression.
(finish_co_return_stmt): Likewise.
(build_init_or_final_await): Likewise.
(morph_fn_to_coro): Likewise, for several cases.
gcc/testsuite/ChangeLog:
PR c++/95519
* g++.dg/coroutines/torture/pr95519-00-return_void.C: New test.
* g++.dg/coroutines/torture/pr95519-01-initial-suspend.C: New test.
* g++.dg/coroutines/torture/pr95519-02-final_suspend.C: New test.
* g++.dg/coroutines/torture/pr95519-03-return-value.C: New test.
* g++.dg/coroutines/torture/pr95519-04-yield-value.C: New test.
* g++.dg/coroutines/torture/pr95519-05-gro.C: New test.
* g++.dg/coroutines/torture/pr95519-06-grooaf.C: New test.
* g++.dg/coroutines/torture/pr95519-07-unhandled-exception.C: New test.
Iain Sandoe [Mon, 29 Jun 2020 09:52:07 +0000 (10:52 +0100)]
coroutines: Handle bad g-r-o-o-a-f cases.
If we see a get_return_object_on_allocation_failure in the
promise, we expect to be able to use it. If this isn't
possible (because of some error in the declaration) then we
need to handle the erroneous return to allow following code
to complete.
gcc/cp/ChangeLog:
* coroutines.cc (morph_fn_to_coro): Handle error
returns in building g-r-o-o-a-f expressions.
gcc/testsuite/ChangeLog:
* g++.dg/coroutines/coro1-allocators.h (BAD_GROOAF_STATIC):
New.
* g++.dg/coroutines/coro-bad-grooaf-00-static.C: New test.
PR libstdc++/95915
* include/std/variant (_Uninitialized):
Adjust the condition and the comment.
* testsuite/20_util/variant/95915.cc: New.
* testsuite/20_util/variant/compile.cc: Add new test.
Jakub Jelinek [Sat, 27 Jun 2020 10:38:23 +0000 (12:38 +0200)]
c-family: Use TYPE_OVERFLOW_UNDEFINED instead of !TYPE_UNSIGNED in pointer_sum [PR95903]
For lp64 targets and int off ... ptr[off + 1]
is lowered in pointer_sum to *(ptr + ((sizetype) off + (sizetype) 1)).
That is fine when signed integer wrapping is undefined (and is not done
already if off has unsigned type), but changes behavior for -fwrapv, where
overflow is well defined. Runtime test could be:
int
main ()
{
char *p = __builtin_malloc (0x100000000UL);
if (!p) return 0;
char *q = p + 0x80000000UL;
int o = __INT_MAX__;
q[o + 1] = 1;
if (q[-__INT_MAX__ - 1] != 1) __builtin_abort ();
return 0;
}
with -fwrapv or so, not included in the testsuite because it requires 4GB
allocation (with some other test it would be enough to have something
slightly above 2GB, but still...).
2020-06-27 Jakub Jelinek <jakub@redhat.com>
PR middle-end/95903
gcc/c-family/
* c-common.c (pointer_int_sum): Use TYPE_OVERFLOW_UNDEFINED instead of
!TYPE_UNSIGNED check to see if we can apply distributive law and handle
smaller precision intop operands separately.
gcc/testsuite/
* c-c++-common/pr95903.c: New test.
Jakub Jelinek [Wed, 24 Jun 2020 08:40:02 +0000 (10:40 +0200)]
fold-const: Fix A <= 0 ? A : -A folding [PR95810]
We folded A <= 0 ? A : -A into -ABS (A), which is for signed integral types
incorrect - can invoke on INT_MIN UB twice, once on ABS and once on its
negation.
The following patch fixes it by instead folding it to (type)-ABSU (A).
2020-06-24 Jakub Jelinek <jakub@redhat.com>
PR middle-end/95810
* fold-const.c (fold_cond_expr_with_comparison): Optimize
A <= 0 ? A : -A into (type)-absu(A) rather than -abs(A).
* dmd/cond.c (lowerArrayAggregate): Directly use the elements of the
array for TupleExp creation.
(lowerNonArrayAggregate): Inline creation of foreach range indexes.
Iain Sandoe [Sun, 28 Jun 2020 08:48:33 +0000 (09:48 +0100)]
coroutines: Copy attributes to the outlined functions [PR95518,PR95813]
We had omitted the copying of function attributes, we now copy
the used, alignment, section values from the original decal and
the complete set of function attributes. It is likely that
some function attributes don't really make sense for coroutines,
but that can be disgnosed separately. Also mark the outlined
functions as artificial, since they are; some diagnostic
processing tests this.
gcc/cp/ChangeLog:
PR c++/95518
PR c++/95813
* coroutines.cc (act_des_fn): Copy function
attributes onto the outlined coroutine helpers.
gcc/testsuite/ChangeLog:
PR c++/95518
PR c++/95813
* g++.dg/coroutines/pr95518.C: New test.
* g++.dg/coroutines/pr95813.C: New test.
Iain Sandoe [Sun, 28 Jun 2020 07:10:12 +0000 (08:10 +0100)]
coroutines: Update tests for get-return-object errors.
We updated the handling of the errors for cases when the
ramp return cannot be constructed from the user's provided
get-return-object method. This updates the testcases to
cover this.
gcc/testsuite/ChangeLog:
* g++.dg/coroutines/void-gro-non-class-coro.C: Moved to...
* g++.dg/coroutines/coro-bad-gro-01-void-gro-non-class-coro.C: ...here.
* g++.dg/coroutines/coro-bad-gro-00-class-gro-scalar-return.C: New test.
Iain Sandoe [Thu, 25 Jun 2020 13:33:23 +0000 (14:33 +0100)]
coroutines: Add a cleanup expression for g-r-o when needed [PR95477].
The PR reports that we fail to destroy the object initially created from
the get-return-object call. Fixed by adding a cleanup when the DTOR is
non-trivial. In addition, to meet the specific wording that the call to
get_return_object creates the glvalue for the return, we must construct
that in-place in the return object to avoid a second copy/move CTOR.
gcc/cp/ChangeLog:
PR c++/95477
* coroutines.cc (morph_fn_to_coro): Apply a cleanup to
the get return object when the DTOR is non-trivial.
gcc/testsuite/ChangeLog:
PR c++/95477
* g++.dg/coroutines/pr95477.C: New test.
* g++.dg/coroutines/void-gro-non-class-coro.C: New test.
Peter Bergner [Sun, 21 Jun 2020 04:23:02 +0000 (23:23 -0500)]
rs6000: Add MMA built-in function definitions and test cases
Add the Matrix-Multiply Assist (MMA) built-ins. The MMA accumulators are
INOUT operands for most MMA instructions, but they are also very expensive
to move around. For this reason, we have implemented a built-in API where
the accumulators are passed using pass-by-reference/pointers, so the user
won't use one accumulator as input and another as output, which wouldentail
a lot of copies. However, using pointers gives us poor code generation
when we expand the built-ins at normal expand time. We therefore expand
the MMA built-ins early into gimple, converting the pass-by-reference calls
to an internal built-in that uses pass-by-value calling convention, where
we can enforce the input and output accumulators are the same. This gives
us much better code generation.
2020-06-20 Peter Bergner <bergner@linux.ibm.com>
gcc/
* config/rs6000/predicates.md (mma_assemble_input_operand): New.
* config/rs6000/rs6000-builtin.def (BU_MMA_1, BU_MMA_V2, BU_MMA_3,
BU_MMA_5, BU_MMA_6, BU_VSX_1): Add support macros for defining MMA
built-in functions.
(ASSEMBLE_ACC, ASSEMBLE_PAIR, DISASSEMBLE_ACC, DISASSEMBLE_PAIR,
PMXVBF16GER2, PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN,
PMXVBF16GER2PP, PMXVF16GER2, PMXVF16GER2NN, PMXVF16GER2NP,
PMXVF16GER2PN, PMXVF16GER2PP, PMXVF32GER, PMXVF32GERNN,
PMXVF32GERNP, PMXVF32GERPN, PMXVF32GERPP, PMXVF64GER, PMXVF64GERNN,
PMXVF64GERNP, PMXVF64GERPN, PMXVF64GERPP, PMXVI16GER2, PMXVI16GER2PP,
PMXVI16GER2S, PMXVI16GER2SPP, PMXVI4GER8, PMXVI4GER8PP, PMXVI8GER4,
PMXVI8GER4PP, PMXVI8GER4SPP, XVBF16GER2, XVBF16GER2NN, XVBF16GER2NP,
XVBF16GER2PN, XVBF16GER2PP, XVCVBF16SP, XVCVSPBF16, XVF16GER2,
XVF16GER2NN, XVF16GER2NP, XVF16GER2PN, XVF16GER2PP, XVF32GER,
XVF32GERNN, XVF32GERNP, XVF32GERPN, XVF32GERPP, XVF64GER, XVF64GERNN,
XVF64GERNP, XVF64GERPN, XVF64GERPP, XVI16GER2, XVI16GER2PP, XVI16GER2S,
XVI16GER2SPP, XVI4GER8, XVI4GER8PP, XVI8GER4, XVI8GER4PP, XVI8GER4SPP,
XXMFACC, XXMTACC, XXSETACCZ): Add MMA built-ins.
* config/rs6000/rs6000.c (rs6000_emit_move): Use CONST_INT_P.
Allow zero constants.
(print_operand) <case 'A'>: New output modifier.
(rs6000_split_multireg_move): Add support for inserting accumulator
priming and depriming instructions. Add support for splitting an
assemble accumulator pattern.
* config/rs6000/rs6000-call.c (mma_init_builtins, mma_expand_builtin,
rs6000_gimple_fold_mma_builtin): New functions.
(RS6000_BUILTIN_M): New macro.
(def_builtin): Handle RS6000_BTC_QUAD and RS6000_BTC_PAIR attributes.
(bdesc_mma): Add new MMA built-in support.
(htm_expand_builtin): Use RS6000_BTC_OPND_MASK.
(rs6000_invalid_builtin): Add handling of RS6000_BTM_FUTURE and
RS6000_BTM_MMA.
(rs6000_builtin_valid_without_lhs): Handle RS6000_BTC_VOID attribute.
(rs6000_gimple_fold_builtin): Call rs6000_builtin_is_supported_p
and rs6000_gimple_fold_mma_builtin.
(rs6000_expand_builtin): Call mma_expand_builtin.
Use RS6000_BTC_OPND_MASK.
(rs6000_init_builtins): Adjust comment. Call mma_init_builtins.
(htm_init_builtins): Use RS6000_BTC_OPND_MASK.
(builtin_function_type): Handle VSX_BUILTIN_XVCVSPBF16 and
VSX_BUILTIN_XVCVBF16SP.
* config/rs6000/rs6000.h (RS6000_BTC_QUINARY, RS6000_BTC_SENARY,
RS6000_BTC_OPND_MASK, RS6000_BTC_QUAD, RS6000_BTC_PAIR,
RS6000_BTC_QUADPAIR, RS6000_BTC_GIMPLE): New defines.
(RS6000_BTC_PREDICATE, RS6000_BTC_ABS, RS6000_BTC_DST,
RS6000_BTC_TYPE_MASK, RS6000_BTC_ATTR_MASK): Adjust values.
* config/rs6000/mma.md (MAX_MMA_OPERANDS): New define_constant.
(UNSPEC_MMA_ASSEMBLE_ACC, UNSPEC_MMA_PMXVBF16GER2,
UNSPEC_MMA_PMXVBF16GER2NN, UNSPEC_MMA_PMXVBF16GER2NP,
UNSPEC_MMA_PMXVBF16GER2PN, UNSPEC_MMA_PMXVBF16GER2PP,
UNSPEC_MMA_PMXVF16GER2, UNSPEC_MMA_PMXVF16GER2NN,
UNSPEC_MMA_PMXVF16GER2NP, UNSPEC_MMA_PMXVF16GER2PN,
UNSPEC_MMA_PMXVF16GER2PP, UNSPEC_MMA_PMXVF32GER,
UNSPEC_MMA_PMXVF32GERNN, UNSPEC_MMA_PMXVF32GERNP,
UNSPEC_MMA_PMXVF32GERPN, UNSPEC_MMA_PMXVF32GERPP,
UNSPEC_MMA_PMXVF64GER, UNSPEC_MMA_PMXVF64GERNN,
UNSPEC_MMA_PMXVF64GERNP, UNSPEC_MMA_PMXVF64GERPN,
UNSPEC_MMA_PMXVF64GERPP, UNSPEC_MMA_PMXVI16GER2,
UNSPEC_MMA_PMXVI16GER2PP, UNSPEC_MMA_PMXVI16GER2S,
UNSPEC_MMA_PMXVI16GER2SPP, UNSPEC_MMA_PMXVI4GER8,
UNSPEC_MMA_PMXVI4GER8PP, UNSPEC_MMA_PMXVI8GER4,
UNSPEC_MMA_PMXVI8GER4PP, UNSPEC_MMA_PMXVI8GER4SPP,
UNSPEC_MMA_XVBF16GER2, UNSPEC_MMA_XVBF16GER2NN,
UNSPEC_MMA_XVBF16GER2NP, UNSPEC_MMA_XVBF16GER2PN,
UNSPEC_MMA_XVBF16GER2PP, UNSPEC_MMA_XVF16GER2, UNSPEC_MMA_XVF16GER2NN,
UNSPEC_MMA_XVF16GER2NP, UNSPEC_MMA_XVF16GER2PN, UNSPEC_MMA_XVF16GER2PP,
UNSPEC_MMA_XVF32GER, UNSPEC_MMA_XVF32GERNN, UNSPEC_MMA_XVF32GERNP,
UNSPEC_MMA_XVF32GERPN, UNSPEC_MMA_XVF32GERPP, UNSPEC_MMA_XVF64GER,
UNSPEC_MMA_XVF64GERNN, UNSPEC_MMA_XVF64GERNP, UNSPEC_MMA_XVF64GERPN,
UNSPEC_MMA_XVF64GERPP, UNSPEC_MMA_XVI16GER2, UNSPEC_MMA_XVI16GER2PP,
UNSPEC_MMA_XVI16GER2S, UNSPEC_MMA_XVI16GER2SPP, UNSPEC_MMA_XVI4GER8,
UNSPEC_MMA_XVI4GER8PP, UNSPEC_MMA_XVI8GER4, UNSPEC_MMA_XVI8GER4PP,
UNSPEC_MMA_XVI8GER4SPP, UNSPEC_MMA_XXMFACC, UNSPEC_MMA_XXMTACC): New.
(MMA_ACC, MMA_VV, MMA_AVV, MMA_PV, MMA_APV, MMA_VVI4I4I8,
MMA_AVVI4I4I8, MMA_VVI4I4I2, MMA_AVVI4I4I2, MMA_VVI4I4,
MMA_AVVI4I4, MMA_PVI4I2, MMA_APVI4I2, MMA_VVI4I4I4,
MMA_AVVI4I4I4): New define_int_iterator.
(acc, vv, avv, pv, apv, vvi4i4i8, avvi4i4i8, vvi4i4i2,
avvi4i4i2, vvi4i4, avvi4i4, pvi4i2, apvi4i2, vvi4i4i4,
avvi4i4i4): New define_int_attr.
(*movpxi): Add zero constant alternative.
(mma_assemble_pair, mma_assemble_acc): New define_expand.
(*mma_assemble_acc): New define_insn_and_split.
(mma_<acc>, mma_xxsetaccz, mma_<vv>, mma_<avv>, mma_<pv>, mma_<apv>,
mma_<vvi4i4i8>, mma_<avvi4i4i8>, mma_<vvi4i4i2>, mma_<avvi4i4i2>,
mma_<vvi4i4>, mma_<avvi4i4>, mma_<pvi4i2>, mma_<apvi4i2>,
mma_<vvi4i4i4>, mma_<avvi4i4i4>): New define_insn.
* config/rs6000/rs6000.md (define_attr "type"): New type mma.
* config/rs6000/vsx.md (UNSPEC_VSX_XVCVBF16SP): New.
(UNSPEC_VSX_XVCVSPBF16): Likewise.
(XVCVBF16): New define_int_iterator.
(xvcvbf16): New define_int_attr.
(vsx_<xvcvbf16>): New define_insn.
* doc/extend.texi: Document the mma built-ins.
gcc/testsuite/
* gcc.target/powerpc/mma-builtin-1.c: New test.
* gcc.target/powerpc/mma-builtin-2.c: New test.
* gcc.target/powerpc/mma-builtin-3.c: New test.
* gcc.target/powerpc/mma-builtin-4.c: New test.
* gcc.target/powerpc/mma-builtin-5.c: New test.
* gcc.target/powerpc/mma-builtin-6.c: New test.
Peter Bergner [Sun, 21 Jun 2020 03:00:15 +0000 (22:00 -0500)]
rs6000: Add base support and types for defining MMA built-ins
Add the new -mmma option as well as the initial MMA support, which includes
the target specific __vector_pair and __vector_quad types, the POImode and
PXImode partial integer modes they are mapped to, and their associated
move patterns. Support for the restrictions on the registers these modes
can be assigned to as also been added.
2020-06-20 Peter Bergner <bergner@linux.ibm.com>
Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/mma.md: New file.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
__MMA__ for mma.
* config/rs6000/rs6000-call.c (rs6000_init_builtins): Add support
for __vector_pair and __vector_quad types.
* config/rs6000/rs6000-cpus.def (OTHER_FUTURE_MASKS): Add
OPTION_MASK_MMA.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000-modes.def (OI, XI): New integer modes.
(POI, PXI): New partial integer modes.
* config/rs6000/rs6000.c (TARGET_INVALID_CONVERSION): Define.
(rs6000_hard_regno_nregs_internal): Use VECTOR_ALIGNMENT_P.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
Add support for POImode being allowed in VSX registers and PXImode
being allowed in FP registers.
(rs6000_modes_tieable_p): Adjust comment.
Add support for POImode and PXImode.
(rs6000_debug_reg_global) <print_tieable_modes>: Add OImode, POImode
XImode, PXImode, V2SImode, V2SFmode and CCFPmode..
(rs6000_setup_reg_addr_masks): Use VECTOR_ALIGNMENT_P.
Set up appropriate addr_masks for vector pair and vector quad addresses.
(rs6000_init_hard_regno_mode_ok): Add support for vector pair and
vector quad registers. Setup reload handlers for POImode and PXImode.
(rs6000_builtin_mask_calculate): Add support for RS6000_BTM_MMA.
(rs6000_option_override_internal): Error if -mmma is specified
without -mcpu=future.
(rs6000_slow_unaligned_access): Use VECTOR_ALIGNMENT_P.
(quad_address_p): Change size test to less than 16 bytes.
(reg_offset_addressing_ok_p): Add support for ISA 3.1 vector pair
and vector quad instructions.
(avoiding_indexed_address_p): Likewise.
(rs6000_emit_move): Disallow POImode and PXImode moves involving
constants.
(rs6000_preferred_reload_class): Prefer VSX registers for POImode
and FP registers for PXImode.
(rs6000_split_multireg_move): Support splitting POImode and PXImode
move instructions.
(rs6000_mangle_type): Adjust comment. Add support for mangling
__vector_pair and __vector_quad types.
(rs6000_opt_masks): Add entry for mma.
(rs6000_builtin_mask_names): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE.
(rs6000_function_value): Use VECTOR_ALIGNMENT_P.
(address_to_insn_form): Likewise.
(reg_to_non_prefixed): Likewise.
(rs6000_invalid_conversion): New function.
* config/rs6000/rs6000.h (MASK_MMA): Define.
(BIGGEST_ALIGNMENT): Set to 512 if MMA support is enabled.
(VECTOR_ALIGNMENT_P): New helper macro.
(ALTIVEC_VECTOR_MODE): Use VECTOR_ALIGNMENT_P.
(RS6000_BTM_MMA): Define.
(RS6000_BTM_COMMON): Add RS6000_BTM_MMA and RS6000_BTM_FUTURE.
(rs6000_builtin_type_index): Add RS6000_BTI_vector_pair and
RS6000_BTI_vector_quad.
(vector_pair_type_node): New.
(vector_quad_type_node): New.
* config/rs6000/rs6000.md: Include mma.md.
(define_mode_iterator RELOAD): Add POI and PXI.
* config/rs6000/t-rs6000 (MD_INCLUDES): Add mma.md.
* config/rs6000/rs6000.opt (-mmma): New.
* doc/invoke.texi: Document -mmma.
Jason Merrill [Wed, 24 Jun 2020 01:25:21 +0000 (21:25 -0400)]
c++: Fix ICE with using and virtual function. [PR95719]
conversion_path points to the base where we found the using-declaration, not
where the function is actually a member; look up the actual base. And then
maybe look back to the derived class if the base is primary.
gcc/cp/ChangeLog:
PR c++/95719
* call.c (build_over_call): Look up the overrider in base_binfo.
* class.c (lookup_vfn_in_binfo): Look through BINFO_PRIMARY_P.
gcc/testsuite/ChangeLog:
PR c++/95719
* g++.dg/tree-ssa/final4.C: New test.
Jonathan Wakely [Wed, 24 Jun 2020 10:45:01 +0000 (11:45 +0100)]
libstdc++: Fix std::from_chars to ignore leading zeros in base 2
The parser for binary numbers returned an error if the entire string
contains more digits than the result type. Leading zeros should be
ignored.
libstdc++-v3/ChangeLog:
* include/std/charconv (__from_chars_binary): Ignore leading zeros.
* testsuite/20_util/from_chars/1.cc: Check "0x1" for all bases,
not just 10 and 16.
* testsuite/20_util/from_chars/3.cc: New test.
The __detail::__to_chars_2 function assumes it won't be called with zero
values. However, when the output buffer is empty the caller doesn't
handle zero values correctly, and calls __to_chars_2 with a zero value,
resulting in an overflow of the empty buffer.
The __detail::__to_chars_i function should just return immediately for
an empty buffer, and otherwise ensure zero values are handled properly.
libstdc++-v3/ChangeLog:
PR libstdc++/95851
* include/std/charconv (__to_chars_i): Check for zero-sized
buffer unconditionally.
* testsuite/20_util/to_chars/95851.cc: New test.
Richard Biener [Wed, 17 Jun 2020 12:57:59 +0000 (14:57 +0200)]
tree-optimization/95717 - fix SSA update for vectorizer epilogue
This fixes yet another issue with the custom SSA updating in the
vectorizer when we copy from the non-if-converted loop. We must
not mess with current defs before we updated the BB copies.
2020-06-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/95717
* tree-vect-loop-manip.c (slpeel_tree_duplicate_loop_to_edge_cfg):
Move BB SSA updating before exit/latch PHI current def copying.
Thomas Koenig [Tue, 23 Jun 2020 19:59:47 +0000 (21:59 +0200)]
Make forall statement in testsuite conforming.
The recent patch for dependency checking introduced one failing test
case for pointer assignments in a forall statement. This test case
was invalid because of an interdependency in a forall statement.
This patch fixes that by removing that dependency.
gcc/testsuite/ChangeLog:
2020-06-23 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/95812
* gfortran.fortran-torture/execute/forall_5.f90: Make forall
statement conforming.
Eric Botcazou [Tue, 23 Jun 2020 16:33:28 +0000 (18:33 +0200)]
Fix memory corruption with vector and variant record
The problem is that Has_Constrained_Partial_View must be tested on the
base type of the designated type of an allocator.
gcc/ada/ChangeLog:
* gcc-interface/trans.c (gnat_to_gnu) <N_Allocator>: Minor tweaks.
Call Has_Constrained_Partial_View on base type of designated type.
Richard Biener [Thu, 4 Jun 2020 11:44:58 +0000 (13:44 +0200)]
middle-end/95493 - bogus MEM_ATTRS for variable array access
The following patch avoids keeping the inherited MEM_ATTRS when
set_mem_attributes_minus_bitpos is called with a variable ARRAY_REF.
The inherited ones may not reflect the correct offset and neither
does the updated alias-set match the inherited MEM_EXPR. This all
ends up confusing path-based alias-analysis, causing wrong-code.
The fix is to stop not adopting a MEM_EXPR for certain kinds of
expressions and instead handle everything we can. There's still
the constant kind trees case which I'm too lazy to look into right
now. I did refrain from adding SSA_NAME there and instead avoided
calling set_mem_attributes_minus_bitpos when debug expression
expansion ended up expanding a SSA definition RHS which should
already have taken care of setting the appropriate MEM_ATTRS.
It also avoids calling set_mem_attributes on the
DECL_INITIAL of a CONST_DECL which seems pointless since there
cannot be a sensible MEM_EXPR derived from that. We're overwriting
both other possibly useful info, alias-set and alignment immediately
so the following patch simply removes the call instead of making
the function deal with even more (unexpected) trees that are not
memory accesses.
2020-06-23 Richard Biener <rguenther@suse.de>
PR middle-end/95493
PR middle-end/95690
* cfgexpand.c (expand_debug_expr): Avoid calling
set_mem_attributes_minus_bitpos when we were expanding
an SSA name.
* emit-rtl.c (set_mem_attributes_minus_bitpos): Remove
ARRAY_REF special-casing, add CONSTRUCTOR to the set of
special-cases we do not want MEM_EXPRs for. Assert
we end up with reasonable MEM_EXPRs.
* varasm.c (build_constant_desc): Remove set_mem_attributes call.
* g++.dg/torture/pr95493.C: New testcase.
* g++.dg/torture/pr95493-1.C: Likewise.
* gfortran.dg/pr95690.f90: Likewise.
Thomas Koenig [Tue, 23 Jun 2020 06:14:51 +0000 (08:14 +0200)]
Handle AR_FULL vs. AR_FULL in dependency checking.
Previously, handling of full vs. full references failed to take
AR_FULL vs. AR_FULL into account. A change in dependency
checking in gcc 10 created a code path that could lead there;
with this patch, this is now correctly handled.
gcc/fortran/ChangeLog:
2020-06-23 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/95812
* dependency.c (ref_same_as_full_array): Handle case of AR_FULL
vs. AR_FULL.
gcc/testsuite/ChangeLog:
2020-06-23 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/95812
* gfortran.dg/dependency_59.f90: New test.
projects / thirdparty / gcc.git / log
